Altera EVB-EN5367QI 6a powersoc highly integrated synchronous buck with integrated inductor Datasheet

Enpirion® Power Datasheet
EN5367QI 6A PowerSoC
Highly Integrated Synchronous Buck
With Integrated Inductor
Description
Features
The EN5367QI is a Power System on a Chip
(PowerSoC) DC to DC converter with an integrated
inductor,
PWM
controller,
MOSFETs
and
compensation to provide the smallest solution size in
a 5.5x10x3mm 54-pin QFN module. It offers high
efficiency, excellent line and load regulation over
temperature and up to the full 6A load range. The
EN5367QI is specifically designed to meet the
precise voltage and fast transient requirements of
high-performance, low-power processor, DSP, FPGA,
memory boards and system level applications in
distributed power architecture. The EN5367QI also
features switching frequency synchronization with an
external clock, programmable soft-start as well as
thermal shutdown, over-current and short circuit
protection. The device’s advanced circuit techniques,
ultra high switching frequency, and proprietary
integrated inductor technology deliver high-quality,
ultra compact, non-isolated DC-DC conversion.
The Altera Enpirion integrated inductor solution
significantly helps to reduce noise. The complete
power converter solution enhances productivity by
offering greatly simplified board design, layout and
manufacturing requirements. All Altera Enpirion
products are RoHS compliant and lead-free
manufacturing environment compatible.
•
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•
•
•
•
•
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0.1µF
High Efficiency (Up to 93%)
Excellent Ripple and EMI Performance
Up to 6A Continuous Operating Current
Input Voltage Range (2.5V to 5.5V)
Frequency Synchronization (External Clock)
3% VOUT Accuracy (Over Line/Load/Temperature)
Optimized Total Solution Size (160mm2)
Programmable Soft-Start
Output Enable Pin and Power OK
Thermal Shutdown, Over-Current, Short Circuit,
and Under-Voltage Lockout Protection (UVLO)
• RoHS Compliant, MSL Level 3, 260°C Reflow
Applications
• Point of Load Regulation for Low-Power, ASICs
Multi-Core and Communication Processors, DSPs,
FPGAs and Distributed Power Architectures
• Blade Servers, RAID Storage and LAN/SAN
Adapter Cards, Wireless Base Stations, Industrial
Automation, Test and Measurement, Embedded
Computing, and Printers
• Beat Frequency/Noise Sensitive Applications
0.1µF
Efficiency vs. Output Current
100
BTMP PG VDDB BGND
PVIN
10Ω
47µF
1206
VOUT
EN5367QI
80
47µF
1206
RA
CA
AVIN
47nF
0805
ENABLE
0.1µF
VFB
RCA
SS
PGND
AGND
SYNC
70
60
Actual Solution Size
160mm2
CONDITIONS
VIN = 5.0V
50
40
30
VOUT = 3.3V
20
PGND
47nF
90
VOUT
EFFICIENCY (%)
VIN
RB
VOUT = 1.2V
10
0
0
Figure 1. Simplified Applications Circuit
1
2
3
4
OUTPUT CURRENT (A)
5
6
Figure 2. Highest Efficiency in Smallest Solution Size
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Ordering Information
Part Number
Package Markings
Temp Rating (°C)
Package Description
EN5367QI
EN5367QI
-40 to +85
54-pin (5.5mm x 10mm x 3mm) QFN T&R
EN5367QI
QFN Evaluation Board
EVB-EN5367QI
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
NC
1
NC
VFB
SS
NC
44
43
42
NC
NC
45
ENABLE
AGND
46
37
AVIN
47
POK
NC
48
39
NC(SW)
49
38
NC(SW)
50
NC
NC(SW)
51
40
NC(SW)
52
EAOUT
NC
53
41
NC
54
Pin Assignments (Top View)
36
SYNC
2
35
BGND
NC
3
34
VDDB
NC
4
33
BTMP
NC
5
32
PG
NC
6
31
PVIN
NC
7
30
PVIN
NC
8
29
PVIN
NC
9
28
PVIN
KEEP OUT
KEEP OUT
55
PGND
14
15
16
17
18
19
20
21
22
23
24
25
26
27
VOUT
VOUT
VOUT
VOUT
NC
NC(SW)
NC(SW)
PGND
PGND
PGND
PGND
PGND
PGND
PGND
12
VOUT
13
11
VOUT
VOUT
10
VOUT
KEEP OUT
Figure 3: Pin Out Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to the PCB. Refer to Figure 9 for details.
NOTE C: White ‘dot’ on top left is pin 1 indicator on top of the device package.
Pin Description
PIN
NAME
1-9, 18,
37, 40,
42, 45,
48, 53-54
NC
10-17
VOUT
19-20,
49-52
NC(SW)
21-27
PGND
28-31
PVIN
32
PG
FUNCTION
NO CONNECT – These pins may be internally connected. Do not connect them to each other
or to any other electrical signal. Failure to follow this guideline may result in device damage.
Regulated converter output. Connect these pins to the load and place output capacitor
between these pins and PGND pins 21-24.
NO CONNECT – These pins are internally connected to the common switching node of the
internal MOSFETs. They are not to be electrically connected to any external signal, ground, or
voltage. Failure to follow this guideline may result in damage to the device.
Input/Output power ground. Connect these pins to the ground electrode of the input and
output filter capacitors. See VOUT and PVIN pin descriptions for more details.
Input power supply. Connect to input power supply. Decouple with input capacitor to PGND
pins 25-27.
High-side FET gate. This pin needs to be connected to BTMP using a 0.1µF capacitor.
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PIN
NAME
33
BTMP
34
VDDB
35
BGND
36
SYNC
38
ENABLE
39
POK
41
EAOUT
43
SS
44
VFB
46
AGND
47
AVIN
55
PGND
FUNCTION
Low side of the flying capacitor that drives the high-side FET gate. Connect to PG using a
0.1µF capacitor.
Regulated voltage used for internal control circuitry. Decouple with a 0.1µF capacitor to
BGND.
Internal GND for VDDB. Connect to VDDB using a 0.1µF capacitor. Do not tie to any grounds
on the PCB.
A clocked input to this pin will synchronize the internal switching frequency to the external
signal. If the SYNC function is not to be used, this pin has to be grounded. Do not float this pin
or tie it to a static high voltage.
Input Enable. Applying a logic high enables the output and initiates a soft-start. Applying a
logic low disables the output.
Power OK is an open drain transistor used for power system state indication. POK is logic
high when VOUT is within -10% of VOUT nominal.
Optional Error Amplifier output. Allows for customization of the control loop.
Soft-Start node. The soft-start capacitor is connected between this pin and AGND. The value
of this capacitor determines the startup time.
External Feedback Input. The feedback loop is closed through this pin. A voltage divider at
VOUT is used to set the output voltage. The midpoint of the divider is connected to VFB. A
phase lead capacitor from this pin to VOUT is also required to stabilize the loop.
Analog Ground. This is the Ground return for the controller. Needs to be connected to the
GND plane using a via right next to the pin.
Input power supply for the controller. Needs to be decoupled to AGND with a 0.1µF capacitor
and connected to the input voltage at a quiet point through a 10Ω resistor.
Not a perimeter pin. Device thermal pad to be connected to the system GND plane for heat
sinking purposes through a matrix of vias.
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Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating
conditions is not implied. Stress beyond the absolute maximum ratings may impair device life. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Voltages on : PVIN, AVIN, VOUT
-0.3
6.5
V
Voltages on: ENABLE, POK, SYNC
-0.3
VIN+0.3
V
Voltages on: VFB, SS
-0.3
2.75
V
-65
150
°C
150
°C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
ESD Rating (based on CDM)
500
V
Storage Temperature Range
TSTG
Maximum Operating Junction Temperature
TJ-ABS Max
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
VIN
2.5
5.5
V
Output Voltage Range (Note 1)
VOUT
0.60
VIN – VDO
V
Output Current
IOUT
6
A
Input Voltage Range
Operating Ambient Temperature
TA
-40
+85
°C
Operating Junction Temperature
TJ
-40
+125
°C
Thermal Characteristics
SYMBOL
TYP
UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 2)
PARAMETER
θJA
22
°C/W
Thermal Resistance: Junction to Case (0 LFM)
θJC
2
°C/W
Thermal Shutdown
TSD
150
°C
Thermal Shutdown Hysteresis
TSDH
20
°C
Note 1: VDO (Dropout Voltage) is defined as (ILOAD x Dropout Resistance). Please refer to Electrical Characteristics Table.
Note 2: Based on 2oz. external copper layers and proper thermal design in line with EIJ/JEDEC JESD51-7 standard for
high thermal conductivity boards.
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Electrical Characteristics
NOTE: VIN=5.5V, Minimum and Maximum values are over operating ambient temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER
SYMBOL
Operating Input
Voltage
VIN
TEST CONDITIONS
MIN
TYP
2.5
MAX
UNITS
5.5
V
Under Voltage LockVUVLOR
out – VIN Rising
Voltage above which UVLO is not
asserted
2.25
V
Under Voltage LockVUVLOF
out – VIN Falling
Voltage below which UVLO is
asserted
2.05
V
Shut-Down Supply
Current
IS
ENABLE=0V
100
µA
Feedback Pin
Voltage
VFB
Feedback Pin
Voltage
VFB
Feedback pin Input
Leakage Current
(Note 3)
IFB
VFB pin input leakage current
VOUT Rise Time
(Note 3)
tRISE
Measured from when VIN > VUVLOR &
ENABLE pin voltage crosses its logic
high threshold to when VOUT reaches
its final value. CSS = 47 nF
Soft Start Capacitor
Range
CSS_RANGE
Output Drop Out
Voltage Resistance
(Note 3)
VDO
RDO
Continuous Output
Current
IOUT_Max_Cont
Over Current Trip
Level
IOCP
VIN = 5V, VOUT = 1.2V
Disable Threshold
VDISABLE
ENABLE pin logic low.
0.0
0.6
V
ENABLE Threshold
VENABLE
ENABLE pin logic high
2.5V ≤ VIN ≤ 5.5V
1.8
VIN
V
ENABLE Lockout
Time
TENLOCKOUT
ENABLE pin Input
Current
IENABLE
Switching
Frequency (Free
Running)
Feedback node voltage at:
VIN = 5V, ILOAD = 0, TA = 25°C
Feedback node voltage at:
2.5V ≤ VIN ≤ 5.5V
0A ≤ ILOAD ≤ 6A
0.735
0.75
0.765
V
0.7275
0.75
0.7725
V
5
nA
4.70
ms
68
nF
600
100
mV
mΩ
6
A
-5
2.82
3.76
10
VINMIN - VOUT at Full load
Input to Output Resistance
300
50
0
9
A
2.4
ms
ENABLE pin has ~180kΩ pull down
30
µA
FSW
Free Running frequency of oscillator
4
MHz
External SYNC
Clock Frequency
Lock Range
FPLL_LOCK
Range of SYNC clock frequency
SYNC Pin
Threshold – Lo
VSYNC_LO
SYNC Clock Logic Level
SYNC Pin
Threshold – Hi
VSYNC_HI
SYNC Clock Logic Level (Note 4)
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3.2
1.8
4.2
MHz
0.8
V
2.5
V
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EN5367QI
PARAMETER
SYMBOL
POK Threshold
POKT
Output voltage as a fraction of
expected output voltage
POK Output low
Voltage
VPOKL
With 1mA current sink into POK
0.4
V
POK Output Hi
Voltage
VPOKH
2.5V ≤ VIN ≤ 5.5V
VIN
V
POK pin VOH
leakage current
(Note 3)
IPOK
POK high
1
µA
SYNC Pin Current
TEST CONDITIONS
SYNC Pin is <2.5V
MIN
TYP
MAX
90
<100
UNITS
%
nA
Note 3: Parameter not production tested but is guaranteed by design.
Note 4: For proper operation of the SYNC circuit, the high-level amplitude of the SYNC signal should not be above 2.5V.
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Typical Performance Curves
Efficiency vs. Output Current
100
90
90
80
80
EFFICIENCY (%)
EFFICIENCY (%)
Efficiency vs. Output Current
100
70
60
VOUT = 2.5V
50
VOUT = 1.8V
40
30
VOUT = 1.2V
20
VOUT = 1.0V
10
CONDITIONS
VIN = 3.3V
70
60
VOUT = 3.3V
50
VOUT = 2.5V
40
30
VOUT = 1.8V
20
VOUT = 1.2V
10
VOUT = 1.0V
0
0
0
1
2
3
4
OUTPUT CURRENT (A)
5
0
6
1.215
VOUT = 1.0V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2
3
4
OUTPUT CURRENT (A)
5
6
1.220
1.015
1.010
1.005
1.000
0.995
0.990
CONDITIONS
VIN = 3.3V
0.985
VOUT = 1.2V
1.210
1.205
1.200
1.195
1.190
CONDITIONS
VIN = 3.3V
1.185
1.180
0.980
0
1
2
3
4
OUTPUT CURRENT (A)
5
0
6
Output Voltage vs. Output Current
1
2
3
4
OUTPUT CURRENT (A)
5
6
Output Voltage vs. Output Current
1.820
2.520
1.815
2.515
VOUT = 1.8V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.020
1.810
1.805
1.800
1.795
1.790
CONDITIONS
VIN = 3.3V
1.785
VOUT = 2.5V
2.510
2.505
2.500
2.495
2.490
CONDITIONS
VIN = 3.3V
2.485
1.780
2.480
0
1
2
3
4
OUTPUT CURRENT (A)
5
6
0
7
07013
CONDITIONS
VIN = 5.0V
October 11, 2013
1
2
3
4
OUTPUT CURRENT (A)
5
6
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Rev D
EN5367QI
Typical Performance Curves (Continued)
Output Voltage vs. Output Current
Output Voltage vs. Output Current
1.820
1.015
1.815
VOUT = 1.0V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.020
1.010
1.005
1.000
0.995
0.990
CONDITIONS
VIN = 5.0V
0.985
1.805
1.800
1.795
1.790
1.780
0
1
2
3
4
OUTPUT CURRENT (A)
5
6
0
2
3
4
OUTPUT CURRENT (A)
5
6
3.320
2.515
3.315
VOUT = 2.5V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1
Output Voltage vs. Output Current
Output Voltage vs. Output Current
2.520
2.510
2.505
2.500
2.495
2.490
CONDITIONS
VIN = 5.0V
2.485
VOUT = 3.3V
3.310
3.305
3.300
3.295
3.290
CONDITIONS
VIN = 5.0V
3.285
3.280
2.480
0
1
2
3
4
OUTPUT CURRENT (A)
5
6
0
1
2
3
4
OUTPUT CURRENT (A)
5
6
Output Voltage vs. Input Voltage
Output Voltage vs. Input Voltage
1.020
1.820
LOAD = 0A
1.015
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
CONDITIONS
VIN = 5.0V
1.785
0.980
LOAD = 2A
1.010
LOAD = 4A
LOAD = 6A
1.005
1.000
0.995
0.990
CONDITIONS
TA = 25 C
VOUT_NOM = 1.0V
0.985
LOAD = 0A
1.815
LOAD = 2A
1.810
LOAD = 4A
LOAD = 6A
1.805
1.800
1.795
1.790
CONDITIONS
TA = 25 C
VOUT_NOM = 1.8V
1.785
1.780
0.980
2.5
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
2.5
5.5
8
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VOUT = 1.8V
1.810
October 11, 2013
3
3.5
4
4.5
INPUT VOLTAGE (V)
5
5.5
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Rev D
EN5367QI
Typical Performance Curves (Continued)
Output Voltage vs. Temperature
Output Voltage vs. Temperature
1.820
LOAD = 0.1A
1.815
LOAD = 2A
1.810
LOAD = 4A
1.805
LOAD = 6A
CONDITIONS
VIN = 3.3V
VOUT_NOM = 1.8V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.820
LOAD = 8A
1.800
1.795
1.790
1.785
LOAD = 0.1A
1.815
LOAD = 2A
1.810
LOAD = 4A
1.805
LOAD = 6A
LOAD = 8A
1.800
1.795
1.790
1.785
1.780
1.780
-40
-15
10
35
60
AMBIENT TEMPERATURE ( C)
-40
85
Output Voltage vs. Temperature
LOAD = 0.1A
1.815
LOAD = 2A
1.810
LOAD = 4A
1.805
LOAD = 6A
CONDITIONS
VIN = 5.0V
VOUT_NOM = 1.8V
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
85
1.820
LOAD = 8A
1.800
1.795
1.790
LOAD = 0.1A
1.815
LOAD = 2A
1.810
LOAD = 4A
1.805
LOAD = 6A
CONDITIONS
VIN = 5.5V
VOUT_NOM = 1.8V
LOAD = 8A
1.800
1.795
1.790
1.785
1.785
1.780
1.780
-40
10
35
60
-15
AMBIENT TEMPERATURE ( C)
85
-40
Output Current De-rating
5.500
5.000
4.500
4.000
3.500
3.000
VOUT = 1.8V
2.500
VOUT = 2.5V
-15
10
35
60
AMBIENT TEMPERATURE ( C)
85
Output Current De-rating
6.000
MAXIMUM OUTPUT CURRENT (A)
MAXIMUM OUTPUT CURRENT (A)
-15
10
35
60
AMBIENT TEMPERATURE ( C)
Output Voltage vs. Temperature
1.820
CONDITIONS
VIN = 3.3V
TJMAX = 125 C
θJA = 22 C/W
5.5x10x3mm QFN
No Air Flow
2.000
6.000
5.500
5.000
4.500
4.000
3.500
VOUT = 1.0V
3.000
VOUT = 1.8V
VOUT = 2.5V
2.500
VOUT = 3.3V
CONDITIONS
VIN = 5.0V
TJMAX = 125 C
θJA = 22 C/W
5.5x10x3mm QFN
No Air Flow
2.000
55
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
85
55
9
07013
CONDITIONS
VIN = 4.3V
VOUT_NOM = 1.8V
October 11, 2013
60
65
70
75
80
AMBIENT TEMPERATURE ( C)
85
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Rev D
EN5367QI
Typical Performance Characteristics
Output Ripple at 20MHz Bandwidth
Output Ripple at 20MHz Bandwidth
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 3.3V
VOUT = 2.5V
NO LOAD
CIN = 47µF (1206)
COUT = 47µF(1206) + 10µF(0805)
CONDITIONS
VIN = 3.3V
VOUT = 2.5V
LOAD = 6A
CIN = 47µF (1206)
COUT = 47µF(1206) + 10µF(0805)
Output Ripple at 20MHz Bandwidth
Output Ripple at 20MHz Bandwidth
VOUT
(AC Coupled)
VOUT
(AC Coupled)
CONDITIONS
VIN = 5V
VOUT = 1V
NO LOAD
CIN = 47µF (1206)
COUT = 47µF(1206) + 10µF(0805)
CONDITIONS
VIN = 5V
VOUT = 1V
LOAD = 6A
CIN = 47µF (1206)
COUT = 47µF(1206) + 10µF(0805)
Enable Power Up/Down
Enable Power Up/Down
ENABLE
ENABLE
VOUT
VOUT
POK
POK
No Load
CONDITIONS
VIN = 5.5V, VOUT = 3.3V
CIN = 47µF(1206) + 47nF(0805)
COUT = 47µF(1206), Css = 47nF
Load = 6A
CONDITIONS
VIN = 5.5V, VOUT = 3.3V
CIN = 47µF(1206) + 47nF(0805)
COUT = 47µF(1206), Css = 47nF
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Typical Performance Characteristics (Continued)
Load Transient from 0.01 to 6A
Load Transient from 0.01 to 6A
VOUT
(AC Coupled)
LOAD
VOUT
(AC Coupled)
CONDITIONS
VIN = 5.5V, VOUT = 1.0V
CIN = 47µF(1206) + 47nF (0805)
COUT = 47µF (1206)
LOAD
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CONDITIONS
VIN = 5.5V, VOUT = 3.3V
CIN = 47µF(1206) + 47nF (0805)
COUT = 47µF (1206)
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Rev D
EN5367QI
Functional Block Diagram
PG
BTMP
PVIN
UVLO
Thermal Limit
P-Drive
Current Limit
NC(SW)
VOUT
Mode
Logic
N-Drive
(-)
PWM
Comp
(+)
SYNC
PGND
Compensation
Network
PLL/Sawtooth
Generator
Regulated
Voltage
(-)
Error
Amp
(+)
ENABLE
SS
BGND
VDDB
VFB
Power
Good
Logic
POK
AVIN
Soft Start
Voltage
Reference
Regulated
Voltage
AGND
EAOUT
Figure 4: Functional Block Diagram
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EN5367QI
Functional Description
signal has to be low for at least the ENABLE Lockout Time (2.4ms) in order for the device to respond
to a falling edge on this pin. Note that the device
should not be enabled into a pre-biased output.
Synchronous Buck Converter
The EN5367QI is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor. The nominal input
voltage range is 2.5V to 5.5V. The output voltage is
programmed using an external resistor divider
network. The control loop is voltage-mode with a
type III compensation network. Much of the
compensation circuitry is internal to the device.
However, a phase lead capacitor is required along
with the output voltage feedback resistor divider to
complete the type III compensation network. The
device uses a low-noise PWM topology. Up to 6A
of continuous output current can be drawn from this
converter. The 4 MHz switching frequency allows
the use of small size input / output capacitors, and
realizes a wide loop bandwidth within a small foot
print.
Pre-Bias Operation
The EN5367QI is not designed to be turned on into
a pre-biased output voltage. Be sure the output
capacitors are not charged or the output of the
EN5367QI is not pre-biased when the EN5367QI is
first enabled.
Frequency Synchronization
The power supply has the following protection
features:
• Over-Current Protection
• Thermal Shutdown with Hysteresis.
• Under-voltage Lockout
The switching frequency of the DC/DC converter
can be phase-locked to an external clock source to
move unwanted beat frequencies out of band. To
avail this feature, the clock source should be
connected to the SYNC pin. An activity detector
recognizes the presence of an external clock signal
and automatically phase-locks the internal oscillator
to this external clock. Phase-lock will occur as long
as the input clock frequency is in the lock range
specified in the Electrical Characteristics Table.
If the SYNC function is not to be used, this pin has
to be grounded. Do not float this pin or tie it to a
static high voltage.
Additional Features:
Spread Spectrum Mode
•
•
•
The external clock frequency may be swept within
the SYNC frequency lock range at repetition rates
of up to 10 kHz in order to reduce EMI frequency
components.
Protection Features:
Frequency Synchronization (External Clock)
Programmable Soft-start
Output Enable and Power OK
Power Up-Down Sequencing
Soft-Start Operation
During power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements. ENABLE can also be tied to
AVIN and come up with it, while PVIN can be safely
ramped up and down. Alternatively, PVIN can be
brought high after AVIN is asserted, and the device
can be turned on and off by toggling the ENABLE
pin.
During Soft-start, the output voltage is ramped up
gradually upon start-up. The output rise time is
controlled by the choice of soft-start capacitor,
which is placed between the SS pin (30) and the
AGND pin (32).
Rise Time [ms]: T R ≈ (Css [nF]* 0.08) ± 25%
where rise time is in ms, and CSS is in nF. During
start-up of the converter, the reference voltage to
the error amplifier is linearly increased to its final
level by an internal current source of approximately
10uA. Typical soft-start rise time is ~3.75ms with a
soft-start capacitor of 47nF. The rise time is
measured from when VIN > VUVLOR and ENABLE pin
voltage crosses its logic high threshold, to when
VOUT reaches its programmed value.
Enable Operation
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the ENABLE pin is asserted (high)
the device will undergo a normal soft start. A logic
low will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
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POK Operation
approximately 150ºC. After a thermal shutdown
event, when the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start.
The POK signal is an open drain signal (requires a
pull up resistor to VIN or similar voltage) from the
converter indicating the output voltage is within the
specified range. The POK signal will be logic high
(VIN ) when the output voltage is above 90% of
programmed VOUT. If the output voltage goes below
this threshold, the POK signal will be a logic low.
Input Under-Voltage Lock-Out
Internal circuits ensure that the converter will not
start switching until the input voltage is above the
specified minimum voltage. Hysteresis, input deglitch and output leading edge blanking ensure high
noise immunity and prevent false UVLO triggers.
Over-Current Protection
The current limit function is achieved by sensing
the current flowing through the Power PFET. When
the sensed current exceeds the over current trip
point, both power FETs are turned off for the
remainder of the switching cycle. If the over-current
condition is removed, the over-current protection
circuit will enable normal PWM operation. If the
over-current condition persists, the soft start
capacitor will gradually discharge causing the
output voltage to fall. When the OCP fault is
removed, the output voltage will ramp back up to
the desired voltage. This circuit is designed to
provide high noise immunity.
Compensation
The EN5367QI uses a type 3 compensation
network. As noted earlier, a piece of the
compensation network is the phase lead capacitor
CA in Figure 1. This network is optimized for use
with about 50μF of output capacitance and will
provide wide loop bandwidth and excellent transient
performance for most applications. Voltage mode
operation provides high noise immunity at light
load.
In some applications modifications to the
compensation may be required. For more
information, contact Altera Power Applications
support.
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the Junction temperature exceeds
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Application Information
The EN5367QI output voltage is programmed using
a simple resistor divider network. Figure 1 shows
the resistor divider configuration.
Recommended Input Capacitors
Description
VOUT
CA
RA
MFG
47nF, 50V or 25V, 10%
X7R, 0805
(1 capacitor needed right
next to device input pins)
47µF, 10V, 20%
X5R, 1206
(1 capacitor needed in
parallel with 47nF above)
22µF, 10V, 20%
X5R, 1206
(2 capacitors needed in
parallel with 47nF above)
RCA
VFB
P/N
Murata
GRM21BR71H473KA01L
Taiyo Yuden
TMK212B7473KD-T
Murata
GRM31CR61A476ME15L
Taiyo Yuden
LMK316BJ476ML-T
Murata
GRM31CR61A226ME19L
Taiyo Yuden
LMK316BJ226ML-T
Table 1. Recommended Input Capacitors
RB
Output Capacitor Selection
The EN5367QI has been nominally optimized for
use with a 47µF/1206 output capacitor. For better
output ripple performance, use an additional
10µF/0805 capacitor. Low ESR ceramic capacitors
are required with X5R or X7R rated dielectric
formulation.
Y5V or equivalent dielectric
formulations must not be used as these lose too
much capacitance with frequency, temperature and
bias
voltage.
Refer
to
Table
2
for
recommendations.
Figure 1: VOUT Resistor Divider &
Compensation Capacitor
The feedback and compensation network values
depend on the input voltage and output voltage.
Calculate the external feedback and compensation
network values with the equations below.
RA [kΩ] = 30 x VIN [V]
*Round RA up to closest standard value
Output ripple voltage is determined by the
aggregate output capacitor impedance. Output
impedance, denoted as Z, is comprised of effective
series resistance, ESR, and effective series
inductance, ESL:
CA [pF] = 2975 / RA [kΩ]
*Round CA down to closest standard value
RB[kΩ] = (VFB x RA) / (VOUT – VFB) [V]
VFB = 0.75V nominal
*Use closest suitable value for RB [kΩ]
Z = ESR + ESL
RCA = VIN x (1.95 – 0.46 x VOUT) kΩ
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
Input Capacitor Selection
1
Z Total
The EN5367QI requires a 47μF/1206 and a
47nF/0805 input capacitor. Low-cost, low-ESR
ceramic capacitors should be used as input
capacitors for this converter. The dielectric must be
X5R or X7R rated. Y5V or equivalent dielectric
formulations must not be used as these lose too
much capacitance with frequency, temperature and
bias voltage.
1
1
1
+
+ ... +
Z1 Z 2
Zn
Typical Ripple Voltages
Output Capacitor
Configuration
The first capacitor next to the PVIN and PGND pins
must be a 47nF, 0805, X7R capacitor. Behind this
first capacitor there can be either a single 47µF
capacitor or 2x22µF capacitors. Refer to Table 1 for
recommendations.
Typical Output Ripple (mVp-p)
(as measured on EN5367QI
Evaluation Board)*
1 x 47µF
47µF + 10µF
17
9
* Note: 20 MHz BW limit
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Power-Up Sequencing
Recommended Output Capacitors
Description
47µF, 6.3V, 20%
X5R, 1206
(1 capacitor needed)
10µF, 10V, 10%
X5R, 1206
(Optional 1 capacitor in
parallel with 47µF above)
MFG
During power-up, ENABLE should not be asserted
before PVIN, and PVIN should not be asserted
before AVIN. Tying all three pins together meets
these requirements.
P/N
Murata
GRM31CR60J476ME19L
Taiyo Yuden
JMK316BJ476ML-T
Murata
GRM31CR71A106KA01L
Taiyo Yuden
LMK316BJ226ML-T
Technical Suport
Contact Altera Power Applications
regarding
the
use
of
this
(www.altera.com/mysupport).
Table 2. Recommended Output Capacitors
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Thermal Considerations
PIN = POUT / η
Thermal considerations are important power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for.
PIN ≈ 19.8W / 0.88 ≈ 22.5W
The power dissipation (PD ) is the power loss in the
system and can be calculated by subtracting the
output power from the input power.
The Altera Enpirion EN5367QI DC-DC converter is
packaged in a 5.5x10x3mm 54-pin QFN package.
The QFN package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The recommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
150°C.
The following example and calculations illustrate
the thermal performance of the EN5367QI.
PD = PIN – POUT
≈ 22.5W – 19.8W ≈ 2.7W
With the power dissipation known, the temperature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how much the temperature will rise in the device for
every watt of power dissipation. The EN5367QI has
a θJA value of 22 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 2.7W x 22°C/W = 59.4°C ≈ 60°C
VIN = 5V
The junction temperature (T J ) of the device is
approximately the ambient temperature (T A) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
VOUT = 3.3V
T J = T A + ΔT
IOUT = 6A
T J ≈ 25°C + 60°C ≈ 85°C
First calculate the output power.
The maximum operating junction temperature
(T JMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
maximum ambient temperature (T AMAX) allowed can
be calculated.
Example:
POUT = 3.3V x 6A = 19.8W
Next, determine the input power based on the
efficiency (η) shown in Figure 6.
T AMAX = T JMAX – PD x θJA
Efficiency vs. Output Current
≈ 125°C – 60°C ≈ 65°C
The maximum ambient temperature the device can
reach is 65°C given the input and output conditions.
Note that the efficiency will be slightly lower at
higher temperatures and this calculation is an
estimate.
100
90
88%
EFFICIENCY (%)
80
70
60
50
40
30
20
VOUT = 3.3V
10
CONDITIONS
VIN = 5.0V
0
0
1
2
3
4
OUTPUT CURRENT (A)
5
6
Figure 6: Efficiency vs. Output Current
For VIN = 5V, VOUT = 3.3V at 6A, η ≈ 88%
η = POUT / PIN = 88% = 0.88
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Engineering Schematic
Figure 7: Engineering Schematic with Engineering Notes
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Layout Recommendation
Recommendation 4: The thermal pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vias must have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output current loops.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. It should be
connected to the input voltage at a quiet point. In
Figure 8 this connection is made at the input
capacitor.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure 8.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines underneath the converter package on
other layers.
Recommendation 8: The VOUT sense point should
be just after the last output filter capacitor. Keep the
sense trace short in order to avoid noise coupling
into the node.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the VFB pin (Refer to Figure 8). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB directly to the AGND pin
instead of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera Enpirion provides schematic
and layout reviews for all customer designs. Please
contact local Sales Representatives for references
to Altera Power Applications support.
Figure 8: Top Layout with Critical Components Only
(Top View). See Figure 7 for corresponding schematic.
This layout only shows the critical components and
top layer traces for minimum footprint in singlesupply mode with ENABLE tied to AVIN. Alternate
circuit configurations & other low-power pins need
to be connected and routed according to customer
application. Please see the Gerber files at
www.altera.com/enpirion for details on all layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN5367QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respective nodes. The +V and
GND traces between the capacitors and the
EN5367QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitors.
Recommendation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation between input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the converter
and the input/output capacitors.
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Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the lead-frame
cantilevers be exposed at the point where wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package, as shown in Figure 9.
Only the thermal pad and the perimeter pads are to be mechanically or electrically connected to the PC board.
The PCB top layer under the EN5367QI should be clear of any metal (copper pours, traces, or vias) except for
the thermal pad. The “shaded-out” area in Figure 9 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by soldermask.
The solder stencil aperture should be smaller than the PCB ground pad. This will prevent excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult EN5367QI
QFN Package Soldering Guidelines for more details and recommendations.
Figure 9: Lead-Frame exposed metal (Bottom View)
Shaded area highlights exposed metal that is not to be mechanically or electrically connected to the PCB.
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Recommended PCB Footprint
Figure 10: EN5367QI PCB Footprint (Top View)
The solder stencil aperture for the thermal pad is shown in blue and is based on Enpirion power product manufacturing
specifications.
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Package and Mechanical
Figure 11: EN5367QI Package Dimensions (Bottom View)
Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
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Contact Information
Altera Corporation
101 Innovation Drive
San Jose, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other
countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's
standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or
liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders
for products or services.
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