Qimonda HYB18T512400BF-3.7 512-mbit double-data-rate-two sdram Datasheet

January 2007
HYB18T512400BF
HYB18T512800BF
HYB18T512160BF
512-Mbit Double-Data-Rate-Two SDRAM
DDR2 SDRAM
RoHS Compliant Products
Internet Data Sheet
R ev . 1 . 05
Internet Data Sheet
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
HYB18T512400BF, HYB18T512800BF
Revision History: 2007-01, Rev. 1.05
Page
Subjects (major changes since last revision)
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Qimonda update
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Adapted internet edition
Previous Version: 2005-11, Rev. 1.04
32
added AL 5 and 6 and Rtt 50 ohms
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-YBYM-WG0Z
2
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
1
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate-Two SDRAM product family and describes its
main characteristics.
1.1
Features
The 512-Mbit Double-Data-Rate-Two SDRAM offers the following key features:
•
•
•
•
•
•
•
•
•
•
•
1.8 V ± 0.1 V Power Supply
1.8 V ± 0.1 V (SSTL_18) compatible I/O
DRAM organizations with 4, 8 and 16 data
in/outputs
Double Data Rate architecture: two data transfers
per clock cycle four internal banks for concurrent
operation
Programmable CAS Latency: 3, 4, 5 and 6
Programmable Burst Length: 4 and 8
Differential clock inputs (CK and CK)
Bi-directional, differential data strobes (DQS and
DQS) are transmitted / received with data. Edge
aligned with read data and center-aligned with write
data.
DLL aligns DQ and DQS transitions with clock
DQS can be disabled for single-ended data strobe
operation
Commands entered on each positive clock edge,
data and data mask are referenced to both edges of
DQS
Data masks (DM) for write data
•
•
•
•
•
•
•
•
•
•
•
•
•
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver impedance adjustment (OCD) and
On-Die-Termination (ODT) for better signal quality.
Auto-Precharge operation for read and write bursts
Auto-Refresh, Self-Refresh and power saving
Power-Down modes
Average Refresh Period 7.8 µs at a TCASE lower
than 85 °C, 3.9 µs between 85 °C and 95 °C
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2
settings
DCC enabling via EMRS2 setting
Full and reduced Strength Data-Output Drivers
1kB page size for ×4 & ×8, 2kB page size for ×16
Packages: P-TFBGA-60 for ×4 & ×8 components PTFBGA-84 for ×16 components
RoHS Compliant Products1)
All Speed grades faster than DDR400 comply with
DDR400 timing specifications when run at a clock
rate of 200 MHz.
A list of the performance tables for the various speeds can be found below
•
•
•
•
Table 1 “Performance for DDR2–800” on Page 4
Table 2 “Performance for DDR2–667” on Page 4
Table 3 “Performance for DDR2–533C” on Page 4
Table 4 “Performance for DDR2–400B” on Page 5
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic
equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January
2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and
polybrominated biphenyl ethers.
Internet Data Sheet
3
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 1
Performance for DDR2–800
Product Type Speed Code
–2.5F
–2.5
Unit
Speed Grade
DDR2–800D 5–5–5
DDR2–800E 6–6–6
—
@CL6 fCK6 400
400
MHz
@CL5 fCK5 400
333
MHz
@CL4 fCK4 266
266
MHz
@CL3 fCK3 200
200
MHz
12.5
15
ns
12.5
15
ns
45
45
ns
57.5
60
ns
–3S
Unit
max. Clock Frequency
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
Table 2
tRCD
tRP
tRAS
tRC
Performance for DDR2–667
Product Type Speed Code
–3
Speed Grade
DDR2–667C 4–4–4
max. Clock Frequency
DDR2–667D 5–5–5
—
@CL5 fCK5 333
333
MHz
@CL4 fCK4 333
266
MHz
@CL3 fCK3 200
200
MHz
12
15
ns
12
15
ns
45
45
ns
57
60
ns
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
Table 3
tRCD
tRP
tRAS
tRC
Performance for DDR2–533C
Product Type Speed Code
–3.7
Unit
Speed Grade
DDR2–533C 4–4–4
—
266
MHz
266
MHz
200
MHz
15
ns
15
ns
45
ns
60
ns
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
Internet Data Sheet
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
4
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 4
Performance for DDR2–400B
Product Type Speed Code
–5
Units
Speed Grade
DDR2–400B 3–3–3
—
200
MHz
200
MHz
200
MHz
15
ns
15
ns
40
ns
55
ns
max. Clock Frequency
@CL5
@CL4
@CL3
min. RAS-CAS-Delay
min. Row Precharge Time
min. Row Active Time
min. Row Cycle Time
1.2
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
Description
Inputs are latched at the cross point of differential
clocks (CK rising and CK falling). All I/Os are
synchronized with a single ended DQS or differential
DQS-DQS pair in a source synchronous fashion.
The 512-Mb DDR2 DRAM is a high-speed DoubleData-Rate-Two CMOS DRAM device containing
536,870,912 bits and internally configured as a quadbank DRAM. The 512-Mb device is organized as either
32 Mbit × 4 I/O ×4 banks, 16 Mbit ×8 I/O × 4 banks or
8 Mbit ×16 I/O ×4 banks chip. These devices achieve
high speed transfer rates starting at 400 Mb/sec/pin for
general applications. See Table 1 to Table 4 for
performance figures.
A 16-bit address bus for ×4 and ×8 organized
components and a 15-bit address bus for ×16
components is used to convey row, column and bank
address information in a RAS-CAS multiplexing style.
The DDR2 device operates with a 1.8 V ± 0.1 V power
supply. An Auto-Refresh and Self-Refresh mode is
provided along with various power-saving power-down
modes.
The device is designed to comply with all DDR2 DRAM
key features:
1.
2.
3.
4.
5.
Posted CAS with additive latency,
Write latency = read latency - 1,
Normal and weak strength data-output driver,
Off-Chip Driver (OCD) impedance adjustment
On-Die Termination (ODT) function.
The functionality described and the timing
specifications included in this data sheet are for the
DLL Enabled mode of operation.
The DDR2 SDRAM is available in PG-TFBGA
package.
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Internet Data Sheet
5
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 5
Ordering Information for RoHS compliant products
Product Type
Org. Speed
CAS-RCD-RP Clock
Latencies1)2)3) (MHz)
CAS-RCD-RP Clock Package
Latencies
(MHz)
HYB18T512160BF-25F ×16
DDR2-800D 5-5-5
400
4-4-4
266
PG-TFBGA-84-8
HYB18T512800BF-25F ×8
DDR2-800D 5-5-5
400
4-4-4
266
PG-TFBGA-60-24
HYB18T512400BF-25F ×4
DDR2-800D 5-5-5
400
4-4-4
266
PG-TFBGA-60-24
HYB18T512160BF-2.5
×16
DDR2-800E 6-6-6
400
5-5-5
333
PG-TFBGA-84-8
HYB18T512800BF-2.5
×8
DDR2-800E 6-6-6
400
5-5-5
333
PG-TFBGA-60-24
HYB18T512400BF-2.5
×4
DDR2-800E 6-6-6
400
5-5-5
333
PG-TFBGA-60-24
HYB18T512160BF-3
×16
DDR2-667C 4-4-4
333
3-3-3
200
PG-TFBGA-84-8
HYB18T512400BF-3
×4
DDR2-667C 4-4-4
333
3-3-3
200
PG-TFBGA-60-24
HYB18T512800BF-3
×8
DDR2-667C 4-4-4
333
3-3-3
200
PG-TFBGA-60-24
HYB18T512160BF-3S
×16
DDR2-667D 5-5-5
333
4-4-4
266
PG-TFBGA-84-8
HYB18T512400BF-3S
×4
DDR2-667D 5-5-5
333
4-4-4
266
PG-TFBGA-60-24
HYB18T512800BF-3S
×8
DDR2-667D 5-5-5
333
4-4-4
266
PG-TFBGA-60-24
HYB18T512160BF-3.7
×16
DDR2-533C 4-4-4
266
3-3-3
200
PG-TFBGA-84-8
HYB18T512400BF-3.7
×4
DDR2-533C 4-4-4
266
3-3-3
200
PG-TFBGA-60-24
HYB18T512800BF-3.7
×8
DDR2-533C 4-4-4
266
3-3-3
200
PG-TFBGA-60-24
HYB18T512160BF-5
×16
DDR2-400B 3-3-3
200
—
—
PG-TFBGA-84-8
HYB18T512400BF-5
×4
DDR2-400B 3-3-3
200
—
—
PG-TFBGA-60-24
HYB18T512800BF-5
×8
DDR2-400B 3-3-3
200
—
—
PG-TFBGA-60-24
1) CAS: Column Address Strobe
2) RCD: Row Column Delay
3) RP: Row Precharge
Note: For product nomenclature see Chapter 9 of this data sheet
Internet Data Sheet
6
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of a DDR2 SDRAM is listed by function in Table 6. The abbreviations used in the Pin# and
Buffer Type columns are explained in Table 7 and Table 8 respectively. The pin numbering for the FBGA package
is depicted in Figure 1 for ×4, Figure 2 for ×8 and Figure 3 for ×16.
Table 6
Ball#/Pin#
Pin Configuration of DDR2 SDRAM
Name
Pin
Type
Buffer
Type
Function
Clock Signals ×4/×8 organizations
E8
CK
I
SSTL
Clock Signal CK, Complementary Clock Signal CK
F8
CK
I
SSTL
F2
CKE
I
SSTL
Clock Enable
Clock Signals ×16 organization
J8
CK
I
SSTL
Clock Signal CK, Complementary Clock Signal CK
K8
CK
I
SSTL
Note: See functional description in x4/x8 organization
K2
CKE
I
SSTL
Clock Enable
Note: See functional description in x4/x8 organization
Control Signals ×4/×8 organizations
F7
RAS
I
SSTL
G7
CAS
I
SSTL
F3
WE
I
SSTL
G8
CS
I
SSTL
Chip Select
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Row Address Strobe (RAS), Column Address Strobe (CAS),
Write Enable (WE)
Control Signals ×16 organization
K7
RAS
I
SSTL
L7
CAS
I
SSTL
K3
WE
I
SSTL
L8
CS
I
SSTL
Chip Select
Address Signals ×4/×8 organizations
G2
BA0
I
SSTL
G3
BA1
I
SSTL
Internet Data Sheet
Bank Address Bus 1:0
7
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 6
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
H8
A0
I
SSTL
Address Signal 12:0, Address Signal 10/Autoprecharge
H3
A1
I
SSTL
H7
A2
I
SSTL
J2
A3
I
SSTL
J8
A4
I
SSTL
J3
A5
I
SSTL
J7
A6
I
SSTL
K2
A7
I
SSTL
K8
A8
I
SSTL
K3
A9
I
SSTL
H2
A10
I
SSTL
AP
I
SSTL
K7
A11
I
SSTL
L2
A12
I
SSTL
L8
A13
I
SSTL
NC
–
–
Address Signal 13
Note: x4/x8 512 Mbit components
Note: and x16 512 Mbit components
Address Signals ×16 organization
L2
BA0
I
SSTL
L3
BA1
I
SSTL
L1
NC
–
–
M8
A0
I
SSTL
M3
A1
I
SSTL
M7
A2
I
SSTL
N2
A3
I
SSTL
N8
A4
I
SSTL
N3
A5
I
SSTL
N7
A6
I
SSTL
P2
A7
I
SSTL
P8
A8
I
SSTL
P3
A9
I
SSTL
M2
A10
I
SSTL
AP
I
SSTL
P7
A11
I
SSTL
R2
A12
I
SSTL
Bank Address Bus 1:0
Address Signal 12:0, Address Signal 10/Autoprecharge
Data Signals ×4 organizations
C8
DQ0
I/O
SSTL
C2
DQ1
I/O
SSTL
D7
DQ2
I/O
SSTL
D3
DQ3
I/O
SSTL
Internet Data Sheet
Data Signal 3:0
8
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 6
Ball#/Pin#
Pin Configuration of DDR2 SDRAM
Name
Pin
Type
Buffer
Type
Function
Data Signal 7:0
Data Signals ×8 organization
C8
DQ0
I/O
SSTL
C2
DQ1
I/O
SSTL
D7
DQ2
I/O
SSTL
D3
DQ3
I/O
SSTL
D1
DQ4
I/O
SSTL
D9
DQ5
I/O
SSTL
B1
DQ6
I/O
SSTL
B9
DQ7
I/O
SSTL
Data Signals ×16 organization
G8
DQ0
I/O
SSTL
G2
DQ1
I/O
SSTL
H7
DQ2
I/O
SSTL
H3
DQ3
I/O
SSTL
H1
DQ4
I/O
SSTL
H9
DQ5
I/O
SSTL
F1
DQ6
I/O
SSTL
F9
DQ7
I/O
SSTL
C8
DQ8
I/O
SSTL
C2
DQ9
I/O
SSTL
D7
DQ10
I/O
SSTL
D3
DQ11
I/O
SSTL
D1
DQ12
I/O
SSTL
D9
DQ13
I/O
SSTL
B1
DQ14
I/O
SSTL
B9
DQ15
I/O
SSTL
Data Signal 15:0
Data Strobe ×4/×8 organisations
B7
DQS
I/O
SSTL
A8
DQS
I/O
SSTL
Data Strobe
Data Strobe ×8 organisations
B3
RDQS
O
SSTL
A2
RDQS
O
SSTL
Read Data Strobe
Data Strobe ×16 organization
B7
UDQS
I/O
SSTL
A8
UDQS
I/O
SSTL
F7
LDQS
I/O
SSTL
E8
LDQS
I/O
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
Data Mask ×4/×8 organizations
B3
DM
I
SSTL
Data Mask
Data Mask ×16 organization
Internet Data Sheet
9
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 6
Pin Configuration of DDR2 SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
B3
UDM
I
SSTL
Data Mask Upper/Lower Byte
F3
LDM
I
SSTL
Power Supplies ×4/×8/×16 organizations
A9,C1,C3,C7,
C9
VDDQ
PWR
–
I/O Driver Power Supply
A1
VDD
PWR
–
Power Supply
A7,B2,B8,D2,
D8
VSSQ
PWR
–
I/O Driver Power Supply
A3,E3
VSS
PWR
–
Power Supply
Power Supplies ×4/×8 organizations
E2
VREF
AI
–
I/O Reference Voltage
E1
VDDL
PWR
–
Power Supply
E9,H9,L1
VDD
PWR
–
Power Supply
E7
VSSDL
PWR
–
Power Supply
J1,K9
VSS
PWR
–
Power Supply
Power Supplies ×16 organization
J2
VREF
AI
–
I/O Reference Voltage
E9, G1, G3,
G7, G9
VDDQ
PWR
–
I/O Driver Power Supply
J1
VDDL
PWR
–
Power Supply
E1, J9, M9, R1 VDD
PWR
–
Power Supply
E7, F2, F8, H2, VSSQ
H8
PWR
–
I/O Driver Power Supply
J7
VSSDL
PWR
–
Power Supply
J3,N1,P9
VSS
PWR
–
Power Supply
–
Not Connected
–
Not Connected
–
Not Connected
SSTL
On-Die Termination Control
SSTL
On-Die Termination Control
Not Connected ×4 organizations
A2, B1, B9,
D1, D9,
G1, L3,L7, L8
NC
NC
Not Connected ×8 organization
G1, L3,L7, L8
NC
NC
Not Connected ×16 organization
A2, E2, L1, R3, NC
R7, R8
NC
Other Pins ×4/×8 organizations
F9
ODT
I
Other Pins ×16 organization
K9
ODT
Internet Data Sheet
I
10
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
Table 8
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
Internet Data Sheet
11
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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Notes
2. Ball position L8 is A13 for 512-Mbit and is Not
Connected on 256-Mbit
1. VDDL and VSSDL are power and ground for the
DLL.They are isolated on the device from VDD,
VDDQ, VSS, and VSSQ
Internet Data Sheet
12
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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Pin Configuration for ×8 components, PG-TFBGA-60-24
4. VDDL and VSSDL are power and ground for the DLL.
VDDL is connected to VDD on the device. VDD, VDDQ,
VSSDL, VSS, and VSSQ are isolated on the device.
5. Ball position L8 is A13 for 512-Mbit and is Not
Connected on 256-Mbit.
Notes
1. RDQS / RDQS are enabled by EMRS(1) command.
2. If RDQS / RDQS is enabled, the DM function is
disabled
3. When enabled, RDQS & RDQS are used as strobe
signals during reads.
Internet Data Sheet
13
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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!
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2
.#
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633
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6331
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633
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Figure 3
Pin Configuration for ×16 components, PG-TFBGA-84-8
Notes
2. LDM is the data mask signal for DQ[7:0], UDM is the
data mask signal for DQ[15:8]
3. VDDL and VSSDL are power and ground for the DLL.
VDDL is connected to VDD on the device. VDD, VDDQ,
VSSDL, VSS, and VSSQ are isolated on the device.
1. UDQS/UDQS is data strobe for DQ[15:8],
LDQS/LDQS is data strobe for DQ[7:0]
Internet Data Sheet
14
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
2.2
512 Mbit DDR2 Addressing
Table 9
512-Mbit DDR2 Addressing
Configuration
128Mb x 41)
Bank Address
Number of Banks
64Mb x 8
32Mb x 16
Note
BA[1:0]
BA[1:0]
BA[1:0]
—
4
4
4
—
Auto-Precharge
A10 / AP
A10 / AP
A10 / AP
—
Row Address
A[13:0]
A[13:0]
A[12:0]
—
Column Address
A11, A[9:0]
A[9:0]
A[9:0]
—
Number of Column
Address Bits
11
10
10
2)
Number of I/Os
4
8
16
—
Page Size [Bytes]
1024 (1K)
1024 (1K)
2048(2K)
3)
1) Refered to as ’org’
2) Refered to as ’colbits’
3) PageSize = 2colbits × org/8 [Bytes]
Internet Data Sheet
15
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
3
Functional Description
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W
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Table 10
Mode Register Definition (BA[2:0] = 000B)
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B
BA2, Bank Address
BA1
15
Bank Address [1]
0B
BA1, Bank Address
BA0
14
Bank Address [0]
0B
BA0, Bank Address
A13
13
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
PD
12
w
WR
[11:9] w
A13, Address bit 13
Active Power-Down Mode Select
0B
PD, Fast exit
1B
PD, Slow exit
Write Recovery2)
Note: All other bit combinations are illegal.
001B
010B
011B
100B
101B
WR, 2
WR, 3
WR, 4
WR, 5
WR, 6
DLL
8
w
DLL Reset
0B
DLL, No
1B
DLL, Yes
TM
7
w
Test Mode
0B
TM, Normal Mode
1B
TM, Vendor specific test mode
CL
[6:4]
w
CAS Latency
Note: All other bit combinations are illegal.
010B
011B
100B
101B
110B
Internet Data Sheet
CL, 2
CL, 3
CL, 4
CL, 5
CL, 6
16
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 10
Mode Register Definition (BA[2:0] = 000B)
Field
Bits
Type1)
Description
BT
3
w
Burst Type
0B
BT, Sequential
1B
BT, Interleaved
BL
[2:0]
w
Burst Length
Note: All other bit combinations are illegal.
010B BL, 4
011B BL, 8
1) w = write only register bits
2) Number of clock cycles for write recovery during auto-precharge. WR in clock cycles is calculated by dividing tWR (in ns) by
tCK (in ns) and rounding up to the next integer: WR [cycles] ≥ tWR (ns) / tCK (ns). The mode register must be programmed to
fulfill the minimum requirement for the analogue tWR timing WRMIN is determined by tCK.MAX and WRMAX is determined by
tCK.MIN.
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W
W
W
W
W
W
REG ADDR
W
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Table 11
Extended Mode Register Definition (BA[2:0] = 001B)
Field
Bits
Type1)
Description
BA2
16
reg. addr.
Bank Address [2]
Note: BA2 not available on 256 Mbit and 512 Mbit components
0B
BA2, Bank Address
BA1
15
Bank Address [1]
0B
BA1, Bank Address
BA0
14
Bank Address [0]
0B
BA0, Bank Address
Internet Data Sheet
17
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 11
Extended Mode Register Definition (BA[2:0] = 001B)
Field
Bits
Type1)
Description
A13
13
w
Address Bus[13]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A13, Address bit 13
Qoff
12
Output Disable
0B
QOff, Output buffers enabled
1B
QOff, Output buffers disabled
RDQS
11
Read Data Strobe Output (RDQS, RDQS)
0B
RDQS, Disable
1B
RDQS, Enable
DQS
10
Complement Data Strobe (DQS Output)
0B
DQS, Enable
1B
DQS, Disable
OCD
[9:7]
Program
Off-Chip Driver Calibration Program
000B OCD, OCD calibration mode exit, maintain setting
001B OCD, Drive (1)
010B OCD, Drive (0)
100B OCD, Adjust mode
111B OCD, OCD calibration default
AL
Additive Latency
[5:3]
Note: All other bit combinations are illegal.
000B
001B
010B
011B
100B
101B
AL, 0
AL, 1
AL, 2
AL, 3
AL, 4
AL, 5
RTT
2,6
Nominal Termination Resistance of ODT
00B RTT, ∞ (ODT disabled)
01B RTT, 75 Ohm
10B RTT, 150 Ohm
11B RTT, 50 Ohm2)
DIC
1
Off-chip Driver Impedance Control
0B
DIC, Full (Driver Size = 100%)
1B
DIC, Reduced
DLL
0
DLL Enable
0B
DLL, Enable
1B
DLL, Disable
1) w = write only register bits
2) optional for DDR2-400/533 & 667
Internet Data Sheet
18
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
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Table 12
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EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B)
Field
Bits
Type1)
Description
BA2
16
w
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
0B
BA2, Bank Address
BA
[15:14] w
Bank Adress[15:14]
00B BA, MRS
01B BA, EMRS(1)
10B BA, EMRS(2)
11B BA, EMRS(3): Reserved
A
[13:8]
Address Bus[13:8]
w
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A[13:8], Address bits
A
7
w
Address Bus[7], adapted self refresh rate for TCase > 85°C
0B
A7, disable
1B
A7, enable 2)
A
[6:4]
w
Address Bus[6:4]
0B
A[6:4], Address bits
A
3
w
Address Bus[3], Duty Cycle Correction (DCC)
0B
A[3], DCC disabled
1B
A[3], DCC enabled
Partial Self Refresh for 4 banks
A
[2:0]
w
Address Bus[2:0], Partial Array Self Refresh for 4 Banks3)
000B PASR0, Full Array
001B PASR1, Half Array (BA[1:0]=00, 01)
010B PASR2, Quarter Array (BA[1:0]=00)
011B PASR3, Not defined
100B PASR4, 3/4 array (BA[1:0]=01, 10, 11)
101B PASR5, Half array (BA[1:0]=10, 11)
110B PASR6, Quarter array (BA[1:0]=11)
111B PASR7, Not defined
1) w = write only
2) When DRAM is operated at 85°C ≤ TCase ≤ 95°C the extended self refresh rate must be enabled by setting bit A7 to "1"
before the self refresh mode can be entered.
3) If PASR (Partial Array Self Refresh) is enabled, data located in areas of the array beyond the specified location will be lost
if self refresh is entered. Data integrity will be maintained if tREF conditions are met and no Self Refresh command is issued
Internet Data Sheet
19
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
"! "! "!
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REG ADDR
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Table 13
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B)
Field
Bits
Type1)
Description
BA2
16
reg.addr
Bank Address[2]
Note: BA2 is not available on 256Mbit and 512Mbit components
0B
BA2, Bank Address
BA1
15
Bank Adress[1]
1B
BA1, Bank Address
BA0
14
Bank Adress[0]
1B
BA0, Bank Address
A
[13:0] w
Address Bus[13:0]
Note: A13 is not available for 256 Mbit and x16 512 Mbit configuration
0B
A[13:0], Address bits
1) w = write only
Internet Data Sheet
20
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
ODT Truth Tables
organisations (×4, ×8 and ×16). To activate termination
of any of these pins, the ODT function has to be
enabled in the EMRS(1) by address bits A6 and A2.
The ODT Truth Table shows which of the input pins are
terminated depending on the state of address bit A10
and A11 in the EMRS(1) for all three device
Table 14
ODT Truth Table
Input Pin
EMRS(1)
Address Bit A10
EMRS(1)
Address Bit A11
x4 components
DQ[3:0]
X
DQS
X
DQS
0
DM
X
X
x8 components
DQ[7:0]
X
DQS
X
DQS
0
X
RDQS
X
1
RDQS
0
1
DM
X
0
x16 components
DQ[7:0]
X
DQ[15:8]
X
LDQS
X
LDQS
0
UDQS
X
UDQS
0
LDM
X
UDM
X
X
X
Note: X = don’t care; 0 = bit set to low; 1 = bit set to high
Internet Data Sheet
21
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 15
Burst Length and Sequence
Burst Length
Starting Address
(A2 A1 A0)
Sequential Addressing
(decimal)
4
x00
0, 1, 2, 3
0, 1, 2, 3
x01
1, 2, 3, 0
1, 0, 3, 2
x10
2, 3, 0, 1
2, 3, 0, 1
x11
3, 0, 1, 2
3, 2, 1, 0
000
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
001
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
010
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
011
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
8
100
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
101
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
110
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
111
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
KByte; Page Length = 1024
32Mb x 16 organization (CA[9:0]); Page Size = 2
KByte; Page Length = 1024
2. Order of burst access for sequential addressing is
“nibble-based” and therefore different from SDR or
DDR components
Notes
1. Page Size and Length is a function of I/O
organization:
128Mb x 4 organization (CA[9:0], CA11); Page Size
= 1 KByte; Page Length = 2048
64Mb x 8 organization (CA[9:0]); Page Size = 1
Internet Data Sheet
Interleave Addressing
(decimal)
22
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
4
Truth Tables
Table 16
Command Truth Table
Function
CKE
Previous
Cycle
CS RAS CAS WE BA0 A[13:11] A10 A[9:0]
BA1
Current
Cycle
Note1)2)3)
4)5)
(Extended) Mode
Register Set
H
H
L
L
L
L
BA
OP Code
Auto-Refresh
H
H
L
L
L
H
X
X
X
X
—
Self-Refresh Entry
H
L
L
L
L
H
X
X
X
X
6)
Self-Refresh Exit
L
H
H
X
X
X
X
X
X
X
7)
L
H
H
H
Single Bank Precharge H
H
L
L
H
L
BA
X
L
X
—
Precharge all Banks
H
H
L
L
H
L
X
X
H
X
—
Bank Activate
H
H
L
L
H
H
BA
Row Address
Write
H
H
L
H
L
L
BA
Column
L
Column
Write with AutoPrecharge
H
H
L
H
L
L
BA
Column
H
Column —
Read
H
H
L
H
L
H
BA
Column
L
Column —
Read with AutoPrecharge
H
H
L
H
L
H
BA
Column
H
Column —
No Operation
H
X
L
H
H
H
X
X
X
X
Device Deselect
H
X
H
X
X
X
X
X
X
X
Power Down Entry
H
L
H
X
X
X
X
X
X
X
9)
L
H
H
H
Power Down Exit
L
H
H
X
X
X
X
X
X
X
—
L
H
H
H
—
8)
—
1) The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
2) “X” means “H or L (but a defined logic level)”.
3) Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
4) All DDR2 SDRAM commands are defined by states of CS, WE, RAS, CAS, and CKE at the rising edge of the clock.
5) Bank addresses BA[1:0] determine which bank is to be operated upon. For (E)MRS BA[1:0] selects an (Extended) Mode
Register.
6) VREF must be maintained during Self Refresh operation.
7) Self Refresh Exit is asynchronous.
8) Burst reads or writes at BL = 4 cannot be terminated.
9) The Power Down Mode does not perform any refresh operations.
Internet Data Sheet
23
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 17
Clock Enable (CKE) Truth Table for Synchronous Transitions
Current State1) CKE
Previous Cycle6) Current Cycle
(N)
(N-1)
Power-Down
Command (N)2)3)
Action (N)
RAS, CAS, WE, CS
Note4)5)
7)8)
L
L
X
L
H
DESELECT or NOP Power-Down Exit
9)10)11)
L
L
X
12)
L
H
DESELECT or NOP Self Refresh Exit
13)14)
Bank(s)
Active
H
L
DESELECT or NOP Active Power-Down Entry
15)
All Banks Idle
H
L
DESELECT or NOP Precharge Power-Down
Entry
—
H
L
AUTOREFRESH
16)
Any State other H
than
listed above
H
Refer to the Command Truth Table
Self Refresh
Maintain Power-Down
Maintain Self Refresh
Self Refresh Entry
17)
1)
2)
3)
4)
5)
Current state is the state of the DDR2 SDRAM immediately prior to clock edge N.
Command (N) is the command registered at clock edge N, and Action (N) is a result of Command (N)
The state of ODT does not affect the states described in this table. The ODT function is not available during Self Refresh.
CKE must be maintained HIGH while the device is in OCD calibration mode.
Operation that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must
be powered down and then restarted through the specified initialization sequence before normal operation can continue.
6) CKE (N) is the logic state of CKE at clock edge N; CKE (N-1) was the state of CKE at the previous clock edge.
7) The Power-Down Mode does not perform any refresh operations. The duration of Power-Down Mode is therefor limited by
the refresh requirements
8) “X” means “don’t care (including floating around VREF)” in Self Refresh and Power Down. However ODT must be driven
HIGH or LOW in Power Down if the ODT function is enabled (Bit A2 or A6 set to “1” in EMRS(1)).
9) All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.
10) Valid commands for Power-Down Entry and Exit are NOP and DESELECT only.
11) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid
input level the entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not
transition from its valid level during the time period of tIS + 2×tCKE + tIH.
12) VREF must be maintained during Self Refresh operation.
13) On Self Refresh Exit DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR
period. Read commands may be issued only after tXSRD (200 clocks) is satisfied.
14) Valid commands for Self Refresh Exit are NOP and DESELCT only.
15) Power-Down and Self Refresh can not be entered while Read or Write operations, (Extended) mode Register operations,
Precharge or Refresh operations are in progress.
16) Self Refresh mode can only be entered from the All Banks Idle state.
17) Must be a legal command as defined in the Command Truth Table.
Table 18
Data Mask (DM) Truth Table
Name (Function)
DM
DQs
Note
Write Enable
L
Valid
1)
Write Inhibit
H
X
—
1) Used to mask write data; provided coincident with the corresponding data.
Internet Data Sheet
24
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
5
Electrical Characteristics
5.1
Absolute Maximum Ratings
Table 19
Absolute Maximum Ratings
Symbol
Parameter
Rating
Unit
Note
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Voltage on VDD pin relative to VSS
–1.0 to +2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5 to +2.3
V
—
Voltage on VDDL pin relative to VSS
–0.5 to +2.3
V
—
Voltage on any pin relative to VSS
–0.5 to +2.3
V
—
°C
2)
Storage Temperature
–55 to +100
1) When VDD and VDDQ and VDDL are less than 500mV; Vref may be equal to or less than 300mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses above the max. values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device
reliability. Maximum ratings are absolute ratings; exceeding only one of these values maycause
irreversible damage to the integrated circuit.
Table 20
DRAM Component Operating Temperature Range
Symbol
Parameter
TOPER
Operating Temperature
Rating
0 to 95
Unit
Note
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation,
the DRAM case temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be
enabled by setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6
by approximately 50%
Internet Data Sheet
25
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
5.2
DC Characteristics
Table 21
Recommended DC Operating Conditions (SSTL_18)
Symbol
Parameter
Rating
Min.
Typ.
Max.
VDD
VDDDL
VDDQ
VREF
VTT
Supply Voltage
1.7
1.8
Supply Voltage for DLL
1.7
Supply Voltage for Output
1.7
1)
2)
3)
4)
Input Reference Voltage
0.49 × VDDQ
Unit
Note
1.9
V
1)
1.8
1.9
V
—
1.8
1.9
V
—
V
2)3)
0.5 × VDDQ
0.51 × VDDQ
4)
Termination Voltage
VREF – 0.04
VREF
VREF + 0.04
V
VDDQ tracks with VDD, VDDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together.
The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF
is expected to be about 0.5 × VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
Peak to peak ac noise on VREF may not exceed ± 2% VREF (dc)
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal
to VREF, and must track variations in die dc level of VREF.
Table 22
ODT DC Electrical Characteristics
Parameter / Condition
Symbol
Min.
Nom.
Max.
Unit
Note
Termination resistor impedance value for
EMRS(1)[A6,A2] = [0,1]; 75 Ohm
Rtt1(eff)
60
75
90
Ω
1)
Termination resistor impedance value for
EMRS(1)[A6,A2] =[1,0]; 150 Ohm
Rtt2(eff)
120
150
180
Ω
—
Termination resistor impedance value for
EMRS(1)(A6,A2)=[1,1]; 50 Ohm
Rtt3(eff)
40
50
60
Ω
—
Deviation of VM with respect to VDDQ / 2
delta VM
–6.00
—
+ 6.00
%
2)
1)
Measurement Definition for Rtt(eff): Apply VIH(ac) and VIL(ac) to test pin separately, then measure current I(VIHac) and I(VILac)
respectively. Rtt(eff) = (VIH(ac) – VIL(ac)) /(I(VIHac) – I(VILac)).
2) Measurement Definition for VM: Turn ODT on and measure voltage (VM) at test pin (midpoint) with no load:
delta VM = ((2 x VM / VDDQ) – 1) x 100%
Table 23
Input and Output Leakage Currents
Symbol
Parameter / Condition
IIL
IOL
Min.
Max.
Unit
Note
Input Leakage Current; any input 0 V < VIN < VDD
–2
+2
µA
1)
Output Leakage Current; 0 V < VOUT < VDDQ
–5
+5
µA
2)
1) All other pins not under test = 0 V
2) DQ’s, LDQS, LDQS, UDQS, UDQS, DQS, DQS, RDQS, RDQS are disabled and ODT is turned off
Internet Data Sheet
26
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
5.3
DC & AC Characteristics
relative to the rising or falling edges of DQS crossing at
DDR2 SDRAM pin timing are specified for either single
ended or differential mode depending on the setting of
the EMRS(1) “Enable DQS” mode bit; timing
advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin
timing are measured is mode dependent. In single
ended mode, timing relationships are measured
Table 24
Symbol
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
Table 25
Symbol
VIH(dc)
VIL(dc)
VIH(ac)
VIL(ac)
Table 26
Symbol
VREF
VSWING.MAX
VREF. In differential mode, these timing relationships
are measured relative to the crosspoint of DQS and its
complement, DQS. This distinction in timing methods is
verified by design and characterization but not subject
to production test. In single ended mode, the DQS (and
RDQS) signals are internally disabled and don’t care.
DC & AC Logic Input Levels for DDR2-667 and DDR2-800
Parameter
DDR2-667, DDR2-800
Units
Min.
Max.
DC input logic high
VREF + 0.125
V
DC input low
–0.3
VDDQ + 0.3
VREF – 0.125
AC input logic high
VREF + 0.200
—
V
AC input low
—
VREF – 0.200
V
V
DC & AC Logic Input Levels for DDR2-533 and DDR2-400
Parameter
DDR2-533, DDR2-400
Units
Min.
Max.
DC input logic high
VREF + 0.125
DC input low
–0.3
VDDQ + 0.3
VREF - 0.125
V
AC input logic high
VREF + 0.250
—
V
AC input low
—
VREF - 0.250
V
V
Single-ended AC Input Test Conditions
Condition
Value
Unit
Note
Input reference voltage
0.5 x VDDQ
V
1)
Input signal maximum peak to peak swing
1.0
V
—
2)3)
1.0
V / ns
1) Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
2) The input signal minimum Slew Rate is to be maintained over the range from VIH(ac).MIN to VREF for rising edges and the
range from VREF to VIL(ac).MAX for falling edges as shown in Figure 4
3) AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to VIL(ac)
SLEW
Input signal minimum Slew Rate
on the negative transitions.
Internet Data Sheet
27
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
9''4
9,+ DF PLQ
9,+ GF PLQ
96:,1* 0$;
95()
9,/ GF PD[
9,/ DF PD[
966
'HOWD7)
)DOOLQJ6OHZ
'HOWD75
95()9,/ DF PD[
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9,+ DF PLQ95()
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03(7
Figure 4
Single-ended AC Input Test Conditions Diagram
Table 27
Differential DC and AC Input and Output Logic Levels
Symbol
Parameter
Min.
VIN(dc)
VID(dc)
VID(ac)
VIX(ac)
DC input signal voltage
–0.3
DC differential input voltage
0.25
AC differential input voltage
0.5
AC differential cross point input
voltage
VOX(ac)
AC differential cross point output
voltage
Max.
Unit
Note
—
1)
—
2)
V
3)
0.5 × VDDQ – 0.175
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.5 × VDDQ + 0.175
V
4)
0.5 × VDDQ – 0.125
0.5 × VDDQ + 0.125
V
5)
VIN(dc) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS etc.
VID(dc) specifies the input differential voltage VTR– VCP required for switching. The minimum value is equal to VIH(dc) – VIL(dc).
VID(ac) specifies the input differential voltage VTR – VCP required for switching. The minimum value is equal to VIH(ac) – VIL(ac).
The value of VIX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VIX(ac) is expected to track variations in
VDDQ. VIX(ac) indicates the voltage at which differential input signals must cross.
5) The value of VOX(ac) is expected to equal 0.5 × VDDQ of the transmitting device and VOX(ac) is expected to track variations in
VDDQ. VOX(ac) indicates the voltage at which differential input signals must cross.
1)
2)
3)
4)
6$$1
642
#ROSSING 0OINT
6)$
6)8 OR 6/8
6#0
6331
Figure 5
Differential DC and AC Input and Output Logic Levels Diagram
Internet Data Sheet
28
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
5.4
Output Buffer Characteristics
Table 28
SSTL_18 Output DC Current Drive
Symbol
Parameter
SSTL_18
Unit
Note
IOH
IOL
Output Minimum Source DC Current
–13.4
mA
1)2)
3)
Output Minimum Sink DC Current
13.4
mA
1) VDDQ = 1.7 V; VOUT = 1.42 V. (VOUT–VDDQ) / IOH must be less than 21 Ohm for values of VOUT between VDDQ and
VDDQ – 280 mV.
2) The values of IOH(dc) and IOL(dc) are based on the conditions given in and . They are used to test drive current capability to
ensure VIH.MIN. plus a noise margin and VIL.MAX minus a noise margin are delivered to an SSTL_18 receiver. The actual
current values are derived by shifting the desired driver operating points along 21 Ohm load line to define a convenient
current for measurement.
3) VDDQ = 1.7 V; VOUT = 280 mV. VOUT / IOL must be less than 21 Ohm for values of VOUT between 0 V and 280 mV.
Table 29
SSTL_18 Output AC Test Conditions
Symbol
Parameter
SSTL_18
Unit
Note
VOH
VOL
VOTR
Minimum Required Output Pull-up
VTT + 0.603
VTT – 0.603
0.5 × VDDQ
V
1)
V
—
Maximum Required Output Pull-down
Output Timing Measurement Reference Level
V
—
1) SSTL_18 test load for VOH and VOL is different from the referenced load. The SSTL_18 test load has a 20 Ohm series
resistor additionally to the 25 Ohm termination resistor into VTT. The SSTL_18 definition assumes that ± 335 mV must be
developed across the effectively 25 Ohm termination resistor (13.4 mA × 25 Ohm = 335 mV). With an additional series
resistor of 20 Ohm this translates into a minimum requirement of 603 mV swing relative to VTT, at the ouput device (13.4
mA × 45 Ohm = 603 mV).
Table 30
OCD Default Characteristics
Symbol
Description
Min.
Nominal
Max.
Unit
Note
Ohms
1)2)
—
Output Impedance
—
—
Pull-up / Pull down mismatch
0
—
4
Ohms
3)
—
Output Impedance step size
for OCD calibration
0
—
1.5
Ohms
4)
1.5
—
5.0
V / ns
5)6)7)
SOUT
Output Slew Rate
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) Impedance measurement condition for output source dc current: VDDQ = 1.7 V, VOUT = 1420 mV;
(VOUT–VDDQ) / IOH must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ – 280 mV. Impedance
measurement condition for output sink dc current: VDDQ = 1.7 V; VOUT = –280 mV; VOUT / IOL must be less than 23.4 Ohms
for values of VOUT between 0 V and 280 mV.
3) Mismatch is absolute value between pull-up and pull-down, both measured at same temperature and voltage.
4) This represents the step size when the OCD is near 18 ohms at nominal conditions across all process parameters and
represents only the DRAM uncertainty. A 0 Ohm value (no calibration) can only be achieved if the OCD impedance is 18
± 0.75 Ohms under nominal conditions.
5) The absolute value of the Slew Rate as measured from DC to DC is equal to or greater than the Slew Rate as measured
from AC to AC. This is verified by design and characterization but not subject to production test.
6) Timing skew due to DRAM output Slew Rate mis-match between DQS / DQS and associated DQ’s is included in tDQSQ and
tQHS specification.
7) DRAM output Slew Rate specification applies to 400, 533 and 667 MT/s speed bins.
Internet Data Sheet
29
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
5.5
Input / Output Capacitance
Table 31
Input / Output Capacitance
Symbol
Parameter
Min.
Max.
Unit
CCK
Input capacitance, CK and CK
1.0
2.0
pF
CDCK
Input capacitance delta, CK and CK
—
0.25
pF
CI
Input capacitance, all other input-only pins
1.0
1.75
pF
CDI
Input capacitance delta, all other input-only pins
—
0.25
pF
CIO
Input/output capacitance,
DQ, DM, DQS, DQS, RDQS, RDQS
2.5
3.5
pF
CDIO
Input/output capacitance delta,
DQ, DM, DQS, DQS, RDQS, RDQS
—
0.5
pF
Internet Data Sheet
30
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
5.6
Overshoot and Undershoot Specification
Table 32
AC Overshoot / Undershoot Specification for Address and Control Pins
Parameter
DDR2–400 DDR2–533 DDR2–667 DDR2–800 Unit
Maximum peak amplitude allowed for overshoot area 0.9
0.9
0.9
0.9
V
Maximum peak amplitude allowed for undershoot area 0.9
0.9
0.9
0.9
V
Maximum overshoot area above VDD
1.33
1.00
0.80
0.80
V.ns
Maximum undershoot area below VSS
1.33
1.00
0.80
0.80
V.ns
0D[LPXP$PSOLWXGH
9ROWV 9
2YHUVKRRW$UHD
9''
966
8QGHUVKRRW$UHD
0D[LPXP$PSOLWXGH
7LPH QV
03(7
Figure 6
AC Overshoot / Undershoot Diagram for Address and Control Pins
Table 33
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
Parameter
DDR2–400 DDR2–533 DDR2–667 DDR2–800 Unit
Maximum peak amplitude allowed for overshoot area
0.9
0.9
0.9
0.9
V
Maximum peak amplitude allowed for undershoot area 0.9
0.9
0.9
0.9
V
Maximum overshoot area above VDDQ
0.38
0.28
0.23
0.23
V.ns
Maximum undershoot area below VSSQ
0.38
0.28
0.23
0.23
V.ns
Internet Data Sheet
31
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
0D[LPXP$PSOLWXGH
9ROWV 9
2YHUVKRRW$UHD
9''4
9664
8QGHUVKRRW$UHD
0D[LPXP$PSOLWXGH
7LPH QV
03(7
Figure 7
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
Internet Data Sheet
32
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
6
Specifications and Conditions
Table 34
IDD Measurement Conditions
Parameter
Symbol Note
Operating Current - One bank Active - Precharge
tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), CKE is HIGH, CS is HIGH between valid
commands. Address and control inputs are switching; Databus inputs are switching.
IDD0
1)2)3)4)
5)6)
Operating Current - One bank Active - Read - Precharge
IDD1
IOUT = 0 mA, BL = 4, tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS.MIN(IDD), tRCD = tRCD(IDD), AL = 0, CL =
CL(IDD); CKE is HIGH, CS is HIGH between valid commands. Address and control inputs are
switching; Databus inputs are switching.
Precharge Power-Down Current
IDD2P
All banks idle; CKE is LOW; tCK = tCK(IDD);Other control and address inputs are stable; Data bus
inputs are floating.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
switching, Data bus inputs are switching.
IDD2N
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK(IDD); Other control and address inputs are
stable, Data bus inputs are floating.
IDD2Q
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable; Data bus
inputs are floating. MRS A12 bit is set to “0” (Fast Power-down Exit).
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK(IDD), CKE is LOW; Other control and address inputs are stable, Data bus
inputs are floating. MRS A12 bit is set to 1 (Slow Power-down Exit);
Active Standby Current
IDD3N
All banks open; tCK = tCK(IDD); tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between
valid commands. Address inputs are switching; Data Bus inputs are switching;
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD);
tRAS = tRAS.MAX.(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address
inputs are switching; Data Bus inputs are switching; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL(IDD); tCK = tCK(IDD);
tRAS = tRAS.MAX(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands. Address
inputs are switching; Data Bus inputs are switching;
Burst Refresh Current
IDD5B
tCK = tCK(IDD), Refresh command every tRFC = tRFC(IDD) interval, CKE is HIGH, CS is HIGH between
valid commands, Other control and address inputs are switching, Data bus inputs are switching.
Distributed Refresh Current
IDD5D
tCK = tCK(IDD), Refresh command every tREFI = 7.8 µs interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are switching, Data bus inputs are
switching.
Internet Data Sheet
33
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 34
IDD Measurement Conditions
Parameter
Symbol Note
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are floating,
Data bus inputs are floating.
Operating Bank Interleave Read Current
IDD7
1. All banks interleaving reads, IOUT = 0 mA; BL = 4, CL = CL(IDD), AL = tRCD(IDD) -1 × tCK(IDD); tCK
= tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD); CKE is HIGH, CS is HIGH between valid commands.
Address bus inputs are stable during deselects; Data bus is switching.
2. Timing pattern:
7)
DDR2-400-333: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D (11 clocks)
DDR2-533-333: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D (15 clocks)
DDR2-667-444: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D (19 clocks)
DDR2-667-555: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D D (20 clocks)
DDR2-800-555: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D(22 clocks)
DDR2-800-666: A0 RA0 D D D A1 RA1 D D D A2 RA2 D D D A3 RA3 D D D D D D(23 clocks)
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized.
3) IDD parameter are specified with ODT disabled.
4)
5)
6)
7)
Data Bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS and UDQS.
Definitions for IDD: see Table 35
Timing parameter minimum and maximum values for IDD current measurements are defined in chapter 7..
A = Activate, RA = Read with Auto-Precharge, D=DESELECT
Table 35
Definition for IDD
Parameter
Description
LOW
defined as VIN ≤ VIL(ac).MAX
HIGH
defined as VIN ≥ VIH(ac).MIN
STABLE
defined as inputs are stable at a HIGH or LOW level
FLOATING
defined as inputs are VREF = VDDQ / 2
SWITCHING
defined as: Inputs are changing between high and low every other clock (once per two clocks)
for address and control signals, and inputs changing between high and low every other clock
(once per clock) for DQ signals not including mask or strobes
Internet Data Sheet
34
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
IDDSpecification for HYB18T512xxxBF
Table 36
–2.5F
–2.5
–3
–3S
–3.7
–5
Unit
Note
DDR2-800D DDR2-800E DDR2-667C DDR2-667D DDR2-533C DDR2-400B
Symbol
Max.
Max.
Max.
Max.
Max.
Max.
IDD0
84
80
75
71
65
61
mA
×4/×8
105
100
95
90
80
75
mA
×16
100
95
90
85
75
70
mA
×4/×8
120
115
105
100
90
83
mA
×16
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
7
7
7
7
7
7
mA
—
51
51
45
45
38
34
mA
—
45
45
40
40
35
32
mA
—
39
39
33
33
28
24
mA
1)
9
9
9
9
9
9
mA
2)
60
60
50
50
43
39
mA
—
155
155
130
130
110
95
mA
×4/×8
180
180
155
155
130
115
mA
×16
155
155
130
130
110
95
mA
×4/×8
200
200
170
170
145
130
mA
×16
145
145
140
140
130
125
mA
—
9
9
9
9
9
9
mA
3)
7
7
7
7
7
7
mA
—
170
160
160
152
145
141
mA
×4/×8
265
255
252
240
230
220
mA
×16
1) MRS(12)=0
2) MRS(12)=1
3) 0° ≤ TCASE ≤ 85°C.
Internet Data Sheet
35
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7
Timing Characteristics
This chapter contains speed grade definition, AC timing parameter and ODT tables.
7.1
Speed Grade Definitions
All Speed grades faster than DDR2-DDR400B comply with DDR2-DDR400B timing specifications(tCK = 5ns with
tRAS = 40ns).
List of Speed Grade Definition tables:
•
•
•
•
Table 37 “Speed Grade Definition Speed Bins DDR2–800” on Page 36
Table 38 “Speed Grade Definition Speed Bins for DDR2–667” on Page 37
Table 39 “Speed Grade Definition Speed Bins for DDR2–533C” on Page 37
Table 40 “Speed Grade Definition Speed Bins for DDR2–400B” on Page 38
Table 37
Speed Grade Definition Speed Bins DDR2–800
Speed Grade
DDR2–800D
DDR2–800E
IFX Sort Name
–2.5F
–2.5
CAS-RCD-RP latencies
5–5–5
6–6–6
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
@ CL = 6
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
3.75
8
3.75
8
ns
—
2.5
8
3
8
ns
—
2.5
8
2.5
8
ns
—
1)2)3)4)
45
70000
45
70000
ns
5)
57.5
—
60
—
ns
—
12.5
—
15
—
ns
—
12.5
—
15
—
ns
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI.
Internet Data Sheet
36
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 38
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667
DDR2–667
IFX Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3
8
3.75
8
ns
—
3
8
3
8
ns
—
45
70000
45
70000
ns
5)
57
—
60
—
ns
—
12
—
15
—
ns
—
12
—
15
—
ns
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI.
Table 39
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533
IFX Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
ns
1)2)3)4)
3.75
8
ns
—
3.75
8
ns
—
45
70000
ns
5)
60
—
ns
—
15
—
ns
—
15
—
ns
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS,
RDQS / RDQS, input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI.
Internet Data Sheet
37
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 40
Speed Grade Definition Speed Bins for DDR2–400B
Speed Grade
DDR2–400
IFX Sort Name
–5
CAS-RCD-RP latencies
3–3–3
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
ns
1)2)3)4)
5
8
ns
—
5
8
ns
—
40
70000
ns
5)
55
—
ns
—
15
—
ns
—
15
—
ns
—
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS,
RDQS/RDQS, input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is
equal to 9 x tREFI.
Internet Data Sheet
38
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7.2
AC Timing Parameters
List of Timing Parameters Tables.
•
•
•
•
Table 41 “Timing Parameter by Speed Grade - DDR2–800” on Page 39
Table 42 “Timing Parameter by Speed Grade - DDR2–667” on Page 41
Table 43 “Timing Parameter by Speed Grade - DDR2-533” on Page 44
Table 44 “Timing Parameter by Speed Grade - DDR2-400” on Page 47
Table 41
Timing Parameter by Speed Grade - DDR2–800
Parameter
Symbol
DDR2–800
Min.
tAC
CAS A to CAS B command period
tCCD
CK, CK high-level width
tCH
CKE minimum high and low pulse width
tCKE
CK, CK low-level width
tCL
Auto-Precharge write recovery + precharge tDAL
DQ output access time from CK / CK
Unit
Note1)2)3)4)5)
6)
Max.
–400
+400
ps
—
2
—
—
0.45
0.55
3
—
0.45
0.55
—
tCK
tCK
tCK
tCK
tCK
tIS + tCK + tIH ––
ns
8)
WR + tRP
—
—
—
7)
time
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
DQ and DM input hold time (differential
data strobe)
tDH(base)
125
––
ps
—
DQ and DM input hold time (single ended
data strobe)
tDH1(base)
––
—
ps
—
0.35
—
tCK
—
–350
+350
ps
—
0.35
—
tCK
—
—
200
ps
9)
DQ and DM input pulse width (each input) tDIPW
DQS output access time from CK / CK
DQS input low (high) pulse width (write
cycle)
tDQSCK
tDQSL,H
DQS-DQ skew (for DQS & associated DQ tDQSQ
signals)
Write command to 1st DQS latching
transition
tDQSS
– 0.25
+ 0.25
tCK
—
DQ and DM input setup time (differential
data strobe)
tDS(base)
50
—
ps
—
DQ and DM input setup time (single ended tDS1(base)
data strobe)
––
—
ps
—
DQS falling edge hold time from CK (write tDSH
cycle)
0.2
—
tCK
—
DQS falling edge to CK setup time (write
cycle)
tDSS
0.2
—
tCK
—
Clock half period
tHP
tHZ
MIN. (tCL, tCH)
—
10)
—
tAC.MAX
ps
11)
tIH(base)
tIPW
250
—
ps
—
0.6
—
tCK
—
Data-out high-impedance time from CK /
CK
Address and control input hold time
Address and control input pulse width
(each input)
Internet Data Sheet
39
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 41
Timing Parameter by Speed Grade - DDR2–800 (cont’d)
Parameter
Symbol
DDR2–800
Min.
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
Unit
Note1)2)3)4)5)
6)
Max.
175
—
ps
—
2 × tAC.MIN
ps
—
tAC.MIN
tAC.MAX
tAC.MAX
ps
—
2
—
tCK
—
0
12
ns
—
tHP–tQHS
—
—
—
—
300
ps
—
—
7.8
µs
12)13)
3.9
µs
14)
—
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
105
—
ns
15)
Precharge-All (4 banks) command period
tRP
tRPRE
tRPST
tRRD
tRP
—
ns
16)
0.9
1.1
—
0.40
0.60
tCK
tCK
7.5
—
ns
17)
—
ns
—
7.5
—
ns
—
0.35 x tCK
—
Read preamble
Read postamble
Active bank A to Active bank B command
period
Internal Read to Precharge command
delay
10
tRTP
tWPRE
Write postamble
tWPST
Write recovery time for write without Auto- tWR
Write preamble
—
0.40
0.60
tCK
tCK
15
—
ns
—
—
18)
Precharge
Write recovery time for write with AutoPrecharge
WR
tWR/tCK
—
tCK
19)
Internal Write to Read command delay
tWTR
tXARD
7.5
—
ns
20)
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
8 – AL
—
tCK
—
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
—
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
—
200
—
tCK
—
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
1) VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1 V. See notes
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT.
Internet Data Sheet
40
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as
valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
12) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
13) 0 °C≤ TCASE ≤ 85 °C
14) 85 °C < TCASE ≤ 95 °C
15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank
precharge.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where
WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not
already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR
parameter stored in the MRS.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Table 42
Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Min.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
6)
Max.
–450
+450
ps
—
2
—
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
tDELAY
tIS + tCK + tIH
—
ns
8)
175
––
ps
—
––
—
ps
—
0.35
—
tCK
—
–400
+400
ps
—
0.35
—
tCK
—
tDH1(base)
tDIPW
DQS output access time from CK / CK
tDQSCK
DQS input low (high) pulse width (write cycle) tDQSL,H
DQ and DM input pulse width (each input)
Internet Data Sheet
Note1)2)3)4)5)
tAC
tCCD
tCH
tCKE
tCL
tDAL
DQ and DM input hold time (differential data tDH(base)
strobe)
DQ and DM input hold time (single ended
data strobe)
Unit
41
—
—
—
7)
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 42
Timing Parameter by Speed Grade - DDR2–667 (cont’d)
Parameter
Symbol
DDR2–667
Unit
Min.
Max.
Note1)2)3)4)5)
6)
DQS-DQ skew (for DQS & associated DQ
signals)
tDQSQ
—
240
ps
9)
Write command to 1st DQS latching
transition
tDQSS
– 0.25
+ 0.25
tCK
—
100
—
ps
—
DQ and DM input setup time (differential data tDS(base)
strobe)
DQ and DM input setup time (single ended
data strobe)
tDS1(base)
––
—
ps
—
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
—
DQS falling edge to CK setup time (write
cycle)
tDSS
0.2
—
tCK
—
—
10)
tHP
Data-out high-impedance time from CK / CK tHZ
Address and control input hold time
tIH(base)
Address and control input pulse width
tIPW
MIN. (tCL, tCH)
Clock half period
—
tAC.MAX
ps
11)
275
—
ps
—
0.6
—
tCK
—
200
—
ps
—
2 × tAC.MIN
ps
—
tAC.MIN
tAC.MAX
tAC.MAX
ps
—
2
—
tCK
—
0
12
ns
—
tHPQ – tQHS
—
—
—
—
340
ps
—
—
7.8
µs
12)13)
3.9
µs
14)
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
tQHS
tREFI
—
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
105
—
ns
15)
Precharge-All (4 banks) command period
tRP
tRPRE
tRPST
tRRD
tRP
—
ns
16)
0.9
1.1
—
0.40
0.60
tCK
tCK
7.5
—
ns
17)
10
—
ns
—
7.5
—
ns
—
tWPRE
tWPST
tWR
0.35 x tCK
—
Write recovery time for write with AutoPrecharge
Internal Write to Read command delay
Read preamble
Read postamble
Active bank A to Active bank B command
period
Internal Read to Precharge command delay tRTP
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
Internet Data Sheet
—
0.40
0.60
tCK
tCK
15
—
ns
—
WR
tWR/tCK
—
tCK
19)
tWTR
7.5
—
ns
20)
42
—
18)
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 42
Timing Parameter by Speed Grade - DDR2–667 (cont’d)
Parameter
Symbol
DDR2–667
Min.
Unit
Note1)2)3)4)5)
6)
Max.
Exit power down to any valid command
(other than NOP or Deselect)
tXARD
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
7 – AL
—
tCK
—
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
—
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
—
200
—
tCK
—
Exit Self-Refresh to Read command
1) VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1 V. See notes
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as
valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
12) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
13) 0 °C≤ TCASE ≤ 85 °C
14) 85 °C < TCASE ≤ 95 °C
15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank
precharge.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where
WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not
already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR
parameter stored in the MRS.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Internet Data Sheet
43
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 43
Timing Parameter by Speed Grade - DDR2-533
Parameter
Symbol
DDR2–533
Min.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
tAC
tCCD
tCH
tCKE
tCL
tDAL
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
Unit
Note1)2)3)4)
5)6)
Max.
–500
+500
ps
—
2
—
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
tIS + tCK + tIH
––
ns
8)
—
—
—
7)
DQ and DM input hold time (differential
data strobe)
tDH(base)
225
––
ps
—
DQ and DM input hold time (single ended
data strobe)
tDH1(base)
–25
—
ps
—
0.35
—
tCK
—
–450
+450
ps
—
0.35
—
tCK
—
—
300
ps
9)
DQ and DM input pulse width (each input) tDIPW
DQS output access time from CK / CK
DQS input low (high) pulse width (write
cycle)
tDQSCK
tDQSL,H
DQS-DQ skew (for DQS & associated DQ tDQSQ
signals)
Write command to 1st DQS latching
transition
tDQSS
– 0.25
+ 0.25
tCK
—
DQ and DM input setup time (differential
data strobe)
tDS(base)
100
—
ps
—
DQ and DM input setup time (single ended tDS1(base)
data strobe)
–25
—
ps
—
DQS falling edge hold time from CK (write tDSH
cycle)
0.2
—
tCK
—
DQS falling edge to CK setup time (write
cycle)
tDSS
0.2
—
tCK
—
Clock half period
tHP
tHZ
MIN. (tCL, tCH)
—
10)
—
tAC.MAX
ps
11)
tIH(base)
tIPW
375
—
ps
—
0.6
—
tCK
—
250
—
ps
—
2 × tAC.MIN
tAC.MAX
tAC.MAX
ps
—
tAC.MIN
ps
—
2
—
tCK
—
0
12
ns
—
tHP –tQHS
—
—
—
Data-out high-impedance time from CK /
CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Internet Data Sheet
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
44
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 43
Timing Parameter by Speed Grade - DDR2-533 (cont’d)
Parameter
Data hold skew factor
Average periodic refresh Interval
Symbol
DDR2–533
tQHS
tREFI
Unit
Note1)2)3)4)
5)6)
Min.
Max.
—
400
ps
—
—
7.8
µs
12)13)
3.9
µs
14)
—
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
105
—
ns
15)
Precharge-All (4 banks) command period
tRP
tRPRE
tRPST
tRRD
tRP
—
ns
16)
0.9
1.1
0.60
tCK
tCK
—
0.40
7.5
—
ns
17)
—
ns
—
7.5
—
ns
—
0.25 x tCK
—
Read preamble
Read postamble
Active bank A to Active bank B command
period
Internal Read to Precharge command
delay
10
tRTP
tWPRE
Write postamble
tWPST
Write recovery time for write without Auto- tWR
Write preamble
—
0.40
0.60
tCK
tCK
15
—
ns
—
—
18)
Precharge
Write recovery time for write with AutoPrecharge
WR
tWR/tCK
—
tCK
19)
Internal Write to Read command delay
tWTR
tXARD
7.5
—
ns
20)
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
—
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
—
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
—
200
—
tCK
—
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
1) VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1 V. See notes
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
Internet Data Sheet
45
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as
valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
12) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
13) 0 °C≤ TCASE ≤ 85 °C
14) 85 °C < TCASE ≤ 95 °C
15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank
precharge.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where
WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not
already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR
parameter stored in the MRS.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Internet Data Sheet
46
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 44
Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Min.
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery +
precharge time
tAC
tCCD
tCH
tCKE
tCL
tDAL
Minimum time clocks remain ON after CKE tDELAY
asynchronously drops LOW
Unit
Note1)2)3)4)5)
6)
Max.
–600
+600
ps
—
2
—
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
tIS + tCK + tIH
––
ns
8)
—
—
—
7)
DQ and DM input hold time (differential
data strobe)
tDH(base)
275
––
ps
—
DQ and DM input hold time (single ended
data strobe)
tDH1(base)
–25
—
ps
—
0.35
—
tCK
—
–500
+500
ps
—
0.35
—
tCK
—
—
350
ps
9)
DQ and DM input pulse width (each input) tDIPW
DQS output access time from CK / CK
DQS input low (high) pulse width (write
cycle)
tDQSCK
tDQSL,H
DQS-DQ skew (for DQS & associated DQ tDQSQ
signals)
Write command to 1st DQS latching
transition
tDQSS
– 0.25
+ 0.25
tCK
—
DQ and DM input setup time (differential
data strobe)
tDS(base)
150
—
ps
—
DQ and DM input setup time (single ended tDS1(base)
data strobe)
–25
—
ps
—
DQS falling edge hold time from CK (write tDSH
cycle)
0.2
—
tCK
—
DQS falling edge to CK setup time (write
cycle)
tDSS
0.2
—
tCK
Clock half period
tHP
tHZ
MIN. (tCL, tCH)
—
tIH(base)
tIPW
Data-out high-impedance time from CK /
CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Internet Data Sheet
tIS(base)
tLZ(DQ)
—
10)
tAC.MAX
ps
11)
475
—
ps
—
0.6
—
tCK
—
350
—
ps
—
2×
tAC.MAX
ps
—
tAC.MAX
ps
—
tAC.MIN
tAC.MIN
tLZ(DQS)
tMRD
tOIT
tQH
47
2
—
tCK
—
0
12
ns
—
tHP –tQHS
—
—
—
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table 44
Timing Parameter by Speed Grade - DDR2-400
Parameter
Data hold skew factor
Average periodic refresh Interval
Symbol
DDR2–400
tQHS
tREFI
tRFC
tRP
Read preamble
tRPRE
Read postamble
tRPST
Active bank A to Active bank B command tRRD
Precharge-All (4 banks) command period
period
Internal Read to Precharge command
delay
tWPRE
Write postamble
tWPST
Write recovery time for write without Auto- tWR
Write preamble
6)
Max.
—
450
ps
—
—
7.8
µs
12)13)
3.9
µs
14)
105
—
ns
15)
tRP
—
ns
16)
0.9
1.1
0.60
tCK
tCK
—
0.40
7.5
—
ns
17)
—
ns
—
7.5
—
ns
—
0.25 x tCK
—
—
0.40
0.60
tCK
tCK
15
—
ns
10
tRTP
Note1)2)3)4)5)
Min.
—
Auto-Refresh to Active/Auto-Refresh
command period
Unit
—
18)
Precharge
Write recovery time for write with AutoPrecharge
WR
tWR/tCK
—
tCK
19)
Internal Write to Read command delay
tWTR
tXARD
10
—
ns
20)
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
—
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
—
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
—
200
—
tCK
—
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
1) VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1 V. See notes
2) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be
powered down and then restarted through the specified initialization sequence before normal operation can continue.
3) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a
differential Slew Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
4) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross.
The DQS / DQS, RDQS/ RDQS, input reference level is the crosspoint when in differential strobe mode.
5) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is
recognized as low.
6) The output timing reference voltage level is VTT.
7) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period.
WR refers to the WR parameter stored in the MR.
8) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode. In case of clock
frequency change during power-down, a specific procedure is required.
9) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as
output Slew Rate mis-match between DQS / DQS and associated DQ in any given cycle.
10) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e.
this value can be greater than the minimum specification limits for tCL and tCH).
Internet Data Sheet
48
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
11) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is
no longer driving (tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as
valid data transitions.These parameters are verified by design and characterization, but not subject to production test.
12) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range
between 85 °C and 95 °C.
13) 0 °C≤ TCASE ≤ 85 °C
14) 85 °C < TCASE ≤ 95 °C
15) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
16) tRP(A) for a Precharge-All command for an 8 bank device is equal to tRP + 1tCK, where tRP are the values for a single bank
precharge.
17) The tRRD timing parameter depends on the page size of the DRAM organization. See Chapter 1
18) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter,
but system performance (bus turnaround) degrades accordingly.
19) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where
WRMIN[cycles] = tWR(ns)/tCK(ns) rounded up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not
already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to the WR
parameter stored in the MRS.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard
active power-down mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down
mode” (MR, A12 =”1”) a slow power-down exit timing tXARDS has to be satisfied.
Internet Data Sheet
49
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
7.3
ODT AC Electrical Characteristics
Table 45
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667
Symbol
Parameter / Condition
Values
Unit
Note
Min.
Max.
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
ODT turn-on delay
2
2
tCK
—
ODT turn-on
ns
1)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MAX + 0.7 ns
tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
ns
—
ODT turn-off delay
2.5
tCK
—
2.5
tAC.MIN
tAC.MAX + 0.6 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns
ODT to Power Down Mode Entry Latency 3
—
tCK
ODT Power Down Exit Latency
8
—
tCK
ODT turn-off
2)
—
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD.
Table 46
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400
Parameter / Condition
Values
Unit
Note
Min.
Max.
ODT turn-on delay
2
2
tCK
—
ODT turn-on
ns
1)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MAX + 1 ns
tAC.MIN + 2 ns 2 tCK + tAC.MAX + 1 ns
ns
—
ODT turn-off delay
2.5
tCK
—
2.5
tAC.MIN
tAC.MAX + 0.6 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN + 2 ns 2.5 tCK + tAC.MAX + 1 ns ns
ODT to Power Down Mode Entry Latency 3
—
tCK
ODT Power Down Exit Latency
8
—
tCK
ODT turn-off
2)
—
—
—
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time
max is when the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high
impedance. Both are measured from tAOFD.
Internet Data Sheet
50
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
8
Package Dimensions
X !
X -!8
"
-!8
#
-!8
Figure 8
-).
#
’ ›
X
! "
’ #
’ -
# 3%!4).' 0,!.%
$UMMY PADS WITHOUT BALL
-IDDLE OF PACKAGES EDGES
0ACKAGE ORIENTATION MARK !
"AD UNIT MARKING "5$IE SORT FIDUCIAL
Package Pinout PG-TFBGA-60
Internet Data Sheet
51
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
X !
X -!8
"
-!8
#
Figure 9
-).
-!8
#
’ ›
X
’ ! "
#
’ -
# 3%!4).' 0,!.%
$UMMY PADS WITHOUT BALL
-IDDLE OF PACKAGES EDGES
0ACKAGE ORIENTATION MARK !
"AD UNIT MARKING "5$IE SORT FIDUCIAL
Package Outline P-TFBGA-84
Internet Data Sheet
52
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
9
Product Nomenclature
For reference the Qimonda SDRAM component nomenclature is enclosed in this chapter.
Table 47
Nomenclature Fields and Examples
Example for
Field Number
1
DDR2 DRAM
HYB
2
3
4
5
18
T
512
16
6
7
8
9
10
0
A
C
–3.7
Table 48
DDR2 Memory Components
Field
Description
Values
Coding
1
QIMONDA
Component Prefix
HYB
Constant
2
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
5+6
Number of I/Os
256
256 M
512
512 M
1G
1 Gb
40
×4
80
×8
160
×16
7
Product Variations
0 .. 9
look up table
8
Die Revision
A
First
B
Second
9
Package,
Lead-Free Status
C
FBGA,
lead-containing
F
FBGA, lead-free
10
Speed Grade
–3
DDR2–667 4–4–4
–3S
DDR2–667 5–5–5
–3.7
DDR2–533 4–4–4
–5
DDR2–400 3–3–3
11
11
N/A for Components
Internet Data Sheet
53
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
List of Figures
Figure 1
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Pin Configuration for ×4 components, PG-TFBGA-60-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration for ×8 components, PG-TFBGA-60-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Configuration for ×16 components, PG-TFBGA-84-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-ended AC Input Test Conditions Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential DC and AC Input and Output Logic Levels Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Overshoot / Undershoot Diagram for Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . .
AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . . . . .
Package Pinout PG-TFBGA-60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package Outline P-TFBGA-84 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internet Data Sheet
54
12
13
14
28
28
31
32
51
52
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Table 41
Table 42
Table 43
Table 44
Table 45
Table 46
Table 47
Table 48
Performance for DDR2–800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Performance for DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Performance for DDR2–533C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Performance for DDR2–400B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Ordering Information for RoHS compliant products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration of DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
512-Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Mode Register Definition (BA[2:0] = 000B). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Extended Mode Register Definition (BA[2:0] = 001B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . 19
EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B) . . . . . . . . . . . . . . . . . . 20
ODT Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Burst Length and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Command Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Clock Enable (CKE) Truth Table for Synchronous Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Data Mask (DM) Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DRAM Component Operating Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Recommended DC Operating Conditions (SSTL_18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ODT DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Input and Output Leakage Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DC & AC Logic Input Levels for DDR2-667 and DDR2-800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC & AC Logic Input Levels for DDR2-533 and DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Single-ended AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Differential DC and AC Input and Output Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SSTL_18 Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SSTL_18 Output AC Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
OCD Default Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
AC Overshoot / Undershoot Specification for Address and Control Pins . . . . . . . . . . . . . . . . . . . 31
AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins . . . . . . . . . . . . 31
IDD Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Definition for IDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
IDDSpecification for HYB18T512xxxBF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Speed Grade Definition Speed Bins DDR2–800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Speed Grade Definition Speed Bins for DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Speed Grade Definition Speed Bins for DDR2–533C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Speed Grade Definition Speed Bins for DDR2–400B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Timing Parameter by Speed Grade - DDR2–800 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Timing Parameter by Speed Grade - DDR2–667 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Timing Parameter by Speed Grade - DDR2-533 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Timing Parameter by Speed Grade - DDR2-400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ODT AC Electrical Characteristics and Operating Conditions for DDR2-667 . . . . . . . . . . . . . . . . 50
ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400 . . . . 50
Nomenclature Fields and Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
DDR2 Memory Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Internet Data Sheet
55
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
HYB18T512xxxBF–[2.5…5]
512-Mbit Double-Data-Rate-Two SDRAM
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
2.1
2.2
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
512 Mbit DDR2 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4
Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5
5.1
5.2
5.3
5.4
5.5
5.6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC & AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Buffer Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input / Output Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overshoot and Undershoot Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6
Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
7
7.1
7.2
7.3
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9
Product Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Internet Data Sheet
56
25
25
26
27
29
30
31
36
36
39
50
Rev. 1.05, 2007-01
03292006-YBYM-WG0Z
Internet Data Sheet
Edition 2007-01
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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