ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER GENERAL DESCRIPTION FEATURES The ICS8432-51 is a general purpose, dual output Crystal-to-3.3V Differential LVPECL High FreHiPerClockS™ quency Synthesizer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8432-51 has a selectable TEST_CLK or crystal input. The VCO operates at a frequency range of 250MHz to 700MHz. The VCO frequency is programmed in steps equal to the value of the input reference or crystal frequency. The VCO and output frequency can be programmed using the serial or parallel interface to the configuration logic. The low phase noise characteristics of the ICS8432-51 make it an ideal clock source for Gigabit Ethernet, Fibre Channel 1 and 2, and Infiniband applications. • Dual differential 3.3V LVPECL outputs ICS • Selectable crystal oscillator interface or LVCMOS/LVTTL TEST_CLK • Output frequency range: 31.25MHz to 700MHz • Crystal input frequency range: 12MHz to 25MHz • VCO range: 250MHz to 700MHz • Parallel or serial interface for programming counter and output dividers • RMS period jitter: 3.5ps (maximum) • Cycle-to-cycle jitter: 25ps (maximum) • 3.3V supply voltage • 0°C to 70°C ambient operating temperature • Replaces the ICS8432-01 • Lead-Free package fully RoHS compliant BLOCK DIAGRAM PIN ASSIGNMENT XTAL1 nP_LOAD PLL PHASE DETECTOR MR VCO ÷M 0 1 ÷1 ÷2 ÷4 ÷8 M5 1 24 XTAL2 M6 2 23 TEST_CLK M7 3 22 XTAL_SEL M8 4 21 VCCA N0 5 20 S_LOAD N1 6 19 S_DATA nc 7 18 S_CLOCK VEE 8 17 MR FOUT0 nFOUT0 FOUT1 nFOUT1 ICS8432-51 9 10 11 12 13 14 15 16 VEE nFOUT0 FOUT0 VCCO nFOUT1 FOUT1 VCC TEST CONFIGURATION INTERFACE LOGIC TEST 32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View M0:M8 N0:N1 8432BY-51 M0 32 31 30 29 28 27 26 25 1 XTAL2 S_LOAD S_DATA S_CLOCK nP_LOAD M1 OSC M2 0 XTAL1 M3 M4 XTAL_SEL TEST_CLK VCO_SEL VCO_SEL www.icst.com/products/hiperclocks.html 1 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FUNCTIONAL DESCRIPTION NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1. M divider and N output divider to a specific default state that will automatically occur during power-up. The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the M divider is defined as follows: fVCO = fxtal x M The ICS8432-51 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth. A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector. A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of 250MHz to 700MHz. The output of the M divider is also applied to the phase detector. The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table. Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 10 ≤ M ≤ 28. The frequency out is defined as follows: FOUT = fVCO = fxtal x M N N Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1 determine the state of the TEST output as follows: The phase detector and the M divider force the VCO output frequency to be M times the reference frequency by adjusting the VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle. The programmable features of the ICS8432-51 support two input modes to program the M divider and N output divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode, the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the M divider and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the T1 T0 TEST Output 0 0 LOW 0 1 S_Data, Shift Register Input 1 0 Output of M divider 1 1 CMOS Fout SERIAL LOADING S_CLOCK S_DATA T1 t S S_LOAD T0 *NULL N1 N0 M8 M7 M6 M5 M4 M3 M2 M1 M0 t H t nP_LOAD S PARALLEL LOADING M0:M8, N0:N1 M, N nP_LOAD t S t Time H FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS *NOTE: The NULL timing slot must be observed. 8432BY-51 www.icst.com/products/hiperclocks.html 2 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 1. PIN DESCRIPTIONS Number Name Type 1 M5 2, 3, 4, 28, 29, 30, 31, 32 M6, M7, M8, M0, M1, M2, M3, M4 Input M divider inputs. Data latched on LOW-to-HIGH transition Pulldown of nP_LOAD input. LVCMOS / LVTTL interface levels. 5, 6 N0, N1 Input Pulldown 7 nc Unused 8, 16 VEE Power Negative supply pins. 9 TEST Output Test output which is ACTIVE in the serial mode of operation. Output driven LOW in parallel mode. LVCMOS / LVTTL interface levels. 10 VCC Power Core supply pin. 11, 12 FOUT1, nFOUT1 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. 13 VCCO Power Output supply pin. 14, 15 FOUT0, nFOUT0 Output Differential output for the synthesizer. 3.3V LVPECL interface levels. Input Description Pullup Determines output divider value as defined in Table 3C, Function Table. LVCMOS / LVTTL interface levels. No connect. Active High Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs FOUTx to go low and the inver ted outputs nFOUTx to go high. When logic LOW, the internal dividers and the outputs are enabled. Asser tion of MR does not effect loaded M, N, and T values. LVCMOS / LVTTL interface levels. Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Shift register serial input. Data sampled on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels. 17 MR Input Pulldown 18 S_CLOCK Input Pulldown 19 S_DATA Input Pulldown 20 S_LOAD Input Pulldown 21 VCCA Power Analog supply pin. Selects between crystal or test inputs as the PLL reference source. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. LVCMOS / LVTTL interface levels. 22 XTAL_SEL Input 23 TEST_CLK Input 24, 25 XTAL2, XTAL1 Input 26 nP_LOAD Input 27 VCO_SEL Input Pullup Pulldown Test clock input. LVCMOS / LVTTL interface levels. Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output. Parallel load input. Determines when data present at M8:M0 is Pulldown loaded into M divider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. Determines whether synthesizer is in PLL or bypass mode. Pullup LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ 8432BY-51 www.icst.com/products/hiperclocks.html 3 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. TABLE 3A. PARALLEL AND 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER SERIAL MODE FUNCTION TABLE Inputs Conditions MR nP_LOAD M N S_LOAD S_CLOCK S_DATA H X X X X X X Reset. Forces outputs LOW. L L Data Data X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. L ↑ Data Data L X X L H X X L ↑ Data L H X X ↑ L Data L H X X ↓ L Data M divider and N output divider values are latched. L H X X L X X Parallel or serial input do not affect shift registers. L H X X H ↑ Data Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK. Contents of the shift register are passed to the M divider and N output divider. S_DATA passed directly to M divider as it is clocked. NOTE: L = LOW H = HIGH X = Don't care ↑ = Rising edge transition ↓ = Falling edge transition TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE 256 128 64 32 16 8 4 2 1 M8 M7 M6 M5 M4 M3 M2 M1 M0 0 0 0 0 0 1 0 1 0 11 0 0 0 0 0 1 0 1 1 • • • • • • • • • • • • • • • • • • • • • • VCO Frequency (MHz) M Divide 250 10 275 650 26 0 0 0 0 1 1 0 1 0 675 27 0 0 0 0 1 1 0 1 1 700 28 0 0 0 0 1 1 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to cr ystal or TEST_CLK input frequency of 25MHz. 0 TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE Inputs 8432BY-51 N1 N0 0 0 N Divider Value 1 Output Frequency (MHz) Minimum Maximum 250 700 0 1 2 12 5 350 1 0 4 62.5 175 1 1 8 31.25 87.5 www.icst.com/products/hiperclocks.html 4 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5 V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 47.9°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VCC VCCA Test Conditions Minimum Typical Maximum Units Core Supply Voltage 3.135 3.3 3.465 V Analog Supply Voltage 3.135 3.3 3.465 V 3.135 3. 3 VCCO Output Supply Voltage 3.465 V IEE Power Supply Current 135 mA ICCA Analog Supply Current 15 mA Maximum Units 2 VCC + 0.3 V 2 VCC + 0.3 V -0.3 0.8 V -0.3 1.3 V VCC = VIN = 3.465V 150 µA VCC = VIN = 3.465V 5 µA TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter VIH Input High Voltage VIL IIH Input Low Voltage Input High Current Test Conditions VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK VCO_SEL, XTAL_SEL, MR, S_LOAD, nP_LOAD, N0:N1, S_DATA, S_CLOCK, M0:M8 TEST_CLK M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD M5, XTAL_SEL, VCO_SEL IIL Input Low Current Minimum Typical M0-M4, M6-M8, N0, N1, MR, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD VCC = 3.465V, VIN = 0V -5 µA M5, XTAL_SEL, VCO_SEL VCC = 3.465V, VIN = 0V -150 µA 2. 6 V VOH Output High Voltage TEST; NOTE 1 VOL Output Low Voltage TEST; NOTE 1 0.5 V NOTE 1: Outputs terminated with 50Ω to VCCO/2. 8432BY-51 www.icst.com/products/hiperclocks.html 5 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter Test Conditions VOH Output High Voltage; NOTE 1 VOL Output Low Voltage; NOTE 1 Minimum Typical Maximum Units VCCO - 1.4 VCCO - 1.0 V VCCO - 2.0 VCCO - 1.7 V 1.0 V Peak-to-Peak Output Voltage Swing 0.6 VSWING NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V. See "Parameter Measurement Information" section, figure "3.3V Output Load Test Circuit". TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter fIN Test Conditions Input Frequency Maximum Units TEST_CLK; NOTE 1 Minimum 12 Typical 25 MHz XTAL1, XTAL2; NOTE 1 12 25 MHz S_CLOCK 50 MHz NOTE 1: For the input cr ystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the 250MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 21 ≤ M ≤ 58. Using the maximum frequency of 25MHz, valid values of M are 10 ≤ M ≤ 28. TABLE 6. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Maximum Units Fundamental 25 MHz Equivalent Series Resistance (ESR) Frequency 12 70 Ω Shunt Capacitance 7 pF TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C Symbol Parameter FOUT Test Conditions Output Frequency Minimum Typical 31.25 Maximum Units 700 MHz tjit(cc) Cycle-to-Cycle Jitter ; NOTE 1, 3 25 ps tjit(per) Period Jitter, RMS; NOTE 1 3.5 ps tsk(o) Output Skew; NOTE 2, 3 15 ps tR / tF Output Rise/Fall Time 700 ps fVCO > 350MHz 20% to 80% 200 M, N to nP_LOAD tS Setup Time 5 ns S_DATA to S_CLOCK 5 ns S_CLOCK to S_LOAD 5 ns M, N to nP_LOAD 5 ns S_DATA to S_CLOCK 5 ns tH Hold Time odc Output Duty Cycle N>1 48 52 % tPW Output Pulse Width N=1 tPERIOD/2 - 150 tPERIOD/2 + 150 ps S_CLOCK to S_LOAD 5 ns PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Jitter performance using XTAL inputs. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 8432BY-51 www.icst.com/products/hiperclocks.html 6 1 ms REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 2V VCC, VCCA, VCCO Qx SCOPE nFOUTx FOUTx LVPECL nFOUTy nQx VEE FOUTy t sk(o) -1.3V± 0.165V 3.3V OUTPUT LOAD AC TEST CIRCUIT OUTPUT SKEW VOH nFOUTx VREF FOUTx ➤ tcycle tcycle n+1 ➤ 1000 Cycles Mean Period (Trigger Edge) ➤ t jit(cc) = tcycle n –tcycle n+1 Histogram Reference Point n ➤ VOL 1σ contains 68.26% of all measurements 2σ contains 95.4% of all measurements 3σ contains 99.73% of all measurements 4σ contains 99.99366% of all measurements 6σ contains (100-1.973x10-7)% of all measurements (First edge after trigger) PERIOD JITTER CYCLE-TO-CYCLE JITTER nFOUTx 80% FOUTx 80% VSW I N G Pulse Width t odc = Clock Outputs PERIOD 20% 20% t PW tR tF t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 8432BY-51 OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 7 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION STORAGE AREA NETWORKS A variety of technologies are used for interconnection of the elements within a SAN. The tables below lists the common frequencies used as well as the settings for the ICS8432-51 to generate the appropriate frequency. Table 8. Common SANs Application Frequencies Clock Rate Reference Frequency to SERDES (MHz) Crystal Frequency (MHz) 1.25 GHz 125, 250, 156.25 25, 19.53125 FC1 1.0625 GHz FC2 2.1250 GHz 106.25, 53.125, 132.8125 16.6015625, 25 2.5 GHz 125, 250 25 Interconnect Technology Gigabit Ethernet Fibre Channel Infiniband Table 9. Configuration Details for SANs Applications Interconnect Technology Crystal Frequency (MHz) ICS8432-51 Output Frequency to SERDES (MHz) 25 125 0 0 0 0 1 0 1 0 25 250 0 0 0 0 1 0 1 25 156.25 0 0 0 0 1 1 19.53125 156.25 0 0 0 1 0 25 53.125 0 0 0 0 25 106.25 0 0 0 16.6015625 132.8125 0 0 25 125 0 25 250 0 ICS8432-51 M & N Settings M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 0 0 0 0 1 0 1 0 0 0 1 Gigabit Ethernet Fiber Channel 1 Fiber Channel 2 Infiniband POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8432-51 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 2 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 8432BY-51 3.3V VCC .01μF 10Ω V CCA .01μF 10 μF FIGURE 2. POWER SUPPLY FILTERING www.icst.com/products/hiperclocks.html 8 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER CRYSTAL INPUT INTERFACE The ICS8432-51 has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 3 below were determined using a 25MHz, 18pF parallel reso- nant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. XTAL2 C1 22p X1 18pF Parallel Cry stal XTAL1 C2 22p Figure 3. CRYSTAL INPUt INTERFACE TERMINATION FOR LVPECL OUTPUTS drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUTx and nFOUTx are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to 3.3V Zo = 50Ω 125Ω FOUT 125Ω FIN Zo = 50Ω Zo = 50Ω 50Ω RTT = 1 Z ((VOH + VOL) / (VCC – 2)) – 2 o FOUT 50Ω VCC - 2V Zo = 50Ω RTT 84Ω FIGURE 4A. LVPECL OUTPUT TERMINATION 8432BY-51 FIN 84Ω FIGURE 4B. LVPECL OUTPUT TERMINATION www.icst.com/products/hiperclocks.html 9 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER LAYOUT GUIDELINE The layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the P.C. board. The schematic of the ICS8432-51 layout example used in this layout guideline is shown in Figure 5A. The ICS8432-51 recommended PCB board layout for this example is shown in Figure 5B. This layout example is used as a general guideline. C1 C2 M5 M6 M7 M8 N0 N1 nc VEE VCC ICS8432-51 XTAL2 REF_IN nXTAL_SEL VCCA S_LOAD S_DATA S_CLOCK MR TEST VCC FOUT1 nFOUT1 VCCO FOUT0 nFOUT0 VEE 1 2 3 4 5 6 7 8 9 10 11 12 VCC 13 FOUT 14 FOUTN 15 16 U1 M4 M3 M2 M1 M0 VCO_SEL nP_LOAD XTAL1 32 31 30 29 28 27 26 25 X1 VCC 24 23 22 21 20 19 18 17 R7 10 REF_IN XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK C11 0.01u C16 10u VCC R1 125 R3 125 Zo = 50 Ohm C14 0.1u TL1 C15 0.1u + Zo = 50 Ohm - TL2 R2 84 FIGURE 5A. SCHEMATIC 8432BY-51 OF RECOMMENDED LAYOUT www.icst.com/products/hiperclocks.html 10 R4 84 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER The following component footprints are used in this layout example: • The differential 50Ω output traces should have the same length. All the resistors and capacitors are size 0603. • Avoid sharp angles on the clock trace. Sharp angle turns cause the characteristic impedance to change on the transmission lines. POWER AND GROUNDING Place the decoupling capacitors C14 and C15, as close as possible to the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. • Keep the clock traces on the same layer. Whenever possible, avoid placing vias on the clock traces. Placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. Maximize the power and ground pad sizes and number of vias capacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. • To prevent cross talk, avoid routing other signal traces in parallel with the clock traces. If running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible. • Make sure no other signal traces are routed between the clock trace pair. CLOCK TRACES • The matching termination resistors should be located as close to the receiver input pins as possible. AND TERMINATION Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. CRYSTAL The crystal X1 should be located as close as possible to the pins 24 (XTAL2) and 25 (XTAL1). The trace length between the X1 and U1 should be kept to a minimum to avoid unwanted parasitic inductance and capacitance. Other signal traces should not be routed near the crystal traces. GND C2 C1 VCC X1 VIA U1 PIN 1 C16 C11 VCCA R7 Close to the input pins of the receiver TL1N C15 TL1 C14 TL1 R1 R2 TL1N R3 R4 TL1, TL21N are 50 Ohm traces and equal length FIGURE 5B. PCB BOARD LAYOUT 8432BY-51 FOR ICS8432-51 www.icst.com/products/hiperclocks.html 11 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS8432-51. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8432-51 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 467.8mW Power (outputs)MAX = 30.2mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW Total Power_MAX (3.465V, with all outputs switching) = 467.8mW + 60.4mW = 528.2mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 10 below. Therefore, Tj for an ambient temperature of 70°C with all outputs switching is: 70°C + 0.528W * 42.1°C/W = 92.2°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 10. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 8432BY-51 www.icst.com/products/hiperclocks.html 12 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 6. VCCO Q1 VOUT RL 50 VCCO - 2V FIGURE 6. LVPECL DRIVER CIRCUIT TERMINATION AND To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CCO • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V CCO_MAX – 1.0V ) = 1.0V For logic low, VOUT = V (V =V =V CCO_MAX – 1.7V ) = 1.7V OL_MAX Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CCO_MAX - 2V))/R ] * (V CCO_MAX L -V OH_MAX ) = [(2V - (V CCO_MAX -V OH_MAX ))/R ] * (V CCO_MAX L -V )= OH_MAX [(2V - 1V)/50Ω) * 1V = 20.0mW Pd_L = [(V OL_MAX – (V CCO_MAX - 2V))/R ] * (V L CCO_MAX -V OL_MAX ) = [(2V - (V CCO_MAX -V OL_MAX ))/R ] * (V L CCO_MAX -V )= OL_MAX [(2V - 1.7V)/50Ω) * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW 8432BY-51 www.icst.com/products/hiperclocks.html 13 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE 11. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 67.8°C/W 47.9°C/W 55.9°C/W 42.1°C/W 50.1°C/W 39.4°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS8432-51 is: 3743 8432BY-51 www.icst.com/products/hiperclocks.html 14 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. PACKAGE OUTLINE - Y SUFFIX 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER FOR 32 LEAD LQFP TABLE 12. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL MINIMUM NOMINAL 32 N A -- -- 1.60 A1 0.05 -- 0.15 A2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. e 0.80 BASIC L 0.45 0.60 θ 0° -- --ccc Reference Document: JEDEC Publication 95, MS-026 8432BY-51 MAXIMUM www.icst.com/products/hiperclocks.html 15 0.75 7° 0.10 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER TABLE 13. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8432BY-51 ICS8432BY-51 32 Lead LQFP tray 0°C to 70°C ICS8432BY-51T ICS8432BY-51 32 Lead LQFP 1000 tape & reel 0°C to 70°C ICS8432BY-51LF ICS8432BY51L 32 Lead "Lead-Free" LQFP tray 0°C to 70°C ICS8432BY-51LFT ICS8432BY51L 32 Lead "Lead-Free" LQFP 1000 tape & reel 0°C to 70°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8432BY-51 www.icst.com/products/hiperclocks.html 16 REV. C APRIL 8, 2005 ICS8432-51 Integrated Circuit Systems, Inc. 700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER REVISION HISTORY SHEET Rev Table Page Corrected labels on the Parallel & Serial Load Operations diagram. Revised MR pin description. Power Supply table - changed IDD to 155mA max. from 130mA max., changed IDDA to 20mA max. from 15mA max., and changed IDDO to 55mA max. from 45mA max. 12/18/02 T1 T4A 2 3 5 9 1 Added LVDS Driver Termination Section. General Description & Features - changed VCO min. from 200MHz to 250MHz and replaced throughout the datasheet in: (Functional Description pg2, T3C Program. Output Divider Func. Table pg4, and T5 Input Freq Charac. Table pg6). - Features - changed min. Output Frequency Range from 25MHz to 31.25MHz. 3/12/03 T1 3 Pin Descriptions Table - revised XTAL1,XTAL2 pin description. T2 3 Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. T3B 4 Prog. VCO Freq. Func. Table - deleted 200 and 225 rows, does not apply. 5 Power Supply DC Characteristics Table - deleted VDDO & IDDO rows, does not apply. A B B C T7 C C 8432BY-51 T1 T13 Description of Change Date 2/13/03 5/9/03 6 AC Characteristics Table - change FOUT 25MHz min. to 31.25MHz min. 1 Pin Assignment - corrected XTAL pins. Pin 24 is labeled XTAL2 and pin 25 is labeled XTAL1. 2 Revised Parallel & Serial Load Operations diagram. 3 Pin Descriptions Table - corrected XTAL pins to correspond with the pin number. Changed XTAL1 to read input and XTAL2 to read output. 10 Updated Figure 5A schematic to correspond the XTAL pins with the Pin Assignment. Cr ystal section, corrected pin 24 to read XTAL2 and pin 25 to read XTAL1. 11 1 16 Features Section - added Lead-Free bullet. Ordering Information - added Lead-Free par t number. www.icst.com/products/hiperclocks.html 17 5/28/03 4/8/05 REV. C APRIL 8, 2005