OKI MSM7719-01TS-K Echo canceler with adpcm transcoder Datasheet

E2U0058-18-85
¡ Semiconductor
MSM7719-01
¡ Semiconductor
This version:MSM7719-01
Aug. 1998
Echo Canceler with ADPCM Transcoder
GENERAL DESCRIPTION
The MSM7719, developed for PHS (Personal Handyphone System) applications, is an LSI device
and contains a line echo canceler, an acoustic echo canceler (for handsfree conversation), and
a single channel full-duplex ADPCM transcoder.
This device includes DTMF tone and several types of tone generation, transmit/receive data mute
and gain control, and VOX function and is best suited for PHS applications.
FEATURES
• Single 5 V power supply
VDD : 4.5 V to 5.5 V
• ADPCM :
ITU-T Recommendations G.726
• PCM interface coding format :
µ-law
• Built-in 2-channel (line and acoustic) echo canceler
Line echo canceler
Acoustic echo canceler (for handsfree conversation)
Echo attenuation : 30 dB (typ.)
Cancelable echo delay time :
27 ms (max.) for line echo canceler +27 ms (max.) for acoustic echo canceler
Line echo canceler mode only :
54 ms (max.)
• Serial PCM/ADPCM transmission data rate : 64 kbps to 2048 kbps
• Low supply current
Operating mode :
Typically 50 mA (VDD = 5.0 V)
Power-down mode :
Typically 0.2 mA (VDD = 5.0 V)
• Master clock frequency :
9.6 to 10.0 MHz/19.2 to 20.0 MHz
• Transmit/receive mute, transmit/receive programmable gain control
• Built-in DTMF tone generator and various tones generator
• Control through parallel microcontroller interface
Pin control available for line and acoustic echo cancelers
• Built-in VOX control
Transmit side :
Voice/silence detect
Receive side :
Background noise generation at the absence of voice signal
• Package:
100-pin plastic TQFP (TQFP100-P-1414-0.50-K) (Product name : MSM7719-01TS-K)
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MSM7719-01
¡ Semiconductor
BLOCK DIAGRAM
Tone Generator (DTMF etc).
ATTtgrx
SinL
ATTtgtx
ATTgL
ATTsL
+
+
ATTIL
RoutA
ATTrA GainA
Center
Clip
+
SoutL
RinA
Line
Adaptive FIR Filter
(LAFF)
Power Calc.
Howling Detector
Double Talk Detector
Power Calc.
Howling Detector
Acoustic
Adaptive FIR Filter
(AAFF)
Double Talk Detector
RinL
SoutA
+
+
Center
Clip
GainL ATTrL
RoutL
ATTIA
–
+
ATTsA
SinA
ATTgA
Line Echo Canceler
Acoustic Echo Canceler
Mute
DETSL
DETT
DETP
Note Gen.
MLV0-2
MUTE
LTHR
LDCL
LCCL
LHD
LCLP
LHLD
LATT
LGC
LATTG2-0
LATTL2-0
Power Detect
VOXI
Voice Detect
VOXO
VREF
SG
Line
Echo
Timing
Gen.
ADPCM TRANSCODER
Canceler
Controller
ADPCM
CODER
ECMODE
SYNCA
IS
P/S
&
ADPCM
DECODER
ATHR
ADCL
ACCL
AHD
ACLP
AHLD
AATT
AGC
AATTG2-0
AATTL2-0
BCLKA
S/P
IR
Acoustic
Echo
CONTA
I/O Controller
IOSL0-1
Canceler
VDDD1-3
Controller
N/L L/N
N/L L/N
VDDA
DG1-3
N/L L/N
AG
TSTI1-6
Test I/F
PDWN
MCK
PDN/RST
Clock Gen.
MCKSL
BCLKP
SYNCP
DTHR
PCMADO
PCMADI
PCMACO
PCMACI
PCMLNO
PCMLNI
PCMSL
INT
D7-0
WR
A4-0
CS
RD
MTYPE
MCUSL
Timing
Gen.
P/S&S/P
MCU I/F
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76 NC
77 IOSL0
78 IOSL1
79 ECMODE
80 DETSL
81 DETT
82 DG3
83 DETP
84 TSTI2
85 INT
86 TSTI1
87 PDWN
88 VDDD3
89 PDN/RST
90 SYNCA
91 SYNCP
92 D0
93 D1
94 D2
95 D3
96 D4
97 D5
98 D6
99 D7
100 NC
PIN CONFIGURATION (TOP VIEW)
NC
1
75 A4
WR
2
74 CS
RD
3
73 A3
A0
4
72 VOX0
A1
5
71 MCUSL
A2
6
70 PCMSL
VDDD1
7
69 IS
LDCL
8
68 PCMLN0
LCCL
9
67 PCMAD0
LHD 10
66 PCMAC0
LCLP 11
65 VDDD2
DG1 12
64 MUTE
LHLD 13
63 VOXI
LATT 14
62 TSTI6
LTHR 15
61 TSTI5
LGC 16
60 BCLKP
AGC 17
59 BCLKA
ATHR 18
58 MTYPE
AATT 19
57 DTHR
AHLD 20
56 MLV0
ACLP 21
55 MLV1
AHD 22
54 MLV2
MCK 50
MCKSL 49
TSTI3 48
TSTI4 47
SG 46
VDDA 45
CONTA 44
PCMLNI 43
IR 42
PCMADI 41
PCMACI 40
AATTG0 39
AATTG1 38
AATTG2 37
DG2 36
AATTL0 35
AATTL1 34
AATTL2 33
LATTG0 32
LATTG1 31
LATTG2 30
29
LATTL0
NC
28
51 NC
LATTL1
52 NC
NC 25
26
53 AG
ADCL 24
LATTL2 27
ACCL 23
NC: No-connect pin
100-Pin Plastic TQFP
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MSM7719-01
PIN FUNCTIONAL DESCRIPTION
SG
Outputs of the analog signal ground voltage.
The output voltage is approximately 2.4 V. Connect bypass capacitors of 10 mF and 0.1 mF
(ceramic type) between these pins and the AG pin. During power-down, the output changes
to 0 V.
AG
Analog ground.
DG1, 2, 3
Digital ground.
VDDA
+5 V power supply for analog circuits.
VDDD1, 2, 3
+5 V power supply for digital circuits.
PDN/RST
Power-down reset control input.
A logic “0” makes the LSI device enter a power-down state. At the same time, all control register
data are reset to the initial state. Set this pin to a logic “1” during normal operating mode. Since this pin
is ORed with CR0-B5 (bit 5 (B5) of control register CR0), set CR0-B5 to logic “0” when using this pin.
When this pin control is not used (i.e., when controlling by the control register), set this pin to logic
“1”.
PDWN
Power-down control input.
The device changes to the power-down state, and each bit of control register and internal variables
of control register are not reset when set to a logic “0”. During normal operation, set this pin to logic
“1”. Since this pin is ORed with CR0-B6 (bit 6 (B6) of control register CR0), set CR0-B6 to logic “0”
when using this pin. When this pin control is not used (i.e., when controlling by the control register),
set this pin to logic “1”.
MCK
Master clock input.
The frequency must be 9.6 to 10.0 MHz/19.2 to 20.0 MHz. The master clock signal is allowed to be
asynchronous with SYNCP, SYNCA, BCLKP, and BCLKA.
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MSM7719-01
MCKSL
Master clock selection input.
Set MCKSL to logic “0” when the master clock frequency is 9.6 to 10.0 MHz, and to logic “1”
when it is 19.2 to 20.0 MHz.
PCMACO
PCM data output of the echo canceler.
PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and
SYNCP.
This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic
“1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as
it is. In this case, this pin is in a high impedance state except during 4-bit output. Note that the echo
canceler signal output mode for this pin changes depending on the setting of IOSL0-1. (This pin is
also in a high impedance state during power-down or initial mode.)
Refer to Figs. 1-5.
PCMACI
PCM data input of the echo canceler.
PCM is shifted in at the falling edge of BCLKP and input from MSB.
The start of the PCM data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”,
this pin becomes a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is.
This pin is provided with a 500-kW pull-up resistor. Note that the echo canceler signal input mode
for this pin changes depending on the setting of IOSL0-1.
Refer to Figs. 1-5.
PCMADO
PCM data output.
PCM is serially output from MSB in synchronization with the rising edge of BCLKP and SYNCP.
This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic
“1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as
it is. In this case, this pin is in a high impedance state except during 4-bit output.
Note that the signal ouput mode for this pin changes and the I/O control signal for this pin switches
between BCLKA/SYNCA and BCLKP/SYNCP depending on the setting of IOSL0-1. (This pin is
also in a high impedance state during power-down or initial mode.)
Refer to Figs. 1-5.
PCMADI
PCM data input.
PCM is shifted in at the falling edge of the BCLKP signal and input from MSB. The start of the PCM
data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”, this pin becomes
a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided
with a 500-kW pull-up resistor. Note that the signal input mode for this pin changes and the I/O
control signal for this pin switches between BCLKA/SYNCA and BCLKP/SYNCP depending on
the setting of IOSL0-1.
Refer to Figs. 1-5.
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IOSL0-1
These pins specify PCM signal I/O mode for the PCMACO, PCMACI, PCMADO, and PCMADI
pins. Since The IOSL0 and IOSL1 pins are ORed with the control register bits CR3-B6 and B5, set
these bits to logic “0” before using these pins. When this pin control is not used (i.e., in the case of
control with the control register), set these pins to logic “0”.
Refer to Figs. 1-5.
IS
Transmit ADPCM data output.
This data is serially output from MSB in synchronization with the rising edge of BCLKA and SYNCA.
This pin is in a high impedance state except during 4-bit ADPCM output. When CONTA is set to
logic “1”, this pin becomes an 8-bit output and the data that passed through the ADPCM transcoder
is output. In this case, this pin is in a high impedance state except during 8-bit output.
(This pin is also in a high imedance state during power-down or initial mode.)
Refer to Figs. 1-5.
IR
Receive ADPCM data input.
ADPCM is shifted in on the rising edge of BCLKA in synchronization with SYNCA and input
data orderly from MSB. When CONTA is set to logic “1”, this pin becomes an 8-bit input and the
data is passed through the ADPCM transcoder and processed. This pin is provided with a 500-kW
pull-up resistor.
PCMLNO
PCM receive data output of the line echo canceler.
PCM is output from MSB in a sequential order, synchronizing with the rising edge of BCLKP and
SYNCP.
This pin is in a high impedance state except during 8-bit PCM output. When DTHR is set to logic
“1”, this pin becomes a 4-bit output and the input data to the input pin set by IOSL0-1 is output as
it is. In this case, this pin is in a high impedance state except during 4-bit output.
(This pin is also in a high impedance state during power-down or initial mode.)
Refer to Figs. 1-5.
PCMLNI
PCM transmit data input of the line echo canceler.
PCM is shifted in at the falling edge of the BCLKP signal and input from MSB. The start of the PCM
data (MSB) is identified at the rising edge of SYNCP. When DTHR is set to logic “1”, this pin becomes
a 4-bit input and the input data is output to the output pin set by IOSL0-1 as it is. This pin is provided
with a 500-kW pull-up resistor.
Refer to Figs. 1-5.
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BCLKA
Shift clock input for the ADPCM data (IS, IR).
The frequency is from 64 kHz to 2048 kHz.
SYNCA
8 kHz synchronous signal input for ADPCM data.
Synchronize this data with BCLKA signal. SYNCA is used for indicating the MSB of the serial
ADPCM data stream.
BCLKP
Shift clock input for the PCM data (PCMLNO/PCMLNI, PCMACO/PCMACI, PCMADO/
PCMADI). The frequency is set in the range of 64 kHz to 2048 kHz.
SYNCP
8 kHz synchronous signal input for PCM data.
This signal must be synchronized with the BCLKP signal.
MCUSL, MTYPE
If the microcontroller interface is not to be used, set the MCUSL input pin to logic “1”. This setting
skips the intitial mode as the operating mode. For the MTYPE pin, which is the microcontroller
interface selection pin, logic “0” sets the read/write independent control mode and logic “1” sets
read/write shared control mode.
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
CS, RD, WR
A 19-byte control register is provided in this LSI device. Data is read and written by using these pins
from the external microcontroller. See the microcontroller write and read timing diagrams in the
Electrical Characteristics.
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“1”.
A4-A0, D7-D0
A4-A0 are address input pins of the control register, and D7-D0 are data I/O pins.
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
INT
Reserved.
PCMSL
Reserved.
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CONTA
ADPCM transcoder setting pin. When this pin is set to logic “1”, the transcoder-through mode is
set. In this mode, the IS and IR pins become 8-bit PCM serial input and output pins. Since this pin
is ORed with the control register bit CR1-B7, set CR1-B7 to logic “0” to use this pin.
When this pin control is not used (i.e., when controlling by the control register), set this pin to logic
“0”.
Refer to Figs. 1-5.
DTHR
Through mode setting pin. When this pin is set to logic “1”, the entire circuit is put in the through
mode. In this mode, the PCM input and output pins become 4-bit serial input and output pins and
all functions of the echo canceler, ADPCM transcoder, and MUTEVOX are disabled. Use this pin
when making 32-kbps data communication.
Since this pin is ORed with the control register bit CR1-B5, set CR1-B5 to logic “0” to use this pin.
When this pin control is not used (i.e., when controlling by the control register), set this pin to logic
“0”.
Note that 64-kbps data communication is not supported in this device.
Refer to Figs. 1-5.
Echo
Canceler
(54ms)
Line
Echo
Canceler
(27ms)
(a)
(b)
(a)
Acoustic
Echo
Canceler
(27ms)
ADPCM
Transcoder
(b)
(c)
(c)
Output Control
(c)
SYNCP
Input Control
Input Control
Output Control
Output Control
Input Control
(b)
(c)
PCMLNO PCMLNI
Input Control
PCMACI
PCMACO
PCMADO
PCMADI
BCLKP
Output Control
(b)
IR
IS SYNCA
BCLKA
CR2-B3, B2
Figure 1 Signal I/O Control 1
IOSL1="0", IOSL0="0"
Control (a): ECMODE, CR0-B0
Control (b): CONTA, CR1-B7
Control (c): DTHR, CR1-B5
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Echo
Canceler
(54ms)
Line
Echo
Canceler
(27ms)
(a)
Acoustic
Echo
Canceler
(27ms)
ADPCM
Transcoder
(b)
(c)
SYNCP
(b)
(a)
(c)
Output Control
Input Control
Input Control
Output Control
(c)
(c)
(c)
(c)
PCMLNO PCMLNI
SYNCP
PCMACI PCMACO
Output Control
Input Control
Input Control
Output Control
(b)
(b)
IR
PCMADO PCMADI SYNCP
BCLKP
BCLKP
BCLKP
CR2-B3, B2
CR2-B1, B0
CR2-B4
IS SYNCA
BCLKA
Figure 2 Signal I/O Control 2
IOSL1="0", IOSL0="1"
Control (a): ECMODE, CR0-B0
Control (b): CONTA, CR1-B7
Control (c): DTHR, CR1-B5
(b)
Line
Echo
Canceler
(27ms)
Acoustic
Echo
Canceler
(27ms)
ADPCM
Transcoder
(b)
Output Control
Input Control
Input Control
Output Control
Output Control
Input Control
Input Control
PCMADO
PCMADI SYNCP
(b)
SYNCP
PCMLNO
PCMLNI SYNCP PCMACI
PCMACO
BCLKP
BCLKP
BCLKP
CR2-B3, B2
CR2-B1, B0
CR2-B4
Output Control
(b)
IR
IS
SYNCA
BCLKA
Figure 3 Signal I/O Control 3
IOSL1="1", IOSL0="0"
Control (a): ECMODE, CR0-B0
Control (b): CONTA, CR1-B7
Control (c): DTHR, CR1-B5
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¡ Semiconductor
(b)
Line
Echo
Canceler
(27ms)
Acoustic
Echo
(b)
Canceler
(27ms)
(c)
Output Control
(c)
SYNCP
PCMLNO
(c)
Input Control
Input Control
(c)
(c)
PCMLNI SYNCP
PCMACI
ADPCM
Transcoder
(c)
Output Control
Output Control
(c)
(c)
PCMACO
(c)
Input Control
(c)
PCMADO
PCMADI SYNCA
BCLKP
BCLKP
BCLKA
CR2-B3, B2
CR2-B1, B0
CR2-B4
Input Control
Output Control
(b)
(b)
IR
IS
SYNCA
BCLKA
Figure 4 Signal I/O Control 4
IOSL1="1", IOSL0="1"
Control (a): ECMODE, CR0-B0
Control (b): CONTA, CR1-B7
Control (c): DTHR, CR1-B5
SYNCP/SYNCA
BCLKP/BCLKA
PCM multiplexing
time slot 1
time slot 2
time slot 3
time slot 4
PCMADI/O data
(DTHR="0")
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
MSB
PCMADI/O data
(DTHR="1")
1 2 3 4
MSB
PCMLNI/O data
PCMACI/O data
(DTHR="0")
PCMLNI/O data
PCMACI/O data
(DTHR="1")
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
MSB
IR/IS data
1 2 3 4 5 6 7 8
MSB
(CONTA="1")
IR/IS data
(CONTA="0")
1 2 3 4
MSB
1 2 3 4
1 2 3 4
1 2 3 4
1 2 3 4
MSB
Note: The PCM signals (PCMADI and PCMADO) of the ADPCM transcoder can be assigned to
time slot 1 or 2.
The PCM signals (PCMLNI, PCMLNO, PCMACI, and PCMACO) of the echo canceler can
be assigned to one of the time slots 1 to 4.
The ADPCM signals (IR and IS) of the ADPCM transcoder are always assigned to time slot
1.
Figure 5 PCM Multiplexing/ADPCM Timing
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ECMODE
This pin specifies the operating mode of the echo canceler. When set to logic “0”, this device
operates as a line echo canceler (with cancelable echo delay time of 27 ms max.) + an acoustic echo
canceler (with cancelabel echo delay time of 27 ms max.); when set to logic “1”, it operates as a line
echo canceler (with cancelable echo delay time of 54 ms max.).
When this pin control is not used (i.e., when controlling by the control register), set these pins
to logic “0”.
LTHR, ATHR
(L: Line A: Acoustic)
These pins control the through mode of the echo canceler. In this mode, SinL/A data and RinL/A
data is output directly to SoutL/A and RoutL/A respectively, while retaining their echo canceler
coefficients.
0: Normal mode (Echo cancellation) 1: Through mode
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“1”.
LDCL, ADCL
These pins control clearing the coefficient 1 of the adaptive FIR filter used by the echo canceler. If
the echo path changes, reset both the coefficient 1 (by setting LDCL/ADCL to “0”) and the coefficient
2 (by setting LCCL/ACCL to “0”) of the adaptive FIR filter whenever possible.
0: Resets the coefficient 1: Normal operation
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“1”.
LCCL, ACCL
These pins control clearing the coefficient 2 of the adaptive FIR filter used by the echo canceler. If
the echo path changes, reset both the coefficient 1 (by setting LDCL/ADCL to “0”) and the coefficient
2 (by setting LCCL/ACCL to “0”) of the adaptive FIR filter whenever possible.
0: Resets the coefficient 1: Normal operation
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“1”.
LHD, AHD
Howling detection ON/OFF control pins.
0: OFF, 1: ON
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
LCLP, ACLP
These pins turn ON or OFF the Center Clipping funciton that forcibly sets the SoutL output of the
line echo canceler to minimum positive value when it is –57 dBm0 or less.
0: Center Clipping OFF
1: Center Clipping ON
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
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LHLD, AHLD
These pins control updating the coefficient of the adaptive FIR filter (AFF) for the echo canceler.
0: Normal mode (updates the coefficient)
1: Coefficient Fixed mode
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
LATT, AATT
These pins turn ON or OFF the ATT function that prevents howling from occurring by means of
attenuators ATTsL/A and ATTrL/A provided for the RinL/A input and the SoutL/A output of the
echo canceler.
When a signal is input to RinL/A only, the attenuator ATTsL/A of the SoutL/A output is activated.
When a signal is input to SinL/A only or to both SinL/A and RinL/A, the attenuator ATTrL/A of
the RinL/A input is activated. The ATT values are both about 6 dB.
0: ATT function ON
1: ATT function OFF
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
LGC, AGC
These pins turn ON or OFF the gain control function that controls the RinL/A input level and
prevents howling from occurring by the gain controller (GainL/A) provided for the RinL/A input
of the echo canceler. The RinL/A input level is adjusted in the attenuation range of 0 to –8.5 dB.
This adjusting starts at the RinL/A input level of –24 dBm0.
0: gain control OFF
1: gain control ON
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
MUTE
Receive side voice path mute level enable pin. To set a mute level, set this pin to logic “1”.
When this pin control is not used (i.e., when controlling by the control register), set this pin to logic
“0”.
MLV0-2
Receive side voice path mute level setting pins. For the control method, refer to the control register
(CR1) description. Since this signal is ORed with CR1-B2, B1, and B0 internally, set the bits of the
register to logic “0” before using these pins.
DETSL
Reserved pin.
Set this pin to logic “0”.
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DETT
Reserved pin.
Set this pin to logic “0”.
DETP
Reserved pin.
Set this pin to logic “0”.
LATTG2-0, AATTG2-0
Pad setting pins for the echo canceler's SoutL/A output gain.
Level
ATTG2
ATTG1
ATTG0
0 dB
0
0
0
2 dB
0
0
1
4 dB
0
1
0
6 dB
0
1
1
8 dB
1
0
0
10 dB
1
0
1
12 dB
1
1
0
14 dB
1
1
1
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
LATTL2-0, AATTL2-0
Pad setting pins for the echo canceler's SinL/A input loss.
Level
ATTL2
ATTL1
ATTL0
–0 dB
0
0
0
–2 dB
0
0
1
–4 dB
0
1
0
–6 dB
0
1
1
–8 dB
1
0
0
–10 dB
1
0
1
–12 dB
1
1
0
–14 dB
1
1
1
When this pin control is not used (i.e., when controlling by the control register), set these pins to logic
“0”.
TSTI1-6
Test input pins.
Tie to logic “0”.
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VOXO
Signal outut for transmit side VOX function.
This pin is effective when CR6-B7 is set to logic “1” (VOX ON).
The VOX function recognizes the presence or absence of the transmit voice signal by detecting the
level of the transmit signal to the line echo canceler. “1” and “0” levels set to this pin correspond to
the presence and the absence of voice, respectively. This result appears also at the register bit CR7B7. The signal energy detect threshold is set by the control register bits CR6-B6, B5.
The timing diagram of the VOX function is shown in Figure 3.
The transmit signal to the line echo canceler refers to the signal input to the PCMLNI pin.
Refer to Figure 6.
VOXI
Signal input for receive side (acoustic echo canceler Sin side) VOX function.
The “1” level at VOXI indicates the presence of a voice signal, the decoder block processes normal
receive signal, and the voice signal on the PCMACI pin goes through. The “0” level indicates the
absence of a voice signal and the background noise generated in this device is output.
The background noise amplitude is set by the control register CR6.
Because this signal is ORed with the register bit CR6-B3, set CR6-B3 to logic “0” when using this
pin.
When this pin control is not used (i.e., when controlling by the control register), set this pin to logic
“0”.
Refer to Figure 6.
Transmit Signal
PCMLNI
(shown as an
analog signal)
Voice
VOXO
Silence
Voice
TVXOFF
Silence
Detect (Hangover time)
TVXON
Voice
Detect
(a) Transmit Side VOX Function Timing Diagram
VOXI
Voice
Silence
Receive Signal
Decoded Time Period
Background
Noise
Voice
Receive Signal
Acoustic Echo
Canceler Sin
(shown as an
analog signal)
(b) Receive Side VOX Function Timing Diagram
Figure 6 VOX Function
14/40
MSM7719-01
¡ Semiconductor
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Condition
Rating
Unit
Power Supply Voltage
VDD
Digital Input Voltage
VDIN
—
–0.3 to +7.0
V
—
–0.3 to VDD + 0.3
V
Digital Output Voltage
VOUT
—
–0.3 to VDD + 0.3
V
TSTG
Storage Temperature
—
–55 to +150
°C
RECOMMENDED OPERATING CONDITIONS
Parameter
Power Supply Voltage
(VDD = 4.5 V to 5.5 V, Ta = –25°C to +70°C)
Max.
Min.
Typ.
Unit
Symbol
Condition
VDD
—
+4.5
—
–25
2.4
+5.5
V
+25
+70
°C
—
VDD+0.3
V
Operating Temperature
Ta
—
Input High Voltage
VIH
All digital inputs
Input Low Voltage
VIL
All digital inputs
0
—
0.8
V
Digital Input Rise Time
tIr
All digital inputs
—
—
5
ns
Digital Input Fall Time
tIf
Measurement point=0.8V&2.4V
—
—
5
ns
Master Clock Frequency
fMCK
Master Clock Duty Ratio
DC
MCK (When MCKSL="1")
MCK (When MCKSL="0")
–100 ppm
19.2-20.0
9.6-10.0
+100 ppm MHz
MCK
40
50
60
%
fBCK
BCLKP, BCLKA
64
—
2048
kHz
Synchronous Pulse Frequency (*1) fSYNC
SYNCP, SYNCA
—
8.0
—
kHz
DCK
BCLKP, BCLKA
40
50
60
%
100
—
—
ns
100
—
—
ns
—
—
100
ns
100
—
—
ns
100
—
—
ns
—
—
100
ns
1 BCLK
—
100
ms
Bit Clock Frequency
Clock Duty Cycle (*2)
tXS
Transmit Sync Pulse Setting Time
tSX
tXO
tRS
Receive Sync Pulse Setting Time
tSR
tRO
BCLKP to SYNCP,
BCLKA to SYNCA
SYNCP to BCLKP,
SYNCA to BCLKA
SYNCP to BCLKP,
SYNCA to BCLKA
BCLKP to SYNCP,
BCLKA to SYNCA
SYNCP to BCLKP,
SYNCA to BCLKA
SYNCP to BCLKP,
SYNCA to BCLKA
tWS
SYNCP, SYNCA
PCM, ADPCM Set-up Time
tDS
—
100
—
—
ns
PCM, ADPCM Hold Time
tDH
—
100
—
—
ns
Receive Sync Pulse Setting Time
*1
*2
If SYNCP and SYNCA are generated from different clocks, be sure to keep the relative
timing of the rising edges of SYNCP and SYNCA (that is, which rising edge is earlier) after
releasing the reset.
The recommended condition (values) for the clock duty cycle need not be observed if the clock
duty cycle fulfills the digital interface timing.
15/40
MSM7719-01
¡ Semiconductor
ELECTRICAL CHARACTERISTICS
DC Characteristics
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Parameter
Power Supply Current 1
Power Supply Current 2
Input Leakage current
High Level Digital
Output Voltage
Low Level Digital
Output Voltage
Digital Output
Leakage Current
Input Capacitance
Symbol
Condition
Min.
Typ.
Max.
Unit
—
50
80
mA
—
0.2
1
mA
VI= VDD
–10
—
+10
mA
VOH
IOH= –0.4 nA
4.2
—
VDD
V
VOL
IOL=3.2 mA
0
0.2
0.4
V
ILO
VI=VDD/0 V
—
—
10
mA
—
5
—
pF
Operating mode, no signal
IDD1
(VDD=5 V)
Power down mode
IDD2
(VDD=5 V, only the master clock is input)
IIL
—
CIN
Analog Interface Characteristics
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Min.
Typ.
Max.
Unit
SG Output Voltage
Parameter
Symbol
VSG
SG
Condition
2.35
2.4
2.45
V
SG Output Impedance
RSG
SG
—
40
80
kW
Reset Timing
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
tRSTW
—
1
—
—
ms
Reset Start Time
tRSTS
—
—
—
1
ms
Reset Termination Time
tRSTE
—
—
—
200
ms
Reset Signal Width
Note: Values in the table are common to the PDN/RST pin and the control register bit CR0-B5.
• Reset timing
tRSTW
PDN/RST
Internal
Processing
tRSTE
tRSTS
Reset
Initial mode
16/40
MSM7719-01
¡ Semiconductor
Echo Canceler Coefficient Reset Timing
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
tECRSTW
—
125
—
—
ms
Echo Canceler Reset Detection Time tECRSTD
—
0
—
125
ms
Echo Canceler Reset Operating Time
—
—
—
125
ms
Echo Canceler Reset Signal Width
tECRST
Note: Values in the table are common to the PDN/RST pin and the control register bit CR0-B5.
• Echo canceler coefficient reset timing
tECRSTW
LDCL
ADCL
LCCL
tECRSTD
tECRSTD
ACCL
Detect
(8 kHz sampling)
Reset
Echo canceler operating
Coefficient reset processing (tECRST)
Note : In the above timing, the LDCL, ADCL, LCCL, and ACCL register bits are active high, and
the LDCL, ADCL, LCCL, and ACCL pins are active low.
Control Pin Timing
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Control Signal Width
tSETUPW
—
125
—
—
ms
Control Signal Detection Time
tSETUPD
—
0
—
125
ms
Operation Start Time
tSETUPS
—
0
—
125
ms
Note: The control pins / register bits are as follows:
DETSL, DETT, DETP, (A/L)THR, (A/L)DCL, (A/L)CCL, (A/L)HLD, (A/L)ATT, (A/L) GC,
(A/L)ATTG2-0, (A/L)ATTL2-0, PCMSL, DTHR, IOSL0-1, CINTA, MUTE, MLV0-2
• Control pin timing
tSETUPW
Control Pin
tSETUPD
tSETUPD
Detect
(8 kHz sampling)
Internal Processing
tSETUPS
tSETUPS
Internal Processing
Internal Processing
17/40
MSM7719-01
¡ Semiconductor
Digital Interface Characteristics
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Digital Output Delay Time
tSDX, tSDR
0
—
100
ns
PCM, ADPCM Interface
tXD1, tRD1
0
—
100
ns
0
—
100
ns
0
—
100
ns
7
8
9
—
tXD2, tRD2
tXD3, tRD3
• PCM/ADPCM output timing
BCLKP
0
tXS
SYNCP
High-Z
tXO
1
tSX
2
tWS
tXD1
tXD2
3
4
5
6
tXD3
LSB
MSB
PCMO
10
High-Z
tSDX
BCLKA
0
tXS
SYNCA
IS
High-Z
tXO
1
tSX
2
tXD1
tXD2
3
4
5
6
7
tXD3
MSB
8
9
10
High-Z
LSB
tSDX
• PCM/ADPCM input timing
BCLKA
0
tRS
1
tSR
SYNCA
tRO
IR
MSB
BCLKP
0
tRS
SYNCP
2
4
5
6
7
8
9
10
5
6
7
8
9
10
tDS tDH
LSB
1
tSR
2
3
4
tWS
tRO
tDS
PCMI
3
tWS
MSB
tDH
LSB
18/40
MSM7719-01
¡ Semiconductor
AC Characteristics (Gain Settings)
Parameter
Transmit/Receive Gain
Setting Accuracy
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Symbol
Condition
Min. Typ. Max. Unit
For all gain set values
DG
–1
0
+1
dB
AC Characteristics (VOX Function)
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Parameter
Symbol
Transmit VOX Detection Time
Condition
VOXO pin:see Fig.6
Voice/silence
differential:10 dB
tVXON
SilenceÆvoice
(Voice Signal ON/OFF Detect Time) tVXOFF
VoiceÆsilence
Transmit VOX Detection Level
For detection level set values by
Accuracy (Voice Detection Level)
DVX
CR6-B6,B5
AC Characteristics (DTMF and Other Tones)
Parameter
Frequency Deviation
Tone Reference
Output Level (*1)
Relative Value of
DTMF Tones
*1
Min.
Typ.
Max.
—
5
—
Unit
ms
140/300 160/320 180/340
–2.5
0
ms
+2.5
dB
(VDD = 2.7 to 3.6 V, Ta = –25 to +70°C)
Symbol
Condition
Min. Typ. Max. Unit
DfT1
DTMF Tones
–1.5
—
+1.5
%
Other various tones
–1.5
—
+1.5
%
–10
–8
–6 dBm0
DfT2
VTL
Transmit side tone
VTH
(Gain set value:0dB) DTMF (High group), Others
VRL
Receive side tone
VRH
RDTMF
DTMF (Low group)
–8
–6
–4 dBm0
–10
–8
–6 dBm0
(Gain set value:0dB) DTMF (High group), Others
–8
–6
–4 dBm0
VTH/VTL, VRH/VRL
1
2
3
DTMF (Low group)
dB
Not including programmable gain set values
19/40
MSM7719-01
¡ Semiconductor
Microcontroller Interface (WR and RD Pins Controlled Independently)
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Parameter
Min.
Typ.
Max.
tCWS
30
—
—
tCWH
15
—
—
45
—
—
Data Input Setup Time
tWW
tDWS
30
—
—
Data Input Hold Time
tDWH
15
—
—
tCRS
30
—
—
tCRH
15
—
—
RD Pulse Width
tRW
45
—
—
Data Output Setup Time
tDOD
—
—
40
Data Output Hold Time
tDOH
0
—
—
Address and Chip Select Setup Time
(with respect to the falling edge of WR)
Address and Chip Select Setup Time
(with respect to the rising edge of WR)
WR Pulse Width
Address and Chip Select Setup Time
(with respect to the falling edge of RD)
Address and Chip Select Setup Time
(with respect to the rising edge of RD)
Symbol
Condition
MTYPE=0
Unit
ns
• Microcontroller write timing (WR and RD controlled independently)
A4-0
CS
tCWS
tWW
tCWH
WR
D7-0
High-Z
tDWS
tDOH
High-Z
• Microcontroller read timing (WR and RD controlled independently)
A4-0
CS
tCRS
tRW
tCRH
RD
D7-0
High-Z
tDOD
tDOH
High-Z
20/40
MSM7719-01
¡ Semiconductor
Microcontroller Interface (Shared Control of WR and RD Pins)
(VDD = 4.5 to 5.5 V, Ta = –25 to +70°C)
Parameter
Address Setup Time
(with respect to the falling edge of WR)
Address Setup Time
(with respect to the rising edge of WR)
WR Pulse Width
Address Setup Time
(with respect to the falling edge of CS)
Address Setup Time
(with respect to the rising edge of CS)
CS Pulse width
Min.
Typ.
Max.
tWRWS
30
—
—
tWRWH
15
—
—
tWRW
45
—
—
tCSWS
30
—
—
15
—
—
45
—
—
Symbol
Condition
tCSWH
MTYPE=1
tCSW
Data Input Setup Time
tDWS
30
—
—
Data Input Hold Time
tDWH
15
—
—
tCSRS
30
—
—
tCSRH
15
—
—
Data Output Delay Time
tDOD
—
—
40
Data Output Hold Time
tDOH
0
—
—
Address Setup Time
(with respect to the falling edge of CS)
Address Setup Time
(with respect to the rising edge of CS)
Unit
ns
• Microcontroller write timing (shared control of WR and RD)
A4-0
tCSWS
tCSWH
tCSW
CS
tWRWS
WR
D7-0
tWRWH
tWRW
High-Z
tDWS
tDWH
High-Z
• Microcontroller read timing (shared control of WR and RD)
A4-0
RD
tCSRS
tCSW
tCSRH
CS
D7-0
High-Z
tDOD
tDOH
High-Z
21/40
MSM7719-01
¡ Semiconductor
Echo return loss (E. R. L.) vs. echo attenuation
Conditions:
- Input level of white noise of –10 dBm, 3.4 kHz band at Rin
- Echo delay time: 2 ms
- ATT, GC, NLP: Off
E. R. L. vs. Echo Attenuation
40
Echo Attenuation [dB]
35
30
25
20
15
10
5
0
–40
–30
–20
–10
0
E. R. L. [dBm]
Rin input vs. echo attenuation
Conditions:
- Input level of 3.4 kHz-band white noise at Rin
- Echo delay time: 2 ms
E. R. L.=–6 dBm
- ATT, GC, NLP: Off
Rin Input Level vs. Echo Attenuation
40
Echo Attenuation [dB]
35
30
25
20
15
10
5
0
–50
–40
–30
–20
Rin Input Level [dBm]
–10
0
22/40
MSM7719-01
¡ Semiconductor
Echo delay time vs. echo attenuation
Conditions:
- Input level of white noise of –10 dBm, 3.4 kHz band at Rin
E. R. L.= –6 dBm
- ATT, GC, NLP: Off
ECMODE=27 ms
Echo Delay Time vs. Echo Attenuation
40
Echo Attenuation [dB]
35
30
25
20
15
10
5
0
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
55
60
65
70
Echo Delay Time [ms]
Conditions:
- Input level of white noise of –10 dBm, 3.4 kHz band at Rin
E. R. L.= –6 dBm
- ATT, GC, NLP: Off
ECMODE=54 ms
40
Echo Delay Time vs. Echo Attenuation
Echo Attenuation [dB]
35
30
25
20
15
10
5
0
0
5
10
15
20
25
30
35
40
45
50
Echo Delay Time [ms]
23/40
MSM7719-01
¡ Semiconductor
FUNCTIONAL DESCRIPTION
Control Registers
Table 1 Control Register Map
Address
Reg
Name A4 A3 A2 A1 A0
Contents
B7
B6
B5
—
PDWN
PDN/
RST
CONTA ADPCM
RESET
DTHR
B4
B3
B2
B1
B0
R/W
OPE
OPE
OPE
OPE
MODE3 MODE2 MODE1 MODE0 R/W
TX
RX
RX
RX
RX
MUTE MUTE
MLV2
MLV1
MLV0 R/W
PCM AD PCM LN PCM LN PCM AC PCM AC
SEL
SEL1
SEL0
SEL1
SEL0 R/W
CR0
0
0
0
0
0
CR1
0
0
0
0
1
CR2
0
0
0
1
0
—
—
—
CR3
0
0
0
1
1
PCMSL
IOSL1
IOSL0
CR4
0
0
1
0
0
CR5
0
0
1
0
1
CR6
0
0
1
1
0
CR7
0
0
1
1
1
CR8
0
1
0
0
0
LTHR
LDCL
LCCL
LHD
CR9
0
1
0
0
1
ATHR
ADCL
ACCL
AHD
CR10
0
1
0
1
0
—
—
—
CR11
0
1
0
1
1
LATTL2 LATTL1 LATTL0 LATTG2 LATTG1 LATTG0
—
—
R/W
CR12
0
1
1
0
0
AATTL2 AATTL1 AATTL0 AATTG2 AATTG1 AATTG0
—
—
R/W
CR13
0
1
1
0
1
A15
A14
A13
A12
A11
A10
A9
A8
R/W
CR14
0
1
1
1
0
A7
A6
A5
A4
A3
A2
A1
A0
R/W
CR15
0
1
1
1
1
D15
D14
D13
D12
D11
D10
D9
D8
R/W
CR16
1
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
CR17
1
0
0
0
1
—
—
—
—
—
—
—
—
R/W
CR18
1
0
0
1
0
—
—
—
—
—
—
—
—
R/W
—
—
DETSL
TX TONE TX TONE TX TONE TX TONE RX TONE
GAIN3 GAIN2 GAIN1 GAIN0 GAIN3
DTMF/OTHERS TX TONE RX TONE
SEL
SEND
SEND TONE4 TONE3
ON
OFF
VOX
VOX
ON
LVL0
TIME
IN
ON/OFF LVL1
DET
VOX Silence Level Silence Level
INT
CPT
OUT
1
0
DETAUTO
DETT
DETP
R/W
RX TONE RX TONE RX TONE
GAIN2 GAIN1 GAIN0 R/W
TONE2
TONE1
TONE0 R/W
RX. NOISE RX. NOISE RX. NOISE
LEVEL SEL
LVL1
LVL0 R/W
DET
DETL
DETA
R
DTMF
LCLP
LHLD
(NLP)* (ADP)*
ACLP
AHLD
(NLP)* (APD)*
LATT
(ATT)*
AATT
(ATT)*
LGC
R/W
(GC)*
AGC R/W
(GC)*
DMWR D TONE3 D TONE2 D TONE1 D TONE0 R/W
R/W : Read/Write enable R : Read only register
* : These are the symbols of control pins used in the MSM7602
(echo canceler LSI device).
24/40
MSM7719-01
¡ Semiconductor
(1)CR0 (Basic operating mode settings)
B7
B6
B5
B4
CR0
—
PDWN
PDN/RST
—
Initial value *
0
0
0
0
*:
B3
B2
B1
B0
OPE
OPE
OPE
OPE
MODE3
MODE2
MODE1
MODE0
0
0
0
0
Indicates the value to be set when a resetting is made through the PDN/RST pin. (Also when
reset by bit 5 (B5, PDN/RST), the other bits of CR0 are reset to initial values.)
B7 … Not used
B6 … Power-down (entire system)
0: Power-on 1: Power-down
ORed with the inverted external power-down signals
Set the PDWN pin to “1” when this register is used. The control registers and their internal
variables are retained.
B5 … Power-down reset (entire system)0: Power-on 1: Power-down reset
ORed with the inverted external power-down reset signals
Set the PDN/RST pin to “1” when this register is used. The control registers and their internal
variables are reset.
B4 … Not used
B3, 2, 1, 0 … Selection of an operating mode
(0, 0, 0, 0) : Initial mode
This mode enables a change (see Fig. 5) in memory that contains internal default values such
as tone generation frequencies.
In this mode, the PCM output pin acts to output idle patterns and the PCM input pin acts to
input idle patterns; the echo canceler and the ADPCM transcoder do not operate. When
power-down reset occurs or when power-down is released, the device enters the initial mode
about 200 ms after that. When the MCUSL pin is set to “1”, this mode is skipped. This mode
is released by setting any of the following modes:
(0, 1, 0, 0) : Handsfree conversation mode
The tone detector, the ADPCM encoder/decoder, the tone generator, the line echo canceler,
and the acoustic echo canceler become operative and can be controlled by the contents of the
control registers.
(0, 1, 0, 1) : Line echo canceler expansion mode
The tone detector, the ADPCM encoder/decoder, the tone generator, and the line echo
canceler (54 ms) become operative and can be controlled according to the contents of the
control registers.
(Others): Not used
This register is internally processed by a logical OR of the MCUSL pin and B2, and
between the ECMODE pin and B0.
25/40
MSM7719-01
¡ Semiconductor
(2) CR1 (Setting of ADPCM operating mode and PCM I/O signals)
B7
CR1
CONTA
Initial value
0
B6
ADPCM
RESET
0
B5
DTHR
0
B4
B3
B2
B1
B0
TX
RX
RX
RX
RX
MUTE
MUTE
MLV2
MLV1
MLV0
0
0
0
0
0
B7 … Control of through mode for the ADPCM CODEC
0: Normal mode 1: Through mode
This bit is valid when the CONTA pin is set to “0”.
B6 … Transmitter/receiver ADPCM resetting (conforming to G.721)
1: Reset
B5 … Control of through mode for transmit/receive signal (4-bit) through the entire circuit
0: Normal mode 1: Through mode
When set to “1”, the device enters the through mode for 4-bit transmit/receive signal through
the entire circuit, and the PCM input and output pins are configured to be 4-bit serial input and
output. All the functions of the echo canceler, ADPCM transcoder, MUTE, and VOX become
invalid. Use this bit when making 32-kbps data communication. Note that 64-kbps data
communication is not supported in this device.
B4 … Muting of transmitter ADPCM data 1: Mute
B3 … Muting of receiver ADPCM data
1: Muting specified by bits B2, B1, and B0 is enabled.
This bit is valid when the MUTE pin is set to “0”.
B2, B1, B0… Setting of a receiver voice path mute level
(MLV2, MLV1, MLV0) =
(0, 0, 0) :
(0, 0, 1) :
(0, 1, 0) :
(0, 1, 1) :
(1, 0, 0) :
(1, 0, 1) :
(1, 1, 0) :
(1, 1, 1) :
Through
– 6 dB
–12 dB
–18 dB
–24 dB
–30 dB
–36 dB
MUTE
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(3) CR2 (Setting of PCM I/O multiplex control)
CR2
Initial value
B7
B6
B5
—
—
—
0
0
0
B4
B3
B2
B1
B0
PCM AD
PCM LN
PCM LN
PCM AC
PCM AC
SEL
SEL1
SEL0
SEL1
SEL0
0
0
0
0
0
B7, 6, 5… Not used
B4 … PCM I/O multiplex timing control (PCMADI and PCMADO pins) of the ADPCM transcoder.
0: Time Slot 1 1: Time Slot 2
B3, 2 … PCM I/O multiplex timing control (PCMLNI, PCMLNO pins) of the line echo canceler (See
Table 2.)
B1, 0 … PCM I/O multiplex timing control (PCMACI and PCMACO pins) of the acoustic echo
canceler (See Table 2.)
Table 2 PCM Multiplex Timing Control Table
B3
(B1
B2
B0)
Corresponding time slot
0
0
1
0
1
2
1
0
3
1
1
4
Note : The outputs are all in high impedance state for all time slots from the time a resetting is made
to the initial mode.
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(4) CR3 (Setting of PCM signal I/O)
CR3
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
PCMSL
IOSL1
IOSL0
—
DETSL
DETAUTO
DETT
DETP
0
0
0
0
0
0
0
0
B7 … Reserved
B6, 5 … PCM signal I/O control (see Figs. 1 to 4)
B4 … Not used
B3, 2, 1, 0… Reserved
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(5) CR4 (Adjustment of tone generator gain)
CR4
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
TX TONE
TX TONE
TX TONE
TX TONE
RX TONE
RX TONE
RX TONE
RX TONE
GAIN3
GAIN2
GAIN1
GAIN0
GAIN3
GAIN2
GAIN1
GAIN0
0
0
0
0
0
0
0
0
B7, 6, 5, 4 ... Transmit side gain adjustment for the tone generator [ATTtgtx] (See Table 3.)
B3, 2, 1, 0 ... Receive side gain adjustment for the tone generator [ATTtgrx] (See Table 4.)
Table 3 Setting of Transmit Side Gain of Tone Generator
B7
B6
B5
B4
Tone generator gain
B7
B6
B5
B4
Tone generator gain
0
0
0
0
–36 dB
1
0
0
0
–20 dB
0
0
0
1
–34 dB
1
0
0
1
–18 dB
0
0
1
0
–32 dB
1
0
1
0
–16 dB
0
0
1
1
–30 dB
1
0
1
1
–14 dB
0
1
0
0
–28 dB
1
1
0
0
–12 dB
0
1
0
1
–26 dB
1
1
0
1
–10 dB
0
1
1
0
–24 dB
1
1
1
0
–8 dB
0
1
1
1
–22 dB
1
1
1
1
–6 dB
Table 4 Setting of Receive Side Gain of Tone Generator
B3
B2
B1
B0
Tone generator gain
B3
B2
B1
B0
Tone generator gain
0
0
0
0
–36 dB
1
0
0
0
–20 dB
0
0
0
1
–34 dB
1
0
0
1
–18 dB
0
0
1
0
–32 dB
1
0
1
0
–16 dB
0
0
1
1
–30 dB
1
0
1
1
–14 dB
0
1
0
0
–28 dB
1
1
0
0
–12 dB
0
1
0
1
–26 dB
1
1
0
1
–10 dB
0
1
1
0
–24 dB
1
1
1
0
–8 dB
0
1
1
1
–22 dB
1
1
1
1
–6 dB
Settings of Table 4 are made in relation to the following tone levels:
DTMF tone (Low frequency group)
: –2 dBm0
DTMF tone (High frequency group) and other tone : 0 dBm0
For example, when bits B3, B2, B1, and B0 are set to “1, 1, 1, 1” (–6 dB), the PCMLNO pin outputs a
tone of the following levels:
DTMF tone (Low frequency group)
: –8 dBm0
DTMF tone (High frequency group) and other tone : –6 dBm0
The default value change command enables the gain adjustment by –1 dB step.
Writing “390Ah” into the address 16Dh adds a gain of –1 dB to the values in the above table. The
default value is “4000h”.
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(6) CR5 (Setting of tone generator operating mode and tone frequency)
B7
B6
DTMF/OTHERS TX TONE
CR5
B5
RX TONE
SEL
SEND
SEND
0
0
0
Initial value
B4
B3
B2
B1
B0
TONE4
TONE3
TONE2
TONE1
TONE0
0
0
0
0
0
B7 … Selection of DTMF signal and S stone
0: Others 1: DTMF signal
B6 … Transmission of transmit side tone
0: Not transmit 1: Transmit
B5 … Transmission of receive side tone
0: Not transmit 1: Transmit
B4, 3, 2, 1, 0… Setting of a tone frequency (See Table 5.)
Table 5 Setting of Tone Generator Frequencies
(a) When B7 = “1” (DTMF tone)
B4 B3 B2 B1 B0
Description
B4 B3 B2 B1 B0
Description
*
0
0
0
0
697 Hz + 1209 Hz (1)
*
1
0
0
0
852 Hz + 1209 Hz (7)
*
0
0
0
1
697 Hz + 1336 Hz (2)
*
1
0
0
1
852 Hz + 1336 Hz (8)
*
0
0
1
0
697 Hz + 1477 Hz (3)
*
1
0
1
0
852 Hz + 1477 Hz (9)
*
0
0
1
1
697 Hz + 1633 Hz (A)
*
1
0
1
1
852 Hz + 1633 Hz (C)
*
0
1
0
0
770 Hz + 1209 Hz (4)
*
1
1
0
0
941 Hz + 1209 Hz (*)
*
0
1
0
1
770 Hz + 1336 Hz (5)
*
1
1
0
1
941 Hz + 1336 Hz (0)
*
0
1
1
0
770 Hz + 1477 Hz (6)
*
1
1
1
0
941 Hz + 1477 Hz (#)
*
0
1
1
1
770 Hz + 1633 Hz (B)
*
1
1
1
1
941 Hz + 1633 Hz (D)
(b) When B7 = “0” (Others)
The table below lists default frequencies. Eight tones from “10000” to “10111” are single tones. For
procedures to change frequencies, see the next page.
B4 B3 B2 B1 B0
Description
B4 B3 B2 B1 B0
Description
0
0
0
0
0
—
1
0
0
0
0
400 Hz Single tone
0
0
0
0
0
—
1
0
0
0
1
1000 Hz Single tone
0
0
0
1
0
—
1
0
0
0
1
2000 Hz Single tone
0
0
0
1
1
—
1
0
0
1
1
2667 Hz Single tone
0
0
1
0
0
—
1
0
1
0
0
1300 Hz Single tone
0
0
1
0
1
—
1
0
1
0
1
2080 Hz Single tone
0
0
1
1
0
—
1
0
1
1
0
*Hz Single tone
0
0
1
1
1
—
1
0
1
1
1
*Hz Single tone
0
1
0
0
0
—
1
1
0
0
0
—
0
1
0
0
1
—
1
1
0
0
1
—
1
1
0
1
0
—
0
1
0
1
0
—
0
1
0
1
1
—
1
1
0
1
1
—
0
1
1
0
0
—
1
1
1
0
0
—
0
1
1
0
1
—
1
1
1
0
1
—
0
1
1
1
0
—
1
1
1
1
0
—
0
1
1
1
1
—
1
1
1
1
1
—
* User specified frequency (see Table 6)
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Frequencies of tones (other than DTMF signals) to be generated by the tone generator can be changed.
Tone frequencies can be changed in the Initial mode. See Figure 8 for procedures to change tone
frequencies. The related subaddresses are shown below.
Note: Transmitted Tone Frequency = A ¥ 8.192 (A = frequency)
ex. When frequency = 1000 Hz, 1000 ¥ 8.192 = 9011.2 = 9011d (eliminate after the decimal point) =
2333h
Table 6 Tone Generator Subaddresses
Single tone
B4 B3 B2 B1 B0
Subaddress 1
(Frequency 1)
(See Note above)
1
0
0
0
0
178h
1
0
0
0
1
179h
1
0
0
1
0
17Ah
1
0
0
1
1
17Bh
1
0
1
0
0
17Ch
1
0
1
0
1
17Dh
1
0
1
1
0
17Eh
1
0
1
1
1
17Fh
Transmit single tone
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(7)CR6 (VOX function control)
CR6
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
VOX
ON
ON
OFF
VOX
RX. NOISE
RX. NOISE
RX. NOISE
ON/OFF
LVL1
LVL0
TIME
IN
LEVEL SEL
LVL1
LVL0
0
0
0
0
0
0
0
0
B7 … Turns ON or OFF the VOX function 0: OFF, 1: ON
B6,5 …Setting of transmit side voice or silence detection level
(0, 0) : –20 dBm0
(0, 1) : –25 dBm0
(1, 0) : –30 dBm0
(1, 1) : –35 dBm0
Note: • The detection level is changeable by inserting the pad of –1dB to –5dB in addion to the alove
values.
• Write 16384 ¥ 10(–A/20) at address “2DEh”.
Example: When –1dB pad is inserted, 16384 ¥ 10(– (–1)/20)
=18383.15=18383d (eliminate after the decimal point)=47CFh
B4 … Setting of hangover time (TVXOFF) (See Figure 6.)
0: 160 ms 1: 320 ms
B3 … VOX input signal (receiver side)
0: Transmits an internal background noise.
1: Transmits a voice reception signal.
Set the VOXI pin to “0” to use this data.
B2 … Setting of a receiver side background noise level
0: Reserved
B1, 0… Externally-set background noise level
(0, 0) : No noise
(0, 1) : –55 dBm0
(1, 0) : –45 dBm0
(1, 1) : –35 dBm0
(8) CR7 (Detection register : read-only)
B7
CR7
Initial value
VOX
B6
B5
Silence level Silence level
OUT
1
0
0
0
0
B4
INT
0
B3
DET
B2
DET
CPT
DTMF
0
0
B1
B0
DETL
DETA
0
0
B7… Detection of transmit side voice or noise
0: Silence 1: Voice
B6, 5… Transmit side silence level (Indicator)
(0, 0) : –10dB or less with respect to the detection level defined by CR6-B6, B5.
(0, 1) : –5 to –10 dB with respect to the detection level defined by CR6-B6, B5.
(1, 0) : –0 to –5 dB with respect to the detection level defined by CR6-B6, B5.
(1, 1) : –0 dB or more with respect to the detection level defined by CR6-B6, B5.
Note : The above outputs are valid only when the VOX function is enabled by bit 7 of CR6.
B4, 3, 2, 1, 0 … Reserved
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(9) CR8 (Setting of line echo canceler operating mode)
B7
CR8
Initial value
B6
B5
B4
LTHR
LDCL
LCCL
LHD
1
0
0
0
B3
B2
B1
B0
LCLP
LHLD
LATT
LGC
(NLP)*1
(ADP)*1
(ATT)*1
(GC)*1
0
0
0
0
*1 Name of a control pin used by the MSM7602
B7 … Through mode control bit for the line echo canceler
In this mode, RinL data and SinL data is output directly to RoutL and SoutL respectively.
The coefficient is not cleared.
1: Through mode 0: Normal mode (echo cancellation)
B6 … Selects whether or not to clear the coefficient 1 of the adaptive FIR filter (LAFF) used by
the line echo canceler.
1: Resets the coefficient
0: Normal operation
B5 … Selects whether or not to clear the coefficient 2 of the adaptive FIR filter (LAFF) used by
the line echo canceler.
1: Resets the coefficient
0: Normal operation
B4 … Howling detector (HD) ON/OFF control
1: ON 0: OFF
B3 … Turns ON or OFF the Center Clipping function which forcibly sets the SoutL output of the line
echo canceler to minimum positive value when it is –57 dBm0 or less.
1: Center Clipping ON
0: Center Clipping OFF
B2 … Selects whether or not to update the coefficient of the adaptive FIR filter (LAFF) for the line
echo canceler.
1: Coefficient Fixed mode
0: Normal mode (updates the coefficient.)
B1 … Turns ON or OFF the ATT function which prevents howling from occurring by means of
attenuators ATTsL and ATTrL provided for the RinL input and the SoutL output of the line
echo canceler.
When a signal is input to RinL only, the attenuator ATTsL of the SoutL output is activated.
When a signal is input to SinL only or to both SinL and RinL, the attenuator ATTrL of the RinL
input is activated. Their ATT values are both about 6 dB.
1: ATT function OFF
0: ATT function ON
B0 … Turns ON or OFF the gain control function which controls the RinL input level and
prevents howling from occurring by the gain controller (GainL) for the RinL input of the line
echo canceler.
The RinL/A input level is adjusted in the attenuation range of 0 to –8.5 dB. This adjusting starts
at the RinL/A input level of –24 dBm0.
1: Gain control function ON
0: Gain control function OFF
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(10) CR9 (Setting of acoustic echo canceler operating mode)
B7
CR9
Initial value
B6
B5
B4
ATHR
ADCL
ACCL
AHD
1
0
0
0
B3
B2
B1
B0
ACLP
AHLD
AATT
AGC
(NLP)*1
(ADP)*1
(ATT)*1
(GC)*1
0
0
0
0
*1 Name of a control pin used by the MSM7602
B7 … Through mode control bit for acoustic echo canceler.
In this mode, RinA data and SinA data is output directly to RoutL and SoutL respectively.
The coefficient is not cleared.
1: Through mode 0: Normal mode (echo cancellation)
B6 … Selects whether or not to clear the coefficient 1 of the adaptive FIR filter (AAFF) for the
acoustic echo canceler.
1: Resets the coefficient 0: Normal operation
B5 … Selects whether or not to clear the coefficient 2 of the adaptive FIR filter (AAFF) for the
acoustic echo canceler.
1: Resets the coefficient 0: Normal operation
B4 … Howling detector (HD) ON/OFF control
1: ON 0: OFF
B3 … Turns ON or OFF the Center Clipping function which forcibly sets the Sout output of the
acoustic echo canceler to a minimum positive value when it is –57 dBm0 or less.
1: Center Clipping ON
2: Center Clipping OFF
B2 … Selects whether or not to update the coefficient of the adaptive FIR filter (AAFF) for the
acoustic echo canceler.
1: Coefficient fixed mode
0: Normal mode (updates the coefficient.)
B1 … Turns ON or OFF the ATT function which prevents howling from occurring by means of
attenuators ATTrA and ATTsA provided for the RinA input and the SoutA output of the
acoustic echo canceler.
When a signal is input to RinA only, the attenuator ATTsA of the SoutA output is
activated. When a signal is input to SinA only or to both SinA and RinA, the attenuator ATTrA
of the RinA input is activated. Their ATT values are both about 6 dB.
1: ATT function OFF
0: ATT function ON
B0 … Turns ON or OFF the gain control function which controls the RinA input level and
prevents howling from occurring by the gain controller (GainA) for the RinA input of the
acoustic echo canceler.
The RinL/A input level is adjusted in the attenuation range of 0 to –8.5 dB. This adjusting starts
at the RinL/A input level of –24 dBm0.
1: Gain control ON
0: Gain control OFF
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(11) CR10 (Tone detection frequency)
CR10
B7
B6
B5
B4
—
—
—
DMWR
B3
D TONE3
B2
D TONE2
B1
D TONE1
B0
D TONE0
0
0
0
0
0
0
0
0
Initial value
B7, 6, 5 ... Not used
B4 ... Controls changing the default value in default store memory
1: Write
Writes the 16-bit data that is set in CR15 (D15-D8) and CR16 (D7-D0) into the 16-bit addresses
that are set in CR13 (A15-A8) and CR14 (A7-A0)
B3, 2, 1, 0 ... Reserved
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(12) CR11 (Transmit side pad control)
CR11
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
LATTL2
LATTL1
LATTL0
LATTG2
LATTG1
LATTG0
—
—
0
0
0
0
0
0
0
0
B7, 6, 5 ... Setting of pad for transmit loss
(0, 0, 0) : 0 dB
(0, 0, 1) : –2 dB
(0, 1, 0) : –4 dB
(0, 1, 1) : –6 dB
(1, 0, 0) : –8 dB
(1, 0, 1) : –10 dB
(1, 1, 0) : –12 dB
(1, 1, 1) : –14 dB
B4, 3, 2 ... Setting of pad for transmit gain
(0, 0, 0) : 0 dB
(0, 0, 1) : 2 dB
(0, 1, 0) : 4 dB
(0, 1, 1) : 6 dB
(1, 0, 0) : 8 dB
(1, 0, 1) : 10 dB
(1, 1, 0) : 12 dB
(1, 1, 1) : 14 dB
(13) CR12 (Receive side pad control)
CR12
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
AATTL2
AATTL1
AATTL0
AATTG2
AATTG1
AATTG0
—
—
0
0
0
0
0
0
0
0
B7, 6, 5 ... Setting of pad for receive loss
(0, 0, 0) : 0 dB
(0, 0, 1) : –2 dB
(0, 1, 0) : –4 dB
(0, 1, 1) : –6 dB
(1, 0, 0) : –8 dB
(1, 0, 1) : –10 dB
(1, 1, 0) : –12 dB
(1, 1, 1) : –14 dB
B4, 3, 2 ... Setting of pad for receive gain
(0, 0, 0) : 0 dB
(0, 0, 1) : 2 dB
(0, 1, 0) : 4 dB
(0, 1, 1) : 6 dB
(1, 0, 0) : 8 dB
(1, 0, 1) : 10 dB
(1, 1, 0) : 12 dB
(1, 1, 1) : 14 dB
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(14) CR13, 14, 15, 16 (Default value store registers)
CR13
Initial value
CR14
Initial value
CR15
Initial value
CR16
Initial value
B7
B6
B5
B4
B3
B2
B1
B0
A15
A14
A13
A12
A11
A10
A9
A8
0
0
0
0
0
0
0
0
B7
B6
B5
B4
B3
B2
B1
B0
A7
A6
A5
A4
A3
A2
A1
A0
0
0
0
0
0
0
0
0
B7
B6
B5
B4
B3
B2
B1
B0
D15
D14
D13
D12
D11
D10
D9
D8
0
0
0
0
0
0
0
0
B7
B6
B5
B4
B3
B2
B1
B0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
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Direct Access to Default Store Memory
The contents of the default store memory can be
changed (e.g., to change tone detection levels
and tone generation frequencies) in the initial
mode (CR0-B3 to CR0-B0=“0000”).
Refer to the following procedure:
• Set the default value store memory address
(CR13, CR14).
• Set the write data into CR15 and CR16.
• Set the DMWR (change default) command
(CR10-B4=“1”).
Default Value Store Memory
Direct Access
Set address.
Set write data.
Set command to
write in upper byte
(DMWR)
Yes
(1) CR13, CR14
CR15, CR16
(2) CR10
Continue to
write?
No
END
Figure 8 Flow Chart of Default Value Store
Memory Direct Access
Default Value Store
Memory
Data (CR15, CR16)
Address (CR13, CR14)
Figure 7 Memory Map for Default Value Store Memory Direct Access
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Resetting of Echo Canceler Coefficient
In cases where an echo path changes, the echo canceler may be slow in converging. In such cases,
resetting the coefficient of the echo canceler can force it to converge immediately.
In addtion, if the echo path changes after the coefficient is reset, the echo canceler may again be slow
in converging.
There are four resetting modes available, as shown in the table below. If an echo path changes,
execute coefficient reset both by LDCL/ADCL and by LCCL/ACCL pin control (Reset 3) whenever
possible, because resetting by both of them do not affect any echo path state.
Control
No reset (LTHR/ATHR)
Echo Convergence Time
Degree of Effect
on Echo Route
Fast
Significant
Slow
No effect
Reset 1 (LDCL/ADCL)
Reset 2 (LCCL/ACCL)
Reset 3 (both LDCL/ADCL and LCCL/ACCL)
Notes on Data Communication
Use the following setting when making data communication:
For 4-bit (32 kbps) data communication:
DTHR=“1” (common to handsfree communication mode and line echo canceler expansion
mode)
Notes:
1. The MSM7719 does not support 8-bit (64 kbps) data communication.
2. Data dropouts or a data error of a few SYNCs occurs upon switching between data
communication and voice communication.
3. Of the voice data through modes, ATHR and LTHR converts PCM data “7Fh” into “FFh”.
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PACKAGE DIMENSIONS
(Unit : mm)
TQFP100-P-1414-0.50-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.55 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
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