Complete 12-Bit, 25 MSPS Monolithic A/D Converter AD9225 FEATURES Monolithic 12-Bit, 25 MSPS ADC Low Power Dissipation: 280 mW Single 5 V Supply No Missing Codes Guaranteed Differential Nonlinearity Error: 0.4 LSB Complete On-Chip Sample-and-Hold Amplifier and Voltage Reference Signal-to-Noise and Distortion Ratio: 71 dB Spurious-Free Dynamic Range: –85 dB Out-of-Range Indicator Straight Binary Output Data 28-Lead SOIC 28-Lead SSOP Compatible with 3 V Logic GENERAL DESCRIPTION The AD9225 is a monolithic, single-supply, 12-bit, 25 MSPS analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier and voltage reference. The AD9225 uses a multistage differential pipelined architecture with output error correction logic to provide 12-bit accuracy at 25 MSPS data rates, and guarantees no missing codes over the full operating temperature range. The AD9225 combines a low cost, high speed CMOS process and a novel architecture to achieve the resolution and speed of existing bipolar implementations at a fraction of the power consumption and cost. The input of the AD9225 allows for easy interfacing to both imaging and communications systems. With the device’s truly differential input structure, the user can select a variety of input ranges and offsets, including single-ended applications. The dynamic performance is excellent. The sample-and-hold amplifier (SHA) is well suited for both multiplexed systems that switch full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to and well beyond the Nyquist rate. FUNCTIONAL BLOCK DIAGRAM CLK AVDD DRVDD SHA VINA MDAC1 GAIN = 16 VINB ADC CAPT 5 MDAC2 GAIN = 4 3 ADC 5 MDAC3 GAIN = 4 ADC 3 3 ADC 4 3 CAPB DIGITAL CORRECTION LOGIC VREF 12 OUTPUT BUFFERS OTR SENSE MODE SELECT 1V AD9225 REFCOM AVSS DRVSS BIT 1 (MSB) BIT 12 (LSB) CML A single clock input is used to control all internal conversion cycles. The digital output data is presented in straight binary output format. An out-of-range signal indicates an overflow condition that can be used with the most significant bit to determine low or high overflow. PRODUCT HIGHLIGHTS The AD9225 is fabricated on a very cost effective CMOS process. High speed precision analog circuits are combined with high density logic circuits. The AD9225 offers a complete, single-chip sampling, 12-bit, 25 MSPS analog-to-digital conversion function in 28-lead SOIC and SSOP packages. Low Power—The AD9225 at 280 mW consumes a fraction of the power presently available in monolithic solutions. On-Board Sample-and-Hold Amplifier (SHA)—The versatile SHA input can be configured for either single-ended or differential inputs. Out-of-Range (OTR)—The OTR output bit indicates when the input signal is beyond the AD9225’s input range. The AD9225’s wideband input, combined with the power and cost savings over previously available monolithics, suits applications in communications, imaging, and medical ultrasound. Single Supply—The AD9225 uses a single 5 V power supply, simplifying system power supply design. It also features a separate digital driven supply line to accommodate 3 V and 5 V logic families. The AD9225 has an on-board programmable reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of an application. Pin Compatibility—The AD9225 is pin compatible with the AD9220, AD9221, AD9223, and AD9224 ADCs. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/461-3113 ©1998-2011 Analog Devices, Inc. All rights reserved. AD9225* PRODUCT PAGE QUICK LINKS Last Content Update: 02/23/2017 COMPARABLE PARTS REFERENCE MATERIALS View a parametric search of comparable parts. Technical Articles DOCUMENTATION • Correlating High-Speed ADC Performance to Multicarrier 3G Requirements Application Notes • DNL and Some of its Effects on Converter Performance • AN-1142: Techniques for High Speed ADC PCB Layout • MS-2210: Designing Power Supplies for High Speed ADC • AN-501: Aperture Uncertainty and ADC System Performance DESIGN RESOURCES • AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated • AD9225 Material Declaration • AN-737: How ADIsimADC Models an ADC • Quality And Reliability • AN-741: Little Known Characteristics of Phase Noise • Symbols and Footprints • AN-742: Frequency Domain Response of SwitchedCapacitor ADCs • PCN-PDN Information DISCUSSIONS • AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter View all AD9225 EngineerZone Discussions. • AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs SAMPLE AND BUY • AN-835: Understanding High Speed ADC Testing and Evaluation Visit the product page to see pricing options. Data Sheet TECHNICAL SUPPORT • AD9225: Complete, 12-Bit, 25 MSPS Monolithic A/D Converter Data Sheet Submit a technical question or find your regional support number. DOCUMENT FEEDBACK Submit feedback for this data sheet. This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified. AD9225–SPECIFICATIONS DC SPECIFICATIONS (AVDD = 5 V, DRVDD = 5 V, fSAMPLE = 25 MSPS, VREF = 2.0 V, VINB = 2.5 V dc, TMIN to TMAX, unless otherwise noted.) Parameter Min Typ RESOLUTION 12 Bits MAX CONVERSION RATE 25 MHz INPUT REFERRED NOISE VREF = 1.0 V VREF = 2.0 V 0.35 0.17 ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes Zero Error (@ 25∞C) Gain Error (@ 25∞C)1 Gain Error (@ 25∞C)2 ± 1.0 ± 0.4 12 ± 0.3 ± 0.5 ± 0.4 TEMPERATURE DRIFT Zero Error Gain Error1 Gain Error2 ±2 ± 26 ± 0.4 POWER SUPPLY REJECTION AVDD (+5 V ± 0.25 V) ± 0.1 ANALOG INPUT Input Span Input Capacitance INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Output Voltage Tolerance (1 V Mode) Output Voltage (2.0 V Mode) Output Voltage Tolerance (2.0 V Mode) Output Current (Available for External Loads) Load Regulation3 1.0 ±5 2.0 ± 10 1.0 1.0 REFERENCE INPUT RESISTANCE 8 4.75 2.85 POWER CONSUMPTION External Reference Internal Reference Unit LSB rms LSB rms ± 2.5 ± 1.0 ± 0.6 ± 2.2 ± 1.7 LSB LSB Bits Guaranteed % FSR % FSR % FSR ppm/∞C ppm/∞C ppm/∞C ± 0.35 2 4 0 AVDD 10 Input (VINA or VINB) Range POWER SUPPLIES Supply Voltages AVDD DRVDD Supply Currents IAVDD IDRVDD Max % FSR V p-p V p-p V V pF ± 17 ± 35 3.4 V mV V mV mA mV kW 5 5.25 5.25 V (± 5% AVDD Operating) V (± 5% DRVDD Operating) 65 2.0 72.5 4.0 mA mA 280 335 290 345 310 373 mW (VREF = 1 V) mW (VREF = 2 V) mW (VREF = 1 V) mW (VREF = 2 V) NOTES 1 Includes internal voltage reference error. 2 Excludes internal voltage reference error. 3 Load regulation with 1 mA load current (in addition to that required by the AD9225). Specifications subject to change without notice. –2– Rev. C AD9225 AC SPECIFICATIONS (AVDD = 5 V, DRVDD = 5 V, fSAMPLE = 25 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted.) Parameter Min Typ Max Unit SIGNAL-TO-NOISE AND DISTORTION RATIO (S/N+D) fINPUT = 2.5 MHz 67.4 fINPUT = 10 MHz 66.7 70.7 69.6 dB dB SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 2.5 MHz fINPUT = 10 MHz 71 70 dB dB 69.0 68.2 TOTAL HARMONIC DISTORTION (THD) fINPUT = 2.5 MHz fINPUT = 10 MHz SPURIOUS FREE DYNAMIC RANGE fINPUT = 2.5 MHz fINPUT = 10 MHz Full Power Bandwidth Small Signal Bandwidth Aperture Delay Aperture Jitter Acquisition to Full-Scale Step –82 –81 73 72.5 –72 –71.5 –85 –83 105 105 1 1 10 dB dB dB dB MHz MHz ns ps rms ns Specifications subject to change without notice. DIGITAL SPECIFICATIONS (AVDD = 5 V, DRVDD = 5 V, unless otherwise noted.) Parameter Symbol Min LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = DRVDD) Low Level Input Current (VIN = 0 V) Input Capacitance VIH VIL IIH IIL CIN 3.5 LOGIC OUTPUTS High Level Output Voltage (IOH = 50 mA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 mA) Output Capacitance VOH VOH VOL VOL COUT 4.5 2.4 LOGIC OUTPUTS (with DRVDD = 3 V) High Level Output Voltage (IOH = 50 mA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 mA) VOH VOH VOL VOL 2.95 2.80 Typ Max Unit 1.0 +10 +10 5 V V mA mA pF 5 V V V V pF –10 –10 0.4 0.1 0.4 0.05 V V V V Max Unit Specifications subject to change without notice. SWITCHING SPECIFICATIONS (TMIN to TMAX with AVDD = 5 V, DRVDD = 5 V, CL = 20 pF) Parameter Symbol Min Clock Period* CLOCK Pulse Width High CLOCK Pulse Width Low Output Delay Pipeline Delay (Latency) tC tCH tCL tOD 40 18 18 13 3 *The clock period may be extended to 1 ms without degradation in specified performance @ 25 ∞C. Specifications subject to change without notice. Rev. C Typ –3– ns ns ns ns Clock Cycles AD9225 ABSOLUTE MAXIMUM RATINGS* Pin Name AVDD DRVDD AVSS AVDD REFCOM CLK Digital Outputs VINA, VINB VREF SENSE CAPB, CAPT Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to Min Max Unit AVSS DRVSS DRVSS DRVDD AVSS AVSS DRVSS AVSS AVSS AVSS AVSS –0.3 –0.3 –0.3 –6.5 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 –0.3 +6.5 +6.5 +0.3 +6.5 +0.3 AVDD + 0.3 DRVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 150 +150 300 V V V V V V V V V V V ∞C ∞C ∞C –65 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. S1 ANALOG INPUT S2 tCH tC PIN CONFIGURATION 28-Lead SOIC and SSOP S4 tCL S3 INPUT CLOCK tOD DATA OUTPUT DATA 1 Figure 1. Timing Diagram CLK 1 28 DRVDD (LSB) BIT 12 2 27 DRVSS BIT 11 3 26 AVDD BIT 10 4 25 AVSS BIT 9 5 24 VINB BIT 8 6 23 VINA AD9225 TOP VIEW 22 CML BIT 6 8 (Not to Scale) 21 CAPT BIT 7 7 BIT 5 9 20 CAPB BIT 4 10 19 REFCOM BIT 3 11 18 VREF BIT 2 12 17 SENSE (MSB) BIT 1 13 16 AVSS OTR 14 15 AVDD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9225 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. –4– Rev. C AD9225 PIN FUNCTION DESCRIPTIONS Pin Number Mnemonic Description 1 2 3–12 13 14 15, 26 16, 25 17 18 19 20 21 22 23 24 27 28 CLK BIT 12 BIT 11–2 BIT 1 OTR AVDD AVSS SENSE VREF REFCOM CAPB CAPT CML VINA VINB DRVSS DRVDD Clock Input Pin Least Significant Data Bit (LSB) Data Output Bit Most Significant Data Bit (MSB) Out of Range 5 V Analog Supply Analog Ground Reference Select Input Span Select (Reference I/O) Reference Common (AVSS) Noise Reduction Pin Noise Reduction Pin Common-Mode Level (Midsupply) Analog Input Pin (+) Analog Input Pin (–) Digital Output Driver Ground 3 V to 5 V Digital Output Driver Supply Aperture Delay TERMINOLOGY Integral Nonlinearity (INL) Aperture delay is a measure of the sample-and-hold amplifier (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. INL refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. The point used as negative full scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Signal-to-Noise and Distortion Ratio (S/N+D, SINAD) S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Differential Nonlinearity (DNL, No Missing Codes) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. Effective Number of Bits (ENOB) For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, N = (SINAD – 1.76)/6.02 Zero Error it is possible to get a measure of performance expressed as N, the effective number of bits. The major carry transition should occur for an analog value 1/2 LSB below VINA = VINB. Zero error is defined as the deviation of the actual transition from that point. The effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Gain Error The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) Temperature Drift The temperature drift for zero error and gain error specifies the maximum change from the initial (25∞C) value to the value at TMIN or TMAX. SNR is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Power Supply Rejection Spurious-Free Dynamic Range (SFDR) The specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Aperture Jitter Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the ADC. Rev. C –5– AD9225–Typical Performance Characteristics (AVDD, DRVDD = 5 V, fS = 25 MHz (50% Duty Cycle), unless otherwise noted.) 2.00 1.00 1.50 0.75 1.00 0.50 0.50 0.25 Title 0 0.00 –0.25 0.50 –0.50 1.00 –0.75 1.50 2.00 –1.00 0 511 1022 1533 2044 Title 2555 3066 3577 4095 511 0 TITLE 1022 2044 2555 3066 3577 4095 TPC 4. Typical INL TPC 1. Typical DNL 70 75 0.5dB INT 1V 0.5dB 2V INT REF 65 70 6dB 2V INT REF 6dB INT 1V 65 SINAD (dB) SINAD (dB) 1533 60 60 55 20dB INT 1V 50 55 20dB 2V INT REF 45 50 1 FREQUENCY (MHz) TPC 5. SINAD vs. Input Frequency (Input Span = 2 V p-p VCM = 2.5 V Differential Input) TPC 2. SINAD vs. Input Frequency (Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input) –60 –60 –65 20dB INT 1V –65 20.0dB 2V INT REF –70 THD (dB) THD (dB) 10 1 10 FREQUENCY (MHz) –75 –70 –75 6dB INT 1V 6.0dB 2V INT REF –80 –80 0.5dB INT 1V 0.5dB 2V INT REF –85 –85 1 FREQUENCY (MHz) 1 10 10 FREQUENCY (MHz) TPC 6. THD vs. Input Frequency (Input Span = 2 V p-p, VCM = 2.5 V Differential Input) TPC 3. THD vs. Input Frequency (Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input) –6– Rev. C AD9225 90 –70 80 –75 70 THD (dB) SNR AND SFDR (dBFS) SFDR INT 2V REF 60 SNR INT 2V REF –80 INT 1V REF 50 –85 INT 2V REF 40 30 –40 –35 –30 –25 –20 –15 AIN (dB) –10 –5 –90 0 TPC 7. SNR/SFDR vs. AIN (Input Amplitude) (fIN = 12.5 MHz, Input Span = 4.0 V p-p, VCM = 2.5 V Differential Input) 10 FREQUENCY (MHz) TPC 10. THD vs. Sample Rate, (AIN = –0.5 dB, VCM = 2.5 V, Input Span = 4.0 V p-p Differential Input) –65 75 20.0dB 2V INT REF 0.5dB 2V INT REF –70 70 –75 65 –80 SNR (dB) THD (dB) 6.0dB 2V INT REF 6.0dB 2V INT REF 60 0.5dB 2V INT REF –85 55 20.0dB 2V INT REF –90 1 50 10 1 FREQUENCY (MHz) TPC 8. THD vs. Input Frequency (Input Span = 4.0 V p-p, VCM = 2.5 V Single-Ended Input) HITS N–1 4206 N N+1 BIN TPC 9. Grounded-Input Histogram (Input Span = 40 V p-p) Rev. C 10 TPC 11. SNR vs. Input Frequency (Input Span = 4.0 V p-p, VCM = 2.5 V Single-Ended Input) 246447 3299 FREQUENCY (MHz) –7– AD9225 the difference of the voltages applied at the VINA and VINB input pins. Therefore, the equation INTRODUCTION The AD9225 is a high performance, complete single-supply 12-bit ADC. The analog input range of the AD9225 is highly flexible, allowing for both single-ended or differential inputs of varying amplitudes that can be ac-coupled or dc-coupled. VCORE = VINA – VINB (1) defines the output of the differential input stage and provides the input to the ADC core. The AD9225 utilizes a four-stage pipeline architecture with a wideband input sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. Each stage of the pipeline, excluding the last stage, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier (MDAC). The residue amplifier amplifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each of the stages to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The voltage, VCORE, must satisfy the condition –VREF £ VCORE £ VREF (2) where VREF is the voltage at the VREF pin. While an infinite combination of VINA and VINB inputs exist that satisfy Equation 2, there is an additional limitation placed on the inputs by the power supply voltages of the AD9225. The power supplies bound the valid operating range for VINA and VINB. The condition The pipeline architecture allows a greater throughput rate at the expense of pipeline delay or latency. This means that while the converter is capable of capturing a new input sample every clock cycle, it actually takes three clock cycles for the conversion to be fully processed and appear at the output. This latency is not a concern in most applications. The digital output, together with the out-of-range indicator (OTR), is latched into an output buffer to drive the output pins. The output drivers of the AD9225 can be configured to interface with 5 V or 3.3 V logic families. AVSS – 0.3 V < VINA < AVDD + 0.3 V (3) AVSS – 0.3 V < VINB < AVDD + 0.3 V where AVSS is nominally 0 V and AVDD is nominally 5 V, defines this requirement. The range of valid inputs for VINA and VINB is any combination that satisfies both Equations 2 and 3. For additional information showing the relationships among VINA, VINB, VREF, and the digital output of the AD9225, see Table IV. The AD9225 uses both edges of the clock in its internal timing circuitry (see Figure 1 and Specifications tables for exact timing requirements). The ADC samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in the sample mode; during the clock high time it is in hold mode. System disturbances just prior to the rising edge of the clock and/or excessive clock jitter may cause the input SHA to acquire the wrong value, and should be minimized. Refer to Table I and Table II at the end of this section for a summary of the various analog input and reference configurations. ANALOG INPUT OPERATION Figure 3 shows the equivalent analog input of the AD9225, which consists of a differential sample-and-hold amplifier. The differential input structure of the SHA is highly flexible, allowing the devices to be easily configured for either a differential or single-ended input. The dc offset, or common-mode voltage, of the input(s) can be set to accommodate either single-supply or dual-supply systems. Also, note that the analog inputs, VINA and VINB, are interchangeable, with the exception that reversing the inputs to the VINA and VINB pins results in a polarity inversion. ANALOG INPUT AND REFERENCE OVERVIEW Figure 2 is a simplified model of the AD9225. It highlights the relationship between the analog inputs, VINA and VINB, and the reference voltage, VREF. Like the voltage applied to the top of the resistor ladder in a flash ADC, the value VREF defines the maximum input voltage to the ADC core. The minimum input voltage to the ADC core is automatically defined to be –VREF. CH QS2 VINA AD9225 +VREF VCORE VINB ADC CORE VINA CPIN+ CPAR QS1 12 VINB CS QS1 QH1 CS – CPIN CPAR QS2 –VREF CH Figure 2. Equivalent Functional Input Circuit Figure 3. Simplified Input Circuit The addition of a differential input structure gives the user an additional level of flexibility that is not possible with traditional flash converters. The input stage allows the user to easily configure the inputs for either single-ended operation or differential operation. The A/D converter’s input structure allows the dc offset of the input signal to be varied independently of the input span of the converter. Specifically, the input to the ADC core is The AD9225 has a wide input range. The input peaks may be moved to AVDD or AVSS before performance is compromised. This allows for much greater flexibility when selecting singleended drive schemes. Op amps and ac coupling clamps can be set to available reference levels rather than be dictated according to what the ADC needs. –8– Rev. C AD9225 VCC Due to the high degree of symmetry within the SHA topology, a significant improvement in distortion performance for differential input signals with frequencies up to and beyond Nyquist can be realized. This inherent symmetry provides excellent cancellation of both common-mode distortion and noise. Also, the required input signal voltage span is reduced by a half, which further reduces the degree of RON modulation and its effects on distortion. VINA RS VINB VEE VREF 10F 0.1F SENSE REFCOM The optimum noise and dc linearity performance for either differential or single-ended inputs is achieved with the largest input signal voltage span (i.e., 4 V input span) and matched input impedance for VINA and VINB. Only a slight degradation in dc linearity performance exists between the 2 V and 4 V input spans. Figure 4. Series Resistor Isolates Switched Capacitor SHA Input from Op Amp. Matching Resistors Improve SNR Performance. The optimum size of this resistor is dependent on several factors, which include the ADC sampling rate, the selected op amp, and the particular application. In most applications, a 30 W to 100 W resistor is sufficient. However, some applications may require a larger resistor value to reduce the noise bandwidth or possibly to limit the fault current in an overvoltage condition. Other applications may require a larger resistor value as part of an antialiasing filter. In any case, since the THD performance is dependent on the series resistance and the above mentioned factors, optimizing this resistor value for a given application is encouraged. Referring to Figure 3, the differential SHA is implemented using a switched capacitor topology. Its input impedance and its switching effects on the input drive source should be considered in order to maximize the converter’s performance. The combination of the pin capacitance, CPIN, parasitic capacitance, CPAR, and the sampling capacitance, CS, is typically less than 5 pF. When the SHA goes into track mode, the input source must charge or discharge the voltage stored on CS to the new input voltage. This action of charging and discharging CS, averaged over a period of time and for a given sampling frequency, fS, makes the input impedance appear to have a benign resistive component. However, if this action is analyzed within a sampling period (i.e., T = 1/fS), the input impedance is dynamic and therefore certain precautions on the input drive source should be observed. The source impedance driving VINA and VINB should be matched. Failure to provide that matching will result in degradation of the AD9225’s superb SNR, THD, and SFDR. For noise sensitive applications, the very high bandwidth of the AD9225 may be detrimental. The addition of a series resistor and/or shunt capacitor can help limit the wideband noise at the ADC’s input by forming a low-pass filter. Note, however, that the combination of this series resistance with the equivalent input capacitance of the AD9225 should be evaluated for those time domain applications that are sensitive to the input signal’s absolute settling time. In applications where harmonic distortion is not a primary concern, the series resistance may be selected in combination with the SHA’s nominal 10 pF of input capacitance to set the filter’s 3 dB cutoff frequency. The resistive component to the input impedance can be computed by calculating the average charge that gets drawn by CH from the input drive source. It can be shown that if CS is allowed to fully charge up to the input voltage before switches QS1 are opened, then the average current into the input would be the same as it would if there were a resistor of 1/(CS fS) Ohms connected between the inputs. This means that the input impedance is inversely proportional to the converter’s sample rate. Since CS is only 5 pF, this resistive component is typically much larger than that of the drive source (i.e., 8 kW at fS = 25 MSPS). A better method of reducing the noise bandwidth, while possibly establishing a real pole for an antialiasing filter, is to add some additional shunt capacitance between the input (i.e., VINA and/or VINB) and analog ground. Since this additional shunt capacitance combines with the equivalent input capacitance of the AD9225, a lower series resistance can be selected to establish the filter’s cutoff frequency while not degrading the distortion performance of the device. The shunt capacitance also acts like a charge reservoir, sinking or sourcing the additional charge required by the hold capacitor, CH, and further reducing current transients seen at the op amp’s output. The SHA’s input impedance over a sampling period appears as a dynamic input impedance to the input drive source. When the SHA goes into the track mode, the input source ideally should provide the charging current through RON of switch QS1 in an exponential manner. The requirement of exponential charging means that the most common input source, an op amp, must exhibit a source impedance that is both low and resistive up to and beyond the sampling frequency. The output impedance of an op amp can be modeled with a series inductor and resistor. When a capacitive load is switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output recovers, ringing may occur. To remedy the situation, a series resistor can be inserted between the op amp and the SHA input as shown in Figure 4. The series resistance helps isolate the op amp from the switched capacitor load. Rev. C AD9225 RS The effect of this increased capacitive load on the op amp driving the AD9225 should be evaluated. To optimize performance when noise is the primary consideration, increase the shunt capacitance as much as the transient response of the input signal will allow. Increasing the capacitance too much may adversely affect the op amp’s settling time, frequency response, and distortion performance. –9– AD9225 The actual reference voltages used by the internal circuitry of the AD9225 appears on the CAPT and CAPB pins. For proper operation when using the internal or an external reference, it is necessary to add a capacitor network to decouple these pins. Figure 6 shows the recommended decoupling network. This capacitive network performs the following three functions: (1) along with the reference amplifier, A2, it provides a low source impedance over a large frequency range to drive the ADC internal circuitry, (2) it provides the necessary compensation for A2, and (3) it bandlimits the noise contribution from the reference. The turn-on time of the reference voltage appearing between CAPT and CAPB is approximately 15 ms and should be evaluated in any power-down mode of operation. REFERENCE OPERATION The AD9225 contains an on-board band gap reference that provides a pin strappable option to generate either a 1 V or 2 V output. With the addition of two external resistors, the user can generate reference voltages other than 1 V and 2 V. Another alternative is to use an external reference for designs requiring enhanced accuracy and/or drift performance. See Table II for a summary of the pin strapping options for the AD9225 reference configurations. Figure 5 shows a simplified model of the internal voltage reference of the AD9225. A pin strappable reference amplifier buffers a 1 V fixed reference. The output from the reference amplifier, A1, appears on the VREF pin. The voltage on the VREF pin determines the full-scale input span of the ADC. This input span equals 0.1F CAPT Full-Scale Input Span = 2 ¥ VREF AD9225 The voltage appearing at the VREF pin as well as the state of the internal reference amplifier, A1, are determined by the voltage appearing at the SENSE pin. The logic circuitry contains two comparators that monitor the voltage at the SENSE pin. The comparator with the lowest set point (approximately 0.3 V) controls the position of the switch within the feedback path of A1. If the SENSE pin is tied to AVSS (AGND), the switch is connected to the internal resistor network thus providing a VREF of 2.0 V. If the SENSE pin is tied to the VREF pin via a short or resistor, the switch will connect to the SENSE pin. This short will provide a VREF of 1.0 V. An external resistor network will provide an alternative VREF between 1.0 V and 2.0 V. The other comparator controls internal circuitry that will disable the reference amplifier if the SENSE pin is tied AVDD. Disabling the reference amplifier allows the VREF pin to be driven by an external voltage reference. AD9225 TO A/D CAPT 5k A2 5k CAPB 5k LOGIC VREF 1V A1 6.25k SENSE DISABLE A1 LOGIC 10F 0.1F Figure 6. Recommended CAPT/CAPB Decoupling Network The ADC’s input span may be varied dynamically by changing the differential reference voltage appearing across CAPT and CAPB symmetrically around 2.5 V (i.e., midsupply). To change the reference at speeds beyond the capabilities of A2, it will be necessary to drive CAPT and CAPB with two high speed, low noise amplifiers. In this case, both internal amplifiers (i.e., A1 and A2) must be disabled by connecting SENSE to AVDD, connecting VREF to AVSS and removing the capacitive decoupling network. The external voltages applied to CAPT and CAPB must be 2.0 V + Input Span/4 and 2.0 V – Input Span/4, respectively, in which the input span can be varied between 2 V and 4 V. Note that those samples within the pipeline ADC during any reference transition will be corrupted and should be discarded. DRIVING THE ANALOG INPUTS 5k DISABLE A2 0.1F CAPB 6.25k REFCOM Figure 5. Equivalent Reference Circuit The AD9225 has a highly flexible input structure allowing it to interface with single ended or differential input interface circuitry. The applications shown in this section and the Reference Configurations section along with the information presented in the Input and Reference Overview give examples of singleended and differential operation. Refer to Tables I and II for a list of the different possible input and reference configurations and their associated figures in the data sheet. The optimum mode of operation, analog input range, and associated interface circuitry will be determined by the particular applications performance requirements as well as power supply options. For example, a dc-coupled single-ended input would be appropriate for most data acquisition and imaging applications. Many communication applications, which require a dc-coupled input for proper demodulation, can take advantage of the excellent single-ended distortion performance of the AD9225. The input span should be configured so the system’s performance objectives and the headroom requirements of the driving op amp are simultaneously met. –10– Rev. C AD9225 Table I. Analog Input Configuration Summary Input Connection Input Input Range (V) Coupling Span (V) VINA* VINB* Figure No. Single-Ended DC 1 8, 9 Best for stepped input response applications; requires ± 5 V op amp. 2 ¥ VREF 0 to 2 ¥ VREF VREF 8, 9 Same as above but with improved noise performance due to increase in dynamic range. Headroom/settling time requirements of ± 5 V op amp should be evaluated. 4 2.0 8, 9 Optimum noise performance, excellent THD performance, often requires low distortion op amp with VCC > +5 V due to its headroom issues. 2.0 21 Optimum THD performance with VREF = 1. Single-supply operation (i.e., +5 V) for many op amps. 2 0 to 2 0 to 4 2 ¥ VREF 2.0 – VREF to 2.0 + VREF Single-Ended AC Differential AC/DC (via Transformer) or Amplifier Comments 2 or 0 to 1 or 1 or VREF 2 ¥ VREF 0 to 2 ¥ VREF 10, 11 4 2.0 11 Optimum noise performance, excellent THD performance; ability to use ± 5 V op amp. 2 ¥ VREF 2.0 – VREF to 2.0 + VREF 2.0 10 Flexible input range, optimum THD performance with VREF = 1. Ability to use either +5 V or ± 5 V op amp. 2 3 to 2 12, 13 Optimum full-scale THD and SFDR performance well beyond the ADC’s Nyquist frequency. Preferred mode for undersampling applications. 0.5 to 4.5 2 to 3 2 ¥ VREF 2.0 – VREF/2 to 2.0 + VREF/2 2.0 + VREF/2 12, 13 to 2.0 – VREF/2 Same as above with the exception that fullscale THD and SFDR performance can be traded off for better noise performance. 4.0 3.5 to 1.5 Optimum noise performance. 1.5 to 3.5 12, 13 *VINA and VINB can be interchanged if signal inversion is required. Table II. Reference Configuration Summary Reference Operating Mode Input Span (VINA–VINB) (V p-p) Required VREF (V) Connect To Internal Internal Internal 2 4 2 £ SPAN £ 4 and SPAN = 2 ⫻ VREF 1 2 1 £ VREF £ 2.0 and VREF = (1 + R1/R2) SENSE SENSE R1 R2 VREF REFCOM VREF and SENSE SENSE and REFCOM External (Nondynamic) 2 £ SPAN £ 4 1 £ VREF £ 2.0 SENSE VREF AVDD External Reference External (Dynamic) 2 £ SPAN £ 4 CAPT and CAPB Externally Driven SENSE VREF External Reference External Reference AVDD AVSS CAPT CAPB Rev. C –11– AD9225 Single-ended operation is often limited by the availability of driving op amps. Very low distortion op amps that provide great performance out to the Nyquist frequency of the converter are hard to find. Compounding the problem, for dc-coupled, single-ended applications, is the inability of many high performance amplifiers to maintain low distortions as their outputs approach their positive output voltage limit (i.e., 1 dB compression point). For this reason, it is recommended that applications requiring high performance dc coupling use the single-ended-to-differential circuit shown in Figure 12. Differential modes of operation (ac-coupled or dc-coupled input) provide the best THD and SFDR performance over a wide frequency range. Differential operation should be considered for the most demanding spectral based applications (e.g., direct IF-todigital conversion). See Figures 12 and 13 and the Differential Mode of Operation section. Differential input characterization was performed for this data sheet using the configuration shown in Figure 13. Single-ended operation requires that VINA be ac-coupled or dccoupled to the input signal source while VINB of the AD9225 be biased to the appropriate voltage corresponding to a midscale code transition. Note that signal inversion may be easily accomplished by transposing VINA and VINB. Most of the single-ended specifications for the AD9225 are characterized using Figure 21 circuitry with input spans of 4 V and 2 V as well as VINB = 2.5 V. DC COUPLING AND INTERFACE ISSUES Many applications require the analog input signal to be dc-coupled to the AD9225. An operational amplifier can be configured to rescale and level shift the input signal so that it is compatible with the selected input range of the ADC. The input range to the ADC should be selected on the basis of system performance objectives, as well as the analog power supply availability since this will place certain constraints on the op amp selection. Differential operation requires that VINA and VINB be simultaneously driven with two equal signals that are in and out of phase versions of the input signal. Differential operation of the AD9225 offers the following benefits: (1) Signal swings are smaller and, therefore, linearity requirements placed on the input signal source may be easier to achieve, (2) Signal swings are smaller and therefore may allow the use of op amps which may otherwise have been constrained by headroom limitations, (3) Differential operation minimizes even-order harmonic products, and (4) Differential operation offers noise immunity based on the device’s commonmode rejection. Many of the new high performance op amps are specified for only ±5 V operation and have limited input/output swing capabilities. The selected input range of the AD9225 should be considered with the headroom requirements of the particular op amp to prevent clipping of the signal. Since the output of a dual supply amplifier can swing below –0.3 V, clamping its output should be considered in some applications. As is typical of most IC devices, exceeding the supply limits will turn on internal parasitic diodes resulting in transient currents within the device. Figure 7 shows a simple means of clamping an ac-coupled or dc-coupled single-ended input with the addition of two series resistors and two diodes. An optional capacitor is shown for ac-coupled applications. Note that a larger series resistor could be used to limit the fault current through D1 and D2 but should be evaluated since it can cause a degradation in overall performance. A similar clamping circuit could also be used for each input if a differential input signal is being applied. The diodes might cause nonlinearities in the signal. Careful evaluation should be performed on the diodes used. VCC OPTIONAL AC COUPLING CAPACITOR AVDD RS1 30 D2 1N4148 RS2 20 In some applications, it may be advantageous to use an op amp specified for single-supply +5 V operation since it will inherently limit its output swing to within the power supply rails. Amplifiers like the AD8041 and AD8011 are useful for this purpose but their low bandwidths will limit the AD9225’s performance. High performance amplifiers, such as the AD9631, AD9632, AD8056, or AD8055, allow the AD9225 to be configured for larger input spans which will improve the ADC’s noise performance. Op amp circuits using a noninverting and inverting topology are discussed in the next section. Although not shown, the noninverting and inverting topologies can be easily configured as part of an antialiasing filter by using a Sallen-Key or multiple-feedback topology. An additional R-C network can be inserted between the op amp output and the AD9225 input to provide a filter pole. Simple Op Amp Buffer AD9225 D1 1N4148 VEE Figure 7. Simple Clamping Circuit SINGLE-ENDED MODE OF OPERATION The AD9225 can be configured for single-ended operation using dc-coupling or ac-coupling. In either case, the input of the ADC must be driven from an operational amplifier that will not degrade the ADC’s performance. Because the ADC operates from a single supply, it will be necessary to level shift ground based bipolar signals to comply with its input requirements. Both dc and ac coupling provide this necessary function, but each method results in different interface issues that may influence the system design and performance. In the simplest case, the input signal to the AD9225 will already be biased at levels in accordance with the selected input range. It is simply necessary to provide an adequately low source impedance for the VINA and VINB analog pins of the ADC. Figure 8 shows the recommended configuration a single-ended drive using an op amp. In this case, the op amp is shown in a noninverting unity gain configuration driving the VINA pin. The internal reference drives the VINB pin. Note that the addition of a small series resistor of 30 W to 50 W connected to VINA and VINB will be beneficial in nearly all cases. Refer to the Analog Input Operation section on a discussion on resistor selection. Figure 8 shows the proper connection for a 0 V to 4 V input range. Alternative single-ended ranges of 0 V to 2 ¥ VREF can also be realized with the proper configuration of VREF (refer to the Using the Internal Reference section). Headroom limitations of the op amp must always be considered. –12– Rev. C AD9225 +V 4V 0V impedance over a wide frequency range. The combination of the capacitor and the resistor form a high-pass filter with a high-pass – 3 dB frequency determined by the equation AD9225 RS U1 VINA RS f–3 dB = 1/(2 ¥ ¥ R ¥ (C1 + C2)) VINB –V 2.0V VREF 10F The low impedance VREF voltage source biases both the VINB input and provides the bias voltage for the VINA input. Figure 10 shows the VREF configured for 2.0 V thus the input range of the ADC is 0 V to 4 V. Other input ranges could be selected by changing VREF. 0.1F SENSE Figure 8. Single-Ended AD9225 Op Amp Drive Circuit Op Amp with DC Level Shifting Figure 9 shows a dc-coupled level shifting circuit employing an op amp, A1, to sum the input signal with the desired dc set. Configuring the op amp in the inverting mode with the given resistor values results in an ac signal gain of –1. If the signal inversion is undesirable, interchange the VINA and VINB connections to re-establish the original signal polarity. The dc voltage at VREF sets the common-mode voltage of the AD9225. For example, when VREF = 2.0 V, the input level from the op amp will also be centered around 2.0 V. The use of ratio matched, thin-film resistor networks will minimize gain and offset errors. Also, an optional pull-up resistor, RP, may be used to reduce the output load on VREF to less than its 1 mA maximum. 500* +VCC 0.1F +VREF 0VDC –VREF RP** 500* NC 2 7 500* 3 +V 0.1F 500* RS 1 A1 VINA 6 5 4 AD9225 NC RS VREF VINB *OPTIONAL RESISTOR NETWORK-OHMTEK ORNA500D **OPTIONAL PULL-UP RESISTOR WHEN USING INTERNAL REFERENCE Figure 9. Single-Ended Input with DC-Coupled Level Shift +5V +2V 0V –2V VIN +V +V 4.5 2.5 0.5 AD9631 R R AD9225 RS VINA C2 0.1F –5V RS VINB 0.1F R 10F R Figure 10. AC-Coupled Input Alternative AC Interface Figure 11 shows a flexible ac-coupled circuit that can be configured for different input spans. Since the common-mode voltage of VINA and VINB are biased to midsupply independent of VREF, VREF can be pin strapped or reconfigured to achieve input spans between 2 V and 4 V p-p. The AD9225’s CMRR along with the symmetrical coupling R-C networks will reject both power supply variations and noise. The resistors, R, establish the common-mode voltage. They may have a high value (e.g., 5 kW) to minimize power consumption and establish a low cutoff frequency. The capacitors, C1 and C2, are typically a 0.1 mF ceramic and 10 mF tantalum capacitor in parallel to achieve a low cutoff frequency while maintaining a low impedance over a wide frequency range. RS isolates the buffer amplifier from the ADC input. The optimum performance is achieved when VINA and VINB are driven via symmetrical networks. The f–3 dB point can be approximated by the equation AC COUPLING AND INTERFACE ISSUES f –3 dB = For applications where ac coupling is appropriate, the op amp output can be easily level-shifted via a coupling capacitor. This has the advantage of allowing the op amp common-mode level to be symmetrically biased to its midsupply level (i.e., (VCC + VEE)/2). Op amps that operate symmetrically with respect to their power supplies typically provide the best ac performance as well as greatest input/output span. Various high speed/performance amplifiers which are restricted to +5 V/–5 V operation and/or specified for +5 V single-supply operation can be easily configured for the 4 V or 2 V input span of the AD9225. Note that differential transformer coupling, which is another form of ac coupling, should be considered for optimum ac performance. 1 2 p ¥ 6K +(C1+ C2) C2 0.1F RS VIN C1 10F AD9225 VINA 1k C3 0.1F C1 10F VCM 1k C2 0.1F RS VINB Figure 11. AC-Coupled Input-Flexible Input Span, VCM = 2.5 V Simple AC Interface Figure 10 shows a typical example of an ac-coupled, single-ended configuration. The bias voltage shifts the bipolar, ground-referenced input signal to approximately AVDD/2. The value for C1 and C2 will depend on the size of the resistor, R. The capacitors, C1 and C2, are a 0.1 mF ceramic and 10 mF tantalum capacitor in parallel to achieve a low cutoff frequency while maintaining a low Rev. C C1 10F –13– AD9225 500 OP AMP SELECTION GUIDE Op amp selection for the AD9225 is highly dependent on the particular application. In general, the performance requirements of any given application can be characterized by either time domain or frequency domain parameters. In either case, one should carefully select an op amp that preserves the performance of the ADC. This task becomes challenging when the AD9225’s high performance capabilities are coupled with other extraneous system level requirements such as power consumption and cost. 500 VINA 500 500 AD9225 500 500 +V 50 VINB 500 CML 500 The ability to select the optimal op amp may be further complicated by either limited power supply availability and/or limited acceptable supplies for a desired op amp. Newer, high performance op amps typically have input and output range limitations in accordance with their lower supply voltages. As a result, some op amps will be more appropriate in systems where ac coupling is allowable. When dc coupling is required, op amps without headroom constraints such as rail-to-rail op amps or the ones where larger supplies can be used should be considered. The following section describes some op amps currently available from Analog Devices, Inc. The system designer is always encouraged to contact the factory or local sales office to be updated on Analog Devices’ latest amplifier product offerings. Highlights of the areas where the op amps excel and where they may limit the performance of the AD9225 is also included. AD8055: f–3 dB = 300 MHz. Low cost. Best used for driving single-ended accoupled configuration. Limit: THD is compromised when output is not swinging about 0 V. AD8056: Dual Version of above amp. Perfect for single-ended to differential configuration (see Figure 12). Harmonics cancel each other in differential drive, making this amplifier highly recommended for a single-ended input signal source. Handles input signals past the 20 MHz Nyquist frequency. AD9631: f–3 dB = 250 MHz. Moderate cost. Good for single-ended drive applications when signal is anywhere between 0 V and 3 V. Limits: THD is compromised above 8 MHz. DIFFERENTIAL MODE OF OPERATION Since not all applications have a signal preconditioned for differential operation, there is often a need to perform a singleended-to-differential conversion. In systems that do not need to be dc-coupled, an RF transformer with a center tap is the best method to generate differential inputs for the AD9225. It provides all the benefits of operating the ADC in the differential mode without contributing additional noise or distortion. An RF transformer also has the added benefit of providing electrical isolation between the signal source and the ADC. An improvement in THD and SFDR performance can be realized by operating the AD9225 in the differential mode. The performance enhancement between the differential and single-ended mode is most noteworthy as the input frequency approaches and goes beyond the Nyquist frequency (i.e., fIN > fS/2). 50 VREF 0V *OPTIONAL 10F R* 0.1F Figure 12. Direct Coupled Drive Circuit with AD8056 Dual Op Amp The circuit shown in Figure 12 is an ideal method of applying a differential dc drive to the AD9225. We have used this configuration to drive the AD9225 from 2 V to 4 V spans at frequencies approaching Nyquist with performance numbers matching those listed in the Specifications tables (gathered through a transformer). The dc input is shifted to a dc point swinging symmetrically about the reference voltage. The optional resistor will provide additional current if more reference drive is required. The driver circuit shown in Figure 12 is optimized for dc coupling applications requiring optimum distortion performance. This differential op amp driver circuit is configured to convert and level shift a 2 V p-p single-ended, ground referenced signal to a 4 V p-p differential signal centered at the VREF level of the ADC. The circuit is based on two op amps that are configured as matched unity gain difference amplifiers. The single-ended input signal is applied to opposing inputs of the difference amplifiers, thus providing differential drive. The common-mode offset voltage is applied to the noninverting resistor leg of each difference amplifier providing the required offset voltage. The common-mode offset can be varied over a wide span without any serious degradation in distortion performance as shown in Figures 14 and 15, thus providing some flexibility in improving output compression distortion from some ± 5 V op amps with limited positive voltage swing. To protect the AD9225 from an undervoltage fault condition from op amps specified for ±5 V operation, two diodes to AGND can be inserted between each op amp output and the AD9225 inputs. The AD9225 will inherently be protected against any overvoltage condition if the op amps share the same positive power supply (i.e., AVDD) as the AD9225. Note that the gain accuracy and common-mode rejection of each difference amplifier in this driver circuit can be enhanced by using a matched thin-film resistor network (i.e., Ohmtek ORNA5000F) for the op amps. Recall that the AD9225’s small signal bandwidth is 105 MHz and therefore, any noise falling within the baseband bandwidth of the AD9225 will degrade its overall noise performance. The noise performance of each unity gain differential driver circuit is limited by its inherent noise gain of 2. For unity gain op amps ONLY, the noise gain can be reduced from 2 to 1 beyond the input signals passband by adding a shunt capacitor, CF, across each op amp’s feedback resistor. This will essentially establish a low-pass filter, which reduces the noise gain to 1 beyond the filter’s f–3 dB while simultaneously bandlimiting the input signal to f–3 dB. Note that the pole established by this filter can also be used as the real pole of an antialiasing filter. –14– Rev. C AD9225 –76 –78 THD (dB) Figure 13 shows the schematic of the suggested transformer circuit. The circuit uses a minicircuits RF transformer, model #T4-1T, which has an impedance ratio of 4 (turns ratio of 2). The schematic assumes that the signal source has a 50 W source impedance. The 1:4 impedance ratio requires the 200 W secondary termination for optimum power transfer and VSWR. The center tap of the transformer provides a convenient means of level-shifting the input signal to a desired common-mode voltage. –80 fIN = 10MHz –82 fIN = 2.5MHz RS 33 VINA 49.9 –84 CML 200 0.1F CS AD9225 –86 0 1 VINB MINICIRCUITS T4-1T RS 33 2 3 COMMON-MODE VOLTAGE (V) 5 4 Figure 14. Common-Mode Voltage vs. THD (AIN = 2 V Differential) Figure 13. Transformer Coupled Input The configuration in Figure 13 was used to gather the differential data on the Specifications tables. –76 Transformers with other turns ratios may also be selected to optimize the performance of a given application. For example, a given input signal source or amplifier may realize an improvement in distortion performance at reduced output power levels and signal swings. For example, selecting a transformer with a higher impedance ratio (e.g., Minicircuits T16-6T with a 1:16 impedance ratio) effectively steps up the signal level further reducing the driving requirements of the signal source. THD (dB) –78 –80 fIN = 10MHz –82 fIN = 2.5MHz –84 Referring to Figure 13, a series resistors, RS, and shunt capacitor, CS, were inserted between the AD9225 and the secondary of the transformer. The value of 33 W was selected to specifically optimize both the THD and SNR performance of the ADC. RS and CS help provide a low-pass filter to block high frequency noise. –86 0.5 The AD9225 can be easily configured for either a 2 V p-p input span or a 4.0 V p-p input span by setting the internal reference (see Table II). Other input spans can be realized with two external gain setting resistors as shown in Figure 19. Figures 14 and 15 demonstrate how both spans of the AD9225 achieve the high degree of linearity and SFDR over a wide range of amplitudes required by the most demanding communication applications. 1.0 2.0 2.5 3.0 3.5 1.5 COMMON-MODE VOLTAGE (V) 4.0 4.5 Figure 15. Common-Mode Voltage vs. THD (AIN = 4 V Differential) 0.0 FUND fIN = 2.5MHz fS = 25MHz –10.0 –20.0 –30.0 –40.0 Figures 14 and 15 demonstrate the flexibility of common-mode voltage (transformer center tap) with respect to THD. –50.0 –60.0 –70.0 –80.0 2ND 3RD –90.0 4TH –100.0 –110.0 –119.7 2.0E+6 4.0E+6 6.0E+6 8.0E+6 10.0E+6 12.5E+6 Figure 16. Single-Tone Frequency Domain Plot Common-Mode Voltage = 2.5 V (AIN = 4 V Differential) Rev. C –15– AD9225 This reference configuration could also be used for a differential input in which VINA and VINB are driven via a transformer as shown in Figure 13. In this case, the common-mode voltage, VCM , is set at midsupply by connecting the transformer’s center tap to CML of the AD9225. VREF can be configured for 1.0 V or 2.0 V by connecting SENSE to either VREF or REFCOM, respectively. Note that the valid input range for each of the differential inputs is one half of the single-ended input and thus becomes VCM – VREF/2 to VCM + VREF/2. REFERENCE CONFIGURATIONS The figures associated with this section on internal and external reference operation do not show recommended matching series resistors for VINA and VINB for the purpose of simplicity. Refer to the Driving the Analog Inputs and Introduction sections for a discussion of this topic. The figures do not show the decoupling network associated with the CAPT and CAPB pins. Refer to the Reference Operation section for a discussion of the internal reference circuitry and the recommended decoupling network shown in Figure 16. 3.5V 1V 10F VINA 0V VINB 10F 0.1F VREF SHORT FOR 0V TO 2V INPUT SPAN AD9225 SENSE SHORT FOR 0V TO 4V INPUT SPAN AD9225 VREF SENSE 0.1F REFCOM In either case, both the midscale voltage and input span are directly dependent on the value of VREF. More specifically, the midscale voltage is equal to VREF while the input span is equal to 2 ¥ VREF. Thus, the valid input range extends from 0 to 2 ¥ VREF. When VINA is £ 0 V, the digital output will be 0x000; when VINA is ≥ 2 ¥ VREF, the digital output will be 0xFFF. Shorting the VREF pin directly to the SENSE pin places the internal reference amplifier in unity-gain mode and the resulting VREF output is 1 V. Therefore, the valid input range is 0 V to 2 V. However, shorting the SENSE pin directly to the REFCOM pin configures the internal reference amplifier for a gain of 2.0 and the resulting VREF output is 2.0 V. Therefore, the valid input range becomes 0 V to 4 V. The VREF pin should be bypassed to the REFCOM pin with a 10 mF tantalum capacitor in parallel with a low inductance 0.1 mF ceramic capacitor. VCM VINB Figure 16 shows how to connect the AD9225 for a 0 V to 2 V or 0 V to 4 V input range via pin strapping the SENSE pin. An intermediate input range of 0 to 2 ¥ VREF can be established using the resistor programmable configuration in Figure 19. 2 VREF VINA 1.5V USING THE INTERNAL REFERENCE Single-Ended Input with 0 to 2 3 VREF Range Figure 18. Internal Reference—2 V p-p Input Span, VCM = 2.5 V Resistor Programmable Reference Figure 19 shows an example of how to generate a reference voltage other than 1.0 V or 2.0 V with the addition of two external resistors and a bypass capacitor. Use the equation VREF = 1 V ¥ (1 + R1/R2) to determine appropriate values for R1 and R2. These resistors should be in the 2 kW to 100 kW range. For the example shown, R1 equals 2.5 kW and R2 equals 5 kW. From the equation above, the resultant reference voltage on the VREF pin is 1.5 V. This sets the input span to be 3 V p-p. To assure stability, place a 0.1 mF ceramic capacitor in parallel with R1. The midscale voltage can be set to VREF by connecting VINB to VREF to provide an input span of 0 to 2 ¥ VREF. Alternatively, the midscale voltage can be set to 2.5 V by connecting VINB to a low impedance 2.5 V source. For the example shown, the valid input single-ended range for VINA is 1 V to 4 V since VINB is set to an external, low impedance 2.5 V source. The VREF pin should be bypassed to the REFCOM pin with a 10 mF tantalum capacitor in parallel with a low inductance 0.1 mF ceramic capacitor. REFCOM 4V VINA 1V Figure 17. Internal Reference—2 V p-p Input Span, VCM = 1 V, or 4 V p-p Input Span AD9225 2.5V VINB 1.5V Figure 18 shows the single-ended configuration that gives good dynamic performance (SINAD, SFDR). To optimize dynamic specifications, center the common-mode voltage of the analog input at approximately by 2.5 V by connecting VINB to a low impedance 2.5 V source. As described above, shorting the VREF pin directly to the SENSE pin results in a 1 V reference voltage and a 2 V p-p input span. The valid range for input signals is 1.5 V to 3.5 V. The VREF pin should be bypassed to the REFCOM pin with a 10 mF tantalum capacitor in parallel with a low-inductance 0.1 mF ceramic capacitor. 10F 0.1F R1 2.5k VREF C1 0.1F SENSE R2 5k REFCOM Figure 19. Resistor Programmable Reference 3 V p-p Input Span, VCM = 2.5 V –16– Rev. C AD9225 2 REF USING AN EXTERNAL REFERENCE Using an external reference may enhance the dc performance of the AD9225 by improving drift and accuracy. Figures 20 and 21 show examples of how to use an external reference with the ADC. Table III is a list of suitable voltage references from Analog Devices. To use an external reference, the user must disable the internal reference amplifier and drive the VREF pin. Connecting the SENSE pin to AVDD disables the internal reference amplifier. VINA 0V +5V VINB VREF 0.1F 10F 0.1F AD9225 VREF 0.1F +5V Table III. Suitable Voltage References Internal AD589 AD1580 REF191 Internal Output Voltage Drift (ppm/∞C) Initial Accuracy % (max) 1.00 1.235 1.225 2.048 2.0 26 10–100 50–100 5–25 26 1.4 1.2–2.8 0.08–0.8 0.1–0.5 1.4 Figure 21. Input Range = 0 V to 2 ¥ VREF Operating Current DIGITAL INPUTS AND OUTPUTS Digital Outputs 1 mA 50 mA 50 mA 45 mA 1 mA The AD9225 output data is presented in positive true straight binary for all input ranges. Table IV indicates the output data formats for various input ranges regardless of the selected input range. A twos complement output data format can be created by inverting the MSB. Table IV. Output Data Format The AD9225 contains an internal reference buffer, A2 (see Figure 5), that simplifies the drive requirements of an external reference. The external reference must be able to drive about 5 kW (± 20%) load. Note that the bandwidth of the reference buffer is deliberately left small to minimize the reference noise contribution. As a result, it is not possible to change the reference voltage rapidly in this mode. 2.5V+VREF 2.5V 2.5V–VREF +5V 0.1F Input (V) Condition (V) Digital Output OTR VINA–VINB VINA–VINB VINA–VINB VINA–VINB VINA–VINB < – VREF = – VREF =0 = + VREF – 1 LSB ≥ + VREF 0000 0000 0000 0000 0000 0000 1000 0000 0000 1111 1111 1111 1111 1111 1111 1 0 0 0 1 VINA AD9225 2.5V REF 22F 0.1F 1 0 0 0.1F R1 1111 1111 1111 1111 1111 1111 1111 1111 1110 OTR –FS+1/2 LSB VREF R2 +5V +FS –1 1/2 LSB OTR DATA OUTPUTS VINB A1 0 0 1 SENSE 0000 0000 0001 0000 0000 0000 0000 0000 0000 –FS Figure 20. External Reference –FS –1/2 LSB Variable Input Span with VCM = 2.5 V Single-Ended Input with 0 to 2 ¥ VREF Range +FS +FS –1/2 LSB Figure 22. Output Data Format Figure 20 shows an example of the AD9225 configured for an input span of 2 ¥ VREF centered at 2.5 V. An external 2.5 V reference drives the VINB pin thus setting the common-mode voltage at 2.5 V. The input span can be independently set by a voltage divider consisting of R1 and R2, which generates the VREF signal. A1 buffers this resistor network and drives VREF. Choose this op amp based on accuracy requirements. It is essential that a minimum of a 10 mF capacitor in parallel with a 0.1 mF low inductance ceramic capacitor decouple A1’s output to ground. Figure 21 shows an example of an external reference driving both VINB and VREF. In this case, both the common-mode voltage and input span are directly dependent on the value of VREF. More specifically, the common-mode voltage is equal to VREF while the input span is equal to 2 ¥ VREF. The valid input range extends from 0 to 2 ¥ VREF. For example, if the REF191, a 2.048 V external reference was selected, the valid input range extends from 0 to 4.096 V. In this case, 1 LSB of the AD9225 corresponds to 1 mV. It is essential that a minimum of a 10 mF capacitor in parallel with a 0.1 mF low inductance ceramic capacitor decouple the reference output to ground. Rev. C SENSE Out-Of-Range (OTR) An out-of-range condition exists when the analog input voltage is beyond the input range of the converter. OTR is a digital output that is updated along with the data output corresponding to the particular sampled analog input voltage. OTR has the same pipeline delay (latency) as the digital data. It is low when the analog input voltage is within the analog input range. It is high when the analog input voltage exceeds the input range as shown in Figure 23. OTR will remain high until the analog input returns within the input range and another conversion is completed. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table V is a truth table for the overrange circuit in Figure 24 which uses NAND gates. Systems requiring programmable gain conditioning of the AD9225 input signal can immediately detect an out-of-range condition, eliminating gain selection iterations. OTR can also be used for digital offset and gain calibration. –17– AD9225 The AD9225 has a clock tolerance of 5% at 25 MHz. One way to obtain a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in Figure 24. This configuration will also decrease the jitter of the source clock. Table V. Out-of-Range Truth Table OTR MSB Analog Input Is 0 0 1 1 0 1 0 1 In Range In Range Underrange Overrange +5V R D MSB Q OVER = “1” 50MHz OTR Q UNDER = “1” MSB 25MHz S +5V Figure 23. Overrange or Underrange Logic Figure 24. Divide-by-Two Clock Circuit Digital Output Driver Considerations (DRVDD) In this case, a 50 MHz clock is divided by two to produce the 25 MHz clock input for the AD9225. In this configuration, the duty cycle of the 50 MHz clock is irrelevant. The AD9225 output drivers can be configured to interface with 5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V, respectively. The output drivers are sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may affect SINAD performance. Applications requiring the ADC to drive large capacitive loads or large fanout may require additional decoupling capacitors on DRVDD. In extreme cases, external buffers or latches may be required. The input circuitry for the CLOCK pin is designed to accommodate CMOS inputs. The quality of the logic input, particularly the rising edge, is critical in realizing the best possible jitter performance of the part; the faster the rising edge, the better the jitter performance. Clock Input and Considerations The AD9225 internal timing uses the two edges of the clock input to generate a variety of internal timing signals. The clock input must meet or exceed the minimum specified pulse width high and low (tCH and tCL) specifications for the given ADC as defined in the Switching Specifications table to meet the rated performance specifications. For example, the clock input to the AD9225 operating at 25 MSPS may have a duty cycle between 45% to 55% to meet this timing requirement since the minimum specified tCH and tCL is 18 ns. For low clock rates, the duty cycle may deviate from this range to the extent that both tCH and tCL are satisfied. As a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. Jitter-induced errors become more predominant at higher frequency and large amplitude inputs, where the input slew rate is greatest. Most of the power dissipated by the AD9225 is from the analog power supplies. However, lower clock speeds will reduce digital current. Figure 25 shows the relationship between power and clock rate. 380 360 340 All high speed high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given full-scale input frequency (fIN) due to only aperture jitter (tA) can be calculated with the following equation: POWER (mW) È ˘ 1 SNR = 20 log 10 Í ˙ Î2p f IN t A ˚ 300 280 260 1V INTERNAL REFERENCE 240 220 In the equation, the rms aperture jitter, tA, represents the rootsum square of all the jitter sources, which include the clock input, analog input signal, and ADC aperture jitter specification. Undersampling applications are particularly sensitive to jitter. 200 180 Clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9225. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter crystal controlled oscillators make the best clock sources. If the clock is generated from another type of source (by gating, dividing, or other method), it should be retimed by the original clock at the last step. The clock input is referred to as the analog supply. Its logic threshold is AVDD/2. If the clock is being generated by 3 V logic, it will have to be level shifted into 5 V CMOS logic levels. This can also be accomplished by ac coupling and level-shifting the clock signal. 2V INTERNAL REFERENCE 320 0 5 10 15 20 SAMPLE RATE 25 30 35 Figure 25. Power Consumption vs. Clock Rate Direct IF Down Conversion Using the AD9225 Sampling IF signals above an ADC’s baseband region (i.e., dc to fS/2) is becoming increasingly popular in communication applications. This process is often referred to as direct IF down conversion or undersampling. There are several potential benefits in using the ADC to alias (i.e., or mix) down a narrowband or wideband IF signal. First and foremost is the elimination of a complete mixer stage with its associated baseband amplifiers and filters, reducing cost and power dissipation. Second is the ability to apply various DSP techniques to perform such functions as filtering, channel selection, quadrature demodulation, data reduction, –18– Rev. C AD9225 In direct IF down conversion applications, one exploits the inherent sampling process of an ADC in which an IF signal lying outside the baseband region can be aliased back into the baseband region in a similar manner that a mixer will down-convert an IF signal. Similar to the mixer topology, an image rejection filter is required to limit other potential interferring signals from also aliasing back into the ADC’s baseband region. A trade-off exists between the complexity of this image rejection filter and the ADC’s sample rate as well as dynamic range. The AD9225 is well suited for various IF sampling applications. The AD9225’s low distortion input SHA has a full-power bandwidth extending beyond 130 MHz thus encompassing many popular IF frequencies. A DNL of ± 0.4 LSB (typ) combined with low thermal input referred noise allows the AD9225 in the 2 V span to provide 69 dB of SNR for a baseband input sine wave. Its low aperture jitter of 0.8 ps rms ensures minimum SNR degradation at higher IF frequencies. In fact, the AD9225 is capable of still maintaining 68 dB of SNR at an IF of 71 MHz with a 2 V input span. Although the AD9225 can yield a 1 dB to 2 dB improvement in SNR when configured for the larger 4 V span, the 2 V span achieves the optimum full-scale distortion performance at these higher input frequencies. The 2 V span reduces only the performance requirements of the input driver circuitry (i.e., IP3) and thus may also be more attractive from a system implementation perspective. The distortion and noise performance of an ADC at the given IF frequency is of particular concern when evaluating an ADC for a narrowband IF sampling application. Both single-tone and dualtone SFDR versus amplitude are very useful in assessing an ADC’s dynamic and static nonlinearities. SNR versus amplitude performance at the given IF is useful in assessing the ADC’s noise performance and noise contribution due to aperture jitter. In any application, one is advised to test several units of the same device under the same conditions to evaluate the given applications sensitivity to that particular device. Figures 27 to 30 combine the dual-tone SFDR as well as singletone SFDR and SNR performances at IF frequencies of 35 MHz, 45 MHz, 70 MHz, and 85 MHz. Note that the SFDR versus amplitude data is referenced to dBFS while the single-tone SNR data is referenced to dBc. The performance characteristics in these figures are representative of the AD9225 without any preceding gain stage. The AD9225 was operated in the differential mode (via transformer) with a 2 V span and a sample rate between 28 MSPS and 36 MSPS. The analog supply (AVDD) and the digital supply (DRVDD) were set to 5 V and 3.3. V, respectively. Figure 26 shows a simplified schematic of the AD9225 configured in an IF sampling application. To reduce the complexity of the digital demodulator in many quadrature demodulation applications, the IF frequency and/or sample rate are strategically selected such that the band-limited IF signal aliases back into the center of the ADC’s baseband region (i.e., fS/4). This demodulation technique typically reduces the complexity of the post digital demodulator ASIC that follows the ADC. FROM PREVIOUS STAGES MIXER HIGH LINEARITY OPTIONAL RF BANDPASS SAW FILTER FILTER AMPLIFIER MINICIRCUITS T4-6T 90 85 20 75 SNR SINGLE-TONE (dBc) 70 65 50 –15 –10 –5 0 AIN (dBFS) 100 VINA SFDR SINGLE-TONE (dBFS) 95 VINB 90 CML SNR/SFDR (dBFS) 85 VREF SENSE 0.1F REFCOM Figure 26. Example of AD9225 IF Sampling Circuit To maximize its distortion performance, the AD9225 is configured in the differential mode with a 2 V span using a transformer. The center tap of the transformer is biased at midsupply via the CML output of the AD9225. Preceding the AD9225 and transformer is an optional band-pass filter as well as a gain stage. A low Q passive band-pass filter can be inserted to reduce the out-of-band distortion and noise that lies within the AD9225’s 130 MHz bandwidth. A large gain stage(s) is often required to compensate for the high insertion losses of a SAW filter used for channel selection and image rejection. The gain stage will also provide adequate isolation for the SAW filter from the charge kickback currents associated with the AD9225’s switched capacitor input stage. Rev. C SFDR DUAL-TONE (dBFS) 55 0.1F 10F 80 60 200 RF2317 RF2312 SFDR SINGLE-TONE (dBFS) 95 Figure 27. IF Undersampling at 35 MHz (F1 = 34.63 MHz, F2 = 35.43 MHz, CLOCK = 20 MHz) AD9225 20 100 SNR/SFDR (dBFS) and detection, among other things. See Application Note AN-302 on using this technique in digital receivers. –19– 80 75 70 SFDR DUAL-TONE (dBFS) SNR SINGLE-TONE (dBc) 65 60 55 50 –15 –10 –5 0 AIN (dBFS) Figure 28. IF Undersampling at 45 MHz (F1 = 44.81 MHz, F2 = 45.23 MHz, CLOCK = 20 MHz) AD9225 100 carefully managed. Alternatively, the ground plane under the ADC may contain serrations to steer currents in predictable directions where cross coupling between analog and digital would otherwise be unavoidable. The AD9225/AD9225EB ground layout, shown in Figure 38, depicts the serrated type of arrangement. 95 SFDR SINGLE-TONE (dBFS) 90 SNR/SFDR (dBFS) 85 80 The board is built primarily over a common ground plane. It has a slit to route currents near the clock driver. Figure 31 illustrates a general scheme of ground and power implementation, in and around the AD9225. 75 70 SFDR DUAL-TONE (dBFS) 65 60 SNR SINGLE-TONE (dBc) 55 50 –15 –10 AVDD A 0 –5 LOGIC SUPPLY DVDD A D AIN (dBFS) Figure 29. IF Undersampling at 70 MHz (F1 = 69.50 MHz, F2 = 70.11 MHz, CLOCK = 25 MHz) ADC IC ANALOG CIRCUITS 100 VIN 95 SNR/SFDR (dBFS) 85 B IA CSTRAY ID AVSS 80 75 A = ANALOG 70 D = DIGITAL SFDR DUAL-TONE (dBFS) A GND DVSS V A D Figure 31. Ground and Power Consideration SNR SINGLE-TONE (dBc) 60 55 50 –15 DIGITAL CIRCUITS A A SFDR SINGLE-TONE (dBFS) 90 65 DIGITAL LOGIC ICs CSTRAY –10 –5 Analog and Digital Driver Supply Decoupling The AD9225 features separate analog and driver supply and ground pins, helping to minimize digital corruption of sensitive analog signals. In general, AVDD, the analog supply, should be decoupled to AVSS, the analog common, as close to the chip as physically possible. Figure 32 shows the recommended decoupling for the analog supplies; 0.1 mF ceramic chip and 10 mF tantalum capacitors should provide adequately low impedance over a wide frequency range. Note that the AVDD and AVSS pins are co-located on the AD9225 to simplify the layout of the decoupling capacitors and provide the shortest possible PCB trace lengths. The AD9225/AD9225EB power plane layout, shown in Figure 39 depicts a typical arrangement using a multilayer PCB. 0 AIN (dBFS) Figure 30. IF Undersampling at 85 MHz (F1 = 84.81 MHz, F2 = 85.23 MHz, CLOCK = 20 MHz) GROUNDING AND DECOUPLING Analog and Digital Grounding Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: • The minimization of the loop area encompassed by a signal and its return path. • The minimization of the impedance associated with ground and power paths. • The inherent distributed capacitor formed by the power plane, PCB insulation and ground plane. AVDD 10F AD9225 0.1F AVSS Figure 32. Analog Supply Decoupling These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. While the AD9225 features separate analog and driver ground pins, it should be treated as an analog component. The AVSS and DRVSS pins must be joined together directly under the AD9225. A solid ground plane under the ADC is acceptable if the power and ground return currents are The CML is an internal analog bias point used internally by the AD9225. This pin must be decoupled with at least a 0.1 mF capacitor as shown in Figure 33. The dc level of CML is approximately AVDD/2. This voltage should be buffered if it is to be used for any external biasing. –20– CML 0.1F AD9225 Figure 33. CML Decoupling Rev. C AD9225 The digital activity on the AD9225 chip falls into two general categories: correction logic and output drivers. The internal correction logic draws relatively small surges of current, mainly during the clock transitions. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents are a function of the load on the output bits; large capacitive loads are to be avoided. Note that the internal correction logic of the AD9225 is referenced to AVDD while the output drivers are referenced to DRVDD. DRVDD 10F DRVSS Figure 34. Digital Supply Decoupling The decoupling shown in Figure 34, a 0.1 mF ceramic chip capacitor and a 10 mF tantalum capacitor, are appropriate for a reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionally, and/or using external buffers/latches. Rev. C AD9225 0.1F A complete decoupling scheme will also include large tantalum or electrolytic capacitors on the PCB to reduce low frequency ripple to negligible levels. Refer to the AD9225/AD9225EB schematic and layouts in Figures 35 to 41 for more information regarding the placement of decoupling capacitors. –21– AD9225 U5 REF43 TP38 2 VOUT VIN GND 4 JP19 2 1 2 2 C26 0.1F 1 1 TP31 TP30 1 JP21 + C2 2 0.1F 10F 2 10V 6 U4 N2 AD187 OUT N1 –V 2 1 IN 4 2 1 C19 10F 10V TP37 1 1 2 1 + C48 22F 20V AGND 2 1 R29 1k 3 2 2 C31 2 0.1F 1 2 1 J3 1 C53 0.1F 2 1 JP22 JP23 JP24 JP25 1 C21 + 10F 10V 2 C34 0.1F 2 1 R30 316 1 2 C20 2 10F 10V 1 2 R32 50 2 2 C33 0.1F 1 1 2 R21 200 1 2 TP33 R22 200 1 2 TP32 1 T1 1 R24 50 5 3 6 2 P4 3 T4-6T 1 1 1 2 C49 2 VEE 1 20V 1 1 P5 1 JP11 JP12 U9 11 2 1 U9 9 2 2 1 L5 FBEAD P5 2 1 TP8 U9 5 6 1 1 U9 DRVDD 1 1 22F 2 20V DGND 1 L7404 + C51 2 13 D11 12 1 DVDD 1 1 J5 2 R35 50 1 2 U1 REF43 2 1 1 C16 0.1F 2 10F 2 10V 3 C13 0.1F 2 1 R19 4k 1 J2 R2 5k 2 1 TP4 U8 3 1 1 R1 50 2 2 3 2 CCV B 2 A + 1 C9 1 JP6 1 2 JP7 1 2 C15 0.1F 1 8 1 R18 1k JP9 2 L7404 TP1 10 10F 2 10V 1 2 L7404 13 AVDD TP2 12 L7404 1 1 1 U8 2 TP3 1 2 1 C10 0.1F U8 DECOUPLING + C3 10F 2 10V Y2 Y3 Y4 Y5 Y6 Y7 Y8 17 16 15 14 13 12 11 2 1 19 D4 D3 D2 D1 D0 OTR CLK U6 74541 Y1 18 C11 0.1F 2 1 2 1 U8 JP3 A1 A2 A3 A4 A5 A6 A7 A8 1 JP2 2 2 A B 3 1 JP32 U9 3 4 U9 1 U8 11 2 3 4 5 6 7 8 9 D10 D9 D8 D7 D6 D5 + C7 C17 0.1F 1 L7404 TP10 1 6 JP16 3 A B 2 20 VCC 10 GND G1 G2 2 3 4 5 6 7 8 9 C5 10V 10F 1 + 2 18 A1 Y1 17 A2 Y2 U7 16 A3 74541 Y3 15 A4 Y4 14 A5 Y5 13 A6 Y6 12 A7 Y7 11 A8 Y8 1 TP9 1 1 2 3 4 5 6 7 8 VCC CLR RCO CLK QA A U2 B 74LS161 QB QC C QD D ENT ENP GND LOAD 16 15 14 13 12 11 10 1 JP15 1 2 L6 FBEAD A B 2 JP28 1 R6 22 1 2 1 R7 22 1 2 1 R8 22 2 1 1 R9 22 2 1 1 R10 22 1 2 1 R11 22 1 2 1 R12 22 1 2 1 R13 22 1 2 1 R14 22 1 2 1 R15 22 1 2 1 2 1 1 2 1 JP29 1 R20 22 10F 10V DUTAVDDIN 2 P6 2 2 1 + C58 2 22F 20V AGND 1 P6 TP25 1 P1 P1 2 3 P1 P1 4 5 P1 P1 6 7 P1 P1 8 TP24 TP23 TP22 TP21 9 P1 P1 10 11 P1 P1 12 13 P1 P1 14 15 P1 P1 16 17 P1 P1 18 19 P1 P1 20 21 P1 P1 22 23 P1 P1 24 25 P1 P1 26 27 P1 P1 28 29 P1 P1 30 TP20 TP19 TP26 TP18 TP17 TP16 TP15 31 P1 P1 32 33 P1 P1 34 35 P1 P1 36 37 P1 P1 38 39 P1 P1 40 TP14 TP13 TP12 TP11 2 DVDD JP30 1 2 JP31 2 1 9 1 R5 22 1 2 R16 22 DUTAUDD 1 R17 22 1 2 1 3 DRVDD + C23 C38 0.1F 1 R33 1k 2 1 L7404 2 10F 2 10V C59 2 0.1F 20 VCC 10 GND G1 G2 P3 + C1 1 2 1 19 2 1 C4 10V 10F 2 +1 1 JP14 L7404 2 JP8 1 CW 9 4 L7404 U8 L7404 2 U8 2 1 JP13 2 5 1 10F 2 10V 1 JP17 JP5 JP27 1 1 C14 0.1F 2 1 C37 0.1F TP40 DVDD 2 OTR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK 1 2 DUTAVDD 2 JP1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OTR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CLK 1 C40 0.001F TP5 1 2 22F 20V 2 AGND AVDD 1 C41 0.001F 2 C43 15pF P3 + C47 C42 15pF C12 0.1F 1 2 U9 DECOUPLING VIN VOUT GND AVDD + C8 2 2 1 L7404 C56 0.1F 1 TP39 L1 FBEAD 1 C44 15pF 22F 2 20V DGND 2 2 JP4 8 2 2 1 TP7 1 L7404 1 C45 15pF 1 1 1 + C6 TP6 1 10 L7404 DRVDDIN 2 DVDDIN 1 P2 P2 JP10 1 C46 15pF 1 C54 0.1F 2 + 22F 2 1 1 C25 0.1F 2 TP36 L4 FBEAD VEEIN 2 4 2 1 1 1 C52 0.1F AD9225 DUTDRVDD 2 R23 200 2 AVDD2 AVSS2 SENSE VREF REFCOM CAPB CAPT CML U3 VINA VINB AVSS1 AVDD1 DRVSS DRVDD C24 2 0.1F JP18 1 1 2 1 JP26 1 1 TP28 J1 15 16 17 18 19 20 21 22 23 24 25 26 27 28 C35 0.1F 2 AVDDIN1 1 1 1 1 AVDD 1 2 2 C32 0.1F L2 FBEAD 1 2 1 C36 0.1F 2 2 2 TP27 1 C39 0.001F 1 C22 + 10F 10V 2 2 TP29 TP37 VCC 2 1 1 2 1 1 C57 0.1F 2 Q1 2N2222 C27 0.1F 1 2 1 VEE L3 FBEAD VCCIN 8 +V 1 1 R4 10k 2 7 3 1 1 2 R3 10k + C28 R28 1 50 2 R27 4.99k P4 R31 820 2 1 C29 0.1F TP34 DUTAVDD 2 1 IN 1 1 + C18 10F 2 10V 1 2 1 R26 4.99k 2 JP20 1 2 P4 1 C30 0.1F + 1 R25 2.49k 2 1 1 R34 2 50 1 1 J4 VCC + 6 1 2 1 C55 0.1F + C50 10F 2 10V DVDD Figure 35. Evaluation Board Schematic –22– Rev. C AD9225 Figure 36. Evaluation Board Component Side Layout (Not to Scale) Figure 39. Evaluation Board Solder Side Layout (Not to Scale) Figure 37. Evaluation Board Ground Plane Layout (Not to Scale) Figure 40. Evaluation Board Power Plane Layout Figure 41. Evaluation Board Solder Side Silkscreen (Not to Scale) Figure 38. Evaluation Board Component Side Silkscreen (Not to Scale) Rev. C –23– AD9225 OUTLINE DIMENSIONS 18.10 (0.7126) 17.70 (0.6969) 15 28 7.60 (0.2992) 7.40 (0.2913) 1 10.65 (0.4193) 10.00 (0.3937) 14 0.75 (0.0295) 45° 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 1.27 (0.0500) BSC 0.51 (0.0201) 0.31 (0.0122) SEATING PLANE 8° 0° 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157) 06-07-2006-A COMPLIANT TO JEDEC STANDARDS MS-013-AE CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 1. 28-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-28) Dimensions shown in millimeters and (inches) 10.50 10.20 9.90 15 5.60 5.30 5.00 1 14 0.25 0.09 1.85 1.75 1.65 2.00 MAX 0.05 MIN COPLANARITY 0.10 8.20 7.80 7.40 0.65 BSC 0.38 0.22 SEATING PLANE 8° 4° 0° 0.95 0.75 0.55 COMPLIANT TO JEDEC STANDARDS MO-150-AH 060106-A 28 Figure 2. 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9225AR AD9225ARS AD9225ARSRL AD9225ARZ AD9225ARZRL AD9225ARSZ AD9225ARSZRL 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Standard Small Outline Package [SOIC_W] 28-Lead Shrink Small Outline Package [SSOP] 28-Lead Shrink Small Outline Package [SSOP] Z = RoHS Compliant Part. Rev. C | Page 24 of 25 Package Option RW-28 RS-28 RS-28 RW-28 RW-28 RS-28 RS-28 AD9225 REVISION HISTORY 1/11—REV. B to REV. C Updated Outline Dimensions ....................................................... 24 Moved and Changes to Ordering Guide ..................................... 24 8/03—REV. A to REV. B Renumbered TPCs and Figures ........................................ Universal Changes to Ordering Guide ............................................................ 4 Updated Outline Dimensions ....................................................... 24 ©1998–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00577-0-1/11(C) Rev. C | Page 25 of 25