Freescale MC33696FJE/R2 Pll tuned uhf transceiver for data transfer application Datasheet

Freescale Semiconductor
Data Sheet
MC33696
Rev. 12, 02/2010
MC33696
PLL Tuned UHF Transceiver for Data Transfer Applications
Overview
The MC33696 is a highly integrated transceiver
designed for low-voltage applications. It includes a
programmable PLL for multi-channel applications,
an RSSI circuit, a strobe oscillator that periodically
wakes up the receiver while a data manager checks
the content of incoming messages. A configuration
switching feature allows automatic changing of the
configuration between two programmable settings
without the need of an MCU.
© Freescale Semiconductor, Inc., 2006–2010. All rights reserved.
SWITCH
VCC2IN
GNDSUBD
STROBE
NC
VCCIN
GNDIO
31
30
29
28
27
26
25
1
24
SEB
VCC2RF
2
23
SCLK
19
DATACLK
RFOUT
7
18
RSSIC
GNDPA2
8
17
GNDDIG
16
6
GND
GNDPA1
15
CONFB
RBGAP
20
14
5
VCCDIG2
VCC2VCO
13
MISO
VCCDIG
21
12
MOSI
VCC2OUT
22
4
11
3
VCCINOUT
RFIN
GNDLNA
10
•
•
•
20 kbps maximum data rate using
Manchester coding
2.1 V to 3.6 V or 5 V supply voltage
Programmable via SPI
6 kHz PLL frequency step
RSSIOUT
XTAL0UT
•
GND
General:
• 304 MHz, 315 MHz, 426 MHz, 434 MHz,
868 MHz, and 915 MHz ISM bands
• Choice of temperature ranges:
— –40°C to +85°C
— –20°C to +85°C
• OOK and FSK transmission and reception
32
Features
QFN32
9
2
LQFP32
XTALIN
1
Features
•
•
•
Frequency hopping capability with PLL toggle time below 30 µs
Current consumption:
— 13.5 mA in TX mode
— 10.3 mA in RX mode
— Less then 1 mA in RX mode with strobe ratio = 1/10
— 260 nA standby and 24 μA off currents
Configuration switching — allows fast switching of two register banks
Receiver:
• –106.5 dBm sensitivity, up to –108 dBm in FSK 2.4 kbps
• Digital and analog RSSI (received signal strength indicator)
• Automatic wakeup function (strobe oscillator)
•
•
•
•
Embedded data processor with programmable word recognition
Image cancelling mixer
380 kHz IF filter bandwidth
Fast wakeup time
Transmitter:
• Up to 7.25 dBm output power
• Programmable output power
• FSK done by PLL programming
Ordering information
Temperature Range
QFN Package
LQFP Package
–40°C to +85°C
MC33696FCE/R2
MC33696FJE/R2
–20°C to +85°C
MC33696FCAE/R2
MC33696FJAE/R2
MC33696 Data Sheet, Rev. 12
2
Freescale Semiconductor
Freescale Semiconductor
GNDPA2
GNDPA1
RFOUT
VCC2VC0
GNDLNA
RFIN
VCC2RF
ACCLNA
Analog
Data Filter
and Slicer
Strobe
Oscillator
PFD
XCO
WTCH_TESTOUT
DATA_RATE
AGC_CONTROL
FM_AM
Detector
RSSI
4 Bits
A/D
State
Machine
Rx Data
Manager
V&I
Reference
PA
VCC2RF
SLOPE_&_POWER_CONTROL
FREQUENCY_12BITS
MODULATION
Tx Data
Manager
Clock
Generator
Fractional
Divider
FM-to-AM
Converter
AGC
IF
Amplifier
Logarithmic
Amplifier
/2 or
Buffer
VCO
1.5 MHz,
BW 400 kHz
ANALOG_SIGNALS
BAND
/2
AGC_CONTROL
PMA + I/Q
Image
Reject
TEST_CONTROL
Analog
Test
BAND
GAIN_SET
LNA
+I/Q
Mixers
SWITCH_TESTOUT
RSSIOUT_TESTIN
RSSI_8BITS
Voltage
Regulator
DIG_CLOCK
IF_REF_CLOCK
SPI
Voltage
Regulator
Pre
Regulator
VCCDIG2
XTALOUT
XTALIN
VCCDIG
DATACLK
CONFB
GND
GND
GNDDIG
GNDIO
GNDSUBD
GNDSUBA
RSSIC
SEB
MOSI
MISO
SCLK
STROBE
RBGAP
VCC2OUT
VCC2IN
VCCINOUT
VCCIN
Features
MC33696 Data Sheet, Rev. 12
3
Pin Functions
Figure 1. Block Diagram
3
Pin Functions
Table 1. Pin Functions
Pin
Name
Description
1
RSSIOUT
RSSI analog output
2
VCC2RF
2.1 V to 2.7 V internal supply for LNA
3
RFIN
4
GNDLNA
Ground for LNA (low noise amplifier)
5
VCC2VCO
2.1 V to 2.7 V internal supply for VCO
6
GNDPA1
PA ground
7
RFOUT
RF output
8
GNDPA2
PA ground
9
XTALIN
10
XTALOUT
11
VCCINOUT
2.1 V to 3.6 V power supply/regulator output
12
VCC2OUT
2.1 V to 2.7 V voltage regulator output for analog and RF modules
13
VCCDIG
2.1 V to 3.6 V power supply for voltage limiter
14
VCCDIG2
1.5 V voltage limiter output for digital module
15
RBGAP
16
GND
17
GNDDIG
18
RSSIC
19
DATACLK
Data clock output to microcontroller
20
CONFB
Configuration mode selection input
21
MISO
Digital interface I/O
22
MOSI
Digital interface I/O
23
SCLK
Digital interface clock I/O
24
SEB
25
GNDIO
Digital I/O ground
26
VCCIN
2.1 V to 3.6 V or 5.5 V input
27
NC
28
STROBE
29
GNDSUBD
30
VCC2IN
2.1 V to 2.7 V power supply for analog modules for decoupling capacitor
31
SWITCH
RF switch control output
32
GND
RF input
Crystal oscillator input
Crystal oscillator output
Reference voltage load resistance
General ground
Digital module ground
RSSI control input
Digital interface enable input
No connection
Strobe oscillator capacitor or external control input
Ground
General ground
MC33696 Data Sheet, Rev. 12
4
Freescale Semiconductor
Maximum Ratings
4
Maximum Ratings
Table 2. Maximum Ratings
Parameter
Symbol
Value
Unit
VCCIN
VGND–0.3 to 5.5
V
Supply voltage on pins: VCCINOUT, VCCDIG
VCC
VGND–0.3 to 3.6
V
Supply voltage on pins: VCC2IN, VCC2RF, VCC2VCO
VCC2
VGND–0.3 to 2.7
V
—
VGND–0.3 to VCC2
V
Voltage allowed on pin: RFOUT
VCCPA
VGND–0.3 to VCC+2
V
Voltage allowed on digital pins: SEB, SCLK, MISO, MOSI, CONFB,
DATACLK, RSSIC, STROBE
VCCIO
VGND–0.3 to VCC+0.3
V
ESD HBM voltage capability on each pin1
—
±2000
V
ESD MM voltage capability on each pin2
—
±200
V
Solder heat resistance test (10 s)
—
260
°C
Storage temperature
TS
–65 to +150
°C
Junction temperature
TJ
150
°C
Supply voltage on pin: VCCIN
Voltage allowed on each pin (except RFOUT and digital pins)
NOTES:
1 Human body model, AEC-Q100-002 rev. C.
2
Machine model, AEC-Q100-003 rev. C.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
5
Power Supply
5
Power Supply
Table 3. Supply Voltage Range Versus Ambient Temperature
Temperature Range1
Parameter
Symbol
Unit
–40°C to +85°C
–20°C to +85°C
Supply voltage on VCCIN, VCCINOUT, VCCDIG for 3 V operation
VCC3V
2.7 to 3.6
2.1 to 3.6
V
Supply voltage on VCCIN for 5 V operation
VCC5V
4.5 to 5.5
4.5 to 5.5
V
Supply voltage on VCCPA for 3 V or 5 V operation
VCCPA
3.0 to 3.6
3.0 to 3.6
V
NOTES:
1
–40°C to +85°C: MC33696FCE/FJE.
–20°C to +85°C: MC33696FCAE/FJAE.
The circuit can be supplied from a 3 V voltage regulator or battery cell by connecting VCCIN,
VCCINOUT, and VCCDIG (See Figure 43 or Figure 44). It is also possible to use a 5 V power supply
connected to VCCIN; in this case VCCINOUT and VCCDIG should not be connected to VCCIN (See
Figure 45 or Figure 46).
The RFOUT pin cannot be biased with a voltage higher than 3.6 V. For 5 V operation, biasing voltage is
available on VCCINOUT.
An on-chip low drop-out voltage regulator supplies the RF and analog modules (except the strobe
oscillator and the low voltage detector, which are directly supplied from VCCINOUT). This voltage
regulator is supplied from pin VCCINOUT and its output is connected to VCC2OUT. An external
capacitor (C8 = 100 nF) must be inserted between VCC2OUT and GND for stabilization and decoupling.
The analog and RF modules must be supplied by VCC2 by externally wiring VCC2OUT to VCC2IN,
VCC2RF, and VCC2VCO.
A second voltage regulator supplies the digital part. This regulator is powered from pin VCCDIG and its
output is connected to VCCDIG2. An external capacitor (C10 = 100 nF) must be inserted between
VCCDIG2 and GNDDIG, for decoupling. The supply voltage VCCDIG2 is equal to 1.6 V. In standby
mode, this voltage regulator goes into an ultra-low-power mode, but VCCDIG2 = 0.7 × VCCDIG.
This enables the internal registers to be supplied, allowing configuration data to be saved.
6
Supply Voltage Monitoring and Reset
At power-on, an internal reset signal (Power-on Reset, POR) is generated when supply voltage is around
1.3 V. All registers are reset.
When the LVDE bit is set, the low-voltage detection module is enabled. This block compares the supply
voltage on VCCINOUT with a reference level of about 1.8 V. If the voltage on VCCINOUT drops below
1.8 V, status bit LVDS is set. The information in status bit LVDS is latched and reset after a read access.
MC33696 Data Sheet, Rev. 12
6
Freescale Semiconductor
Receiver Functional Description
NOTE
If LVDE = 1, the LVD module remains enabled. The circuit cannot be put
in standby mode, but remains in LVD mode with a higher quiescent current,
due to the monitoring circuitry. LVD function is not accurate in standby
mode.
7
Receiver Functional Description
The receiver is based on a superheterodyne architecture with an intermediate frequency IF (see Figure 1).
Its input is connected to the RFIN pin. Frequency down conversion is done by a high-side injection I/Q
mixer driven by the frequency synthesizer. An integrated poly-phase filter performs rejection of the image
frequency.
The low intermediate frequency allows integration of the IF filter providing the selectivity. The IF Filter
center frequency is tuned by automatic frequency control (AFC) referenced to the crystal oscillator
frequency.
Sensitivity is met by an overall amplification of approximately 96 dB, distributed over the reception chain,
comprising low-noise amplifier (LNA), mixer, post-mixer amplifier, and IF amplifier. Automatic gain
control (AGC), on the LNA and the IF amplifier, maintains linearity and prevents internal saturation.
Sensitivity can be reduced using four programmable steps on the LNA gain.
Amplitude demodulation is achieved by peak detection. Frequency demodulation is achieved in two steps:
the IF amplifier AGC is disabled and acts as an amplitude limiter; a filter performs a frequency-to-voltage
conversion. The resulting signal is then amplitude demodulated in the same way as in the case of amplitude
modulation with an adaptive voltage reference.
A low-pass filter improves the signal-to-noise ratio of demodulated data. A data slicer compares
demodulated data with a fixed or adaptive voltage reference and provides digital level data.
This digital data is available if the integrated data manager is not used.
If used, the data manager performs clock recovery and decoding of Manchester coded data. Data and clock
are then available on the serial peripheral interface (SPI). The configuration sets the data rate range
managed by the data manager and the bandwidth of the low-pass filter.
An internal low-frequency oscillator can be used as a strobe oscillator to perform an automatic wakeup
sequence.
It is also possible to define two different configurations for the receiver (frequency, data rate, data manager,
modulation, etc.) that are automatically loaded during wakeup or under MCU control.
If the PLL goes out of lock, received data is ignored.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
7
Transmitter Functional Description
8
Transmitter Functional Description
The single-ended power amplifier is connected to the RFOUT pin.
In the case of amplitude modulation, coded data sent by the microcontroller unit (MCU) are used for on/off
keying (OOK) the RF carrier. Rise and fall times of the RF transmission are controlled to minimize
spurious emission.
In the case of frequency modulation, coded data sent by the MCU are used for frequency shift keying
(FSK) the RF carrier.
RF output power can be reduced using four programmable steps.
Out-of-lock detection prevents any out-of-band emission, by stopping the transmission.
The logic output SWITCH enables control of an external RF switch for isolating the two RF pins. Its output
toggles when the circuit changes from receive to transmit, and vice versa.
This signal can also be used to control an external power amplifier or LNA, or to indicate to the MCU the
current state of the MC33696 (RX or TX).
9
Frequency Planning
9.1
Clock Generator
All clocks running in the circuit are derived from the reference frequency provided by the crystal oscillator
(frequency fref, period tref). The crystal frequency is chosen in relation to the band in which the MC33696
has to operate. Table 4 shows the value of the CF bits.
Table 4. Crystal Frequency and CF Values Versus Frequency Band
RF
Frequency
(MHz)
CF1
CF0
LOF1
LOF0
FREF (Crystal
Frequency)
(MHz)
FIF (IF
Frequency)
(MHz)
Dataclk
Divider
Fdataclk
(kHz)
Digclk
Divider
Fdigclk
(kHz)
Tdigclk
(µs)
304
0
0
0
0
16.96745
1.414
60
282.791
30
565.582
1.77
315
0
0
1
0
17.58140
1.465
60
293.023
30
586.047
1.71
426
0
1
1
0
23.74913
1.484
80
296.864
40
593.728
1.68
433.92
0
1
0
1
24.19066
1.512
80
302.383
40
604.767
1.65
868.3
1
1
0
1
24.16139
1.510
80
302.017
40
604.035
1.66
916.5
1
1
1
1
25.50261
1.594
80
318.783
40
637.565
1.57
9.2
Intermediate Frequency
The IF filter is controlled by the crystal oscillator to guarantee the frequency over temperature and voltage
range. The IF filter center frequency, FIF, can be computed using the crystal frequency fref and the value
of the CF bits:
• If CF[0] = 0 : FIF = fref/9×1.5/2
MC33696 Data Sheet, Rev. 12
8
Freescale Semiconductor
MCU Interface
•
If CF[0] = 1 : FIF = fref/12×1.5/2
The cut-off frequency given in the parametric section can be computed by scaling to the FIF.
Example 1. Cut-off Frequency Computation
Compute the low cut-off frequency of the IF filter for a 16.9683 MHz crystal oscillator. For this
reference frequency, FIF = 1.414 MHz.
So, the 1.387 MHz1 low cut-off frequency specified for a 1.5 MHz IF frequency becomes
1.387 × 1.414/1.5 = 1.307 MHz.
9.3
Frequency Synthesizer Description
The frequency synthesizer consists of a local oscillator (LO) driven by a fractional N phase locked loop
(PLL).
The LO is an integrated LC voltage controlled oscillator (VCO) operating at twice the RF frequency (for
the 868 MHz frequency band) or four times the RF frequency (for the 434 MHz and 315 MHz frequency
bands). This allows the I/Q signals driving the mixer to be generated by division.
The fractional divider offers high flexibility in the frequency generation for:
• Switching between transmit and receive modes.
• Achieving frequency modulation in FSK modulation transmission.
• Performing multi-channel links.
• Trimming the RF carrier.
Frequencies are controlled by means of registers. To allow for user preference, two programming access
methods are offered (see Section 18.3, “Frequency Registers”).
•
•
10
In friendly access, all frequencies are computed internally from the contents of the carrier
frequency and deviation frequency registers.
In direct access, the user programs direct all three frequency registers.
MCU Interface
The MC33696 and the MCU communicate via a serial peripheral interface (SPI). According to the selected
mode, the MC33696 or the MCU manages the data transfer. The MC33696’s digital interface can be used
as a standard SPI (master/slave) or as a simple interface (SPI deselected). In the following case, the
interface’s pins are used as standard I/O pins. However, the MCU has the highest priority, as it can control
the MC33696 by setting CONFB pin to the low level. During an SPI access, the STROBE pin must remain
at high level to prevent the MC33696 from entering standby mode.
The interface is operated by six I/O pins.
• CONFB — Configuration control input
The configuration mode is reached by setting CONFB to low level.
1. Refer to parameter 3.3 found in Section 21.3, “Receiver Parameters.”
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
9
MCU Interface
•
•
•
•
•
STROBE — Wakeup control input
The STROBE pin controls the ON/OFF sequence of the MC33696. When STROBE is set to low
level, the receiver is off—when STROBE is set to high level, the receiver is on. The current
consumption in receive mode can be reduced by strobing the receiver. The periodic wakeup can be
done by MCU only or by an internal oscillator thanks to an external capacitor (strobe oscillator
must be previously enabled by setting SOE bit to 1). Refer to Section 12.3, “Receiver On/Off
Control,” for more details.
SEB — Serial interface enable control input
When SEB is set high, pins SCLK, MOSI, and MISO are set to high impedance, and the SPI bus
is disabled. When SEB is set low, SPI bus is enabled. This allows individual selection in a multiple
device system, where all devices are connected via the same bus. The rest of the circuit remains in
the current state, enabling fast recovery times, but the power amplifier is disabled to prevent any
uncontrolled RF transmission.
If the MCU shares the SPI access with the MC33696 only, SEB control by the MCU is optional.
If not used, it could be hardwired to 0.
SCLK — Serial clock input/output
Synchronizes data movement in and out of the device through its MOSI and MISO lines. The
master and slave devices can exchange a byte of information during a sequence of eight clock
cycles. Since SCLK is generated by the master device, this line is an input on the slave device.
MOSI — Master output slave input/output
In configuration mode, MOSI is an input.
In transmission mode, MOSI is an input and receives encoded data from MCU.
In receive mode, MOSI is an output. Received data is sent on MOSI (see Table 5).
Transmits bytes when master, and receives bytes when slave, with the most significant bit first.
When no data are output, SCLK and MOSI force a low level.
MISO — Master input/slave output
In configuration mode only, data read from registers is sent to the MCU with the MSB first. There
is no master function. Data are valid on falling edges of SCLK. This means that the clock phase
and polarity control bits of the microcontroller SPI have to be CPOL = 0 and CPHA = 1 (using
Freescale acronyms).
Table 5 summarizes the serial digital interface feature versus the selected mode.
Table 5. Serial Digital Interface Feature versus Selected Mode
Selected Mode
MC33696 Digital Interface Use
Configuration
SPI slave, data received on MOSI, SCLK from MCU, MISO is output (SEB=0)
Transmit
SPI deselected, MOSI receives encoded data from MCU (SEB =0)
Receive
DME = 1
SPI master, data sent on MOSI with clock on SCLK (SEB=0)
DME = 0
SPI deselected, received data are directly sent to MOSI (SEB=0)
Standby / LVD
SPI deselected, all I/O are high impedance (SEB =1)
MC33696 Data Sheet, Rev. 12
10
Freescale Semiconductor
State Machine
Refer to Section 11, “State Machine,” and to Figure 2 for more details about all the conditions that must
be complied with in order to change between two selected modes.
The data transfer protocol for each mode is described in the following section.
11
State Machine
This section describes how the MC33696 controller executes sequences of operations, relative to the
selected mode. The controller is a finite state machine, clocked at Tdigclk. An overview is presented in
Figure 2 (note that some branches refer to other diagrams that provide more detailed information).
There are four different modes: configuration, transmit, receive, and standby/LVD. Each mode is exclusive
and can be entered in different ways, as follows.
• External signal: CONFB for configuration mode
• External signal and configuration bits: CONFB, STROBE, TRXE, and/or MODE for all other
modes
• External signal and internal conditions: see Figure 3 and Figure 12 for information on how to
enter standby/LVD mode
After a Power-on Reset (POR), the circuit is in standby mode (see Figure 2) and the configuration register
contents are set to the reset value.
At any time, a low level applied to CONFB forces the finite state machine into configuration mode,
whatever the current state. This is not always shown in state diagrams, but must always be considered.
Refer to (Section 16, “Power-On Reset and MC33696 Startup”) for timing sequence between standy mode
and configuration mode.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
11
State Machine
CONFB = 1,
and STROBE = 0
Power-on Reset
State 60
SPI Deselected
Standby/LVD
Standby/LVDMode
Mode
SPI Slave
SPI Master
CONFB = 0,
and STROBE = 1
Refer to Table 5 for pins direction
CONFB = 0,
and STROBE = 1
Activate Bank Change,
(A to B or B to A)
State 1
CONFB = 1,
TRXE = 1
Configuration Mode
Configuration
Mode
State 30
Transmit Mode
Transmit Mode
CONFB = 1,
TRXE = 1
Receive Mode
… and DME = 0
… and SOE = 1
See
Figure3
Figure3
… and DME = 1
… and SOE = 0
See
Figure4
Figure4
… and SOE = 1
See
Figure11
… and SOE = 0
See
Figure12
Figure 2. State Machine Overview
MC33696 Data Sheet, Rev. 12
12
Freescale Semiconductor
Receive Mode
12
Receive Mode
The receiver is either waiting for an RF transmission or is receiving one. Two different processes are
possible, as determined by the values of the DME bit. The transmitter part is kept off. A state diagram
describes the sequence of operations in each case.
NOTE
If the STROBE pin is tied to a high level before switching to receive mode,
the receiver does not go through an off or standby state.
12.1 Data Manager Disabled (DME=0)
Data manager disabled means that the SPI is deselected and raw data is sent directly on the MOSI line,
while SCLK remains at low level.
Two different processes are possible, as determined by the values of the SOE bit.
12.1.1 Data Manager Disabled and Strobe Pin Control
Raw received data is sent directly on the MOSI line. Figure 3 shows the state diagram.
SPI Deselected
STROBE = 0
STROBE = 1
State 5
Standby/LVD
STROBE = 1
STROBE = 0
State 5b
On
Raw Data on MOSI
Figure 3. Receive Mode, DME = 0, SOE = 0
•
•
State 5:
The receiver is in standby/LVD mode. For further information, see Section 14, “Standby: LVD
Mode.” A high level applied to STROBE forces the circuit to state 5b.
State 5b:
The receiver is kept on by the STROBE pin. Raw data is output on the MOSI line.
For all states: At any time, a low level applied to CONFB forces the state machine to state 1, configuration
mode.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
13
Receive Mode
12.1.2 Data Manager Disabled and Strobe Oscillator Enabled
Raw received data is sent directly on the MOSI line. Figure 4 shows the state diagram.
SPI Deselected
STROBE = 0
STROBE = 0
STROBE = 1
State 0
Off
Off Counter = ROFF[2:0]
or STROBE = 1
On Counter = RON[3:0]
and STROBE different than 1
State 0b
On
Raw Data on MOSI
Figure 4. Receive Mode, DME = 0, SOE = 1
•
•
State 0:
The receiver is off, but the strobe oscillator and the off counter are running. Forcing the STROBE
pin low freezes the strobe oscillator and maintains the system in this state.
State 0b:
If STROBE pin is set to high level or the off counter reaches the ROFF value, the receiver is on.
Raw data is output on the MOSI line.
For all states: At any time, a low level applied to CONFB forces the state machine to state 1, configuration
mode.
12.2 Data Manager Enabled (DME=1)
The data manager is enabled. The SPI is master. The MC33696 sends the recovered clock on SCLK and
the received data on the MOSI line. Data is valid on falling edges of SCLK.
If an even number of bytes is received, the data manager may add an extra byte. The content of this extra
byte is random. If the data received do not fill an even number of bytes, the data manager will fill the last
byte randomly. Figure 5 shows a typical transfer.
MC33696 Data Sheet, Rev. 12
14
Freescale Semiconductor
Receive Mode
STROBE
1
0
CONFB
1
0
*Refer to
(Section 10)
SEB 1
0
SCLK 1
(Output) 0
Recovered Clock Updated to I ncoming Signal Data Rate
MOSI 1
(Output) 0
D 7 D6 D 5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D 2 D1 D0 D7 D6 D5 D4 D3 D2 D 1 D0
Figure 5. Typical Transfer in Receive mode with Data Manager
12.2.1 Data Manager Functions
In receive mode, Manchester coded data can be processed internally by the data manager. After decoding,
the data is available on the digital interface, in SPI format. This minimizes the load on the MCU.
The data manager, when enabled (DME = 1), has five purposes:
• First ID detection: the received data are compared with the identifier stored in the ID register.
• Then the HEADER recognition: the received data is compared with the data stored in the
HEADER register.
• Clock recovery: the clock is recovered during reception of the preamble and is computed from the
shortest received pulse. While this signal is being received, the recovered clock is constantly
updated to the data rate of the incoming signal.
• Output data and recovered clock on digital interface: see Figure 5.
• End-of-message detection: an EOM consists of two consecutive NRZ ones or zeroes.
Table 6 details some MC33696 features versus DME values.
Table 6. the MC33696 Features versus DME
DME
Digital Interface Use
Data Format
Output
0
SPI deselected, received data
are directly sent to MOSI
when CONFB = 1
Bit stream
No clock
MOSI
—
1
SPI master, data sent on
MOSI with clock on SCLK
when CONFB = 1
Data bytes
Recovered clock
MOSI
SCLK
12.2.2 Manchester Coding Description
The MC33696 data manager is able to decode Manchester-coded messages. For other codings, the data
manager should be disabled (DME=0) for raw data to be available on MOSI.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
15
Receive Mode
DME = 0: The data manager is disabled. The SPI is deselected. Raw data is sent directly on the MOSI line,
while SCLK remains at the low level.
Manchester coding is defined as follows: data is sent during the first half-bit; and the complement of the
data is sent during the second half-bit. The signal average value is constant.
0
1
0
0
1
1
0
ORIGINAL
DATA
MANCHESTER
CODED DATA
Figure 6. Example of Manchester Coding
Clock recovery can be extracted from the data stream itself. To achieve correct clock recovery,
Manchester-coded data must have a duty cycle between 47% and 53%.
12.2.3 Frame Format
A complete telegram includes the following sequences: a preamble, an identifier (ID), a header, the
message, and an end-of-message (EOM).
PREAMBLE ID ID ID ID HEADER DATA ………… EOM
Figure 7. Example of Frame Format
These bit sequences are described below.
12.2.3.1 Preamble
A preamble is required before the first ID detected. It enables:
— In the case of OOK modulation, the AGC to settle, and the data slicer reference voltage to
settle if DSREF = 1
— In the case of FSK modulation, the data slicer reference voltage to settle
— The data manager to start clock recovery
No preamble is needed in case of several IDs are sent as shown in Figure 8. The ID field must be greater
than two IDs. The first ID will have the same function as the preamble, and the second ID will have the
same function as the single ID.
... ID ID ID ID ID ID HEADER DATA …………
Figure 8. Example of Frame with Several IDs, No Preamble Needed
For both cases, the preamble content must be defined carefully, to ensure that it will not be decoded as the
ID or the header. Figure 9 defines the different preamble in OOK and FSK modulation.
MC33696 Data Sheet, Rev. 12
16
Freescale Semiconductor
Receive Mode
OOK MODULATION (DSREF = 0)
AGC Settling Time
Clock Recovery
ID
1 NRZ > 200 μs (1)
1 Manchester
‘0’ Symbol
at Data Rate
OOK MODULATION (DSREF = 1)
AGC Settling Time
Data Slicer Reference Settling Time
Clock Recovery
ID
1 NRZ > 200 μs (1)
1 Manchester
0 Symbol
at Data Rate (3)
At Least 3 Manchester
0 Symbols
at Data Rate (2 and 3)
FSK MODULATION (DSREF = 1)
Data Slicer Reference Settling Time
Clock Recovery
ID
At Least 3 Manchester
0 Symbols
at Data Rate (2 and 3)
1 Manchester
0 Symbol
at Data Rate (3)
NOTES:
1. The AGC settling time pulse can be split over different pulses as long as the overall duration is at least 200 μs.
The 200 μs pulse may be replaced by : (1 bit @ 2400 bps or 2 bits @ 4800 bps or 4 bits @ 9600 bps or 8 bits @ 19200 bps).
2. Table 14 defines the minimum number of Manchester symbols required for the data slicer operation versus the data and average filter cut-off
frequencies.
3. The Manchester 0 symbol can be replaced by a 1.
Figure 9. Preamble Definition
12.2.3.2 ID
When clock recovery is done, the data manager verifies if an ID is received. The ID is used to identify a
useful frame to receive. It is also necessary, when the receiver is strobed, to detect an ID in order to stay
in run mode and not miss the frame.
The ID allows selection of the correct device in an RF transmission, as the content has been loaded
previously in the ID register. Its length is variable, defined by the IDL[1:0] bits. The complement of the
ID is also recognized as the identifier.
It is possible to build a tone to form the detection sequence by programming the ID register with a full
sequence of ones or zeroes.
Once the ID is detected, a HEADER will be searched to detect the beginning of the useful data to send on
the SPI port.
See Section 12.2.4, “State Machine in Receive Mode When DME=1” for more details when ID is not
detected when SOE=1 or SOE=0.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
17
Receive Mode
12.2.3.3 HEADER
The HEADER defines the beginning of the message, as it is compared with the HEADER register. Its
length is variable, defined by the HDL[1:0] bits. The complement of the header is also recognized as the
header—in this case, output data is complemented. The header and its complement should not be part of
the ID.
The ID and the header are sent at the same data rate as data.
12.2.3.4 Data and EOM
The data must follow the header, with no delay.
The message is completed with an end-of-message (EOM), consisting of two consecutive NRZ ones or
zeroes (i.e., a Manchester code violation). Even in the case of FSK modulation, data must conclude with
an EOM, and not simply by stopping the RF transmission.
12.2.4 State Machine in Receive Mode When DME=1
When the strobe oscillator is enabled (SOE = 1), the receiver is continuously cycling on/off. The ID must
be recognized for the receiver to stay on. Consequently, the transmitted ID burst must be long enough to
include two consecutive receiver-on cycles.
When the strobe oscillator is not enabled (SOE = 0), these timing constraints must be respected by the
external control applied to pin STROBE.
Figure 11 shows the correct detection of an ID when STROBE is controled internally using the strobe
oscillator (SOE=1) or externally by the MCU (SOE=0).
RF
Signal
Preamble
ID
ID
ID
ID
ID
ID
ID
Header
Data
EOM
ID Field
Receiver
Status
SPI
Output
On
Off
On Time
Off Time
On
Off
ID
Detected
Data
Figure 10. Complete Transmission with ID Detection
Two different processes are possible, as determined by the values of the SOE bit.
12.2.4.1 Data Manager Enabled and Strobe Oscillator Enabled
Figure 11 shows the state diagram when the data manager and the strobe oscillator are enabled. In this
configuration, the receiver is controlled internally by the strobe oscillator. However, external control via
the STROBE pin is still possible, and overrides the strobe oscillator command.
MC33696 Data Sheet, Rev. 12
18
Freescale Semiconductor
Receive Mode
•
•
•
•
State 10:
The receiver is off, but the strobe oscillator and the off counter are running. Forcing STROBE pin
to the low level maintains the system in this state.
State 11:
The receiver is waiting for a valid ID. If an ID, or its complement, is detected, the state machine
advances to state 12; otherwise, the circuit goes back to state 10 at the end of the RON time, if
STROBE ≠ 1.
State 12:
An ID or its complement has been detected. The data manager is now waiting for a header or its
complement. If neither a header, nor its complement, has been received before a time-out of 256
bits at data rate, the system returns to state 10.
State 13:
A header, or its complement, has been received. Data and clock signals are output on the SPI port
until EOM indicates the end of the data sequence. If the complement of the header has been
received, output data are complemented also.
For all states: At any time, a low level applied to STROBE forces the circuit to state 10, and a low level
applied on CONFB forces the state machine to state 1, configuration mode.
When an EOM occurs before the current byte is fully shifted out, dummy bits are inserted until the number
of shifted bits is a multiple of 8.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
19
Receive Mode
SPI Master
STROBE = 0
STROBE = 0
State 10
Off
STROBE = 1
Off Counter = ROFF[2:0]
or STROBE = 1
On Counter = RON[3:0]
and STROBE ≠ 1
State 11
On
Waiting For a Valid ID
ID Detected
Time Out
State 12
On
Waiting for a Valid Header
EOM Received
and STROBE = 1
Header Received
State 13
On
Output Data and Clock
Waiting for End of Message
EOM Received
and STROBE ≠ 1
Figure 11. Receive Mode, DME = 1, SOE = 1
12.2.4.2 Data Manager Enabled and Receiver Controlled by Strobe Pin
Figure 12 shows the state diagram when the data manager is enabled and the strobe oscillator is disabled.
In this configuration, the receiver is controlled only externally by the MCU.
MC33696 Data Sheet, Rev. 12
20
Freescale Semiconductor
Receive Mode
SPI Master
STROBE = 0
SPI Deselected
State 20
Standby/LVD
STROBE = 1
STROBE = 1
STROBE = 0
State 21
On
Waiting For a Valid ID
ID Detected
STROBE = 0
State 22
On
Waiting for a Valid Header
EOM Received
and STROBE = 1
Header Received
State 23
On
Output Data and Clock
Waiting for End of Message
EOM Received
and STROBE = 0
Figure 12. Receive Mode, DME = 1, SOE = 0
•
•
•
•
State 20:
The receiver is in standby/LVD mode. For further information, see Section 14, “Standby: LVD
Mode.” A high level applied to STROBE forces the circuit to state 21.
State 21:
The circuit is waiting for a valid ID. If an ID, or its complement, is detected, the state machine
advances to state 22; if not, the state machine will remain in state 21, as long as STROBE is high.
State 22:
If a header, or its complement, is detected, the state machine advances to state 23. If not, the state
machine will remain in state 22, as long as STROBE is high.
State 23:
A header or its complement has been received; data and clock signals are output on the SPI port
until an EOM indicates the end of the data sequence. If the complement of the header has been
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
21
Receive Mode
received, output data are complemented also. When an EOM occurs before the current byte is fully
shifted out, dummy bits are inserted until the number of shifted bits is a multiple of 8.
For all states: At any time, a low level applied to STROBE puts the circuit into state 20, and a low level
applied to CONFB forces the state machine to state 1, configuration mode.
12.2.4.3 Timing Definition
As shown in Figure 13, a settling time is required when entering the on state.
Receiver
Status
RF
Signal
Off
On
Off
Ton
Toff
On
Setting
Time
ID
ID
ID
ID
ID
ID
ID
ID
ID
Header
Data
EOM
ID
Detected
Figure 13. Receiver Usable Window
The goal for the receiver is to recognize at least one ID during Ton time. Many IDs are transmitted during
that time.
During Ton, the receiver should be able to detect an ID, but as receiver and transmitter are not
synchronized, an ID may already be transmitted when Ton time begins. That is the reason why Ton should
be sized to receive two IDs: to be sure to recognize one, no matter what the time difference between
beginning of transmission of the ID and beginning of run time for the receiver.
Ton should also include the setting time of the receiver. Setting time is composed of the crystal oscillator
wakeup time1, the PLL lock time2, and setup of all analog parameters3 (AGC and demodulator need some
time to settle).
Toff should be sized to allow the positioning of an on state during the transmission of the ID field.
During the setting time, no reception is possible.
12.3 Receiver On/Off Control
In receive mode, on/off sequencing can be controlled internally using the strobe oscillator, or managed
externally by the MCU through the input pin STROBE.
If the strobe oscillator is selected (SOE = 1):
• Off time is clocked by the strobe oscillator
• On time is clocked by the crystal oscillator, enabling accurate control of the on time, and therefore
of the current consumption of the whole system
1. Refer to parameter 5.10 found in Section 21.5, “PLL & Crystal Oscillator.”
2. Refer to parameter 5.9 found in Section 21.5, “PLL & Crystal Oscillator.”
3. Refer to preamble definition found in Figure 9.
MC33696 Data Sheet, Rev. 12
22
Freescale Semiconductor
Receive Mode
Each time is defined with the associated value found in the RXONOFF register.
• On time = RON[3:0] × 512 × Tdigclk (see Table 19; begins after the crystal oscillator has started)
• Off time = receiver off time = N × TStrobe + MIN (TStrobe / 2, receiver on time), with N decoded
from ROFF[2:0] (see Table 20)
The strobe oscillator is a relaxation oscillator in which an external capacitor C13 is charged by an internal
current source (see Figure 46). When the threshold is reached, C13 is discharged and the cycle restarts.
The strobe frequency is FStrobe = 1/TStrobe with TStrobe = 106 × C13.
In receive mode, setting the STROBE pin to VCCIO at any time forces the circuit on. As VCCIO is above
the oscillator threshold voltage, the condition on which the STROBE pin is set to VCCIO is detected
internally, and the oscillator pulldown circuitry is disabled. This limits the current consumption. After the
STROBE pin is forced to high level, the external driver should pass via a “0” state to discharge the
capacitor before going to high impedance state (otherwise, the on time would last a long time after the
driver release).
When the strobe oscillator is running (i.e., during an off time), forcing the STROBE pin to VGND stops the
strobe clock, and therefore keeps the circuit off.
Figure 14 shows the associated timings.
STROBE
Threshold
STROBE
Clock
Off
Counter
STROBE
SET TO VCCIO
tStrobe
0
0
ROFF-1ROFF
Digital
Clock
On
Counter
0
0
RON
Receiver
Status
RON
Off
On
RON
Off
On
Cycling Period
Crystal Oscillator Startup
Figure 14. Receiver On/Off Sequence
12.4 Received Signal Strength Indicator (RSSI)
12.4.1 Module Description
In receive mode, a received signal strength indicator can be activated by setting bit RSSIE.
The input signal is measured at two different points in the receiver chain by two different means, as
follows.
•
At the IF filter output, a progressive compression logarithmic amplifier measures the input signal,
ranging from the sensitivity level up to –50 dBm.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
23
Receive Mode
•
At the LNA output, the LNA AGC control voltage is used to monitor input signals in the range
–50 dBm to –20 dBm.
Therefore, the logarithmic amplifier provides information relative to the in-band signal, whereas the LNA
AGC voltage senses the input signal over a wider band.
The RSSI information given by the logarithmic amplifier is available in:
•
•
Analog form on pin RSSIOUT
Digital form in the four least significant bits of the status register RSSI
The information from the LNA AGC is available in digital form in the four most significant bits of status
register RSSI.
The whole content of status register RSSI provides 2 ¥ 4 bits of RSSI information about the incoming
signal (see Section 18.6, “RSSI Register”).
Figure 15 shows a simplified block diagram of the RSSI function.
The quasi peak detector (D1, R1, C1) has a charge time of about 20 μs to avoid sensitivity to spikes.
R2 controls the decay time constant of about 5 ms to allow efficient smoothing of the OOK modulated
signal at low data rates. This time constant is useful in continuous mode when S2 is permanently closed.
To allow high-speed RSSI updating in peak pulse measurement, a discharge circuit (S1) is required to reset
the measured voltage and to allow new peak detection.
RSSI Register
LNA AGC Out
IF Filter Output
ADC
MSB
LSB
S2
Σ
D1
R1
RSSIOUT
C1
R2
S1
C2
Figure 15. RSSI Simplified Block Diagram
S2 is used to sample the RSSI voltage to allow peak pulse measurement (S2 used as sample and hold), or
to allow continuous transparent measurement (S2 continuously closed).
The 4-bit analog-to-digital convertor (ADC) is based on a flash architecture. The conversion time is
16 × Tdiglck. As a single convertor is used for the two analog signals, the RSSI register content is updated
on a 32 × Tdigclk timebase.
If RSSIE is reset, the whole RSSI module is switched off, reducing the current consumption. The output
buffer connected to RSSIOUT is set to high impedance.
MC33696 Data Sheet, Rev. 12
24
Freescale Semiconductor
Receive Mode
12.4.2 Operation
Two modes of operation are available: sample mode and continuous mode.
12.4.2.1 Sample Mode
Sample mode allows the peak power of a specific pulse in an incoming frame to be measured.
The quasi peak detector is reset by closing S1. After 7 × Tdigclk, S1 is released. S2 is closed when RSSIC
is set high. On the falling edge of RSSIC, S2 is opened. The voltage on RSSIOUT is sampled and held.
The last RSSI conversion results are stored in the RSSI register and no further conversion is done.
The RSSI register is updated every 32 × Tdigclk. Therefore, the minimum duration of the high pulse on
RSSIC is 32 × Tdigclk.
RSSIC
7 x tdigclk
S1
Closed
Open
Closed
S2
Open
Closed
Open
RSSI Register
Frozen
Updated
Frozen
Sampled and Hold RSSI Voltage
RSSIOUT
Peak Detector
Reset
Sampling
CONFB
CMD
MOSI
RSSI Value
MISO
Figure 16. RSSI Operation in Sample Mode
12.4.2.2 Continuous Mode
Continuous mode is used to make a peak measurement on an incoming frame, without having to select a
specific pulse to be measured.
The quasi peak detector is reset by closing S1. After 7 × Tdigclk, S1 is opened. S2 is closed when RSSIC
is set high. As long as RSSIC is kept high, S2 is closed, and RSSIOUT follows the peak value with a decay
time constant of 5 ms.
The ADC runs continuously, and continually updates the RSSI register. Thus, reading this register gives
the most recent conversion value, prior to the register being read. The minimum duration of the high pulse
on CONFB is 32 × Tdigclk.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
25
Transmit Mode
RSSIC
5 x tdigclk
S1
S2
RSSI Register
Closed
Open
Open
Closed
Frozen
Updated
Frozen
Updated
Frozen
RSSIOUT
Peak Detector
Test
CONFB
MOSI
CMD
CMD
MISO
RSSI
RSSI
Figure 17. RSSI Operation in Continuous Mode
13
Transmit Mode
13.1 Description
The SPI is deselected. The MC33696 receives the message to transmit on the MOSI line (see Figure 18).
1
STROBE 0
1
CONFB 0
*Refer to
(Section 10)
SEB
1
0
MOSI 1
(Input) 0
Data
Figure 18. Transfer in Transmit Mode
In OOK modulation (MODU=0), modulation is performed by switching the RF output stage on and off.
MOSI = 0: output stage off
MOSI = 1: output stage on
In FSK modulation (MODU = 1), modulation is performed by switching the RF carrier between two
values.
MOSI = 0: fcarrier0 corresponding to a logical 0
MOSI = 1: fcarrier1 corresponding to a logical 1
MC33696 Data Sheet, Rev. 12
26
Freescale Semiconductor
Standby: LVD Mode
See the FRM bit description (Figure 26) and Section 18.3, “Frequency Registers,” for more details about
setting carrier frequencies.
See Section 10, “MCU Interface,” for more details about setting the level on the SEB pin.
13.2 State Machine
In transmit mode, the state diagram is reduced to only one state: state 30. The circuit is either waiting for
a digital telegram to send, or is sending one. In this mode, the circuit can be considered as a simple RF
physical interface. The information presented on MOSI is sent directly in RF (according to the selected
modulation), with no internal processing.
Data transmission is possible only if the PLL is within the lock-in range. Therefore, during transmission,
if the PLL switches out of lock-in range, the RF output stage is switched off internally, thereby preventing
data from being transmitted in an unwanted band.
14
Standby: LVD Mode
The SPI is deselected. CONFB is set to high level and STROBE to low level in order to enter this mode.
Nothing is sent and all incoming data are ignored until CONFB and SEB go low to switch back to
configuration mode.
Standby/LVD mode allows minimum current consumption to be achieved. Depending upon the value of
the LVDE bit, the circuit is in standby mode (state 60) or LVD mode (state 5 and 20).
LVDE = 0: The transceiver is in standby; consumption is reduced to leakage current (current state after
POR).
LVDE = 1: The LVD function is enabled; consumption is in the range of tens of microamperes.
The only way to exit this mode is to go back to configuration mode by applying a low level to CONFB and
a high level to STROBE.
15
Configuration Mode
15.1 Description
This mode is used to write or read the internal registers of the MC33696.
As long as a low level is applied to CONFB and a high level to STROBE (see Figure 2), the MCU is the
master node driving the SCLK input, the MOSI line input, and the MISO line output. Whatever the
direction, SPI transfers are 8-bit based and always begin with a command byte, which is supplied by the
MCU on MOSI. To be considered as a command byte, this byte must come after a falling edge on CONFB.
Figure 19 shows the content of the command byte.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
27
Configuration Mode
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
N1
N0
A4
A3
A2
A1
A0
R/W
Figure 19. Command Byte
Bits N[1:0] specify the number of accessed registers, as defined in Table 7.
Table 7. Number N of Accessed Registers
N[1:0]
Number N of Accessed Registers
00
1
01
2
10
4
11
8
Bits A[4:0] specify the address of the first register to access. This address is then incremented internally
by N after each data byte transfer.
R/W specifies the type of operation:
0 = Read
1 = Write
Thus, this bit is associated with the presence of information on MOSI (when writing) or MISO (when
reading).
Figure 20 and Figure 21 show write and read operations in a typical SPI transfer. In both cases, the SPI is
a slave. A received byte is considered internally on the eighth falling edge of SCLK. Consequently, the last
received bits, which do not form a complete byte, are lost.
Refer to Section 21.9, “Digital Interface Timing,” to view the timing definition for SPI communication.
If several SPI accesses are done, a high and low level is applied to CONFB, and so on. By applying a high
level to STROBE, the MC33696 never enters standby mode. If there is no way to configure the level on
STROBE, the time interval between two SPI accesses must be less than one digital clock period Tdigclk.
NOTE
A low level applied to CONFB and a high level to STROBE do not affect
the configuration register contents.
See Section 10, “MCU Interface,” for more details about setting the level on
the SEB pin.
MC33696 Data Sheet, Rev. 12
28
Freescale Semiconductor
Configuration Mode
1
STROBE 0
SEB 1
0
CONFB 1
0
SCLK 1
(Input) 0
MOSI 1
(Input) 0
N1 N0 A4 A3 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
MISO 1
(Output) 0
Figure 20. Write Operation in Configuration Mode (N[1:0] = 01)
STROBE
1
0
SEB 1
0
CONFB 1
0
SCLK 1
(Input) 0
MOSI 1
(Input) 0
N1 N0 A4 A3 A2 A1 A0 R/W
MISO 1
(Output) 0
D7 D6 D5 D4 D3 D2 D1
D0
D7 D6 D5 D4 D3 D2 D1 D0
Figure 21. Read Operation in Configuration Mode (N[1:0] = 01)
15.2 State Machine
The configuration mode is selected by the microcontroller unit (MCU) to write to the internal registers (to
configure the system) or to read them. In this mode, the SPI is a slave. The analog parts (receiver and
transmitter) remain in the state (on, off) they were in prior to entering configuration mode, until a new
configuration changes them. In configuration mode, data can be neither sent nor received. As long as a low
level is applied to CONFB, the circuit stays in State 1, the only state in this mode.
Figure 22 describe the valid sequence for enabling a correct transition from Standby/LVD mode to
configuration mode. SPI startup time corresponds to the addition of the crystal oscillator lock time
(parameter 5.10) and the PLL lock time (parameter 5.9).
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
29
Power-On Reset and MC33696 Startup
STROBE
CONFB
SPI Startup Time
SEB
Figure 22. Valid Sequence from Standby/LVD Mode to Configuration Mode
Figure 23 describes the sequence for enabling a correct transition from receive mode to configuration
mode.
1. MC33696 is in receive mode.
2. CONFB is forced to low level during one digital period Tdigclk in order to reset the state machine
only.
3. CONFB is set to high level during the time length of an ID.
1
2
3
STROBE
CONFB
SEB
SCLK
MOSI
Figure 23. Valid Sequence from Receive Mode to Configuration Mode
16
Power-On Reset and MC33696 Startup
The startup sequence can be divided into three stages as defined in Figure 24:
1. The power supply is applied to the MC33696 and an external pullup resistor on CONFB is required
to enter standby mode. SEB can be either set to low level if the SPI access is not shared with
another external MCU, or connected to an external pullup resistor (see Section 10, “MCU
Interface”).
During this stage and during the ramp-up of the power supply, signals from the MCU connected to
the MC33696 are undefined. That is why the MC33696 must start in standby mode.
NOTE
Along with the ramp-up of power supply, one of these two conditions must
be complied with:
— Power supply of the MC33696 must rise in 1 ms from 0 V to 3 V.
— The level on STROBE pin is lower than 0.75 V until the power supply reaches 3 V.
MC33696 Data Sheet, Rev. 12
30
Freescale Semiconductor
Configuration Switching
Proposed solutions to verify these conditions are :
— If the receiver does not wake periodically and it is only controlled by the STROBE pin (strobe
oscillator disable SOE = 0), an external pulldown resistor on STROBE is required (see
Figure 43 for a 3 V application schematic).
— If the receiver wakes periodically (strobe oscillator enable SOE = 1), the state of the MCU
pins must be defined first and then a power supply must be applied to the MC33696. A
transistor can be used to control the power supply on the VCCIN pin of the MC33696. This
transistor will be driven by an MCU I/O (see Figure 44 for a 3 V application schematic in
strobe oscillator mode).
2. A high level is applied on STROBE in order to wake the MC33696 and enter transmit/receive
mode. The duration of this state should be greater than the sum of lock time parameter 5.9 and
5.10. Refer to Section 15, “Configuration Mode.”
3. CONFB and SEB must be forced to low level to enter configuration mode. Register values are
writen into the internal registers of the MC33696. Refer to Section 15, “Configuration Mode,”
and to Figure 45.
1
VCC
STROBE
2
3
3V
0
1
0
*Refer to
(Section 10) SEB 1
0
CONFB 1
0
1
SCLK
0
MOSI 1
0
N1N0 A4 A3 A2 A1 A0 R/W
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
MISO 1
0
Figure 24. Startup sequence
17
Configuration Switching
This feature allows for defining two different configurations using two different banks, and for switching
them automatically during wakeup when using a strobe oscillator, or by means of the strobe pin actuation
by the MCU. This automatic feature may be used only in receiver mode; however, if one of the register
banks is related to a transmitter configuration, it may be accessed directly by programing some bits to
define the active bank, thus allowing fast switching between receiver mode and transmitter mode, or
between any different possible configurations.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
31
Configuration Switching
17.1 Bit Definition
Two sets of configuration registers are available. They are grouped in two different banks: Bank A and
Bank B. Two bits are used to define which bank represents the state of the component.
Bit Name
BANKA
BANKB
BANKA
X
0
1
Direction
R/W
R/W
Location
Bank A
Bank B
BANKB
Actions
0
Bank A is active (TX or RX)
1
Bank B is active (TX or RX)
1
Bank A and Bank B are active and will be used one after the other (RX only)
At any time, it is possible to know which is the active bank by reading the status bit BANKS.
Bit Name
BANKS
Direction
R
Location
Comment
A&B
Bank status: indicates which register bank is active.
This bit, available in Bank A and Bank B, returns the same value.
MC33696 Data Sheet, Rev. 12
32
Freescale Semiconductor
Configuration Switching
17.1.1 Direct Switch Control
The conditions to enter direct switch control are:
• Strobe pin = VCC
• SOE bit = 0
By simply writing BANKA and BANKB, the active bank will be defined:
BANKA
X
0
1
BANKB
0
Bank A is active (TX or RX)
1
Bank B is active (TX or RX)
1
Not allowed in direct switch control
The defined bank is active after exiting the configuration mode, in other words, CONFB line goes high.
The direct switch control should be used when:
• One or both banks are in transmitter configuration (MODE = 1)
• When the strobe oscillator cannot be used to define the switch timing (for example, not periodic)
• When strobe pin use is not possible (no sleep mode between the two configurations)
• No automatic switching is required and MCU SPI access is possible
17.1.2 Strobe Pin Switch Control
The conditions to enter strobe pin switch control are:
• Strobe pin: controlled by MCU I/O port
• SOE bit = 0
By simply writing BANKA and BANKB, the active banks will be defined.
BANKA
X
0
1
BANKB
0
Bank A is active (TX or RX)
1
Bank B is active (TX or RX)
1
Bank A and Bank B are both active, configuration will toggle at each wakeup;
not allowed with MODE = 1
The strobe pin will control the off/on state of the MC33696. The various available sequences are described
in the following subsections.
17.1.2.1 BANKA = X, BANKB = 0
State A
OFF
State A
OFF
Strobe Pin
If strobe pin is 1, configuration is defined by Bank A, BANKS = 1.
If strobe pin is 0, MC33696 configuration is OFF.
If a message is received during State A, current state remains State A up to end of message.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
33
Configuration Switching
17.1.2.2 BANKA = 0, BANKB = 1
State B
OFF
State B
OFF
Strobe Pin
If strobe pin is 1, configuration is defined by Bank B, BANKS = 0.
If strobe pin is 0, MC33696 configuration is OFF.
If a message is received during State B, current state remains State B up to end of message.
17.1.2.3 BANKA = 1, BANK B = 1
State A
OFF
State B
OFF
State A
Strobe Pin
Banks Bit
If strobe pin is 1, configuration is defined by BANKS. BANKS is toggled at each falling edge of the strobe
pin.
If strobe pin is 0, MC33696 configuration is OFF.
If a message is received during state A or state B, current state remains the same up to end of message.
If a read or write access is done using SPI, the next sequence will begin with state A whatever was the
active state before SPI access by MCU.
17.1.3 Strobe Oscillator Switch Control
The conditions to enter strobe oscillator switch control are:
• Strobe pin connected to an external capacitor to define timing (see Section 12.3, “Receiver
On/Off Control”)
• Strobe pin can also be connected to the MCU I/O port
• SOE bit = 1
By simply writing BANKA and BANKB, the active banks will be defined.
BANKA
X
0
1
BANKB
0
Bank A is active (TX or RX)
1
Bank B is active (TX or RX)
1
Bank A and Bank B are both active, configuration will toggle at each wakeup;
not allowed with MODE = 1
The MCU can override strobe oscillator control by controlling the strobe pin level. If MCU I/O port is in
high impedance, the strobe oscillator will control the OFF/ON state of the MC33696. The various
available sequences are described in the following subsections.
MC33696 Data Sheet, Rev. 12
34
Freescale Semiconductor
Configuration Switching
17.1.3.1 BANKA = X, BANKB = 0
State A
OFF
State A
OFF
State A
If strobe pin is 1, configuration is defined by Bank A, BANKS = 1.
If strobe pin is 0, MC33696 configuration is OFF.
If a message is received during State A, current state remains State A up to end of message.
17.1.3.2 BANKA = 0, BANKB = 1
State B
OFF
State B
OFF
State B
If strobe pin is 1, configuration is defined by Bank B, BANKS = 0.
If strobe pin is 0, MC33696 configuration is OFF.
If a message is received during State B, current state remains State B up to end of message.
17.1.3.3 BANKA = 1, BANK B = 1
State A
State B
OFF
StateA
StateB
OFF
Banks Bit
BANKS toggles at the end of each state A or state B.
If strobe is forced to 1, configuration is frozen according to BANKS value.
If a read or write access is done using SPI, the next sequence will begin with state A in whatever was the
active state before SPI access by MCU.
A
Strobe
B
OFF
A
B
OFF
A
B
OFF
A
B
1
Z
Banks
For all available sequences:
• State A and State B are defined by Bank A and Bank B.
• State A duration, TonA is defined by Bank A RON[3–0].
• State B duration, TonB is defined by Bank B RON[3–0].
• OFF duration, TonB is defined by Bank A ROFF[2–0].
• If strobe pin is 1, the state is ON and defined by BANKS at that time. It remains this state up to
the release of strobe and end of message if a message is being received.
• If a message is being received during State A or B, current state remains State A or B up to end of
message.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
35
Register Description
•
•
If strobe pin is 0 the state is OFF.
If strobe pin is released from 0 while state is OFF, the initial OFF period is completed.
The change of duration of one state (due to the STROBE pin level or a message being received) has no
influence on the timing of the following states (A, B, or OFF).
18
Register Description
This section discusses the internal registers, which are composed of two classes of bits.
• Configuration and command bits allow the MC33696 to operate in a suitable configuration.
• Status bits report the current state of the system.
All registers can be accessed by the SPI. These registers are described below.
At power-on, the POR resets all registers to a known value (in the shaded rows in the following tables).
This defines the MC33696’s default configuration.
18.1 Configuration Registers (Description Bank A only)
Figure 25 describes configuration register 1, CONFIG1.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
LOF1
LOF0
CF1
CF0
RESET
SL
LVDE
CLKE
$00
Reset Value
1
0
0
1
0
0
0
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 25. CONFIG1 Register
Table 8. LOF[1:0] and CF[1:0] Setting Versus Carrier Frequency
Carrier Frequency
LOF1
LOF0
CF1
CF0
304 MHz
0
0
0
0
315 MHz
1
0
0
0
426 MHz
0
1
0
1
434 MHz
0
1
0
1
868 MHz
0
1
1
1
915 MHz
1
1
1
1
RESET is a global reset. The bit is cleared internally, after use.
0 = no action
1 = reset all registers and counters
SL (Switch Level) selects the active level of the SWITCH output pin.
MC33696 Data Sheet, Rev. 12
36
Freescale Semiconductor
Register Description
Table 9. Active Level of SWITCH Output Pin
SL
Transceiver Function
Level on SWITCH
0
Receiving
Low
Transmitting
High
Transmitting
Low
Receiving
High
1
LVDE (Low Voltage Detection Enable) enables the low voltage detection function.
0 = disabled
1 = enabled
NOTE
This bit is cleared by POR. In the event of a complete loss of the supply
voltage, LVD is disabled at power-up, but the information is not lost as the
status bit LVDS is set by POR.
CLKE (Clock Enable) controls the DATACLK output buffer.
0 = DATACLK remains low
1 = DATACLK outputs Fdataclk
Figure 26 describes configuration register 2, CONFIG2.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
DSREF
FRM
MODU
DR1
DR0
TRXE
DME
SOE
$01
Reset Value
0
0
0
1
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 26. CONFIG2 Register
DSREF (Data Slicer Reference) selects the data slicer reference.
0 = Fixed reference (cannot be used in FSK)
1 = Adaptive reference (recommended for maximum sensitivity in OOK and FSK)
In the case of FSK modulation (MODU = 1), DSREF must be set.
FRM (Frequency Register Manager) enables either a user friendly access to one frequency register or a
direct access to the two frequency registers.
0 = The carrier frequency and the FSK deviation are defined by the F register
1 = The local oscillator frequency and the two carrier frequencies are defined by two frequency
registers, F and FT.
MODU (Modulation) sets the data modulation type.
0 = On/Off Keying (OOK) modulation
1 = Frequency Shift Keying (FSK) modulation
DR[1:0] (Data Rate) configure the receiver blocks operating in base band.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
37
Register Description
•
•
•
Low-pass data filter
Low-pass average filter generating the data slicer reference, if DSREF is set
Data manager
Table 10. Base Band Parameter Configuration
DR1
DR0
Data Filter
Cut-off Frequency
Average Filter
Cut-off Frequency
Data Manager
Data Rate Range
0
0
6 kHz
0.5 kHz
2–2.8 kBd
0
1
12 kHz
1 kHz
4–5.6 kBd
1
0
24 kHz
2 kHz
8–10.6 kBd
1
1
48 kHz
4 kHz
16–22.4 kBd
If the data manager is disabled, the incoming signal data rate must be lower than or equal to the data
manager maximum data rate.
TRXE (Transceiver Enable) enables the whole transceiver. This bit must be set to high level if MCU wakes
the MC33696 to enter receive or transmit mode.
0 = standby mode
1 = other modes can be activated
DME (Data Manager Enable) enables the data manager.
0 = disabled
1 = enabled
SOE (Strobe Oscillator Enable) enables the strobe oscillator.
0 = disabled
1 = enabled
Figure 27 describes configuration register 3, CONFIG3.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
AFF1
AFF0
OLS
LVDS
ILA1
ILA0
OLA1
OLA0
$02
Reset Value
0
0
1
1
0
0
0
0
Access
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Figure 27. CONFIG3 Register
OLS (Out of Lock Status) indicates the current status of the PLL.
0 = The PLL is in lock-in range
1 = The PLL is out of lock-in range
LVDS (Low Voltage Detection Status) indicates that a low voltage event has occurred when LVDE = 1.
This bit is read-only and is cleared after a read access.
0 = No low voltage detected
1 = Low voltage detected
ILA[1:0] (Input Level Attenuation) define the RF input level attenuation.
MC33696 Data Sheet, Rev. 12
38
Freescale Semiconductor
Register Description
Table 11. RF Input Level Attenuation
ILA1
ILA0
RF Input Level
Attenuation
See Parameter
Number
0
0
0 dB
2.5
0
1
8 dB
2.6
1
0
16 dB
2.7
1
1
30 dB
2.8
Values in Table 11 assume the LNA gain is not reduced by the AGC.
OLA[1:0] (Output Level Attenuation) define the RF output level attenuation.
Table 12. RF Output Level Attenuation
OLA1
OLA0
RF Output Level
Attenuation
See Parameter
Number
0
0
0 dB
4.2
0
1
8 dB
4.3
1
0
16 dB
4.4
1
1
25 dB
4.5
AFF[1:0] (Average Filter Frequency) define the average filter cut-off frequency if the AFFC bit is set.
Table 13. Average Filter Cut-off Frequency
AFF1
AFF0
Average Filter Cut-off
Frequency
0
0
0.5 kHz
0
1
1 kHz
1
0
2 kHz
1
1
4 kHz
If AFFC is reset, the average filter frequency is directly defined by bits DR[1:0], as shown in Table 10.
If AFFC is set, AFF[1:0] allow the overall receiver sensitivity to be improved by reducing the average
filter cut-off frequency. The typical preamble duration of three Manchester zeroes or ones at the data rate
must then be increased, as shown in Table 14.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
39
Register Description
Table 14. Minimum Number of Manchester Symbols in Preamble
versus DR[1:0] and AFF[1:0]
DR[1:0]
00
01
10
11
00
3
6
12
24
01
—
3
6
12
10
—
—
3
6
11
—
—
—
3
AFF[1:0]
18.2 Command Register
Figure 28 describes the Command register, COMMAND.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
AFFC
IFLA
MODE
RSSIE
EDD
RAGC
FAGC
BANKS
$03
Reset Value
0
0
0
0
1
0
0
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Figure 28. COMMAND Register
AFFC (Average Filter Frequency Control) enables direct control of the average filter cut-off frequency.
0 = Average filter cut-off frequency is defined by DR[1:0]
1 = Average filter cut-off frequency is defined by AFF[1:0]
IFLA (IF Level Attenuation) controls the maximum gain of the IF amplifier in OOK modulation.
0 = No effect
1 = Decreases by 20 dB (typical) the maximum gain of the IF amplifier, in OOK modulation only
The reduction in gain can be observed if the IF amplifier AGC system is disabled (by setting RAGC = 1).
MODE selects the mode.
0 = Receive mode
1 = Transmit mode
RSSIE (RSSI Enable) enables the RSSI function.
0 = Disabled
1 = Enabled
EDD (Envelop Detector Decay) controls the envelop detector decay.
0 = Slow decay for minimum ripple
1 = Fast decay
RAGC (Reset Automatic Gain Control) resets both receiver internal AGCs.
0 = No action
MC33696 Data Sheet, Rev. 12
40
Freescale Semiconductor
Register Description
1 = Sets the gain to its maximum value
A first SPI access allows RAGC to be set; a second SPI access is required to reset it.
FAGC (Freeze Automatic Gain Control) freezes both receiver AGC levels.
0 = No action
1= Holds the gain at its current value
BANKS indicates which register bank is active. This bit, available in Bank A and Bank B, returns the same
value.
0 = Bank B
1 = Bank A
18.3 Frequency Registers
Figure 29 and Figure 30 define the Frequency registers, F and FT.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Addr
Bit Name
FSK3
FSK2
FSK1
FSK0
F11
F10
F9
F8
$04
Reset Value
0
1
0
0
1
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
F7
F6
F5
F4
F3
F2
F1
F0
Reset Value
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
$05
Figure 29. F Register
Bit 23
Bit 22
Bit 21
Bit 20
Bit 19
Bit 18
Bit 17
Bit 16
Addr
Bit Name
FTA11
FTA10
FTA9
FTA8
FTA7
FTA6
FTA5
FTA4
$06
Reset Value
0
1
1
1
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit Name
FTA3
FTA2
FTA1
FTA0
FTB11
FTB10
FTB9
FTB8
Reset Value
0
0
0
0
0
1
1
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
FTB7
FTB6
FTB5
FTB4
FTB3
FTB2
FTB1
FTB0
Reset Value
0
0
0
0
0
0
0
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
$07
$08
Figure 30. FT Register
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
41
Register Description
How these registers are used is determined by the FRM bit, which is described below.
FRM = 0 (User Friendly Access)
Whatever type of modulation is used (OOK or FSK), bits F[11:0] define the carrier frequency Fcarrier. The
local oscillator frequency FLO is then set automatically to Fcarrier + FIF (with FIF = intermediate frequency).
In addition,
•
•
in the case of OOK modulation (MODU = 0):
— FSK[3:0], FTA[11:0], and FTB[11:0] are not used.
in the case of FSK modulation (MODU = 1):
— FSK[3:0] sets the frequency deviation Df as defined in Table 15.
Table 15. Frequency Deviation Definition
CF[1:0]
Frequency Deviation Δf
00, 01
Fref x(FSK[3:0]+1)/ 2048
11
Frefx(FSK[3:0]+1)/ 1024
Table 16 gives a numerical example in the 434 MHz band (CF[1:0] = 01).
Table 16. Frequency Numerical Example (434 MHz Band)
FSK[3:0]
Frequency Deviation Δf
0000
± 12 kHz
0001
± 24 kHz
0010
± 36 kHz
...
...
1111
± 192 kHz
Then, two frequencies are calculated internally, as follows.
— Fcarrier0 = F[11:0] - Δf to transmit a logical 0
— Fcarrier1 = F[11:0] + Δf to transmit a logical 1
FTA[11:0] and FTB[11:0] are not used
FRM = 1 (Direct Access)
Whatever type of modulation is used (OOK or FSK), F[11:0] defines the receiver local oscillator frequency
FLO, and,
• if OOK modulation is used (MODU = 0):
— FTA[11:0] define the carrier frequency Fcarrier
— FTB[11:0] are not used
• if FSK modulation is used (MODU = 1):
— FTA[11:0] define the carrier frequency Fcarrier0 to transmit a logical 0
— FTB[11:0] define the carrier frequency Fcarrier1 to transmit a logical 1
MC33696 Data Sheet, Rev. 12
42
Freescale Semiconductor
Register Description
Table 17 defines the value to be binary coded in the frequency registers F[11;0], FTA/B[11:0], versus the
desired frequency value F (in Hz).
Table 17. Frequency Register Value versus Frequency Value F
CF[1:0]
Frequency Register Value
00, 01
(2 x F/Fref-35) x 2048
11
(F/Fref-35) x 2048
Conversely, Table 18 gives the desired frequency F and the frequency resolution versus the value of the
frequency registers F[11;0].
Table 18. Frequency Value F versus Frequency Register Value
CF[1:0]
Frequency (Hz)
Frequency Resolution (Hz)
00, 01
(35 + F[11;0]/2048)xFref/2
Fref/4096
11
(35 + F[11;0]/2048)xFref
Fref/2048
18.4 Receiver On/Off Duration Register
Figure 31 describes the receiver on/off duration register, RXONOFF.
Bit Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
BANKA
RON3
RON2
RON1
RON0
ROFF2
ROFF1
ROFF0
$09
Reset Value
0
1
1
1
1
1
1
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 31. RXONOFF Register
BANKA defines the register bank selected, as described in Section 17, “Configuration Switching.”
RON[3:0] (Receiver On) define the receiver on time (after crystal oscillator startup) as described in
Section 12.3, “Receiver On/Off Control.”
Table 19. Receiver On Time Definition
RON[3:0]
Receiver On Time: N x 512 x Tdigclk
0000
Forbidden value
0001
1
0010
2
...
...
1111
15
ROFF[2:0] (Receiver Off) define the receiver off time as described in Section 12.3, “Receiver On/Off
Control.”
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
43
Register Description
Table 20. Receiver Off Time Definition
ROFF[2:0]
Receiver Off Time: N x TStrobe
000
1
001
2
010
4
011
8
100
12
101
16
110
32
111
63
18.5 ID and Header Registers
Figure 32 defines the ID register, ID.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
IDL1
IDL0
ID5
ID4
ID3
ID2
ID1
ID0
$0A
Reset Value
1
1
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 32. ID Register
IDL[1:0] (Identifier Length) sets the length of the identifier, as shown on Table 21.
Table 21. ID Length Selection
IDL1
IDL0
ID Length
0
0
2 bits
0
1
4 bits
1
0
5 bits
1
1
6 bits
ID[5:0] (Identifier) sets the identifier. The ID is Manchester coded. Its LSB corresponds to the register’s
LSB, whatever the specified length.
Figure 33 defines the Header register, HEADER.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
HDL1
HDL0
HD5
HD4
HD3
HD2
HD1
HD0
$0B
Reset Value
1
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 33. HEADER Register
HDL[1:0] (Header Length) sets the length of the header, as shown on Table 22.
MC33696 Data Sheet, Rev. 12
44
Freescale Semiconductor
Bank Access and Register Mapping
Table 22. Header Length Selection
HDL1
HDL0
HD Length
0
0
1 bits
0
1
2 bits
1
0
4 bits
1
1
6 bits
HD[5:0] (Header) sets the header. The header is Manchester coded. Its LSB corresponds to the register’s
LSB, whatever the specified length.
18.6 RSSI Register
Figure 34 describes the RSSI Result register, RSSI.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Bit Name
RSSI7
RSSI6
RSSI5
RSSI4
RSSI3
RSSI2
RSSI1
RSSI0
$0C
Reset Value
0
0
0
0
0
0
0
0
Access
R
R
R
R
R
R
R
R
Figure 34. RSSI Register
Bits RSSI[7:4] contain the result of the analog-to-digital conversion of the signal measured at the LNA
output.
Bits RSSI[3:0] contain the result of the analog-to-digital conversion of the signal measured at the IF filter
output.
19
Bank Access and Register Mapping
Registers are physically mapped following a byte organization. The possible address space is 32 bytes. The
base address is specified in the command byte. This is then incremented internally to address each register,
up to the number of registers specified by N[1:0], also specified by this command byte. All registers can
then be scanned, whatever the type of transmission (read or write); however, writing to read-only bits or
registers has no effect. When the last implemented address is reached, the internal address counter
automatically loops back to the first mapped address ($00).
At any time, it is possible to write or read the content of any register of Bank A and Bank B. Register access
is defined as follows:
R/W
Bit can be read and written.
R
Bit can be read. Write has no effect on bit value.
RR
Bit can be read. Read or write resets the value.
R [A]
Bit can be read. This returns the same value as Bank A.
RR [A]
Bit can be read. This returns the same value as Bank A. Read or write resets the value.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
45
Bank Access and Register Mapping
Table 23. Access to Specific Bits
Bit
Bank
Byte
Access
Comment
RESET
A
CONFIG1
R/W
OLS
A, B
CONFIG3
R-R[A]
Bit value is the real time status of the PLL, BANKA,
and BANKB access reflect the same value.
LDVS
A, B
CONFIG3
RR-RR[A}
Bit value is the latched value of the low-voltage
detector. Read or write from any bank resets value.
SOE
A, B
CONFIG2
R/W-R[A}
SOE can be modified in BANKA. Access from BANKB
reflects BANKA value.
RSSIx
A, B
RSSI
R-R[A}
RSSI value is directly read from RSSI converter.
Reflected value is the same whatever the active byte.
Available in BANKA.
MC33696 Data Sheet, Rev. 12
46
Freescale Semiconductor
Freescale Semiconductor
00h CONFIG1-A
91 h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
LOF1
LOF0
CF1
CF0
RESET
SL
LVDE
CLKE
Reset
Value
1
0
0
1
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0=
304–434
304–315
315–434
314
No
T/R
No
1=
315–916
434–916
868
434–868
Yes
R/T
Yes
01h CONFIG2-A
10 h
0Dh CONFIG1-B
91 h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
LOF1
LOF0
CF1
CF0
—
SL
LVDE
CLKE
Reset
Value
1
0
0
1
0
0
0
1
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
No
0=
304–434
304–315
315–434
314
—
T/R
No
No
Yes
1=
315–916
434–916
868
434–868
—
R/T
Yes
Yes
0Eh CONFIG2-B
10 h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
DSREF
FRM
MODU
DR1
DR0
TRXE
DME
SOE
Bit Name
DSREF
FRM
MODU
DR1
DR0
TRXE
DME
SOE
Reset
Value
0
0
0
1
0
0
0
0
Reset
Value
0
0
0
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R[A]
0=
Fixed
Friendly
OOK
2.4–4.8
2.4–9.6
Standby
No
No
0=
Fixed
Friendly
OOK
2.4–4.8
2.4–9.6
Standby
No
No
1=
Adaptive
Direct
FSK
9.6–19.2
4.8–19.2
Enable
Yes
Yes
1=
Adaptive
Direct
FSK
9.6–19.2
4.8–19.2
Enable
Yes
Yes
02h CONFIG3-A
30 h
0Fh CONFIG3-B
30 h
MC33696 Data Sheet, Rev. 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
AFF1
AFF0
OLS
LVDS
ILA1
ILA0
OLA1
OLA0
Bit Name
AFF1
AFF0
OLS
LVDS
ILA1
ILA0
OLA1
OLA0—
Reset
Value
0
0
1
1
0
0
0
0
Reset
Value
0
0
1
1
0
0
0
0
R/W
R/W
R
RR
R/W
R/W
R/W
R/W
0=
0.5–1
kHz
0.5–2
kHz
RAS
RAS
0–8 dB
0–14 dB
0–8 dB
0–14 dB
1=
2–4 kHz
1–4 kHz
Unlocked Low V
03h COMMAND-A
14–24 dB 8–24 dB
14–24 dB 8–24 dB
9h
R/W
R/W
R[A]
RR[A]
R/W
R/W
R/W
R/W
0=
0.5–1
kHz
0.5–2
kHz
RAS
RAS
0–8 dB
0–14 dB
0–8 dB
0–14 dB
1=
2–4 kHz
1–4 kHz
Unlocked Low V
14–24 dB 8–24 dB
14–24 dB 8–24 dB
10h COMMAND-B
9h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit Name
AFFC
IFLA
MODE
RSSIE
EDD
RAGC
FAGC
BANKS
Bit Name
AFFC
IFLA
MODE
RSSIE
EDD
RAGC
FAGC
BANKS
Reset
Value
0
0
0
0
1
0
0
1
Reset
Value
0
0
0
0
1
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R[A]
0=
AFFx
OFF
No
RX
No
Slow dec. No
No
B Bank
0=
AFFx
OFF
No
RX
No
Slow dec. No
No
B Bank
1=
AFFx ON –20 dB
TX
Yes
Fast dec. Yes
Yes
A Bank
1=
AFFx ON –20 dB
TX
Yes
Fast dec. Yes
Yes
A Bank
48 h
11h F1-B
4800 h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
FSK3
FSK2
FSK1
FSK0
F11
F10
F9
F8
Bit Name
FSK3
FSK2
FSK1
FSK0
F11
F10
F9
F8
Reset
Value
0
1
0
0
1
0
0
0
Reset
Value
0
1
0
0
1
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
05h F2-A
0h
R/W
12h F2-B
0h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit Name
F7
F6
F5
F4
F3
F1
F1
F0
Bit Name
F7
F6
F5
F4
F3
F1
F1
F0
Reset
Value
0
0
0
0
0
0
0
0
Reset
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bank A Registers
Bank B Registers
47
Figure 35. Bank Registers
Bank Access and Register Mapping
04h F1-A
Bit 0
700701 h
Bit Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FTA11
FTA10
FTA9
FTA8
FTA7
FTA6
FTA5
FTA4
Reset Value
0
1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FTA3
FTA2
FTA1
FTA0
FTB11
FTB10
FTB9
FTB8
07h FT2-A
7h
Bit Name
Reset Value
0
0
0
0
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FTB7
FTB6
FTB5
FTB4
FTB3
FTB2
FTB1
FTB0
1h
Bit Name
Reset Value
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
75 h
MC33696 Data Sheet, Rev. 12
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BANKA
RON3
RON2
RON1
RON0
ROFF2
ROFF1
ROFF0
0
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0Ah ID-A
Bit Name
Reset Value
C0 h
Bit Name
Reset Value
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IDL1
IDL0
ID5
ID4
ID3
ID2
ID1
ID0
1
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
80 h
Bit Name
Reset Value
Bit 3
Bit 2
Bit 1
Bit 0
FTA8
FTA7
FTA6
FTA5
FTA4
Reset Value
0
1
1
1
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
7h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FTA3
FTA2
FTA1
FTA0
FTB11
FTB10
FTB9
FTB8
Reset Value
0
0
0
0
0
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
1h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
FTB7
FTB6
FTB5
FTB4
FTB3
FTB2
FTB1
FTB0
Reset Value
0
0
0
0
0
0
0
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Reset Value
75 h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BANKB
RON3
RON2
RON1
RON0
ROFF2
ROFF1
ROFF0
0
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit Name
Reset Value
C0 h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IDL1
IDL0
ID5
ID4
ID3
ID2
ID1
ID0
1
1
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
18h HEADER-B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HDL1
HDL0
HD5
HD4
HD3
HD2
HD1
HD0
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0Ch RSSI-A
Bit 4
FTA9
17h ID-B
Bit 7
0Bh HEADER-A
Bit 5
FTA10
16h RXONOFF-B
Bit 7
Reset Value
Bit 6
FTA11
15h FT3-B
R/W
09h RXONOFF-A
Bit Name
700701 h
Bit 7
14h FT2-B
R/W
08h FT3-A
Bit Name
13h FT1-B
Bit 7
80 h
Bit Name
Reset Value
80 h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HDL1
HDL0
HD5
HD4
HD3
HD2
HD1
HD0
1
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
19h RSSI-B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RSSI7
RSSI6
RSSI5
RSSI4
RSSI3
RSSI2
RSSI1
RSSI0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit Name
Reset Value
80 h
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RSSI7
RSSI6
RSSI5
RSSI4
RSSI3
RSSI2
RSSI1
RSSI0
0
0
0
0
0
0
0
0
R[A]
R[A]
R[A]
R[A]
R[A]
R[A]
R[A]
R[A]
Bank A Registers
Bank B Registers
Freescale Semiconductor
Figure 35. Bank Registers (continued)
Bank Access and Register Mapping
48
06h FT1-A
Transition Time
20
Transition Time
Table 24 details the different times that must be considered for a given transition in the state machine, once
the logic conditions for that transition are met.
Table 24. Transition Time Definition
Transition
State x -> y
Crystal
Oscillator
Startup Time,
Parameter 5.10
Standby to SPI running, state 60 -> 1
Standby to receiver running, states 5 -> 5b, 20 -> 21
√
√
Off to receiver running, states 0 -> 0b, 10 -> 11
√
Configuration to receiver running,
states 1 -> (0b, 5b, 11, 21)
Configuration to transmitter mode, state 1 -> 30
Receiver running to configuration mode,
state (0b, 5b, 11, 12, 13, 21, 22, 23) -> 1,
Transmitter mode to configuration mode,
state 30 -> 1
Receiver running to standby mode,
state 5b -> 5, (21, 22, 23) -> 20
Receiver running to off mode,
state 0b -> 0, (11, 12, 13) -> 10
PLL Timing
Lock time parameter
5.9
Lock time parameter
5.9
0 or lock time
parameter 5.1 or lock
time parameter 5.9 2
Receiver
Receiver
Preamble On-to-Off Time,
Parameter 1.12
Time1
√
√
√
0 or lock time
parameter 5.1 or lock
time parameter 5.9 2
When CONFB=0, the transition from receive mode to configuration
mode is immediate.
When CONFB=0, the transition from transmit mode to configuration
mode is immediate.
√
√
NOTES:
1 See Section 12.2.3, “Frame Format.”
2 Depending on the PLL status before entering configuration mode. For example, the transition time from standby to receiver
running (FSK modulation, 19.2 kBd, AFFC = 0, data manager enabled) is: 0.6 ms + 50 µs + (3 + 1)/19.2k = 970 µs.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
49
Electrical Characteristics
21
Electrical Characteristics
21.1 General Parameters
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47, Figure 48, Figure 51, Figure 53 through Figure 54), unless otherwise specified. Typical values reflect
average measurement at VCC = 3.0 V, TA = 25°C.
Parameter
Limits
Test Conditions
Comments
Unit
Min
Typ
Max
1.2 Supply current in receive mode
Receiver on
—
10.3
13
mA
1.3
Strobe oscillator only
—
24
50
μA
1.4 Supply current in transmit mode Continuous wave (CW)
OLA[1:0}=00
—
13.5
17.5
mA
1.5
—
6.1
8
mA
—
260
700
nA
No power output
1.6 Supply current in standby mode –40°C ≤ TA ≤ 25°C
1.8
TA = 85°C
—
800
1200
nA
1.9 Supply current in LVD mode
LVDE = 1
—
35
50
μA
1.12 Receiver on-to-off time
Supply current reduced to 10%
—
100
—
μs
1.13 VCC2 voltage regulator output
2.7 V < VCC
2.4
2.6
2.8
V
1.14
2.1 V ≤ VCC ≤ 2.7 V
—
VCC–0.1
—
V
1.15 VCCDIG2 voltage regulator
output
Circuit in standby mode
(VCCDIG = 3 V)
—
0.7 x
VCCDIG
—
V
1.16
Circuit in all other modes
1.4
1.6
1.8
V
1.19 Voltage on VCC (Preregulator
output)
Receive mode with VCCIN=5V
2.4
—
—
V
21.2 Receiver: RF Parameters
RF parameters assume a matching network between test equipment and the D.U.T, and apply to all bands
unless otherwise specified.
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47, Figure 48, Figure 51, Figure 53 through Figure 54), unless otherwise specified. Typical values reflect
average measurement at VCC = 3.0 V, TA = 25°C.
Limits
Parameter
Test Conditions,
Comments
2.2 OOK sensitivity at 315 MHz DME = 1, DSREF = 1,
DR = 4.8 kbps, PER = 0.1
Typ
Max
(FCE,
FJE)
Max
(FCAE,
FJAE)
Unit
Min
—
–104
–99
–97
dBm
MC33696 Data Sheet, Rev. 12
50
Freescale Semiconductor
Electrical Characteristics
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47, Figure 48, Figure 51, Figure 53 through Figure 54), unless otherwise specified. Typical values reflect
average measurement at VCC = 3.0 V, TA = 25°C.
Limits
Test Conditions,
Comments
Typ
Max
(FCE,
FJE)
Max
(FCAE,
FJAE)
Unit
Min
2.40 OOK sensitivity at 434 MHz DME = 1, DSREF = 1,
DR = 4.8 kbps, PER = 0.1
—
–103.5
–98
–96
dBm
2.41 OOK sensitivity at 868 MHz DME = 1, DSREF = 1,
DR = 4.8 kbps, PER = 0.1
—
–103
–98
–96
dBm
2.42 OOK sensitivity at 916 MHz DME = 1, DSREF = 1,
DR = 4.8 kbps, PER = 0.1
—
–103
–98
–96
dBm
2.24 FSK sensitivity at 315 MHz
DME = 1, DSREF = 1,
DR = 4.8 kbps,
DFcarrier = ±64 kHz, PER = 0.1
—
–106.5
–102
–100
dBm
2.50 FSK sensitivity at 434 MHz
DME = 1, DSREF = 1,
DR = 4.8 kbps,
DFcarrier = ±64 kHz, PER = 0.1
—
–105.5
–101
–99
dBm
2.51 FSK sensitivity at 868 MHz
DME = 1, DSREF = 1,
DR = 4.8 kbps,
DFcarrier = ±64 kHz, PER = 0.1
—
–104.5
–100
–98
dBm
2.52 FSK sensitivity at 916 MHz
DME = 1, DSREF = 1,
DR = 4.8 kbps,
DFcarrier = ±64 kHz, PER = 0.1
—
–105.4
–102
–100
dBm
2.35 Sensitivity improvement in
RAW mode
DME = 0
—
0.6
—
—
dB
2.36 Duty Cycle for Manchester
coded data
47
—
53
53
%
2.37 Data Rate1
2
—
22.6
22.6
kbps
2.38 FSK deviation range
32
64
170
170
kHz
Parameter
2.5 Sensitivity reduction
ILA[1:0] = 00
—
0
—
—
dB
2.6
ILA[1:0] = 01
—
8
—
—
dB
2.7
ILA[1:0] = 10
—
16
—
—
dB
2.8
ILA[1:0] = 11
—
30
—
—
dB
2.9 In-band jammer
desensitization
Sensitivity reduced by 3 dB CW
jammer at Fcarrier ± 50 kHz/OOK
—
–4
—
—
dBc
2.60
Sensitivity reduced by 3 dB CW
jammer at Fcarrier ± 50 kHz/FSK
—
–6
—
—
dBc
2.11 Out-of-band jammer
desensitization
Sensitivity reduced by 3dB
CW jammer at Fcarrier ±1 MHz
—
37
—
—
dBc
2.12
Sensitivity reduced by 3dB
CW jammer at Fcarrier ± 2 MHz
—
40
—
—
dBc
2.13 RFIN parallel resistance
Receive mode
—
300
—
—
Ω
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
51
Electrical Characteristics
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47, Figure 48, Figure 51, Figure 53 through Figure 54), unless otherwise specified. Typical values reflect
average measurement at VCC = 3.0 V, TA = 25°C.
Limits
Test Conditions,
Comments
Typ
Max
(FCE,
FJE)
Max
(FCAE,
FJAE)
Unit
Min
1300
—
—
—
Ω
—
1.2
—
—
pF
2.17 Maximum detectable signal, Modulation depth: 99%,
OOK
level measured on a NRZ ‘1’
–25
—
—
—
dBm
2.25 Maximum detectable signal, ΔFcarrier = ±64kHz
FSK
-10
—
—
—
dBm
2.18 Image frequency rejection
304–434 MHz
20
36
—
—
dB
2.19
868–915 MHz
15
20
—
—
dB
Parameter
2.14 RFIN parallel resistance
Transmit mode
2.15 RFIN parallel capacitance
Receive and transmit modes
NOTES:
1 See Table 10 for additional information.
OOK Sensitivity Variation vs Temperature
(Ref : 3V, 25°C, 4800bps)
1.4
Sensitivity Variation (dB)
1.2
1
0.8
0.6
315 MHz
434 MHz
868 MHz
916 MHz
0.4
0.2
0
-0.2
-0.4
-40°C
25°C
Temperature (°C)
85°C
Figure 36. OOK Sensitivity Variation Versus Temperature
MC33696 Data Sheet, Rev. 12
52
Freescale Semiconductor
Electrical Characteristics
OOK Sensitivity Variation vs Voltage
(Ref : 3V, 25°C, 4800bps)
0.2
Sensitivity Variation (dB)
0.1
0
-0.1
-0.2
315 MHz
-0.3
434 MHz
868 MHz
-0.4
-0.5
2.1 V
916 MHz
2.4 V
Voltage (V)
3V
3.6 V
Figure 37. OOK Sensitivity Variation Versus Voltage
FSK Sensitivity Variation vs Temperature
(Ref : 3V, 25°C, +/-64kHz, 4800 bps )
1.4
Sensitivity Variation (dB)
1.2
1
315 MHz
0.8
434 MHz
0.6
868 MHz
916 MHz
0.4
0.2
0
-0.2
-0.4
-0.6
-40°C
25°C
Temperature (°C)
85°C
Figure 38. FSK Sensitivity Variation Versus Temperature
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
53
Electrical Characteristics
FSK Sensitivity Variation vs Voltage
(Ref : 3V, 25°C, +/-64kHz, 4800bps )
0.5
Sensitivity Variaition (dB)
0.4
315 MHz
434 MHz
0.3
868 MHz
916 MHz
0.2
0.1
0
-0.1
-0.2
2.1 V
2.4 V
3V
Voltage (V)
3.6 V
Figure 39. FSK Sensitivity Variation Versus Voltage
Sensitivity Variation Versus Data Rate
(Ref : 25°C, 3V, 434MHz , OOK, 4800bps)
5
Sensitivity Variation (dB)
4
3
2
1
0
-1
-2
-3
2400
4800
9600
19200
Data Rate (bps)
Figure 40. OOK Sensitivity Variation Versus Data Rate
MC33696 Data Sheet, Rev. 12
54
Freescale Semiconductor
Electrical Characteristics
Sensitivity Variation vs Data Rate
(Ref : 25°C, 3V, 434MHz , FSK +/-64kHz, 4800bps)
5
Sensitivity Variation (dB)
4
3
2
1
0
-1
-2
-3
2400
4800
9600
19200
Data Rate (bps)
Figure 41. FSK Sensitivity Variation Versus Data Rate
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
55
Electrical Characteristics
Sensitivity Variation Versus Frequency Deviation
(Ref : 25°C, 3V, 434MHz, FSK +/-64kHz, 4800bps)
2,0
Sensitivity Variation (dB)
1,5
1,0
0,5
0,0
-0,5
-1,0
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
Frequency Deviation (kHz)
Figure 42. FSK Sensitivity Variation Versus Frequency Deviation
21.3 Receiver Parameters
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematics Figure 47, Figure 48, Figure 53 through Figure 54), unless otherwise specified. Typical values reflect average
measurement at VCC = 3.0 V, TA = 25°C.
Parameter
Limits
Test Conditions
Comments
Unit
Min
Typ
Max
Receiver: IF filter, IF Amplifier, FM-to-AM Converter and Envelope Detector
3.1 IF center frequency
—
1.5
—
MHz
3.2 IF bandwidth at –3dB
—
380
—
kHz
3.3 IF cut-off low frequency at –3 dB Refer to Section 9, “Frequency
Planning”.
3.4 IF cut-off high frequency at –3 dB
—
—
1.387
MHz
1.635
—
—
MHz
—
15
—
ms
3.12 Recovery time from strong signal OOK modulation, 2.4 kbps,
FAGC = 0, input signal from
–50 dBm to –100 dBm
MC33696 Data Sheet, Rev. 12
56
Freescale Semiconductor
Electrical Characteristics
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematics Figure 47, Figure 48, Figure 53 through Figure 54), unless otherwise specified. Typical values reflect average
measurement at VCC = 3.0 V, TA = 25°C.
Parameter
Limits
Test Conditions
Comments
Unit
Min
Typ
Max
380
—
650
mV
3.52 Analog RSSI output signal for
Input signal @–100 dBm
420
—
700
mV
3.53 Analog RSSI output signal for
Input signal @–70 dBm
850
—
1200
mV
3.54 Analog RSSI output signal for
Input signal @–28 dBm
1000
—
1300
mV
0
—
2
3.56 Digital RSSI Registers for Input
signal @–100 dBm
0
—
3
3.57 Digital RSSI Registers for Input
signal @–70 dBm
9
—
13
3.58 Digital RSSI Registers for Input
signal @–28 dBm
13
—
16
0
—
2
3.6 Digital RSSI Registers for Input
signal @–50 dBm
4
—
8
3.61 Digital RSSI Registers for Input
signal @–24 dBm
13
—
15
Receiver: Analog and Digital RSSI
3.51 Analog RSSI output signal for
Input signal @–108 dBm
3.55 Digital RSSI Registers for Input
signal @–108 dBm
3.59 Digital RSSI Registers for Input
signal @–70 dBm
Measured on RSSIOUT
RSSI [0:3]
RSSI [4:7]
21.4 Transmitter: RF Parameters
RF parameters assume a matching network between test equipment and the D.U.T, and apply to all bands
unless otherwise specified.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
57
Electrical Characteristics
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 51, Figure 54), unless otherwise specified. Typical values reflect average measurement at VCC = 3.0 V,
TA = 25°C.
Limits
Parameter
Test Conditions
Comments
Min
(FCE,
FJE)
Min
(FCAE,
FJAE)
Typ
Max
Unit
4.1 Output power at 315 MHz
OLA[1:0] = 00, VCC = 3.0 V,
TA = 25°C
4
2
7.25
11
dBm
4.16 Output power at 434 MHz
OLA[1:0] = 00, VCC = 3.0 V,
TA = 25°C
3.5
1.5
6.8
10
dBm
4.2 Output power at 868 MHz
OLA[1:0] = 00, VCC = 3.0 V,
TA = 25°C
2.3
0.3
5.7
10
dBm
4.25 Output power at 916 MHz
OLA[1:0] = 00, VCC = 3.0 V,
TA = 25°C
—
—
5.8
—
dBm
4.20 Output power attenuation
OLA[1:0] = 00
—
—
0
—
dB
4.3
OLA[1:0] = 01
—
—
6
—
dB
4.4
OLA[1:0] = 10
—
—
12
—
dB
4.5
OLA[1:0] = 11
—
—
25
—
dB
4.10 Harmonic 2 level at 315 MHz
OLA[1:0] = 00
—
—
–33
—
dBc
4.17 Harmonic 2 level at 434 MHz
OLA[1:0] = 00
—
—
–32
—
dBc
4.11 Harmonic 2 level at 868 MHz
OLA[1:0] = 00
—
—
–50
—
dBc
4.20 Harmonic 2 level at 916 MHz
OLA[1:0] = 00
—
—
–54
—
dBc
4.12 Harmonic 3 level at 315 MHz
OLA[1:0] = 00
—
—
–41
—
dBc
4.18 Harmonic 3 level at 434 MHz
OLA[1:0] = 00
—
—
–49
—
dBc
4.13 Harmonic 3 level at 868 MHz
OLA[1:0] = 00
—
—
–53
—
dBc
4.21 Harmonic 3 level at 916 MHz
OLA[1:0] = 00
—
—
–58
—
dBc
4.30 Spurious level at 315 MHz ± Fref OLA[1:0] = 00
—
—
–54
—
dBm
4.14 Spurious level at 434 MHz ± Fref OLA[1:0] = 00
—
—
–57
—
dBm
4.15 Spurious level at 868 MHz ± Fref OLA[1:0] = 00
—
—
–56
—
dBm
4.31 Spurious level at 916 MHz ± Fref OLA[1:0] = 00
—
—
–57
—
dBm
4.6 Output rise/fall time
—
—
3
—
μs
4.7 RFOUT parallel resistance at
315 MHz
OLA[1:0] = 00, RX mode
—
—
2500
—
Ω
4.71 RFOUT parallel resistance at
434 MHz
OLA[1:0] = 00, RX mode
—
—
2100
—
Ω
4.72 RFOUT parallel resistance at
868 MHz
OLA[1:0] = 00, RX mode
—
—
1300
—
Ω
4.73 RFOUT parallel resistance at
916 MHz
OLA[1:0] = 00, RX mode
—
—
1200
—
Ω
4.8 RFOUT optimum load resistance OLA[1:0] = 00, TX mode
at 315 MHz
—
—
310
—
Ω
MC33696 Data Sheet, Rev. 12
58
Freescale Semiconductor
Electrical Characteristics
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 51, Figure 54), unless otherwise specified. Typical values reflect average measurement at VCC = 3.0 V,
TA = 25°C.
Limits
Test Conditions
Comments
Min
(FCE,
FJE)
Min
(FCAE,
FJAE)
Typ
Max
4.81 RFOUT optimum load resistance OLA[1:0] = 00, TX mode
at 434 MHz
—
—
310
—
Ω
4.82 RFOUT optimum load resistance OLA[1:0] = 00, TX mode
at 868 MHz
—
—
310
—
Ω
4.83 RFOUT optimum load resistance OLA[1:0] = 00, TX mode
at 916 MHz
—
—
310
—
Ω
4.9 RFOUT parallel capacitance
—
—
1
—
pF
Parameter
Receive and transmit modes
Unit
Output Power Variation vs Temperature
(Ref : 25°C, 3V)
0.6
Output Power Variation (dB)
0.5
315 MHz
0.4
434 MHz
0.3
868 MHz
0.2
916 MHz
0.1
0
-0.1
-0.2
-0.3
-40°C
25°C
Temperature (°C)
85°C
Figure 43. Output Power Versus Temperature
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
59
Electrical Characteristics
Output Power Variation vs Voltage
(Ref : 3V, 25°C)
0.4
Output Power Variation (dB)
0.2
0
-0.2
-0.4
315 MHz
434 MHz
-0.6
868 MHz
916 MHz
-0.8
-1
2.1 V
2.4 V
3V
3.6 V
Voltage (V)
Figure 44. Output Power Versus Supply Voltage
21.5 PLL & Crystal Oscillator
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47 to Figure 54 through Figure 54), unless otherwise specified. Typical values reflect average
measurement at VCC = 3.0 V, TA = 25 °C.
Parameter
Test Conditions
Comments
Limits
Unit
Min
Typ
Max
5.9 PLL lock time
RF frequency ±25kHz
—
50
100
μs
5.1 Toggle time between 2
frequencies
RF frequency step <1.5MHz,
RF frequency ±25kHz
—
30
—
μs
5.21 Occupied bandwidth @ 99%
OOK 1.2 kbps
—
58
—
kHz
5.22
OOK 19.2 kbps
—
248
—
kHz
5.23
FSK 128 kHz, 1.2 kbps
—
160
—
kHz
5.24
FSK 128 kHz, 19.2 kbps
—
278
—
kHz
5.10 Crystal oscillator startup time
—
0.6
1.2
ms
5.8 Crystal series resistance
—
—
120
Ω
Examples of crystal characteristics are given in Table 25.
MC33696 Data Sheet, Rev. 12
60
Freescale Semiconductor
Electrical Characteristics
Table 25. Typical Crystal Reference and Characteristics
Reference & Type
315 MHz
434 MHz
868 MHz
LN-G102-1183
NX5032GA
NDK
LN-G102-1182
NX5032GA
NDK
EXS00A-01654
NX5032GA
NDK
Unit
17.5814
24.19066
24.16139
MHz
Load capacitance
8
8
8
pF
ESR
25
15
<70
Ω
Parameter
Frequency
21.6 Strobe Oscillator (SOE = 1)
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 48 through Figure 46, Figure 50), unless otherwise specified. Typical values reflect average
measurement at VCC = 3.0 V, TA = 25°C.
Parameter
Limits
Test Conditions
Comments
Unit
Min
Typ
Max
0.1
—
—
ms
0.1
—
10
nF
—
1
—
μA
6.4 High threshold voltage
—
1
—
V
6.5 Low threshold voltage
—
0.5
—
V
–14.2
—
15.8
%
6.1 Period range
TStrobe = 106.C3
6.2 External capacitor C3
6.3 Sourced/sink current
6.6 Overall timing accuracy
With 1% resistor R13
With 1% resistor R13 & 5%
capacitor C3,
±3 sigma variations
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
61
Electrical Characteristics
21.7 Digital Input: CONFB, MOSI, SCLK, SEB, STROBE,
RSSIC
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47 to Figure 54 through Figure 54), unless otherwise specified. Typical values reflect average
measurement at VCC = 3.0 V, TA = 25°C.
Limits
Test Conditions
Comments
Parameter
Unit
Min
Typ
Max
—
—
0.4 x VCC2
V
0.8 x VCC2
—
—
V
0.1 x VCC2
—
—
V
—
—
0.4 x VCCDIG2
V
7.11 Input high voltage
0.8 x VCCDIG2
—
—
V
7.12 Input hysteresis
0.1 x VCCDIG2
—
—
V
1
—
100
nA
0.5
—
10
nA
7.7 Input low voltage
MOSI, SCLK, SEB, RSSIC(1)
7.8 Input high voltage
7.9 Input hysteresis
7.10 Input low voltage
2
CONFB, STROBE
7.5 Sink current
Configuration, receive, transmit
modes
7.6
standby or LVD modes
NOTES:
1 Input levels of those pins are referenced to V
CC2 which depends upon VCC (see Section 5, “Power Supply”).
2
Input levels of those pins are referenced to VCCDIG2 which depends upon the circuit state (see Section 5, “Power Supply”).
21.8 Digital Output
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47 to Figure 54 through Figure 54), unless otherwise specified. Typical values reflect average
measurement at VCC = 3.0 V, TA = 25°C.
Parameter
Limits
Test Conditions
Comments
Unit
Min
Typ
Max
Digital Output: DATACLK, LVD, MISO, MOSI, SCLK
8.1 Output low voltage
|ILOAD| = 50 μA
8.2 Output high voltage
8.3 Fall and rise time
—
—
0.2 x VCCIO
V
0.8 x VCCIO
—
—
V
—
80
150
ns
—
—
0.2 x VCC
V
0.8 x VCC
—
—
V
From 10% to 90% of the
output swing,
CLOAD = 10pF
Digital Output: SWITCH (VCC = 3V)
8.4 Output low voltage
8.5 Output high voltage
|ILOAD| = 50 μA
MC33696 Data Sheet, Rev. 12
62
Freescale Semiconductor
Electrical Characteristics
21.9 Digital Interface Timing
Operating supply voltage and temperature range see Table 3. Values refer to the circuit recommended in the application
schematic (see Figure 47 to Figure 54 through Figure 54), unless otherwise specified. Typical values reflect average
measurement at VCC = 3.0 V, TA = 25°C.
Parameter
Limits
Test Conditions
Comments
Unit
Min
Typ
Max
9.2 SCLK period
1
—
—
μs
9.8 Configuration enable time
20
—
—
μs
9.3 Enable lead time
Tdigclk1
—
—
μs
100
—
—
ns
100
—
—2
ns
3 x Tdigclk1
—
—
μs
—
—
100
ns
Crystal oscillator is running.
3x
9.4 Enable lag time
9.5 Sequential transfer delay
9.6 Data hold time
Receive mode, DME = 1,
from SCLK to MOSI
9.7 Data setup time
Configuration mode,
from SCLK to MISO
9.9
Configuration mode, from
SCLK to MOSI
120
—
—
ns
9.10 Data setup time
Configuration mode, from
SCLK to MOSI
100
—
—
ns
NOTES:
1 See Section 9.1, “Clock Generator” for T
digclk values.
2
The digital interface can be used in SPI burst protocol, i.e., with a continuous clock on SCLK port. For example, one (or more)
read access followed by one (or more) write access and so on. In this case and for a practical use, the pulse required on
CONFB between accesses must be higher than 100 ns only if STROBE signal is always set to high level.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
63
Application Schematics
STROBE
CONFB
9.8
SEB
9.3
9.4
SCLK
9.5
9.2
9.10
9.9
MOSI
9.7
MISO
Figure 45. Digital Interface Timing Diagram in Configuration Mode
SEB
CONFB
STROBE
SCLK
(input)
9.3
9.6
MOSI
(output)
Figure 46. Digital Interface Timing Diagram in Receive Mode (DME = 1)
22
Application Schematics
Examples of application schematics are proposed for different uses: Receiver, Transmitter, Transceiver.
Note: The external pullup resistor set on SEB pin (R2) is not mandatory. Instead of R2, an external
pulldown resistor of 10 k may be connected between SEB pin and ground.
22.1 Receiver Schematics
Figure 43 and Figure 44 show the application schematic in receive mode for 3 V operation.
MC33696 Data Sheet, Rev. 12
64
Freescale Semiconductor
Application Schematics
Figure 45 and Figure 46 show the application schematic in receive mode for 5 V operation.
22.1.1 Receiver Schematics in 3 V Operation—MCU Controls
Wakeup
24
25
VCC
26
C11
100nF
SWITCH
34
26
25
GNDIO
LVD
VCCIN
27
28
GNDSUBD
STROBE
CONFB
MC33696
GNDPA1
DATACLK
RSSIC
GNDDIG
R3
10k
24
27
23
31
22
29
21
32
20
30
19
28
18
33
SEB
SCLK
MOSI
MISO
CONFB
DATACLK
RSSIC
17
16
GND
RBGAP
15
9
10
14
GNDPA2
VCCDIG 2
RFOUT
VCC
C7
1nF
X7
C6
6.8pF
29
30
SWITCH
U16
VCC2VCO
XTALIN
8
MISO
VCCDIG
7
GNDLNA
VCC2OUT
100pF
6
MOSI
13
C5
5
RFIN
VCCINO UT
VCC2
4
SEB
SCLK
12
C2 1nF
VCC
R2
10k
VCC2RF
XTALOUT
C4
3
RSSIOUT
11
C3
2
VCC2IN
31
32
GND
L1
1
R4
10k
3V
GND
VCC
C1
100nF VCC2
STROBE
MICROCONTROLLER
C12
100pF VCC2
RSSIOUT
C8
100nF
VCC2
C9
100nF
C10
100nF
R1
470k 1%
Figure 47. MC33696 Application Schematic (3 V)
The ON/OFF sequencing in receive mode is controlled by driving a low or high level by the MCU on
STROBE pin.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
65
Application Schematics
22.1.2 Receiver Schematics in 3V Operation—Strobe Oscillator
Mode
RSSIOUT
C13
1nF
STROBE
VCC
C11
100nF
SWITCH
GND
25
VCCIN
GNDIO
26
27
LVD
28
STROBE
GNDSUBD
29
30
VCC2IN
GNDPA1
DATACLK
RFOUT
RSSIC
9
10
24
SEB
23
SCLK
22
MOSI
21
MISO
20
CONFB
19
DATACLK
18
RSSIC
17
GND
RBGAP
GNDDIG
R3
10k
16
GNDPA2
VCC
C7
1nF
X4
C6
6.8pF
CONFB
MC33696
XTALIN
8
VCC2VCO
VCCDIG2
7
MISO
U1
15
100pF
6
GNDLNA
14
C5
5
MOSI
VCCDIG
VCC2
4
RFIN
VCC2OUT
1nF
SEB
SCLK
13
C2
VCC
R2
10k
VCC2RF
VCCINOUT
C4
3
RSSIOUT
12
C3
2
11
L1
1
XT ALOUT
C1
100nF VCC2
SW ITCH
GND
31
32
VCC
MICROCONTROLLER
3V
C12
100pF VCC2
C8
100 nF
VCC2
C9
100nF
C10
100nF
R1
470k 1%
Figure 48. MC33696 Application Schematic in Strobe mode (3 V)
The ON/OFF sequencing in receive mode is controlled internally. The STROBE pin from the MCU has to
be configured in high impedance and wakeup mode is available when SOE bit is enabled.
MC33696 Data Sheet, Rev. 12
66
Freescale Semiconductor
Application Schematics
22.1.3 Receiver Schematics in 5 V Operation—MCU Controls
Wakeup
24
25
C12
100pF VCC2
26
C11
100nF
SWITCH
34
5V
25
VCCIN
GNDIO
26
27
LVD
28
STROBE
GNDSUBD
29
30
SWITCH
MC33696
DATACLK
RSSIC
C8
100nF
24
27
23
31
22
29
21
32
20
30
19
28
18
33
SEB
SCLK
MOSI
MISO
CONFB
DATACLK
RSSIC
17
GND
RBGAP
GNDDIG
R3
10k
16
9
10
X8
15
GNDPA2
VCCDIG2
RFOUT
C7
1nF
C6
6.8pF
CONFB
GNDPA1
XTALIN
8
U1
VCC2VCO
14
7
MISO
VCCDIG
100pF
GNDLNA
VCC2OUT
6
MOSI
13
C5
5
RFIN
VCCINOUT
VCC2
4
SEB
SCLK
12
1nF
VCC
R2
10k
VCC2RF
XTALOUT
C4
C2
RSSIOUT
11
3
VCC2IN
31
32
GND
2
L1
C3
1
R5
10k
GND
VCC
C1
100nF VCC2
STROBE
MICROCONTROLLER
VCC
RSSIOUT
VCC2
C9
100nF
C10
100nF
R1
470k 1%
Figure 49. MC33696 Application Schematic (5 V)
The ON/OFF sequencing in receive mode is controlled by driving a low or high level by the MCU on
STROBE pin.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
67
Application Schematics
22.1.4 Receiver Schematics in 5 V Operation—Strobe Oscillator
Mode
13
C13
1nF
14
VCC
15
C11
100nF
SWITCH
23
5V
GND
GNDIO
26
25
VCCIN
27
LVD
28
GNDSUBD
29
30
VCC2IN
STROBE
CONFB
MC33696
GNDPA1
DATACLK
RSSIC
24
16
23
20
22
18
21
21
20
19
19
17
18
22
SEB
SCLK
MOSI
MISO
CONFB
DATACLK
RSSIC
17
GND
RBGAP
GNDDIG
R3
10k
16
9
10
15
GNDPA2
VCCDIG2
RFOUT
XTALIN
8
U17
VCC2VCO
14
7
MISO
VCCDIG
100pF
6
GNDLNA
VCC2OUT
C5
5
MOSI
13
VCC2
4
RFIN
12
1nF
SEB
SCLK
VCCINOUT
C4
C2
VCC
R2
10k
VCC2RF
XT ALOUT
C3
3
RSSIOUT
11
L1
2
SW ITCH
GND
31
32
VCC
1
STROBE
MICROCONTROLLER
C12
100pF VCC2
C1
100nF VCC2
RSSIOUT
C7
1nF
X5
C6
6.8pF
C8
100 nF
VCC2
C9
100nF
C10
100nF
R1
470k 1%
Figure 50. MC33696 Application Schematic in Strobe Mode (5 V)
The ON/OFF sequencing in receive mode is controlled internally. The STROBE pin from the MCU has to
be configured in high impedance and wake up mode is available when SOE bit is enabled.
MC33696 Data Sheet, Rev. 12
68
Freescale Semiconductor
Application Schematics
22.2 Transmitter Schematics
22.2.1 Transmitter Schematics in 3 V Operation
Figure 51 shows the application schematic in transmit mode for 3 V operation.
25
C12
1 00pF VCC2
26
C11
100nF
34
3V
STROBE
R4
10k
GND
SWITCH
3
4
5
26
25
GNDIO
LVD
VCCIN
28
27
30
31
29
GNDSUBD
STROBE
MISO
U1
CONFB
MC33696
GNDPA1
DATACLK
24
27
23
31
22
29
21
32
20
30
19
28
SEB
SCLK
MOSI
MISO
CONFB
DATACLK
18
GND
17
16
VCCDIG 2
RBGAP
15
X TALIN
9
GNDDIG
R3
10k
VCC
C7
1nF
X9
C6
6.8pF
14
GNDPA2
C4
VCCDIG
8
RSSIC
VCC2OUT
RFOUT
13
1nF
MOSI
VCCINO UT
C5
RFIN
VCC2VCO
7
SEB
SCLK
GNDLNA
VCC
R2
10k
VCC2RF
12
C2
100pF VCC2
6
L1
C3
RSSIOUT
2
XTALOUT
L2
1
11
C14
100pF
C1
100nF VCC2
10
C13
100nF
VCC2IN
VCC
SWITCH
G ND
32
VCC
MICROCONTROLLER
VCC
C8
100nF
VCC2
C9
100nF
C10
100nF
R1
470k 1%
Figure 51. MC33696MC33596 Application Schematic (3 V) in Transmit Mode Only
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
69
Application Schematics
22.2.2 Transmitter Schematics in 5 V Operation
Figure 52 shows the application schematic in transmit mode for 5V operation.
24
RSSIOUT
25
C11
100nF
34
5V
R4
10k
GND
SWITCH
26
25
GNDIO
LVD
VCCIN
28
27
STROBE
29
GNDSUBD
31
GNDPA2
10
GNDDIG
24
27
23
31
22
29
21
32
20
30
19
28
18
33
SEB
SCLK
MOSI
MISO
CONFB
DATACLK
RSSIC
17
GND
8
RSSIC
R3
10k
16
1nF
RFOUT
RBGAP
C5
DATACLK
VCCDIG 2
C4
7
MC33696
GNDPA1
9
C3
100pF
CONFB
15
L1
6
U12
VCC2VCO
VCCDIG
C2
MISO
XT ALIN
L2
5
MOSI
GNDLNA
14
VCC2
SEB
RFIN
VCC2OUT
4
VCC
R2
10k
SCLK
13
C14
100pF
VCC2RF
12
3
RSSIOUT
VCCINO UT
2
11
1
VCC2
VCC2IN
32
GND
C1
1uF
XT ALOUT
C13
100nF
SWITCH
VCC
30
VCC
MICROCONTROLLER
26
C12
100pF VCC2
STROBE
VCC
C7
1nF
VCC2
X12
C8
100nF
C9
100nF
C10
100nF
R1
470k 1%
C6
6.8pF
Figure 52. MC33696MC33596 Application Schematic (5 V) in Transmit Mode Only
MC33696 Data Sheet, Rev. 12
70
Freescale Semiconductor
Application Schematics
22.3 Transceiver Schematics
22.3.1 Transceiver Schematics in 3 V Operation
Figure 53 shows the application schematic in transceiver mode for 3 V operation.
24
25
VCC
C11
100nF
SWITCH
34
3V
GND
GNDIO
26
25
VC CIN
28
27
LVD
STROBE
29
GNDSUBD
31
30
VCC2IN
MC33696
DATACLK
RSSIC
24
27
23
31
22
29
21
32
20
30
19
28
18
33
SEB
SCLK
MOSI
MISO
CONFB
DATACLK
RSSIC
17
GND
RBGAP
GNDDIG
R3
10k
16
15
VCCDIG
14
GND PA2
VCCDIG 2
RFOUT
VCC
C7
1nF
X10
C6
6.8pF
CONFB
GND PA1
VCC2OUT
8
U7
13
7
MISO
12
100pF
6
MOSI
GND LNA
XTALIN
C5 1nF
C2
SEB
SCLK
VCC 2VCO
VCC
R2
10k
RFIN
9
C4
C15
1nF
5
VCC 2RF
10
C3
VCC2
4
RSSIOUT
VCCINO UT
L1
2
3
C14
100pF
L15
1
XTALOUT
C1
100nF VCC2
11
C13
100nF
SW ITCH
GND
32
VCC
VCC
STROBE
R4
10k
MICROCONTROLLER
C12
100pF VCC2
26
RSSIOUT
C8
100nF
VCC2
C9
100nF
C10
100nF
R1
470k 1%
Figure 53. MC33696 Application Schematic (3 V) in Transceiver Mode
The ON/OFF sequencing for the receiver is controlled by driving a low or high level by the MCU on
STROBE pin.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
71
Application Schematics
22.3.2 Transceiver Schematics in 5 V Operation
Figure 54 shows the application schematic in transceiver mode for 5 V operation.
24
RSSIOUT
25
C11
100nF
34
5V
R4
10k
GND
SWITCH
25
VCCIN
GNDIO
26
27
LVD
28
STROBE
GNDSUBD
30
29
31
RFOUT
RSSIC
GNDPA2
GNDDIG
27
31
22
29
21
32
20
30
19
28
18
33
SEB
SCLK
MOSI
MISO
CONFB
DAT ACLK
RSSIC
17
VCC
C7
1nF
X11
C6
6.8pF
24
23
GND
8
DATACLK
RBGAP
1nF
MC33696
XTALIN
C5
CONFB
GNDPA1
9
C4
7
U11
VCC2VCO
10
C3
100pF
6
MISO
R3
10k
16
L1
C2
GNDLNA
VCCDIG 2
C15
1nF
MOSI
15
L2
RFIN
14
5
SEB
SCLK
VCCDIG
VCC2
4
VCC
R2
10k
VCC2RF
VCC2OUT
3
C14
100pF
RSSIOUT
13
2
12
1
VCCINO UT
VCC2
11
C1
1uF
XTALOUT
C13
100nF
VCC2IN
VCC
SWITCH
GND
32
VCC
MICROCONTROLLER
26
C12
100pF VCC2
STROBE
C8
100nF
VCC2
C9
100nF
C10
100nF
R1
470k 1%
Figure 54. MC33696 Application Schematic (5 V) in Transceiver Mode
The ON/OFF sequencing for the receiver is controlled by driving a low or high level by the MCU on
STROBE pin.
MC33696 Data Sheet, Rev. 12
72
Freescale Semiconductor
PCB Design Recommendations
23
PCB Design Recommendations
Pay attention to the following points and recommendations when designing the layout of the PCB.
• Ground Plane
— If you can afford a multilayer PCB, use an internal layer for the ground plane, route power
supply and digital signals on the last layer, with RF components on the first layer.
— Use at least a double-sided PCB.
— Use a large ground plane on the opposite layer.
— If the ground plane must be cut on the opposite layer for routing some signals, maintain
continuity with another ground plane on the opposite layer and a lot of via to minimize
parasitic inductance.
• Power Supply, Ground Connection and Decoupling
— Connect each ground pin to the ground plane using a separate via for each signal; do not use
common vias.
— Place each decoupling capacitor as close to the corresponding VCC pin as possible (no more
than 2–3 mm away).
— Locate the VCCDIG2 decoupling capacitor (C10) directly between VCCDIG2 (pin 14) and
GND (pin 16).
— GNDPA1 and GNDPA2 inductance to ground should be minimum. If possible, use two via for
each pin.
• RF Tracks, Matching Network and Other Components
— Minimize any tracks used for routing RF signals.
— Locate crystal X1 and associated capacitors C6 and C7 close to the MC33696. Avoid loops
occurring due to component size and tracks. Avoid routing digital signals in this area.
— Use high frequency coils with high Q values for the frequency of operation (minimum of 15).
Validate any change of coil source.
— Track between RFOUT and RFIN should be as short as possible to minimize lost in TX mode.
NOTE
The values indicated for the matching network have been computed and
tuned for the MC33696 RF Modules available for MC33696 evaluation.
Matching networks should be retuned if any change is made to the PCB
(track width, length or place, or PCB thickness, or component value). Never
use, as is, a matching network designed for another PCB.
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
73
Case Outline Dimensions
24
Case Outline Dimensions
24.1 LQFP32 Case
MC33696 Data Sheet, Rev. 12
74
Freescale Semiconductor
Case Outline Dimensions
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
75
Case Outline Dimensions
MC33696 Data Sheet, Rev. 12
76
Freescale Semiconductor
Case Outline Dimensions
24.2 QFN32 Case
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
77
Case Outline Dimensions
MC33696 Data Sheet, Rev. 12
78
Freescale Semiconductor
Case Outline Dimensions
MC33696 Data Sheet, Rev. 12
Freescale Semiconductor
79
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Document Number: MC33696
Rev. 12
02/2010
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