ON NCP81105MNTXG Drmos supporting 1/2/3 phase power controller Datasheet

NCP81105, NCP81105H
DrMOS Supporting, 1/2/3
Phase Power Controller
with SVID Interface for
Desktop and Notebook
VR12.5 & VR12.6 CPU
Applications
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The NCP81105 is a DrMOS supporting controller optimized for
Intel® VR12.5 & VR12.6 compatible CPUs. The controller combines
true differential voltage sensing, differential inductor DCR current
sensing, input voltage feed−forward, and adaptive voltage positioning
to provide accurately regulated power for both Desktop and Notebook
CPU applications. The control system is based on Dual−Edge
pulse−width modulation (PWM), to provide the fastest initial response
to dynamic load events plus reduced system cost. The NCP81105 is
compatible with DrMOS type power stages such as NCP5367,
NCP5368, NCP5369 and NCP5338.
The NCP81105’s output can be configured to operate in single phase
during light load operation − improving overall system efficiency. A
high performance operational error amplifier is provided to simplify
compensation of the system. Patented Dynamic Reference Injection
further simplifies loop compensation by eliminating the need to
compromise between closed−loop transient response and Dynamic
VID performance. Patented Total Current Summing provides highly
accurate current monitoring for droop and digital current monitoring.
Features
• Meets Intel’s VR12.5 Specifications
• Implements VR12.6 PS4 State and SVID Reporting
• Mixed Voltage/Current Mode, Dual Edge Modulation
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for Fastest Initial Response to Transient Loading
High Impedance Differential Voltage Amplifier
High Performance Operational Error Amplifier
High Impedance Total Current Sense Amplifier
True Differential Current Sense Amplifiers for
Balancing Current in Each Phase
Digital Soft Start Ramp
Dynamic Reference Injection
Accurate Total Summing Current Amplifier
“Lossless” Inductor DCR Current Sensing
Summed, Thermally Compensated Inductor Current
Sensing for Adaptive Voltage Positioning (AVP)
48 mV/ms Fast Output Slew Rate (NCP81105)
10 mV/ms Fast Output Slew Rate (NCP81105H)
Programmable Slow Slew Rates as a Fraction of Fast
Slew Rate
© Semiconductor Components Industries, LLC, 2013
October, 2013 − Rev. 2
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MARKING
DIAGRAM
1
1
36
NCP
81105
AWLYYWWG
QFN36
CASE 485CC
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 35 of this data sheet.
Reduced Enable to First SVID Command Latency
Phase−to−Phase Dynamic Current Balancing
Switching Frequency Range of 280 kHz to 1.5 MHz
Starts up into Pre−Charged Loads while Avoiding False
OVP
Compatible with DrMOS Power Stages
Power−saving Phase Shedding
Vin Feed−forward Ramp Slope Compensation
Pin Programming for Internal SVID parameters
Output Over Voltage Protection (OVP) & Under
Voltage Protection (UVP)
Over Current Protection (OCP)
Power Good Output with Internal Delays
This is a Pb−Free Device
Applications
• Desktop and Notebook Microprocessors
1
Publication Order Number:
NCP81105/D
NCP81105, NCP81105H
1.3V
VCC 2
VSP
VSN
VRMP
VRHOT# 3
OVP
THERMAL
MONITOR
SVID
INTERFACE
& LOGIC
ALERT# 5
DRVON
35 VSN
CSCOMP
34 DIFFOUT
SCALING
_
PS#
33 FB
+
DATA
REGISTERS
VR READY
LOGIC
OVERCURRENT
COMPARATORS
ERROR
AMP
1.3V
32 COMP
CURRENT
MONITOR
OCP
IOUT
TSENSE 9
MUX
(VSP − VSN)
Buffer
ADC
IOUT
VRMP 29
VRMP
CURRENT
SENSE
AMP
OSCILLATOR
& RAMP
GENERATORS
VRMP
27 ILIM
25 CSSUM
+
24 CSREF
OVP
MAX
OVP
23 CSN2
COMP
PWM
GENERATORS
CURRENT
22 CSP2
BALANCE
21 CSN3
AMPLIFIERS
I2
I3
I1
PWM1
PWM2
28 IOUT
26 CSCOMP
_
PS#
DGAIN 31
OVERCURRENT
PROGRAMMING
ENABLE
PWM3
VBOOT 30
DAC
VSN
DAC
FEED−
FORWARD
ENABLE
ROSC 7
INT_SEL 17
DIFF
AMP
OVP
OVP
ENABLE
IMAX 16
VSP
OCP
SCLK 6
VR_RDY 8
36 VSP
DAC
DAC
SDIO 4
CSREF
ENABLE
UVLO & EN
COMPARATORS
_
EN 1
20 CSP3
19 CSN1
18 CSP1
DRVON
15 DRVON
PS#
OVP
DRVON
PS#
NCP81105
OCP
ZERO
CURRENT
DETECTION
11
SMOD
14 PWM1
13 PWM3
POWER
STATE
GATE
Figure 1. Block Diagram
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2
12 PWM2
10 OD#
VSP
VSN
DIFFOUT
FB
COMP
DGAIN
VBOOT
VRMP
IOUT
36
35
34
33
32
31
30
29
28
NCP81105, NCP81105H
EN
1
27
ILIM
VCC
2
26
CSCOMP
VRHOT#
3
25
CSSUM
SDIO
4
24
CSREF
ALERT#
5
23
CSN2
SCLK
6
22
CSP2
ROSC
7
21
CSN3
VR_RDY
8
20
CSP3
TSENSE
9
19
CSN1
NCP81105
10
11
12
13
14
15
16
17
18
OD#
SMOD
PWM2
PWM3
PWM1
DRVON
IMAX
INT_SEL
CSP1
TAB: GROUND
Figure 2. Pin Connections
(Top View)
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3
NCP81105, NCP81105H
PIN LIST AND DESCRIPTION
Pin
No.
Symbol
Description
1
EN
2
VCC
Logic input. Logic high enables the NCP81105 and logic low disables it.
3
VR_HOT#
4
SDIO
Bidirectional Serial VID data interface.
5
ALERT#
Open drain Serial VID ALERT# output.
Power for the internal control circuits. A decoupling capacitor must be connected from this pin to ground.
Open drain (logic level) output for over−temperature reporting. Low indicates high temp.
6
SCLK
Serial VID clock input.
7
ROSC
This pin outputs a constant current. A resistance from this pin to ground programs the switching frequency.
8
VR_RDY
Open drain output. High indicates that the NCP81105 is regulating the output.
Temperature sense input.
9
TSENSE
10
OD#
11
SMOD
Phase 1 Zero Cross Detection (ZCD) disable output. In PS2 & PS3, SMOD pulls LOW when phase 1
inductor current is negative to perform (or allow the DrMOS ZCD function to perform) diode emulation,
and pulls HIGH when phase 1 inductor current is positive. In PS0 & PS1, SMOD stays high to force the
phase 1 DrMOS into Continuous Conduction.
12
PWM2
PWM output to Phase 2 DrMOS
13
PWM3
PWM output to Phase 3 DrMOS
14
PWM1
PWM output to Phase 1 DrMOS
15
DRVON
Enable output for DrMOS
Phase Disabling Output, tied to the Enable, SMOD or ZCD_EN# pin of phases 2 and 3 DrMOS. Except
in PS0 mode, this output pulls low to disable the DrMOS if connected to an enable input. If connected to
a DrMOS SMOD or ZCD_EN# input, both HS & LS FETs are held off since PWM2 & PWM3 are also low.
Actively pulls high in PS0 mode.
16
IMAX
17
INT_SEL
During startup, a resistor from this pin to ground programs ICC_MAX.
18
CSP1
Positive input to phase 1 current sense amplifier for balancing phase currents
19
CSN1
Negative input to phase 1 current sense amplifier
20
CSP3
Positive input to phase 3 current sense amplifier for balancing phase currents
21
CSN3
Negative input to phase 3 current sense amplifier
22
CSP2
Positive input to phase 2 current sense amplifier for balancing phase currents
23
CSN2
Negative input to phase 2 current balance sense amplifier
24
CSREF
Non−inverting input for the total output current sense amplifier. Also, the absolute OVP input.
25
CSSUM
Inverting input of total output current sense amplifier.
26
CSCOMP
27
ILIM
Input to program the over−current shutdown threshold.
28
IOUT
Total current monitor output. A resistor from this pin to ground calibrates SVID output current reporting.
29
VRMP
VDC applied to this pin provides feed−forward compensation for the pulsewidth modulator. The current
into this pin controls the slope of PWM ramp. A low voltage on this pin will inhibit NCP81105 startup.
30
VBOOT
During startup, a resistor from this pin to ground programs the BOOT voltage
31
DGAIN
During startup, a resistor from this pin to ground programs the scaling of the output Droop with respect to
the total output current signal produced between CSCOMP and CSREF.
32
COMP
Output of the error amplifier.
33
FB
34
DIFFOUT
35
VSN
Inverting input to the differential remote sense amplifier (VSS sense).
36
VSP
Non−inverting input to the differential remote sense amplifier (VCC sense).
37
GND
Power supply return (QFN Flag)
During startup, a resistor from this pin to ground programs the low frequency compensator pole of the
NCP81105 voltage control feedback loop.
Output of total output current sense amplifier.
Error amplifier voltage feedback input.
Output of the differential remote sense amplifier.
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4
NCP81105, NCP81105H
VCIN
VIN
BOOT
DRVON
EN
CB1
DRMOS
PWM1
PHASE
PWM
SMOD
VSWH
SMOD
NCP81105
VCIN
VIN
BOOT
EN
CB2
DRMOS
PWM2
PHASE
PWM
OD#
VSWH
SMOD
VCIN
VIN
BOOT
EN
DRMOS
PWM3
PWM
SMOD
Figure 3. Three Phase Application Diagram
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5
CB3
PHASE
VSWH
COUT
NCP81105, NCP81105H
130
RT12
220K
100
100
R50 37.4 C56
VSN
COMP
69.8K
R19
VBOOT
DGAIN
10pF
C57
270pF R43 4.75K
DIFFOUT
FB
R37
1.00K
DIFFOUT
C51
1nF
VSP
R161
EN
VCC
VRHOT#
SDIO
ALERT#
SCLK
ROSC
VR_RDY
TSENSE
ILIM
CSCOMP
U1
CSSUM
NCP81105 CSREF
CSN2
CSP2
CSN3
CSP3
CSN1
VRMP
IMON
C61
0.15uF
27
26
25
24
23
22
21
20
19
INT_SEL
IMAX
R38
23.7K
R40
1.0K
C82
0.01uF
ILIM
CSCOMP
R25
R26
75.0K 51.1K
VDC
R18
17.4K
RT11
220K
RCS11
73.2K
C155
C156
68pF
place
close
to L1
165K
RCS12
680pF
CSSUM
CSREF
CSN2
CSP2
CSN3
CSP3
CSN1
CSP1
R138
100K
R12
10.0
R139
100K
R8
10.0
100K
R140
R185
10.0
C66
10nF
R27
10.0K
C85
22nF
R10
10.0K
C83
22nF
R9
10.0K
C80
22nF
CSPP2
CSN2
CSPP3
CSN3
CSPP1
CSN1
Figure 4. Three Phase Control Circuit Application
R34
VSS_SENSE
VSENSE
VCC_SENSE
R48
ENABLE
R71
1uF
4.99
C79
TSENSE
1.0K
1
2
VCC
VR_HOT3
4
SDIO
ALERT_VR 5
6
ROSC 7
8
9
R154
80.6K
C81
SCLK
VR_HOT
54.9
R31
11.0K
1nF
790kHz switching frequency
95A maximum output current
114A current limit
1.5mOhm loadline
1.7V boot voltage
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VCCU
VR_RDY
V5S
ENABLE
75.0
R156
place
close to L1
DRVON
PWM1
PWM3
PWM2
SMOD
OD#
6
V_1P05_VCCP
R157
R78 43.2
130
R155
37
36
35
34
33
32
31
30
29
28
EPAD
VSP
VSN
DIFFOUT
FB
COMP
DGAIN
VBOOT
VRMP
IOUT
OD#
SMOD
PWM2
PWM3
PWM1
DRVON
IMAX
INT_SEL
CSP1
10
11
12
13
14
15
16
17
18
SDIO
ALERT
SCLK
VR_RDY
R162
NCP81105, NCP81105H
CA1
10uF
SMOD
CB1
10uF
V5S
C5
1uF
CB3
10uF
V5S
C29
1uF
PWM
DISB#
C25
1uF
C26
1uF
C20
VDC
1uF
ZCD_EN#
NC
VCIN
+ C1
33uF
2
3
1
39
40
PWM
DISB#
C31
1uF
ZCD_EN#
NC
VCIN
+ C3
33uF
2
3
1
39
40
C32
1uF
U2
NCP5338
C9
VDC
1uF
U4
NCP5338
V5S
R121
1k
THWN
THWN
PHASE
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
PHASE
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
C4
0.22uF
7
L1
15 MPCG0740LR12
VCCU
43 120nH
35 0.7mOhm
CSN1
34
33
32 SW1
31
30
29
CSPP1
VCCU
CSNN3
CSPP3
VDC
CB2
10uF
C44
1uF
V5S
CA2
10uF
V5S
OD#
DRVON
PWM2
C42
22uF
C41
10uF
C27
1uF
C30
1uF
C36
VDC
1uF
DISB#
ZCD_EN#
NC
VCIN
+ C2
33uF
2
3
1
39
PWM
C45
DNP
40
C43
DNP
C67
22uF
C46
22uF
C68
22uF
C215
10uF
U3
NCP5338
C95
22uF
C78
22uF
C216
10uF
THWN
C97
DNP
C84
22uF
C217
10uF
C227
22uF
C176
22uF
C177
22uF
C183
22uF
PHASE
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
C37
0.22uF
7
L2
15 MPCG0740LR12
VCCU
43
120nH
35 0.7mOhm
34
CSNN2
33
32 SW2
31
30
29
CSPP2
C190
22uF
C210
22uF
C196
DNP
C222
22uF
VCCU
C189
22uF
C100
22uF
C184
22uF
C205
10uF
C273
22uF
C271
22uF
C272
22uF
C207
10uF
C99
22uF
C204
10uF
C206
10uF
C98
22uF
LOCATE BETWEEN L2 & L3 (PRIMARY SIDE)
C52
22uF
C49
10uF
LOCATE BETWEEN L1 & L2 (PRIMARY SIDE)
C48
10uF
C226
22uF
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (BOTTOM SIDE)
C214
10uF
Total VCORE Output
Capacitor:
26 X 22uF(0805)
+ 11 X 10uF(0805)
C28
0.22uF
7
L3
15 MPCG0740LR12
43 120nH
35 0.7mOhm
34
33
32 SW3
31
30
29
C213
22uF
7
DRVON
PWM1
CA3
10uF
OD#
DRVON
PWM3
C212
22uF
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1
2
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (PRIMARY SIDE)
Figure 5. Three Phase Power Stage Circuit
4
BOOT
38
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
16
17
18
19
20
21
22
23
24
25
26
27
28
GL
THWN
42
14
13
12
11
10
9
8
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
CGND
CGND
CGND
41
5
37
GH
4
BOOT
4
BOOT
38
THWN
36
38
THWN
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
16
17
18
19
20
21
22
23
24
25
26
27
28
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
16
17
18
19
20
21
22
23
24
25
26
27
28
GL
GL
6
42
14
13
12
11
10
9
8
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
41
5
37
CGND
CGND
CGND
GH
6
GH
6
CGND
CGND
CGND
41
5
37
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
42
14
13
12
11
10
9
8
36
36
1
2
1
2
NCP81105, NCP81105H
130
R71
1uF
4.99
C79
100
100
R50 37.4 C56
10pF
69.8K
R19
DGAIN
VBOOT
COMP
C57
270pF R43 4.75K
EN
VCC
VRHOT#
SDIO
ALERT#
SCLK
ROSC
VR_RDY
TSENSE
VSN
DIFFOUT
FB
R37
1.00K
DIFFOUT
C51
1nF
R161
VSP
TSENSE
1.0K
1
2
VCC
VR_HOT3
4
SDIO
ALERT_VR 5
6
ROSC 7
8
9
R154
80.6K
C81
ILIM
CSCOMP
U1
CSSUM
NCP81105 CSREF
CSN2
CSP2
CSN3
CSP3
CSN1
R16
24.9K
VRMP
IMON
C61
0.15uF
27
26
25
24
23
22
21
20
19
INT_SEL
IMAX
R38
23.7K
R40
1.0K
C82
0.01uF
ILIM
CSCOMP
R25
R26
43.2K 51.1K
VDC
R18
20.0k
RT11
220K
RCS11
73.2K
C155
C156
68pF
place
close
to L1
165K
RCS12
680pF
CSSUM
CSREF
V5S
R128
1K
CSN2
CSN3
CSP3
CSN1
CSP1
R139
49.9k
R8
10.0
49.9k
R140
R185
10.0
C66
10nF
R10
10.0K
C83
22nF
R9
10.0K
C80
22nF
CSPP3
CSN3
CSPP1
CSN1
Figure 6. Two Phase Control Circuit Application
R34
VSS_SENSE
VSENSE
R31
11.0K
SCLK
VR_HOT
54.9
ENABLE
VCC_SENSE
R48
VR_RDY
RT12
220K
1nF
DRVON
PWM1
PWM3
790kHz switching frequency
55A maximum output current
66A current limit
1.5mOhm loadline
1.7V boot voltage
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VCCU
ENABLE
V5S
75.0
R156
place
close to L1
SMOD
OD#
8
V_1P05_VCCP
R157
R78 43.2
130
R155
37
36
35
34
33
32
31
30
29
28
EPAD
VSP
VSN
DIFFOUT
FB
COMP
DGAIN
VBOOT
VRMP
IOUT
OD#
SMOD
PWM2
PWM3
PWM1
DRVON
IMAX
INT_SEL
CSP1
10
11
12
13
14
15
16
17
18
SDIO
ALERT
SCLK
VR_RDY
R162
NCP81105, NCP81105H
CA1
10uF
SMOD
CB1
10uF
V5S
C5
1uF
33uF
DISB#
C25
1uF
C26
1uF
C20
VDC
1uF
ZCD_EN#
NC
VCIN
+ C1
2
3
1
39
40
C31
1uF
C32
1uF
U2
NCP5338
C9
VDC
1uF
U4
NCP5338
V5S
R121
1kTHWN
THWN
C41
10uF
C213
22uF
C52
22uF
C48
10uF
C226
22uF
C67
22uF
C78
22uF
C84
22uF
C98
22uF
Total VCORE Output
Capacitor:
20 X 22uF(0805)
+ 11 X 10uF(0805)
C68
22uF
C215
10uF
C216
10uF
C217
10uF
C204
10uF
C99
22uF
C205
10uF
C100
22uF
C206
10uF
LOCATE BETWEEN L1 & L2 (PRIMARY SIDE)
C49
10uF
C227
22uF
C176
22uF
C177
22uF
C183
22uF
C184
22uF
C273
22uF
C271
22uF
VCCU
C196
22Uf
C207
10uF
C272
22uF
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (PRIMARY SIDE)
C212
22uF
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (BOTTOM SIDE)
C214
10uF
C4
0.22uF
7
L1
PHASE
15 MPCG0740LR12
43 120nH
35 0.7mOhm
CSN1
34
33
32 SW1
31
30
29
CSPP1
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
C28
0.22uF
7
L3
PHASE
15 MPCG0740LR12
VCCU
43 120nH
35 0.7mOhm
CSNN3
34
33
32 SW3
31
30
29
CSPP3
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
9
PWM
NC
VCIN
+ C3
33uF
2
3
ZCD_EN#
DISB#
PWM
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DRVON
CB3
10uF
V5S
C29
1uF
1
39
40
4
BOOT
38
THWN
PWM1
CA3
10uF
OD#
DRVON
PWM3
Figure 7. Two Phase Power Stage Circuit
4
BOOT
38
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
16
17
18
19
20
21
22
23
24
25
26
27
28
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
16
17
18
19
20
21
22
23
24
25
26
27
28
CGND
CGND
CGND
41
5
37
GL
THWN
42
14
13
12
11
10
9
8
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
CGND
CGND
CGND
41
5
37
GL
42
14
13
12
11
10
9
8
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
GH
36
GH
36
1
2
1
2
6
6
NCP81105, NCP81105H
R34
VSS_SENSE
R71
1uF
4.99
C79
100
R50 37.4 C56
10pF
69.8K
R19
DGAIN
VBOOT
COMP
C57
270pF R43 4.75K
EN
VCC
VRHOT#
SDIO
ALERT#
SCLK
ROSC
VR_RDY
TSENSE
VSN
DIFFOUT
FB
R37
1.00K
DIFFOUT
C51
1nF
R161
VSP
TSENSE
1.0K
1
2
VCC
VR_HOT3
4
SDIO
ALERT_VR 5
6
ROSC 7
8
9
R154
80.6K
C81
27
26
25
24
23
22
21
20
19
R40
1.0K
C82
VDC
R18
RT11
220K
RCS11
73.2K
C155
C156
place
close
to L1
RCS12
165K
680pF
CSN1
CSSUM
CSREF
68pF
V5S
R128
1K
CSN3
8.87K
CSP1
0.01uF
ILIM
CSCOMP
C61
R38
0.15uF 23.7K
VRMP
IMON
R16
24.9K
ILIM
CSCOMP
U1
CSSUM
NCP81105 CSREF
CSN2
CSP2
CSN3
CSP3
CSN1
INT_SEL
IMAX
R25
R26
25.5K 51.1K
R140
75.0K
R185
10.0
C66
10nF
R9
10.0K
C80
22nF
CSPP1
CSN1
Figure 8. Single Phase Control Circuit Application
VSENSE
R31
11.0K
SCLK
VR_HOT
54.9
ENABLE
VCC_SENSE
R48
100
VCCU
V5S
ENABLE
75.0
R156
VR_RDY
RT12
220K
1nF
790kHz switching frequency
32A maximum output current
39A current limit
2.0mOhm loadline
1.7V boot voltage
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V_1P05_VCCP
130
R78 43.2
R157
place
close to L1
DRVON
PWM1
PWM3
PWM2
SMOD
OD#
10
130
R155
37
36
35
34
33
32
31
30
29
28
EPAD
VSP
VSN
DIFFOUT
FB
COMP
DGAIN
VBOOT
VRMP
IOUT
OD#
SMOD
PWM2
PWM3
PWM1
DRVON
IMAX
INT_SEL
CSP1
10
11
12
13
14
15
16
17
18
SDIO
ALERT
SCLK
VR_RDY
R162
NCP81105, NCP81105H
CB1
10uF
V5S
C5
1uF
33uF
DISB#
C25
1uF
C26
1uF
C20
VDC
1uF
ZCD_EN#
NC
VCIN
+ C1
2
3
1
39
PWM
U2
NCP5338
V5S
R121
1k
THWN
PHASE
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
7
C4
0.22uF
L1
SW1
15 MPCG0740LR12
43
120nH
35 0.7mOhm
34
33
32
31
30
29
CSN1
CSPP1
C52
DNP
C68
DNP
C78
22uF
C84
22uF
Total VCORE Output
Capacitor:
16 X 22uF(0805)
+ 11 X 10uF(0805)
C67
DNP
C49
10uF
C215
10uF
C216
10uF
C217
10uF
LOCATE NEAR L1 (PRIMARY SIDE)
C48
10uF
C227
22uF
C176
22uF
C177
22uF
C183
22uF
C98
22uF
C204
10uF
C184
22uF
C99
22uF
C205
10uF
C273
22uF
C100
22uF
C206
10uF
C271
22uF
VCCU
C196
DNP
C207
10uF
C272
22uF
Figure 9. Single Phase Power Stage Circuit
1
2
40
C41
10uF
C226
22uF
11
CA1
10uF
SMOD
DRVON
PWM1
C214
10uF
C213
22uF
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (BOTTOM SIDE)
C212
22uF
LOCATE IN CENTER OF SOCKET rPGA989 CAVITY (PRIMARY SIDE)
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4
BOOT
38
16
17
18
19
20
21
22
23
24
25
26
27
28
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
THWN
42
14
13
12
11
10
9
8
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
CGND
CGND
CGND
41
5
37
GL
36
GH
6
NCP81105, NCP81105H
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL INFORMATION − all signals referenced to GND unless noted otherwise.
Pin Symbol
VMAX
COMP, CSCOMP, DIFFOUT
VMIN
ISOURCE
ISINK
3 mA
3 mA
VCC + 0.3 V
−0.3 V
GND + 300 mV
GND − 300 mV
VCC + 0.3 V
−0.3 V
N/A
5 mA
VCC
6.5 V
−0.3 V
N/A
N/A
VRMP
+25 V
−0.3 V
VR_HOT#, SDIO & ALERT#
VCC + 0.3 V
−0.3 V
0 mA
30 mA
OD#, SMOD, PWM1, PWM2,
PWM3 & DRVON
VCC + 0.3 V
−0.3 V
5 mA
5 mA
All Other Pins
VCC + 0.3 V
−0.3 V
VSN
VR_RDY
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
THERMAL INFORMATION
Description
Symbol
Thermal Characteristic
QFN36 Package (Notes 1 and 2)
Typ
RqJA
Operating Junction Temperature Range*
Unit
_C/W
68
TJ
Operating Ambient Temperature Range
−10 to 125
_C
−10 to 100
_C
_C
Maximum Storage Temperature Range
TSTG
−40 to +150
Moisture Sensitivity Level
MSL
1
*The maximum package power dissipation must be observed.
1. JESD 51−5 (1S2P Direct−Attach Method) with 0 LFM
2. JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
5.25
V
VCC INPUT
4.75
Supply Voltage Range
Quiescent Current
EN = high; PS0, 1, 2 modes
23
29
mA
EN = high; PS3 Mode
14
17.5
mA
30
mA
4.5
V
EN = low
VCC rising
UVLO Threshold
VCC falling
4.0
UVLO Hysteresis
V
160
mV
VRMP (VIN monitor)
UVLO Threshold
VRMP falling
UVLO Hysteresis
Leakage current
3.0
3.2
600
800
3.4
V
mV
PS0, PS1, PS2, PS3; VVRMP = 3.2 V
70
mA
Leakage current
PS4, VVRMP = 20 V
500
nA
Leakage current
VEN = 0 V, VVRMP = 20 V
500
nA
External 1k pull−up to 3.3 V
1.0
mA
ENABLE INPUT
Enable High Input Leakage Current
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12
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
0.8
V
ENABLE INPUT
Upper Threshold
VUPPER
Lower Threshold
VLOWER
Total Hysteresis
0.3
VUPPER − VLOWER
V
300
Time from Enable transitioning HI to when
DRVON goes high.
Enable Delay Time
mV
2.4
ms
0.45
V
SCLK, SDIO, ALERT#
SCLK Input Low Voltage
VILSCLK
SCLK Input High Voltage
VIHSCLK
SDIO Input Low Voltage
VILSDIO
SDIO Input High Voltage
VIHSDIO
0.66
V
0.42
0.72
V
V
Hysteresis Voltage (SCLK, SDIO)
VHYS
100
mV
Output High Voltage (SDIO, ALERT#)
VOH
External resistive pullup to 1.05 V
1.05
V
Output Low Voltage (SDIO, ALERT#)
VOL
Sinking 20 mA
100
mV
Buffer On Resistance (SDIO, ALERT#)
RON
Leakage Current
Measured sinking 4 mA
Pin voltage between 0 and 1.05 V
5
−100
Pin Capacitance
13
W
100
mA
4.0
pF
8.3
ns
VR clock to data delay
TCO
Time between SCLK rising edge and valid
SDIO level
4
Setup time
TSU
Time before SCLK falling (sampling) edge
that SDIO level must be valid
7
ns
Hold time
THLD
Time after SCLK falling edge that the
SDIO level remains valid
14
ns
VR12.5 & VR12.6 DAC
System Voltage Accuracy
1.5 V ≤ DAC < 2.3 V, −10°C ≤ TA ≤ 85°C
−0.5
0.5
%
1.0 V ≤ DAC < 1.49 V, −10°C ≤ TA ≤ 85°C
−8
8
mV
0.5 V ≤ DAC < 0.99 V, −10°C ≤ TA ≤ 85°C
−10
10
mV
DAC SLEW RATES (NCP81105)
Soft Start Slew Rate
Slew Rate Slow
SVID Register 2Ah = default
12
mV/ms
Selectable Fraction of Fast Slew
3 − 24
mV/ms
48
mV/ms
SVID Register 2Ah = default
2.5
mV/ms
Selectable Fraction of Fast Slew
1−5
mV/ms
10
mV/ms
Slew Rate Fast
DAC SLEW RATES (NCP81105H)
Soft Start Slew Rate
Slew Rate Slow
Slew Rate Fast
DIFFERENTIAL SUMMING AMPLIFIER
VSP Input Leakage Current
VSN Bias Current
DVID UP Feedforward Charge
VVSP = 1.3 V
0
15
mA
−0.3 V ≤ VVSN ≤ 0.3 V
−1
1
mA
−0.3 V ≤ VVSN ≤ 0.5 V
Charge per 5 mV DAC increment
6.8
pC
VSP Input Voltage Range
−0.3
3.0
V
VSN Input Voltage Range
−0.3
0.3
V
−3dB Bandwidth
DC gain − VSx to DIFFOUT
CL = 20 pF to GND, RL = 10 kW to GND
10
MHz
VSP − VSN = 0.5 V to 2.3 V
1.0
V/V
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13
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Maximum Output Voltage
ISOURCE = 2 mA
3.0
Minimum Output Voltage
ISINK = 2 mA
Typ
Max
Unit
DIFFERENTIAL SUMMING AMPLIFIER
V
0.5
V
25
mA
ERROR AMPLIFIER
Input Bias Current
VFB = 1.3 V; Internal integrator active
−25
Open Loop DC Gain
CL = 20 pF to GND,
RL = 10 kW to GND
80
dB
Open Loop Unity Gain Bandwidth
CL = 20 pF to GND,
RL = 10 kW to GND
20
MHz
DVin = 100 mV, G = −10 V/V,
DVout = 1.5 V − 2.5 V,
Load = 20 pF to GND + 10 kW to GND
20
V/ms
Slew Rate
Maximum Output Voltage
ISOURCE = 2.0 mA
3.5
V
Minimum Output Voltage
ISINK = 2.0 mA
1
V
IVR_RDY = 4 mA
0.3
V
VR_RDY (Power Good) OUTPUT
Output Low Saturation Voltage
Rise Time
1 kW external pull−up to 3.3 V,
CTOT = 45 pF
100
ns
Fall Time
1 kW external pull−up to 3.3 V,
CTOT = 45 pF
10
ns
Output Voltage at Power−up
Output Leakage Current When High
VR_RDY pulled up to 5 V via 2 kW
VR_RDY = 5.0 V
−1.0
VR_RDY Delay (rising)
DAC = TARGET to VR_RDY high
5.5
VR_RDY Delay (falling)
From OCP or OVP to VR_RDY low
5
1.0
V
1.0
mA
6
ms
ms
OUTPUT OVER VOLTAGE & UNDER VOLTAGE PROTECTION (OVP & UVP)
Absolute Over Voltage Threshold
During Soft−Start
Over Voltage Threshold Above DAC
Over Voltage Delay
VSP rising
2.8
2.9
3.0
V
350
400
425
mV
VSP rising to PWMx low
50
ns
VSP falling
300
mV
5
ms
Under Voltage Threshold Below DAC
Under−voltage Delay
CURRENT BALANCE AMPLIFIERS
Input Bias Current (after phase
detection)
CSPx = CSNx = 1.7 V
−50
50
nA
Common Mode Input Voltage Range
CSPx = CSNx
0
2.3
V
Differential Mode Input Voltage Range
CSNx = 1.7 V
−100
100
mV
CSPx = CSNx = 1.7 V,
Measured from the average offset
−1.5
1.5
mV
Amplifier Gain
0 V < CSPx−CSNx ≤ 0.1 V
5.7
6.3
V/V
Gain Matching
10 mV ≤ CSPx−CSNx ≤ 30 mV
−3
Closed loop Input Offset Voltage
Matching
−3 dB Bandwidth
6.0
3
%
8
MHz
50
kW
4.5
V
1 & 2 PHASE DETECTION
CSN Pin Resistance to Ground
During phase detection only
CSN Pin Threshold Voltage
Phase Detect Timer
Time from Enable transitioning HI to
removal of phase detect resistance
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14
3.5
ms
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
VOS
VCSREF = 1.0 V
−300
CSSUM Input Bias Current
CSSUM = CSREF = 1 V
CSREF Input Bias Current
CSSUM = CSREF = 1 V
Typ
Max
Unit
300
mV
−7.5
7.5
nA
0
4.25
mA
CURRENT SUMMING AMPLIFIER
Offset Voltage
Open Loop Gain
Current Sense Unity Gain Bandwidth
CL = 20 pF to GND, RL = 10 kW to GND
Max CSCOMP Output Voltage
Isource = 2 mA
80
dB
10
MHz
3.5
V
Isink = 500 mA
Minimum CSCOMP Output Voltage
7.0
Isink = 25 mA
100
mV
30
mV
IOUT OUTPUT
Maximum Output Voltage
Input Referred Offset Voltage
Output Source Current
Current Gain
AIIOUT
DIMON Full Scale Voltage
VDIFS
RIOUT = 5 kW
2.0
ILIM minus CSREF
−1.9
ILIM sink current = 80 mA
700
(IOUTCURRENT) / (ILIMCURRENT);
RILIM = 20 kW; RIOUT = 5.0 kW;
VCSREF = 1.7 V
9.5
V
1.9
mV
mA
10
10.5
2.0
A/A
V
OVERCURRENT PROTECTION (ILIM pin)
3 & 2−phase PS0 Threshold Current,
1−phase all−PS Threshold Current
Delayed shutdown
Immediate shutdown
IDS
IIS
3−phase, non−PS0 Threshold Current
Delayed shutdown
Immediate shutdown
IDS
IIS
PS1, 2 or 3 mode (1−phase active)
PS1, 2 or 3 mode (1−phase active)
4
6
2−phase, non−PS0 Threshold Current
Delayed shutdown
Immediate shutdown
IDS
IIS
PS1, 2 or 3 mode (1−phase active)
PS1, 2 or 3 mode (1−phase active)
6.7
10
mA
9.0
13.5
Time for Delayed Shutdown
10
15
11.0
16.5
mA
mA
55
ms
OSCILLATOR
Maximum Switching Frequency
See Precision Oscillator description
Minimum Switching Frequency
See Precision Oscillator description
Switching Frequency Tolerance
PS0 mode; RROSC = 110 kW
925
VROSC = GND
9.5
ROSC Pin Output Current
1425
kHz
275
kHz
1025
1125
kHz
10
10.5
mA
MODULATORS (PWM Comparators)
20
ns
0% Duty Cycle
COMP voltage when the PWM outputs
remain Lo (Dual−edge modulation only)
1.3
V
100% Duty Cycle
COMP voltage when the PWM outputs
remain HI, VRMP = 12.0 V; (Dual−edge
modulation only)
2.5
V
Minimum Pulse Width
Between adjacent phases, 3−phase
operation
−20
20
deg
VRMP pin voltage
5
20
V
Output High Voltage
Sourcing 500 mA
VCC −
0.2
Output Low Voltage
Sinking 500 mA
PWM Phase Angle Error
Ramp Feed−forward Voltage range
PWM OUTPUTS (PWM1/2/3)
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15
V
0.7
V
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
PWM OUTPUTS (PWM1/2/3)
CL (PCB) = 50 pF, measured between
10% & 90% of VCC
Rise and Fall Times
10
ns
DRVON OUTPUT
Output High Voltage
Sourcing 500 mA
Output Low Voltage
Sinking 500 mA
3.0
V
0.1
V
Rise Time
CL (PCB) = 20 pF, DVo = 10% to 90%
150
ns
Fall Time
CL (PCB) = 20 pF, DVo = 90% to 10%
5
ns
PWM delay time
Time from DRVON high to first PWM
Internal Pull Down Resistance
110
EN = Low
120
ms
70
kW
OD# OUTPUT
3.0
V
Output High Voltage
Sourcing 500 mA
Output Low Voltage
Sinking 500 mA
0.1
V
PS0 Delay
Entering PS0; from fall of the earlier of
PWM2 or PWM3 to OD# rising
15
ns
Rise/Fall Time
CL (PCB) = 20 pF, DVo = 10% to 90%
10
ns
EN = Low
70
kW
Internal Pull Down Resistance
SMOD OUTPUT
Output High Voltage
Sourcing 500 mA
Output Low Voltage
Sinking 500 mA
3.0
V
V
50
ns
PS2/3 Delay
PS2&3; PWM1 rising to SMOD rising
Rise/Fall Time
CL (PCB) = 20 pF, DVo = 10% to 90%
10
ns
EN = Low
70
kW
Internal Pull Down Resistance
10
0.1
VR_HOT# OUTPUT
I_VRHOT# = −4 mA
Output Low Voltage
Output Leakage Current
High Impedance State, VVRHOT# = 3.3 V
−1.0
0.3
V
1.0
mA
TSENSE INPUT
Alert# Assert Threshold
TA = 85°C
458
mV
Alert# De−assert Threshold
TA = 85°C
476
mV
VRHOT# Assert Threshold
TA = 85°C
437
mV
VRHOT# De−assert Threshold
TA = 85°C
457
mV
TSENSE Bias Current
VTSENSE = 0.4 V, TA = 85°C
57.7
60
62.7
mA
VBOOT PIN
VVBOOT = GND
Sensing Current
10
mA
IMAX PIN
Sensing Current
IMAX Full Scale Voltage
IIMAX
VIMAX = GND
9.5
VIMAXFS
10
10.5
mA
2.0
V
VINT_SEL = GND
10
mA
VDGAIN = GND
10
mA
INT_SEL PIN
Sensing Current
DGAIN PIN
Sensing Current
ADC
0
Input Voltage Range
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16
2
V
NCP81105, NCP81105H
ELECTRICAL CHARACTERISTICS (VCC = 5.0 V, VEN = 2.0 V, CVCC = 0.1 mF unless specified otherwise) Min/Max values are valid
for the temperature range −10°C ≤ TA ≤ 100°C unless noted otherwise, and are guaranteed by test, design or statistical correlation.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
+1
%
1
LSB
ADC
Total Unadjusted Error (TUE)
−1
Differential Nonlinearity (DNL)
8−bit
Power Supply Sensitivity
±1
%
Conversion Time
10
ms
Time to cycle through all inputs
250
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17
ms
NCP81105, NCP81105H
VR12.5 & VR12.6 VID TABLE
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
0
0
0
0
0
0
0
0
OFF
00
0
0
1
1
1
1
1
0
1.11
3E
0
0
0
0
0
0
0
1
0.50
01
0
0
1
1
1
1
1
1
1.12
3F
0
0
0
0
0
0
1
0
0.51
02
0
1
0
0
0
0
0
0
1.13
40
0
0
0
0
0
0
1
1
0.52
03
0
1
0
0
0
0
0
1
1.14
41
0
0
0
0
0
1
0
0
0.53
04
0
1
0
0
0
0
1
0
1.15
42
0
0
0
0
0
1
0
1
0.54
05
0
1
0
0
0
0
1
1
1.16
43
0
0
0
0
0
1
1
0
0.55
06
0
1
0
0
0
1
0
0
1.17
44
0
0
0
0
0
1
1
1
0.56
07
0
1
0
0
0
1
0
1
1.18
45
0
0
0
0
1
0
0
0
0.57
08
0
1
0
0
0
1
1
0
1.19
46
0
0
0
0
1
0
0
1
0.58
09
0
1
0
0
0
1
1
1
1.20
47
0
0
0
0
1
0
1
0
0.59
0A
0
1
0
0
1
0
0
0
1.21
48
0
0
0
0
1
0
1
1
0.60
0B
0
1
0
0
1
0
0
1
1.22
49
0
0
0
0
1
1
0
0
0.61
0C
0
1
0
0
1
0
1
0
1.23
4A
0
0
0
0
1
1
0
1
0.62
0D
0
1
0
0
1
0
1
1
1.24
4B
0
0
0
0
1
1
1
0
0.63
0E
0
1
0
0
1
1
0
0
1.25
4C
0
0
0
0
1
1
1
1
0.64
0F
0
1
0
0
1
1
0
1
1.26
4D
0
0
0
1
0
0
0
0
0.65
10
0
1
0
0
1
1
1
0
1.27
4E
0
0
0
1
0
0
0
1
0.66
11
0
1
0
0
1
1
1
1
1.28
4F
0
0
0
1
0
0
1
0
0.67
12
0
1
0
1
0
0
0
0
1.29
50
0
0
0
1
0
0
1
1
0.68
13
0
1
0
1
0
0
0
1
1.30
51
0
0
0
1
0
1
0
0
0.69
14
0
1
0
1
0
0
1
0
1.31
52
0
0
0
1
0
1
0
1
0.70
15
0
1
0
1
0
0
1
1
1.32
53
0
0
0
1
0
1
1
0
0.71
16
0
1
0
1
0
1
0
0
1.33
54
0
0
0
1
0
1
1
1
0.72
17
0
1
0
1
0
1
0
1
1.34
55
0
0
0
1
1
0
0
0
0.73
18
0
1
0
1
0
1
1
0
1.35
56
0
0
0
1
1
0
0
1
0.74
19
0
1
0
1
0
1
1
1
1.36
57
0
0
0
1
1
0
1
0
0.75
1A
0
1
0
1
1
0
0
0
1.37
58
0
0
0
1
1
0
1
1
0.76
1B
0
1
0
1
1
0
0
1
1.38
59
0
0
0
1
1
1
0
0
0.77
1C
0
1
0
1
1
0
1
0
1.39
5A
0
0
0
1
1
1
0
1
0.78
1D
0
1
0
1
1
0
1
1
1.40
5B
0
0
0
1
1
1
1
0
0.79
1E
0
1
0
1
1
1
0
0
1.41
5C
0
0
0
1
1
1
1
1
0.80
1F
0
1
0
1
1
1
0
1
1.42
5D
0
0
1
0
0
0
0
0
0.81
20
0
1
0
1
1
1
1
0
1.43
5E
0
0
1
0
0
0
0
1
0.82
21
0
1
0
1
1
1
1
1
1.44
5F
0
0
1
0
0
0
1
0
0.83
22
0
1
1
0
0
0
0
0
1.45
60
0
0
1
0
0
0
1
1
0.84
23
0
1
1
0
0
0
0
1
1.46
61
0
0
1
0
0
1
0
0
0.85
24
0
1
1
0
0
0
1
0
1.47
62
0
0
1
0
0
1
0
1
0.86
25
0
1
1
0
0
0
1
1
1.48
63
0
0
1
0
0
1
1
0
0.87
26
0
1
1
0
0
1
0
0
1.49
64
0
0
1
0
0
1
1
1
0.88
27
0
1
1
0
0
1
0
1
1.50
65
0
0
1
0
1
0
0
0
0.89
28
0
1
1
0
0
1
1
0
1.51
66
0
0
1
0
1
0
0
1
0.90
29
0
1
1
0
0
1
1
1
1.52
67
0
0
1
0
1
0
1
0
0.91
2A
0
1
1
0
1
0
0
0
1.53
68
0
0
1
0
1
0
1
1
0.92
2B
0
1
1
0
1
0
0
1
1.54
69
0
0
1
0
1
1
0
0
0.93
2C
0
1
1
0
1
0
1
0
1.55
6A
0
0
1
0
1
1
0
1
0.94
2D
0
1
1
0
1
0
1
1
1.56
6B
0
0
1
0
1
1
1
0
0.95
2E
0
1
1
0
1
1
0
0
1.57
6C
0
0
1
0
1
1
1
1
0.96
2F
0
1
1
0
1
1
0
1
1.58
6D
0
0
1
1
0
0
0
0
0.97
30
0
1
1
0
1
1
1
0
1.59
6E
0
0
1
1
0
0
0
1
0.98
31
0
1
1
0
1
1
1
1
1.60
6F
0
0
1
1
0
0
1
0
0.99
32
0
1
1
1
0
0
0
0
1.61
70
0
0
1
1
0
0
1
1
1.00
33
0
1
1
1
0
0
0
1
1.62
71
0
0
1
1
0
1
0
0
1.01
34
0
1
1
1
0
0
1
0
1.63
72
0
0
1
1
0
1
0
1
1.02
35
0
1
1
1
0
0
1
1
1.64
73
0
0
1
1
0
1
1
0
1.03
36
0
1
1
1
0
1
0
0
1.65
74
0
0
1
1
0
1
1
1
1.04
37
0
1
1
1
0
1
0
1
1.66
75
0
0
1
1
1
0
0
0
1.05
38
0
1
1
1
0
1
1
0
1.67
76
0
0
1
1
1
0
0
1
1.06
39
0
1
1
1
0
1
1
1
1.68
77
0
0
1
1
1
0
1
0
1.07
3A
0
1
1
1
1
0
0
0
1.69
78
0
0
1
1
1
0
1
1
1.08
3B
0
1
1
1
1
0
0
1
1.70
79
0
0
1
1
1
1
0
0
1.09
3C
0
1
1
1
1
0
1
0
1.71
7A
0
0
1
1
1
1
0
1
1.10
3D
0
1
1
1
1
0
1
1
1.72
7B
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18
NCP81105, NCP81105H
VR12.5 & VR12.6 VID TABLE
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
HEX
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Voltage
(V)
0
1
1
1
1
1
0
0
1.73
7C
1
0
0
1
1
0
0
1
2.02
99
0
1
1
1
1
1
0
1
1.74
7D
1
0
0
1
1
0
1
0
2.03
9A
0
1
1
1
1
1
1
0
1.75
7E
1
0
0
1
1
0
1
1
2.04
9B
0
1
1
1
1
1
1
1
1.76
7F
1
0
0
1
1
1
0
0
2.05
9C
1
0
0
0
0
0
0
0
1.77
80
1
0
0
1
1
1
0
1
2.06
9D
1
0
0
0
0
0
0
1
1.78
81
1
0
0
1
1
1
1
0
2.07
9E
1
0
0
0
0
0
1
0
1.79
82
1
0
0
1
1
1
1
1
2.08
9F
1
0
0
0
0
0
1
1
1.80
83
1
0
1
0
0
0
0
0
2.09
A0
1
0
0
0
0
1
0
0
1.81
84
1
0
1
0
0
0
0
1
2.10
A1
1
0
0
0
0
1
0
1
1.82
85
1
0
1
0
0
0
1
0
2.11
A2
1
0
0
0
0
1
1
0
1.83
86
1
0
1
0
0
0
1
1
2.12
A3
1
0
0
0
0
1
1
1
1.84
87
1
0
1
0
0
1
0
0
2.13
A4
1
0
0
0
1
0
0
0
1.85
88
1
0
1
0
0
1
0
1
2.14
A5
1
0
0
0
1
0
0
1
1.86
89
1
0
1
0
0
1
1
0
2.15
A6
1
0
0
0
1
0
1
0
1.87
8A
1
0
1
0
0
1
1
1
2.16
A7
1
0
0
0
1
0
1
1
1.88
8B
1
0
1
0
1
0
0
0
2.17
A8
1
0
0
0
1
1
0
0
1.89
8C
1
0
1
0
1
0
0
1
2.18
A9
1
0
0
0
1
1
0
1
1.90
8D
1
0
1
0
1
0
1
0
2.19
AA
1
0
0
0
1
1
1
0
1.91
8E
1
0
1
0
1
0
1
1
2.20
AB
1
0
0
0
1
1
1
1
1.92
8F
1
0
1
0
1
1
0
0
2.21
AC
1
0
0
1
0
0
0
0
1.93
90
1
0
1
0
1
1
0
1
2.22
AD
1
0
0
1
0
0
0
1
1.94
91
1
0
1
0
1
1
1
0
2.23
AE
1
0
0
1
0
0
1
0
1.95
92
1
0
1
0
1
1
1
1
2.24
AF
1
0
0
1
0
0
1
1
1.96
93
1
0
1
1
0
0
0
0
2.25
B0
1
0
0
1
0
1
0
0
1.97
94
1
0
1
1
0
0
0
1
2.26
B1
1
0
0
1
0
1
0
1
1.98
95
1
0
1
1
0
0
1
0
2.27
B2
1
0
0
1
0
1
1
0
1.99
96
1
0
1
1
0
0
1
1
2.28
B3
1
0
0
1
0
1
1
1
2.00
97
1
0
1
1
0
1
0
0
2.29
B4
1
0
0
1
1
0
0
0
2.01
98
1
0
1
1
0
1
0
1
2.30
B5
Setup and Hold times − CPU Driving SDIO
SCLK
VR
latch
SDIO
tSU
tHLD
VR Driving SDIO, Clock to Data Delay
SCLK
VR
send
SDIO
TCO_VR = clock to data delay in VR
TCO_VR
Figure 10. SVID Timing Diagrams
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19
HEX
NCP81105, NCP81105H
STATE TRUTH TABLE
VR_RDY
Pin
Error AMP
Comp Pin
OVP & UVP
DRVON Pin
SMOD Pin
OD# Pin
VCC UVLO
0 < VCC < threshold
VRMP > threshold
N/A
N/A
N/A
Resistive pull
down
Resistive pull down
Resistive pull down
VRMP UVLO
VCC > threshold
0 < VRMP < threshold
N/A
N/A
N/A
Resistive pull
down
Resistive pull down
Resistive pull down
Disabled
EN < threshold
VCC > threshold
VRMP > threshold
Low
Low
Disabled
Low
Low
Low
Start up Delay &
Calibration
EN > threshold
VCC > threshold
VRMP > threshold
Low
Low
Disabled
Low
Low
Low
Soft Start
EN > threshold
VCC > threshold
VRMP > threshold
Low
Operational
Active
High
Low until first PWM1
pulse
Low until first PWM2
or PWM3 pulse
Normal Operation
EN > threshold
VCC > threshold
VRMP > threshold
High
Operational
Active
High
High in PS0 & PS1;
High or may toggle in
PS2 & PS3
High in PS0; Low in
PS1, PS2, & PS3
N/A
Over Voltage
Low
Low
DAC + 400 mV
High
High/ Toggles during
output rampdown
High/ Toggles during
output rampdown
EN low or cycle
power
Under Voltage
Low
Operational
DAC−Droop
−300 mV
High
High
High
Output voltage >
DAC−Droop
−300 mV
Over Current
Low
Operational
Last DAC Code
+ 400 mV
Low
Low
Low
EN low or cycle
power
VID Code = 00h
Low
Low
Disabled
High (PWM
outputs low)
Low
Low
Set Valid VID
Code
State
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20
Method of Reset
NCP81105, NCP81105H
Controller
POR
VCC > UVLO
Disable
EN = 0
VCC < UVLO
EN = 1
Calibrate
Drive Off
3.5 ms and CAL DONE
VDRP > ILIM
NO_CPU
INVALID VID
Phase
Detect
VCCP > UVLO and DRON HIGH
Soft Start
Ramp
DAC = Vboot
Soft Start
Ramp
OVP
DAC = VID
VS > OVP
Normal
VR_RDY
VS > UVP
VS < UVP
UVP
Figure 11. State Diagram
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21
NCP81105, NCP81105H
General
The NCP81105 is a single output, one−to−three phase, dual−edge modulated PWM controller with a serial VID control
interface designed to meet the Intel VR12.5 & VR12.6 specifications. The NCP81105 implements PS0, PS1, PS2, PS3 and
PS4 power states. It is designed to work in notebook and desktop CPU power supply applications.
Power Status
PWM Output Operating Mode
PS0
Multi−phase, fixed frequency, dual edge modulation (RPM modulation when optioned for single phase), interleaved PWM outputs (CCM mode)
PS1
Single−phase (PWM1) COT (CCM mode; Phases 2 & 3 disabled by OD#)
PS2
Single−phase (PWM1) RPM (DCM mode by SMOD; Phases 2 & 3 disabled by OD#)
PS3
Single−phase (PWM1) RPM (DCM mode by SMOD; Phases 2 & 3 disabled by OD#)
PS4
No switching; Memory retained; SVID active
For 81105, the VID code change rate is controlled with the SVID interface with three options as below:
Register Address (Contains
the slew rate of VID code
change)
DVID Option
SVID Command
Code
SetVID_Fast
01h
48 mV/ms VID code change slew rate
24h
SetVID_Slow
02h
12 mV/ms VID code change slew rate**
25h
SetVID_Decay
03h
No control, VID code down
N/A
Feature
**The Slow VID code change slew rate can be modified by writing to the 2Ah register with the SVID bus.
For 81105H, the VID code change rate is controlled with the SVID interface with three options as below:
DVID Option
SVID Command
Code
Feature
Register Address (Contains
the slew rate of VID code
change)
SetVID_Fast
01h
10 mV/ms VID code change slew rate
24h
SetVID_Slow
02h
2.5 mV/ms VID code change slew rate**
25h
SetVID_Decay
03h
No control, VID code down
N/A
**The Slow VID code change slew rate can be modified by writing to the 2Ah register with the SVID bus.
Serial VID
The NCP81105 supports the Intel serial VID (SVID) interface. It communicates with the microprocessor through three wires
(SCLK, SDIO, ALERT#). The table of supported registers is shown below.
Index
Name
00h
Vendor ID
01h
Description
Access
Default
Uniquely identifies the VR vendor. The vendor ID assigned by Intel to
ON Semiconductor is 0x1Ah
R
1Ah
Product ID
Uniquely identifies the VR product. The VR vendor assigns this number.
R
15h
02h
Product
Revision
Uniquely identifies the revision or stepping of the VR control IC. The VR
vendor assigns this data.
R
04h
03h
Product date
code ID
R
00
05h
Protocol ID
Identifies the SVID Protocol the NCP81105 supports
R
03h
06h
Capability
Informs the Master of the NCP81105’s Capabilities,
1 for supported, 0 for not supported
Bit 7: Iout_format; Reg 15 FFh = Icc_Max (=1)
Bit 6: ADC Measurement of Temp; Supported (= 1)
Bit 5: ADC Measurement of Pin; Not supported (= 0)
Bit 4: ADC Measurement of Vin; Supported (= 1)
Bit 3: ADC Measurement of Iin; Not supported (= 0)
Bit 2: ADC Measurement of Pout; Supported (= 1)
Bit 1: ADC Measurement of Vout; Supported (= 1)
Bit 0: ADC Measurement of Iout; Supported (= 1)
R
D7h
10h
Status_1
Data register read after the ALERT# signal is asserted. Conveying the status
of the VR.
R
00h
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22
NCP81105, NCP81105H
Index
Name
11h
Status_2
12h
Temp zone
15h
Description
Access
Default
Data register showing optional status_2 data.
R
00h
Data register showing temperature zones the system is operating in
(thermometer format with 3 degree resolution).
R
00h
I_out
8 bit binary word ADC of current. This register reads 0xFF when the output
current is at ICC_Max
R
01h
16h
V_out
8 bit binary word ADC of output voltage, measured between VSP and VSN.
LSB size is 8 mV
R
01h
17h
VR_Temp
8 bit binary word ADC of temperature. Binary format in deg C, IE 100C = 64h.
R
01h
18h
P_out
8 bit binary word representative of output power. The output voltage is
multiplied by the output current value and the result is stored in this register.
R
01h
1Ah
V_in
8 bit binary word ADC of input voltage, measured at VRMP pin. LSB size is
112 mV
R
00h
1Ch
Status 2 Last
read
When the status 2 register is read, its contents are copied into this register.
The format is the same as the Status 2 Register.
R
00h
21h
ICC_Max
Data register containing the ICC_Max supported by the platform. The value is
measured at the IMAX pin upon power up and placed in this register. From
that point on, the register is read only.
R
00h
22h
Temp_Max
Data register containing the max temperature the platform supports and the
level VR_hot asserts. This value defaults to 100°C and is programmable over
the SVID Interface
R/W
64h
24h
SR_fast
NCP81105
NCP81105H
R
R
32h
0Ah
25h
SR_slow
Slew Rate for SetVID_slow commands. A fraction of the SR_fast rate (register
24h) determined by register 2Ah. Binary format in mV/ms
NCP81105
NCP81105H
R
R
0Ch
03h
26h
Vboot
The Boot voltage is programmed using a resistor on the VBOOT pin which is
sensed on power up. The NCP81105 will ramp to Vboot and hold at Vboot until
it receives a new SVID SetVID command to move to a different voltage.
R
00h
2Ah
SR_Slow
selector
0001 = Fast_SR/2
0010 = Fast_SR/4: default
0100 = Fast_SR/8
1000 = Fast_SR/16
R/W
02h
2Bh
PS4 exit
latency
Reflects the latency of exiting the PS4 state. The exit latency is defined as the
time duration, in us, from the ACK of the SETVID Slow/Fast command to the
beginning of the output voltage ramp.
R
8Ch
2Ch
PS3 exit
latency
Reflects the latency of exiting the PS3 state. The exit latency is defined as the
time duration, in us, from the ACK of the SETVID Slow/Fast command until the
NCP81105 is capable of supplying max current of the commanded PS state.
R
55h
2Dh
Enable to
ready for SVID
time
Reflects the latency from Enable assertion to the VR controller being ready to
accept an SVID command. The latency is defined as the time duration, in ms:
(x/16)*2Y.
X = bits [3:0]: 4 bit value 0000 to 1111
Y = bits [7:4]: 4 bit value 0000 to 1111
R
CAh
30h
Vout_Max
Programmed by master and sets the maximum VID the VR will support. If a
higher VID code is received, the VR will respond with a “not supported”
acknowledgement. VR12.5 & VR12.6 VID format, e.g., B5h = 2.3 V (see VID
Table)
RW
B5h
31h
VID setting
Data register containing currently programmed VID voltage. VID data format.
VR12.5 & VR12.6 VID format, e.g., 97h = 2.0 V
RW
00h
32h
Pwr State
Register containing the current programmed power state.
RW
00h
Slew Rate for SetVID_fast commands. Binary format in mV/ms.
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NCP81105, NCP81105H
Index
33h
34h
Name
Description
Access
Default
Offset
Sets offset in VID steps added to the VID setting for voltage margining. Bit 7 is
sign bit, 0 = positive margin, 1 = negative margin. Remaining 7 BITS are # VID
steps for margin 2s complement.
00h=no margin
01h=+1 VID step
02h=+2 VID steps
FFh=−1 VID step
FEh=−2 VID steps.
RW
00h
MultiVR Config
Bit 0 set to 1 causes VR_RDY to respond to a SetVID (0.0 V) command as a
valid VID voltage setting instead of a disable command (only after ramping to a
non−zero VID after startup).
Bit 1 set to 1 locks the current VID and Power State settings until such time as
the VR is issued a SetPS(00h) command.
RW
00h
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NCP81105, NCP81105H
Phase Detection Sequence
During start−up, the number of operational phases is determined by the internal circuitry monitoring the CSN inputs.
Normally, NCP81105 operates as a 3−phase PWM controller. Connecting the CSN2 pin to VCC programs 2−phase operation
using phases 1 and 3. Connecting the CSN3 pin to VCC programs 1−phase operation using phase 1.
Prior to soft start, while ENABLE is high, the CSN2 and CSN3 pins have approximately 50 kW to ground. An internal
comparator checks the voltage of the CSN pins and compares them to a reference voltage. If either pin is tied to VCC, its voltage
is above the reference voltage and the controller is configured for reduced−phase operation. Otherwise, the resistance pulls the
pin voltages to ground, which is below the reference, and the part operates in 3 phase mode.
PHASE COUNT TABLE
Number
of Phases
Programming Pins (CSNx)
What to do with Unused Pins
3
All CSN pins connected normally
No unused pins
2
Tie CSN2 to VCC through 2 kW;
CSN3, CSN1 connected normally
Tie CSP2 to ground;
Float PWM2
1
Tie CSN3 to VCC through 2 kW;
CSN1 connected normally
Tie CSN2, CSP2 & CSP3 to ground;
Float PWM2, PWM3 & OD#
BOOT Voltage Programming
The NCP81105 has a VBOOT voltage register that can be externally programmed. The Boot voltage for the NCP81105 is
set using the VBOOT pin on power up. A 10 mA current is sourced from the VBOOT pin into an external resistance connected
to ground, and the resulting voltage is measured. This is compared with the thresholds in the table below and the corresponding
value is placed in the VBOOT register (26h). This value is set on power up and cannot be changed after the initial power up
sequence is complete.
BOOT VOLTAGE TABLE
Resistance
Boot Voltage
≤30.1k
0V
49.9k
1.65 V
69.8k
1.70 V
Open
1.75 V
Addressing the NCP81105
The NCP81105 has fixed SVID device address 0000.
Remote Sense Amplifier
A high performance, high input impedance, differential amplifier is provided to accurately sense the output voltage of the
regulator. The VSP and VSN inputs should be connected to the regulator’s output voltage sense points. The remote sense
amplifier takes the difference of the output voltage with the DAC voltage and adds the droop voltage and a voltage to bias the
output above ground.
V DIFFOUT + ǒV VSP * V VSNǓ ) ǒ1.3 V * V DACǓ * ǒV DROOP * V CSREFǓ
V DROOP + V CSCOMP
Droop Gain Scaling (see the Droop Gain Table)
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NCP81105, NCP81105H
High Performance Voltage Error Amplifier
The Remote Sense Amplifier output is applied to a Type 3 compensation network formed by the error amplifier, external
tuning components, and internal integrator. The non−inverting input of the error amplifier is connected to the same reference
voltage used to bias the Remote Sense Amplifier output. The integrating function of the Type 3 feedback compensation is
performed internally and does not require external capacitor Cf1 (see below).
Cf
Rin1
Rf
Rin2
Vbias
Cf1
COMP
+
_
Cin
ERROR
Figure 12. Traditional Type 3 External Compensation
Cf
Rin1
Rin2
Rf
+
_
Cin
Vbias
COMP
ERROR
Figure 13. NCP81105 Modified Type 3 External Compensation
Initial tuning should be based on traditional Type 3 compensation. When ideal Type 3 component values have been
determined, the closest setting for the internal integrator is given by the following equation:
INT_SETTING + 4.83
10 −12
Rf
Rin1
CF1;
Rf & Rin1 in Ohms , Cf1 in nF
The internal integrator is programmed using the INT_SEL pin according to the following table:
INTEGRATOR TABLE
RINT_SEL
INT_SETTING
10k
1
22k
2
36k
4
51k
8
68k
10
91k
12
120k
16
160k
32
220k
64
Recalculation of the initial tuning should be performed using the Cf1 value given by the Cf1 equation below in order to
determine whether readjustment of other components would provide more optimal compensation.
Cf1 (nF) + 2.07
10 5
INT_SETTINGń(Rf
Rin1)
If an acceptable tuning cannot be produced by the closest Equivalent Type 3 Cf1, then re−optimization should be tried with
a different internal integrator setting.
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NCP81105, NCP81105H
Differential Current Balance Amplifiers
RCSN
R CSN +
L PHASE
CSNx
CSPx
Each phase has a low offset differential amplifier to sense the current of that phase in order to balance current. The CSNx
and CSPx pins are high impedance inputs, but it is recommended that the external filter resistor RCSN not exceed 10 kW to
avoid offset due to leakage current. It is also recommended that the voltage sense element be no less than 0.5 mW for best current
balance. The external filter RCSN and CCSN time constant should match the inductor L/DCR time constant, but fine tuning
of this time constant is not required.
CCSN
SWNx
VOUT
DCR
C CSN * DCR
1
LPHASE
2
Figure 14.
The individual phase current signals are combined with the COMP and ramp signals at each PWM comparator input. In this
way, current is balanced via a current mode control approach.
Total Current Sense Amplifier
The NCP81105 uses a patented approach to sum the phase currents into a single, temperature compensated, total current
signal. This signal is then used to produce the output voltage droop, monitor total output current, and shut off switching if
current exceeds the set limit.
The Rref resistors average the voltages at the output sides of the inductors to create a low impedance reference voltage at
CSREF. The Rph resistors sum currents from the switchnodes to the virtual CSREF potential created at the CSSUM pin by
the amplifier. The total current signal at the amplifier output is the difference between CSCOMP and CSREF. The amplifier
lowpass filters and amplifies the voltage across the inductors to extract only the voltage across the inductor series resistances
(DCR).
CSN1
Cref
CSN2 Rref1
CSN3 Rref2
CSREF
SWN1 Rref3
CSSUM
CSCOMP
SWN2 Rph1
Ccs1
SWN3 Rph2
Ccs2
Rph3
RCS2
RCS1
Rth
Figure 15.
The equation for the DC total current signal is:
Rcs1*Rth
V CSCOMP−CSREF + −
Rcs2 ) Rcs1)Rth
Rph
* ǒIout Total * DCRǓ
Set the DC gain by adjusting the value of the Rph resistors to make the ratio of total current signal to output current equal
to the desired loadline. The Rph resistor value must be high enough to keep Rph current below 0.5 mA when switchnodes are
at nominal input voltage. If the voltage from CSCOMP to CSREF at ICCMAX is less than 100 mV, increase the gain of the
CSCOMP amp by a multiple of 2 until it is at or above 100 mV, and insert the resistor between the DGAIN pin and ground
that results in the correct loadline. See the Droop Gain Table. This is recommended to provide a high enough total current signal
to avoid impacts of offset voltage on current monitoring and the overcurrent shutdown threshold.
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NCP81105, NCP81105H
An NTC thermistor (Rth) in the feedback network placed near the Phase 1 inductor senses the inductor temperature and
compensates both the DC gain and the filter time constant for the DCR change with temperature. The values of Rcs1 and Rcs2
are set based on the effect of temperature on both the thermistor and inductor. The thermistor should be placed near the Phase
1 inductor so that it measures the temperature of the inductor providing current in the PS1 power mode.
The pole frequency (FP) of the CSCOMP filter should be set equal to the zero frequency (FZ) of the output inductor. This
causes the total current signal to contain only the component of inductor voltage caused by the DCR voltage, and therefore to
be proportional to inductor current. Connecting Ccs2 in parallel with Ccs1 allows fine tuning of the pole frequency using
commonly available capacitor values. It is best to perform fine tuning during transient testing.
FZ +
FP +
DCR@25° C
2 * PI * L Phase
1
2 * PI * ǒRcs2 )
Rcs1*Rth@25° C
Rcs1)Rth@25° C
Ǔ * (Ccs1 ) Ccs2)
Programming the Loadline (Droop Gain)
An output loadline is a power supply characteristic wherein the regulated (DC) output voltage decreases proportional to load
current. This characteristic reduces the amount of output capacitance needed to minimize output voltage variation during load
transients that exceed the speed of the regulation loop. In the NCP81105, a loadline is produced by adding a signal proportional
to output load current to the output voltage feedback signal − thereby satisfying the voltage regulator at an output voltage
reduced in proportion to load current.
The loadline is programmed by the combined gains of the Total Current Sense Amplifier and the gain from the output of
this amplifier to the input of the Remote Sense Amplifier. The latter gain is referred to as Droop Gain Scaling, and has four
possible values programmed by the value of resistance connected from the DGAIN pin to ground. For systems with full load
output voltage droop greater than 100 mV, the Droop Gain Scaling can be 100%. Other systems should use lower Droop Gain
Scaling and correspondingly higher Total Current Sense Amplifier gain, such that at full load the CSCOMP to CSREF voltage
is 100 mV or greater. The following table shows the DGAIN resistances required to program different Droop Scalings.
Droop Gain Table
RDGAIN
Droop Gain Scaling
Effect
≤10k
100%
Droop equals the CSCOMP to CSREF voltage
25k
50%
Droop equals half of the CSCOMP to CSREF voltage
45k
25%
Droop equals one quarter of the CSCOMP to CSREF voltage
w70k
0%
Zero milliohm loadline (no loadline)
Programming the Current Limit
The current limit thresholds are programmed with a resistor between the ILIM and CSCOMP pins. The ILIM pin voltage
is a buffered replica of the CSREF voltage. The ILIM current is mirrored internally to the current limit comparators and to IOUT
(increased by the IOUT Current Gain). The 100% current limit trips if ILIM current exceeds the Delayed Shutdown Threshold
for the Delayed Shutdown Time. Current limit trips with minimal delay if ILIM current exceeds the Immediate Shutdown
Threshold. Set the value of the current limit resistor based on the CSCOMP−CSREF voltage as shown below.
Rcs1*Rth
R LIMIT +
* ǒIout LIMIT * DCRǓ
Rcs2 ) Rcs1)Rth
Rph
I DS
or R LIMIT +
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V CSCOMP−CSREF@ILIMIT
I DS
NCP81105, NCP81105H
Rth
Rcs2
SWN1
SWN2
SWN3
CSN1
CSN2
CSN3
Ccs1
Rph2
Rph3
Rcs1
Ccs2
Rph1
_
CSSUM
CONTROLLER
CSCOMP
+
CSREF
Rref1
SCALING
DGAIN
Rdgain
Rref2
Rref3
to Remote
Sense Amplifier
Cref
ILIM
Rilim
buffer
IOUT
Current
Mirror
Riout
Current Limit
Comparators
Figure 16.
Programming IOUT
The IOUT pin sources a current equal to the ILIM current gained by the IOUT Current Gain. The voltage on the IOUT pin
is monitored by the internal A/D converter and should be scaled with an external resistor to ground such that a load equal to
ICCMAX generates a 2 V signal on IOUT. A pull−up resistor to 5 V VCC can be used to offset the IOUT signal positive if
needed.
V DIMAX * R LIMIT
R IOUT +
ȡ
*ȧ
Ȣ
R
AI IOUT
)
R CS1*Rth
ȣ* Iout
ȧ
Ȥ
CS2 R )Rth
CS1
Rph
ICC_MAX * DCR
Programming ICC_MAX
The SVID interface conveys the platform ICC_MAX value to the CPU from register 21h. A resistor to ground on the
IMAX pin programs this register at the time the part in enabled. Current is sourced from this pin to generate a voltage on the
program resistor. The value of the register is 1 A per LSB and is set by the equation below. The resistor value should be no less
than 10k.
ICC_MAX 21h +
R * I IMAX * 256 A
V IMAXFS
Improving Dynamic VID (DVID) Settling Time
Upon each increment of the internal DAC following a DVID UP command, the NCP81105 outputs a pulse of current from
the VSN pin. If a parallel RC network is inserted into the path from VSN to VSS_SENSE, the voltage between VSP and VSN
is temporarily decreased, which causes the output voltage during DVID to be regulated slightly higher to compensate for the
response of the Droop function to output current flowing into the output capacitors.
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NCP81105, NCP81105H
VCC_SENSE
VSP
VSS_SENSE
VSN
RFF
CFF
+
_
REMOTE SENSE
AMPLIFIER
CONTROLLER
+_
DVID UP
INCREMENT
CURRENT
PULSES
DAC
DAC
VSN
Figure 17.
The R and C values should be chosen according to the following equations:
R FF +
Loadline * Cout
1.35 * 10 −9
C FF +
200
R FF
W
nF
Programming TSENSE
A temperature sense input is provided. A precision current is sourced out the output of the TSENSE pin to generate a voltage
on the temperature sense network. The voltage on the temperature sense input is sampled by the internal A/D converter and
then digitally converted to temperature and stored in SVID register 17h. A 220k NTC similar to the Murata
NCP15WM224E03RC should be used.
Precision Oscillator
A programmable precision oscillator is provided to control the switching frequency of each phase. The oscillator serves as
the master clock to the ramp generator circuits, which each run at the same frequency. The ROSC pin sources a current into
an external programming resistor. The voltage present at the ROSC pin is read by the internal ADC and used to set the frequency
according to the following table.
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NCP81105, NCP81105H
SWITCHING FREQUENCY TABLE (PS0)
ROSC
(kW)
Frequency
(kHz)
ROSC
(kW)
Frequency
(kHz)
ROSC
(kW)
Frequency
(kHz)
ROSC
(kW)
Frequency
(kHz)
10
246
37.4
445
75
656
127
1132
13.3
272
42.2
468
80.6
720
133
1185
16.2
298
46.4
492
86.6
785
143
1236
19.6
323
49.9
515
93.1
845
150
1285
23.2
348
54.9
538
100
906
162
1333
26.1
373
60.4
561
105
966
169
1377
29.4
397
64.9
584
113
1023
187
1426
33.2
421
69.8
605
121
1078
210
1475
Ramp Generator Circuits
In PS0, the oscillator controls the frequency of triangle ramps for the pulse width modulator. Ramp amplitude depends on
the VRMP pin voltage in order to provide input voltage feed forward compensation. The ramps have equal phase displacement
with respect to each other.
Ramp Feed−Forward Circuit and Ramp UVLO
The ramp generator includes voltage feed−forward control that varies the ramp magnitude proportional to the VRMP pin
voltage. The PWM ramp voltage is changed according to the following:
Vin
Vramp_pp V RAMPpk+pkPP + 0.1 * V VRMP
Comp−IL
Duty
The VRMP pin also has a UVLO function. The VRMP UVLO is only active after the controller is enabled. The VRMP pin
is a high impedance input when the controller is disabled or put into PS4. The resistance of an RC filter at the VRMP pin should
not exceed 10 kW.
PWM Comparators
The noninverting input of each comparator (one for each phase) is connected to the summation of the output of the error
amplifier (COMP) and each phase current (IL * DCR * Phase Balance Gain Factor). The inverting input is connected to the
triangle ramp voltage of that phase. The output of the comparator generates the PWM output.
During steady state PS0 operation, the main rail PWM pulses are centered on the valley of the triangle ramp waveforms and
both edges of the PWM signals are modulated. During a transient event, the duty cycle can increase rapidly as the error amp
signal increases with respect to the ramps, to provide a highly linear and proportional response to the step load.
Power State 1 (PS1)
The NCP81105 supports PS1 by providing the OD# output. When the OD# output is connected to the phase 2 and 3 DrMOS
ZCD inputs, the PS1 state causes the NCP81105 to send low levels on OD#, PWM2 and PWM3, causing the power stages of
phases 2 and 3 to be tri−stated (both high and low side FETs off). The modulation mode changes from constant−frequency
dual−edge modulation to Constant ON Time modulation.
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NCP81105, NCP81105H
PS0
PS1
(PWM2 & PWM3 ACTIVE)
PS2
(PWM2 & PWM3 LOW)
(PWM2 & PWM3 LOW)
PS1
(PWM2 & PWM3 LOW)
PS0
(PWM2 & PWM3 ACTIVE)
OD#
PWM1
DRVH1−SW1
PH1
INDUCTOR
CURRENT
0
AVERAGE PHASE CURRENT
SMOD
DRVL1
Figure 18.
Zero Cross Detect (ZCD) Enabling (PS2)
The NCP81105 supports the DrMOS ZCD function (diode emulation) by providing the SMOD output.
When the controller receives an SVID command asking for PS2 mode (lighter load current condition), PWM2, PWM3 and
OD# are held low, causing the power stages of phases 2 and 3 to be inactive (open circuit). When the NCP81105 detects that
inductor current is no longer positive, SMOD is pulled LOW to enable the DrMOS diode emulation function, and the PWM1
output continues full−range two−state outputs (from 0 V to the VCC rail).
For DrMOS without a ZCD function, when SMOD goes low in response to the NCP81105 detecting that inductor current
is no longer positive, DrMOS synchronous rectification is immediately disabled.
For PS0 and PS1 states, SMOD stays HIGH, disabling the DrMOS ZCD function.
Protection Features
Input Under Voltage Protection
NCP81105 monitors the VCC supply voltage at the VCC pin and the VDC power source at the VRMP pin in order to provide
under voltage protection. If either supply dips below their threshold, the controller will shut down the outputs. Upon recovery
of the supplies, the controller reenters its startup sequence, and soft start begins.
Soft Start
Soft start is implemented internally. A digital counter steps the DAC up from zero to the target voltage based on the
predetermined slew rate in the spec table. The CSN2 and CSN3 pins will start out applying a test resistance to collect data on
phase count. After the configuration data is collected, the controller is enabled and sets the OD# and SMOD signals low to force
the drivers to stay in diode mode. DRVON will then be asserted to enable the drivers. A period of time after the controller senses
that DRVON is high, the COMP pin is released to begin soft−start. The DAC ramps from zero to the target DAC code and the
PWM outputs will begin to fire. SMOD will go high when the first PWM1 pulse is produced to preclude discharge of a
pre−charged output. Upon PWM2 or PWM3 going high for the first time, OD# is set high.
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NCP81105, NCP81105H
Soft−Start Sequence
VCC
TA
EN
DrMOS Enabled
DRON
Softstart Delay
DAC
COMP
PWM1
SMOD
PWM2
OD#
VOUT
Figure 19.
Over Current Latch−Off Protection
The NCP81105 provides two different types of current limit protection. During normal operation a programmable total
current limit is provided that is scaled back during reduced−phase, power saving operation. This limit is programmed with a
resistor between the CSCOMP and ILIM pins. The current from the ILIM pin to this resistor is then compared to internal IDS
and IIS currents. If the ILIM pin current exceeds the IDS level, an internal latch−off timer starts. When the timer expires, the
controller shuts down if the fault is not removed. If the current into the pin exceeds IIS, the controller will shut down
immediately. To recover from an OCP fault, the EN pin must be cycled low.
The over−current limit is programmed by a resistor from the ILIM pin to the CSCOMP pin. The resistor value can be
calculated by the following equation:
R ILIM +
V CSCOMP * V CSREF
I DS
Output Under Voltage Monitor
The output voltage is monitored by a dedicated differential amplifier. If the output falls below target by more than the “Under
Voltage Threshold Below DAC−Droop”, the UVL comparator sends the VR_RDY signal low.
Over Voltage Protection
During normal operation the output voltage is monitored at the differential inputs VSP and VSN. If the output voltage
exceeds the DAC voltage by the “Over Voltage Threshold Above DAC”, PWMs will be forced low, and the SMOD pin will
also go low when the voltage drops below that threshold. After the OVP trip the DAC will ramp slowly down to zero to avoid
a negative output voltage spike during shutdown. If the DAC + OVP Threshold drops below the output, SMOD will again go
high, and will toggle between low and high as the output voltage follows the DAC + OVP Threshold down. When the DAC
gets to zero, the PWMs will be held low and the SMOD and DRVON pin voltages will remain high. To reset the part, the EN
pin must be cycled low. During soft−start, the OVP threshold is set to the Absolute Over Voltage Threshold. This allows the
controller to start up without false triggering the OVP if residual voltage from a prior period of operation is already present
at the output.
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NCP81105, NCP81105H
OVP Threshold Behavior − Normal PS0 and PS1 Operation
VSP−VSN
VSP−VSN
DAC
DAC
Fault
(VSP short
OVP
to ground) Triggered
Fault
(VSP short
OVP
to ground) Triggered
Rampdown
Latched
Rampdown
Latched
DAC
DAC
Latch Off
Latch Off
PWM
PWM
SMOD
SMOD
OD#
OD#
PS0
PS1
Figure 20.
OVP Threshold Behaviour During Soft−start into Pre−charged Output
OVP Threshold during Soft−start
OVP Threshold after Soft−start
VSP−VSN (precharged)
Target VID
Reached
0
DAC
PWM
SMOD
OD#
Figure 21.
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NCP81105, NCP81105H
Printed Circuit Board Layout Notes
The NCP81105 has differential voltage and current monitoring. This improves signal integrity and reduces noise issues
related to layout for easy design use. To ensure proper function there are some general PCB layout rules to follow:
Careful layout for per−phase and total current sensing are critical for jitter minimization, accurate current balancing and
limiting, and IOUT reporting. Give the first priority in component placement and trace routing to per phase and total current
sensing circuits. The per phase inductor current sense RC filters should always be placed as close to the CSN and CSP pins
on the controller as possible. The filter cap from CSCOMP to CSSUM should also be close to the controller. The temperature
compensating thermistor should be placed as close as possible to the Phase 1 inductor. The wiring path between Rcs2 and Rphx
should be kept as short as possible and well away from switch node lines. The above layout notes are shown in the following
diagram:
CONTROLLER
43
_
42
+
40
_
34
+
35
_
38
+
39
CSCOMP
CSSUM
Ccs2
KEEP THIS PATH AS SHORT
AS POSSIBLE, AND WELL AWAY
FROM SWITCHNODE LINES
CSREF
Rcs2
Ccs1
Rph1
Ccsp1 Rcsp1
PLACE AS CLOSE
AS POSSIBLE TO
PHASE 1 INDUCTOR
Rref2
TO INDUCTOR
SWITCHNODE
TERMINAL
TO INDUCTOR
VOUT TERMINAL
CSP2
CSN2
Rref1
Rth
TO INDUCTOR
SWITCHNODE
TERMINAL
TO INDUCTOR
VOUT TERMINAL
CSP1
CSN1
Rph2
Rcs1
Ccsp2 Rcsp2
PER PHASE CURRENT SENSE
RC SHOULD BE PLACED
CLOSE TO CSPx PINS
Figure 22.
Place the VCC decoupling caps as close as possible to the controller VCC pin. For any RC filter on the VCC pin, the resistor
should be no higher than 5 W to prevent large voltage drop.
The small feedback cap from COMP to FB should be as close to the controller as possible. Keep the FB traces short to
minimize their capacitance to ground.
ORDERING INFORMATION
Package
Shipping†
NCP81105MNTXG
QFN36
(Pb−Free)
5000 / Tape & Reel
NCP81105HMNTXG
QFN36
(Pb−Free)
5000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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35
NCP81105, NCP81105H
PACKAGE DIMENSIONS
QFN36 5x5, 0.4P
CASE 485CC
ISSUE O
PIN ONE
LOCATION
ÉÉÉ
ÉÉÉ
ÉÉÉ
L1
DETAIL A
ALTERNATE
CONSTRUCTIONS
E
EXPOSED Cu
TOP VIEW
DETAIL B
0.10 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
ÉÉÉ
ÉÉÉ
0.15 C
0.15 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
L
L
A
B
D
MOLD CMPD
DETAIL B
(A3)
ALTERNATE
CONSTRUCTION
A
0.08 C
A1
SIDE VIEW
NOTE 4
C
0.10
M
SEATING
PLANE
RECOMMENDED
SOLDERING FOOTPRINT*
C A B
5.30
D2
DETAIL A
K
10
MILLIMETERS
MIN
MAX
0.80
1.00
−−−
0.05
0.20 REF
0.15
0.25
5.00 BSC
3.40
3.60
5.00 BSC
3.40
3.60
0.40 BSC
0.35 REF
0.30
0.50
−−−
0.15
36X
0.63
3.64
0.10
19
M
C A B
1
E2
36X
L
5.30
3.64
1
36
e
BOTTOM VIEW
36X
b
0.10
M
C A B
0.05
M
C
PKG
OUTLINE
NOTE 3
0.40
PITCH
36X
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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