Intersil ISL9220A Switching charger for 1-cell and 2-cell li-ion battery Datasheet

Switching Charger for 1-Cell and 2-Cell Li-ion Batteries
ISL9220, ISL9220A
Features
The ISL9220, ISL9220A is a cost-effective and versatile battery
charger for 1-cell and 2-cell Li-ion and Li-Polymer based portable
applications.
• Highly Integrated Battery Charger IC
• Charges 1- and 2-Cell Li-ion or Li-Polymer Batteries
• Up to 2A Charge Current
The device features synchronous PWM technology, maximizing
power efficiency, thus minimizing charge time and heat. The
1.2MHz switching frequency allows use of small external
inductors and capacitors.
• Synchronous Buck Topology with Integrated Power FETs
• 1.2MHz Switching Frequency
• 0.5% Charge Voltage Accuracy
A simple charge current programming method is provided.
External resistors program the fast charge and end-of-charge
currents.
• Programmable Input Current Limit with One External Resistor
• Thermistor Interface for Battery Detection and Temperature
Qualified Charging
The two status outputs can be used to drive LEDs, or can be
connected to host processor.
• Two Status Outputs
A programmable charge timer provides the ability to detect
defective batteries, and provides a secondary method of
detecting charge termination.
• Programmable Charge Safety Timer
• Short-Circuit and Thermal Protection
A thermistor interface is provided for battery presence detection,
and for temperature qualified charging conditions.
• Small 4mmx4mm TQFN Package
Additional features include preconditioning of an over-discharged
battery, automatic recharge, and thermally enhanced QFN
package.
Related Literature
• -40°C to +85°C Operating Temperature Range
• TB363 “Guidelines for Handling and Processing Moisture
Sensitive Surface Mount Devices (SMDs)”
Applications
• TB379 “Thermal Characterization of Packaged Semiconductor
Devices”
• PDAs and Smart Phones
• MP3 and Portable Media Players
• TB389 “PCB Land Pattern Design and Surface Mount
Guidelines for QFN Packages”
• Handheld GPS Devices
• AN1589, “ISL9220IRTZEVAL1Z (1-cell), ISL9220AIRTZEVAL1Z
(2-cell) Evaluation Board”
• Digital Still Cameras
• Industrial Handheld Scanners
Pin Configuration
16 PGND
17 VBIAS
18 RTH
19 TIME
20 STAT1
ISL9220, ISL9220A
(20 LD TQFN)
TOP VIEW
STAT2 1
15 PGND
EN 2
14 SW
PAD
(AGND)
AGND 3
1
VIN 10
11 VIN
CISN 9
ISET2 5
CISP 8
12 VHI
ISNS 7
ISET1 4
VBAT 6
February 16, 2012
FN6936.3
13 SW
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010-2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL9220, ISL9220A
Pin Descriptions
PIN
SYMBOL
DESCRIPTION
1
STAT2
Open-drain indication pin. In conjunction with STAT1 this pin provides a unique indication for each charging state of the
cycle. This pin is capable to sink 10mA minimum current to drive an LED.
2
EN
IC enable input. Drive this pin to logic LO to enable the charger. Drive this pin to logic HI to disable the charger. Do not
leave this pin floating.
3
AGND
Analog ground.
4
ISET1
Charge current programing pin. Connect a resistor between this pin and the GND pin to set the charge current.
5
ISET2
End-of-charge current programing pin. Connect a resistor between this pin and the GND pin to set the end-of-charge
current.
6
VBAT
Battery connection pin. Connect this pin to the battery. A 10µF or larger X5R ceramic capacitor is recommended for
decoupling and stability purposes.
7
ISNS
Output current sense pin. Connect a current sense resistor from this pin to VBAT. No decoupling capacitor is needed at
this pin.
8
CISP
Input current sense positive connection pin. Connector a sense resistor from this pin the CISN.
9
CISN
Input current sense negative connection pin. Connector a sense resistor from this pin the CISP.
10, 11
VIN
Input supply voltage. Connect a 4.7µF ceramic capacitor from VIN to PGND.
12
VHI
High-side NMOS FET gate drive supply pin. Connect the anode of a Schottky diode to VBIAS pin and the cathode to VHI
pin. Connect a 0.1µF capacitor from VHI pin to SW pin. See “Typical Application Diagrams” on page 6.
13, 14
SW
Switch node and inductor connection pin.
15, 16
PGND
Power ground.
17
VBIAS
Internal 5V regulator output. Connect a 0.1µF ~ 4.7µF ceramic capacitor from this pin to AGND. A typical 1µF ceramic
capacitor is recommended.
18
RTH
Input for an external NTC thermistor for battery temperature monitoring.
19
TIME
The TIME pin sets the oscillation period by connecting a timing capacitor between this pin and GND. The oscillator also
provides a time reference for the charger. The timer function can be disabled by connecting the TIME pin to GND. If the
timer is disabled, there will be no timeout function for any operation mode including trickle charge and fast charge
modes.
20
STAT1
Open-drain indication pin. In conjunction with STAT2 this pin provides a unique indication for each charging state of the
cycle. This pin is capable to sink 10mA minimum current to drive an LED.
EPAD
Exposed pad. Connect to GND electrically. Thermally, connect as much as possible copper to this pad either on the
component layer or other layers through thermal vias to enhance the thermal performance.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART MARKING
NUMBER
OF CELLS
TEMP. RANGE
(°C)
PACKAGE
Tape & Reel
(Pb-free)
PKG.
DWG. #
ISL9220IRTZ-T
92 20IRTZ
1
-40 to +85
20 Ld 4x4 TQFN
L20.4x4E
ISL9220IRTZ-T7A
92 20IRTZ
1
-40 to +85
20 Ld 4x4 TQFN
L20.4x4E
ISL9220AIRTZ-T
922 0AIRTZ
2
-40 to +85
20 Ld 4x4 TQFN
L20.4x4E
ISL9220AIRTZ-T7A
922 0AIRTZ
2
-40 to +85
20 Ld 4x4 TQFN
L20.4x4E
ISL9220IRTZEVAL1Z
Evaluation Board
ISL9220AIRTZEVAL1Z
Evaluation Board
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pbfree products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL9220, ISL9220A.For more information on MSL please see techbrief
TB363.
2
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Absolute Maximum Ratings
Thermal Information
VIN, CISP, CISN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18V
SW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.7V to 18V
VHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 24V
VBAT, ISNS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 10V
ISET1, ISET2, RTH, VBIAS, STAT1, STAT2, EN . . . . . . . . . . . . . -0.3V to 5.5V
TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V
Input Current (VIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.0A
Output Current (SW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2A
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2500V
Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 175V
Charged Device Model (Tested per JES22-C101D). . . . . . . . . . . . . 1500V
Latch-Up
(Tested per JESD-78B; Class 2 (+85°C), Level A) . . . . . . . . . . . . . 100mA
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
4x4 QFN Package (Notes 4, 5) . . . . . . . .
40
4.3
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Supply Voltage, VIN
ISL9220 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V to 14V
ISL9220A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 14V
Programmable Charge Current . . . . . . . . . . . . . . . . . . . . . . . . 200mA to 2A
Programmable Trickle Current . . . . . . . . . . . . . . . . . . . . . . 20mA to 200mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside.
Electrical Specifications
For ISL9220A, VIN = 12V.
PARAMETER
Typical specifications are measured at the following conditions: TA = +25°C; For ISL9220, VIN = 5V;
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
POWER-ON RESET
Rising VIN Threshold
VPOR_R
3.4
3.6
3.8
V
Falling VIN Threshold
VPOR_F
2.2
2.4
2.6
V
ISL9220
-
95
150
mV
ISL9220A
-
170
300
mV
ISL9220
10
65
-
mV
ISL9220A
20
130
-
mV
10
15
mA
VIN - VBAT OFFSET VOLTAGE
Rising Offset Threshold
VOS_R
Falling Offset Threshold
VOS_F
SUPPLY CURRENT
VIN Pin Supply Current
ICC(VIN)
Battery Discharge Current
(Total of currents flowing into VBAT, ISNS,
SW pins)
IDIS
PGOOD = TRUE, EN = L (Note 6)
PGOOD = TRUE, EN= H (Note 6)
VIN = 5V to 12V
-
-
0.5
mA
VIN < VPOR OR EN = H
2V < VBAT < 11V
-
2
5
µA
OVERVOLTAGE PROTECTION
Input OVP Rising Threshold
VIN_OVPR
14.5
15.0
15.5
V
Input OVP Falling Threshold
VIN_OVPF
14.0
14.5
15.0
V
OUTPUT CURRENT
Fast Charge Current Accuracy
ICHG
RSNS = 0.039Ω
RISET1 = 49.9kΩ (Nominal IOUT = 1000mA)
-10
-
10
%
Charge Termination Current Accuracy
IMIN
RSNS = 0.039Ω
RISET2 = 300kΩ (Nominal IMIN = 100mA)
-35
-
35
%
-
12
-
ms
Charge Termination Detection Deglitch
Time
3
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Electrical Specifications
For ISL9220A, VIN = 12V. (Continued)
Typical specifications are measured at the following conditions: TA = +25°C; For ISL9220, VIN = 5V;
PARAMETER
SYMBOL
Level 1 Pre-Charge Current Range (Linear
mode)
IPCHG1
VBAT < VPCHG1
Level 2 Pre-Charge Current Accuracy
IPCHG2
RSNS = 0.039Ω
RISET2 = 300kΩ (Nominal IPCHG = 140mA)
Level 1 Pre-Charge Threshold Voltage
VPCHG1
Level 2 Pre-Charge Threshold Voltage
VPCHG2
TEST CONDITIONS
MIN
TYP
MAX
UNITS
25
50
90
mA
-
±20
-
%
ISL9220
2.42
2.5
2.56
V
ISL9220A
4.8
5.0
5.3
V
ISL9220
2.9
3.0
3.1
V
ISL9220A
5.75
6.0
6.25
V
ISL9220
3.85
4.0
4.1
V
ISL9220A
7.75
8.0
8.25
V
RECHARGE THRESHOLD
Recharge Voltage Threshold
VRECHG
TEMPERATURE MONITORING
High Battery Temperature Threshold
V TMIN
Specified as % of VBIAS
30
35
40
%
Low Battery Temperature Threshold
VTMAX
Specified as % of VBIAS
70
75
80
%
Battery Removal Threshold
VRMV
Specified as % of VBIAS
90
95
-
%
Thermistor Disable Threshold
VT_DIS
Temperature Threshold Hysteresis
VT,HYS
Temperature Detection Deglitch Time
-
250
-
mV
-
180
-
mV
-
12
-
ms
THERMAL PROTECTION
Thermal Shutdown Threshold
TFD
-
140
-
°C
Thermal Hysteresis
THYS
-
30
-
°C
VBIAS OUTPUT
Output Voltage
VBIAS
5.3 < VIN < 15V, IVBIAS = 5mA
4.70
5.0
5.25
V
Output Current
IBIAS
5.3 < VIN < 15V
-
-
5
mA
tOSC
CTIME = 15nF
-
3.0
-
ms
OSCILLATOR
Oscillation Period
SWITCHING CHARGER AC CHARACTERISTICS
Switching Frequency
FOSC
1.02
1.2
1.38
MHz
Maximum Duty Cycle
DMAX
-
96
-
%
Minimum Duty Cycle
DMIN
-
0
-
%
Cycle-By-Cycle Current Limit
ILIM
-
3.0
-
A
High-Side MOSFET ON-Resistance
rDS(ON), HS1
-
112
-
mΩ
Combined High Side ON-Resistance
(Note 7)
rDS(ON), HS2
-
224
450
mΩ
-
72
180
mΩ
-
1.0
5.0
µA
SWITCHING CHARGER DC CHARACTERISTICS
Low-Side MOSFET ON-Resistance
Measured between VIN and SW pins
rDS(ON), L
High-Side Path Reverse Leakage Current
IREV
Charger Output Voltage
VCHG
4
VIN = 0V, VSW = 15V
ISL9220, IOUT = 100mA, TA = +25°C
4.179
4.2
4.221
V
ISL9220A, IOUT = 100mA, TA = +25°C
8.358
8.4
8.442
V
ISL9220, IOUT = 100mA
4.158
4.2
4.242
V
ISL9220A, IOUT = 100mA
8.316
8.4
8.484
V
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Electrical Specifications
For ISL9220A, VIN = 12V. (Continued)
PARAMETER
Typical specifications are measured at the following conditions: TA = +25°C; For ISL9220, VIN = 5V;
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
100
200
µA
88
100
112
mV
INPUT CURRENT SENSE AMPLIFIER
Input Bias Current at CSIP and CSIN, Pin
(Charger Enabled)
IISIP_ON
EN = L
Input Current Limit Threshold
IIN_LIM
CSIP-CSIN
OUTPUT CURRENT SENSE AMPLIFIER
Input Bias Current at ISNS Pin,
(Charger Enabled)
IISNS_ON
EN = L
-
100
200
µA
Input Bias Current at ISNS Pin,
(Charger Disabled)
IISNS_OFF
EN = H
-
-
1
µA
Input Bias Current at VBAT Pin,
(Charger Enabled)
IVBAT_ON
EN = L
-
75
100
µA
Input Bias Current at VBAT Pin,
(Charger Disabled)
IVBAT_OFF
EN = H
-
-
1
µA
EN Pin Logic High
1.3
-
-
V
EN Pin Logic Low
-
-
0.4
V
LOGIC INPUT AND OUTPUTS
STAT1, STAT2 Sink Current When ON
Pin Voltage = 0.4V
10
-
-
mA
STAT1, STAT2 Leakage Current When OFF
Pin Voltage = 4.2V
-
-
1
µA
NOTES:
6. PGOOD is defined as when VIN and VBAT meet all these conditions: VIN > VPOR, VIN - VBAT > VOS, VIN < VIN(OVP).
7. Limits should be considered typical and are not production tested.
5
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Typical Application Diagrams
1-Cell Application
VBIAS
VHI
4.5V TO 14V
AC
ADAPTER
50m
SW
4.7µF
VIN
0.1µF
10µH
22
ISL9220
ISNS
CISN
10nF
1µF
40m
VBAT
CISP
VBIAS
10µF
1-CELL
LI+
BATTERY
RTH
STAT1
STAT2
PGND
EN
AGND
ISET1
ISET2
TIME
2-Cell Application
VBIAS
0.1µF
VHI
9V TO 14V
SW
4.7µF
VIN
0.1µF
10µH
ISL9220A
22
50m
10nF
ISNS
CISN
40m
VBAT
CISP
VBIAS
RTH
STAT1
10µF
2-CELL
LI+
BATTERY
STAT2
EN
6
PGND
ISET1
AGND
AC
ADAPTER
ISET2
TIME
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Block Diagram
GATE
DRIVE
VREF AND BIAS
GENERATION
REF1V
VREF
1µF
VBIAS
VIN
R ICS
22
4.7µF
10nF
CISN
INPUT
CURRENT
SENSE AMP
CISP
VHI
VREF
VBAT
CELLS
CHGEN
ISET1
0.1µF
SW
PWM
CONTROLLER
CHG
CURR
PROG
ISET2
PGND
PRECHG
10µH
CHGEN
PRECHG
PGOOD
EN
600k
DISABLE
ENABLE
STAT1
STAT2
CONTROL
LOGIC
AND
CHARGE
STATE
MACHINE
OVFAULT
EOCQUAL
GOFAST
BATPRES
NOTHERM
TEMPOK
ISNS
OUTPUT
CURRENT
SENSE AMP
VBAT
CELLS
OVFAULT
EOCQUAL
GOFAST
V_BATTERY
COMPARATORS
VBIAS
BATPRES
NOTHERM
TEMPOK
RTH
COMPARATORS
TIMERST
SUSPEND
TIMEOUT
CHG TIMER
TIMERST
SUSPEND
TIMEOUT
Rsns
VBIAS
10µF
RTH
TIME
1-CELL
OR
2-CELL
LI+
BATTERY
AGND
7
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Typical Operating Conditions
CH4 = INDUCTOR CURRENT (500mA/DIV)
CH4 = INDUCTOR CURRENT (500mA/DIV)
CH1 = SW(5V/DIV)
CH1 = SW(5V/DIV)
FIGURE 2. PWM WAVEFORM IN TRICKLE MODE
FIGURE 1. PWM WAVEFORM IN CC MODE
95
95
VBAT = 8.2V
VBAT = 3.6V
90
EFFICIENCY (%)
EFFICIENCY (%)
90
VBAT = 4V
85
VBAT = 3V
80
VBAT = 7V
85
VBAT = 6V
80
75
75
70
70
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
CHARGE CURRENT (A)
2.2
FIGURE 3. EFFICIENCY vs LOAD 1-CELL (V IN = 5V, L = 10µH)
8
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
CHARGE CURRENT (A)
FIGURE 4. EFFICIENCY vs LOAD 2-CELL (VIN = 12V, L = 10µH
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Theory of Operation
VBIAS
The ISL9220, ISL9220A is an integrated charger optimized for
charging 1-cell and 2-cell Li-ion or Li-polymer batteries. It charges
a battery with constant current (CC) and constant voltage (CV)
profile. The typical charge profile is illustrated in Figure 5.
PRECHG
CC
CV
VBIAS
R1
BATTERY
CP1 REMOVAL
+
V RMV
UNDER
TEMP
V TMIN
CP2 -
OFF
RU
R2
To RTH
Pin
+
BATTERY
VOLTAGE
RTH
R3
Q1
OVER
TEMP
+
RT
R4
CP3 V TMAX
CHARGE
CURRENT
Q2
R5
AGND
EOC
DETECTION
FIGURE 6. THERMISTOR INTERNAL CIRCUIT
TYPICAL CHARGE PROFILE
FIGURE 5. TYPICAL CHARGE PROFILE
VTMIN (4.0V)
VTMIN- (3.5V)
RTH PIN
VOLTAGE
POR and Power-Good
The ISL9220, ISL9220A resets itself when VIN undergoes
transition from below VPOR to above VPOR threshold.
The ISL9220, ISL9220A has an internal PGOOD signal. Charging
is prohibited if PGOOD statement is not true. See Note 6 in the
“Electrical Specifications” table for the definition of PGOOD.
Valid Charge Temperatures
An external NTC thermistor can be used to provide temperaturequalified charging. The VBIAS supply is used as reference for the
internal comparators. Thus, it is important that the VBIAS supply
also be used to bias the external voltage divider comprised of
one or more fixed resistors and the thermistor. This scheme
allows the use of a wide variety of thermistors. The RTH
comparator block monitors the RTH pin voltage to determine if
the battery temperature is within safe charging limits.
The ISL9220, ISL9220A uses two comparators (CP2 and CP3) to
form a window comparator, as shown in Figure 6. When the NTC
pin voltage is “out of the window,” determined by the VTMIN and
VTMAX, the ISL9220, ISL9220A stops charging and indicate a
suspend condition. When the temperature returns to the set range,
the charger resumes charging. The two MOSFETs, Q1 and Q2,
produce hysteresis for both upper and lower thresholds. The
temperature window is shown in Figure 7 for a 0°C to +50°C
typical application using an industry standard type 103AT
thermistor.
The temperature qualification function can be disabled by
connecting the RTH pin to ground.
VTMAX+ (2.0V)
VTMAX (1.5V)
0V
UNDER
TEMP
OVER
TEMP
FIGURE 7. THRESHOLD VOLTAGES FOR 0°C to +50°C WINDOW
(VBIAS = 5.0V)
Battery Detection
The presence or absence of the external thermistor is used to
detect a battery.
When VRTH is greater than VRTH,PRES, i.e. when the RTH pin is not
connected to ground, battery detection is provided by the RTH
comparator block, as shown in Figure 6. With no battery connected, the
RTH pin is pulled to VBIAS by RU, and thus VRTH will exceed the
VRTH,NOBAT threshold. The internal battery presence signal is
deglitched with a 12ms deglitcher, to avoid false indication of battery
insertion or removal due to contact bounce or other noises.
Battery Precharge
When the charger is first enabled and no fault conditions are
detected, if the battery connecting to the charger is deeply
discharged, the charger will charge the battery in a reduced
current for the battery to recover.
If the battery voltage is less than the level 1 pre-charge voltage
(VPCHG1), the charger operates in LDO mode, with an output current
fixed at 50mA typical. In this mode, the output voltage can go to 0V. This
provides the ability to recover a battery that has entered a safety-circuit
undervoltage fault mode.
9
FN6936.3
February 16, 2012
ISL9220, ISL9220A
I PCHG1 = 50mA
(EQ. 1)
If battery voltage is between the level 1 pre-charge voltage
(VPCHG1) and level 2 pre-charge voltage (VPCHG2), the charger
operates in trickle mode, and uses the precharge current limit.
This precharge current is programmed by the resistor between
the ISET2 pin and ground. Note that this resistor also programs
the end-of-charge taper current threshold.
1638
I PCHG2 = --------------------------------------R ISET2 × R SNS
(EQ. 2)
( mA )
When the battery voltage exceeds the level 2 pre-charge voltage
threshold (VPCHG2), fast charging will commence. If this
threshold is not reached within the precharge timer period, a
TIME-OUT-FAULT condition is asserted, and the charger is
disabled.
Charge Safety Timer
An internal oscillator establishes a timing reference. The
oscillation period is programmable with an external capacitor at
the TIME pin, CTime, as shown in the “Typical Application
Diagrams” on page 6. The oscillator charges the timing capacitor
to 1.5V and then discharges it to 0.5V in one period, both with
10µA current. The period tOSC is calculated in Equation 3:
6
(EQ. 3)
( Sec )
Where CTime is in F.
A 1nF capacitor provides 0.2ms oscillation period. The allowable
range of CTime value is 100pF to 1µF, providing a programmable
charge safety-timeout range of about 1.4 minutes to almost 10
days.
Total charge time, excluding any time required for precharge, is
limited to a length of TIMEOUT. This can be calculated as
Equation 4:
TIMEOUT = 2
22
× t OSC
(EQ. 4)
( Sec )
Total charge time for battery precharge is limited to a length of
1/8 TIMEOUT. This can be calculated as Equation 5:
TIMEOUT ( PCHG ) = 2
19
× t OSC
( Sec )
(EQ. 5)
1170
I EOC = --------------------------------------R ISET2 × R SNS
(EQ. 7)
( mA )
Fast Charge
The fast charge current is programmed by the resistor between
the ISET1 pin and ground, and by the value of the RSNS resistor
(see Equation 6).
( mA )
A secondary charge termination method is provided via the
safety timer. The timeout period of this timer is programmable
via a single external capacitor between the TIME pin and ground.
To disable the charge safety timer, short the TIME pin to ground.
Charge Current Sensing
Charge current is sensed with an external current sense resistor.
A low-inductance, precision resistor should be used for accurate
charge current.
Input Current Sensing
Input current is sensed with an external sense resistor. A lowinductance, precision resistor should be used for accurate input
current limit.
The ISL9220, ISL9220A limits the battery charge current when
the input current limit threshold is exceeded. This allows the
most efficient use of AC-adapter power without overloading the
adapter output.
An internal amplifier compares the voltage between CSIP and
CSIN, and reduces the output current when this differential
voltage exceeds the threshold voltage. The effective input current
limit threshold is thus set by the value of the RICS resistor as
calculated by Equation 8.
0.1
I IN ( LIM ) = -----------R ICS
(EQ. 8)
(A)
Where RICS is in Ω.
A low pass filter is suggested to eliminate the switching noise, as
shown in the “Typical Application Diagrams” on page 6.
Status Outputs
TABLE 1. STAT1 AND STAT2 TRUE TABLE
The TIME pin can be grounded to disable the safety timer
functions if not needed.
1946
I CHG = --------------------------------------R ISET1 × R SNS
Charge current is continuously monitored. When the current falls
below the taper current threshold, charging will stop, and BATFUL
is asserted to indicate a successful charge completion. This taper
current threshold is programmed by a single external resistor
between ISET2 and ground as calculated in Equation 7.
Where RISET2 is in kΩ and RSNS is in Ω.
Where RISET2 is in kΩ and RSNS is in Ω.
t OSC = 0.2 × 10 × C Time
Charge Termination
STAT1
STAT2
L
L
Precharge, or fast charge in progress
CHARGING CONDITION
L
H
Charge Complete
H
L
Fault
H
H
Suspend
(EQ. 6)
Where RISET1 is in kΩ and RSNS is in Ω.
For best accuracy, select a RSNS value that provides between
40mV to 80mV differential voltage across RSNS at the desired
maximum peak current (DC plus ripple).
10
FN6936.3
February 16, 2012
ISL9220, ISL9220A
STAT1 and STAT2 are configured to indicate various charging
conditions as given in Table 1.
A fault status is triggered under one of these conditions:
1. VBAT > VOUT_OVP threshold
2. Timeout occurs before the EOC current has been reached
To exit the fault mode, the input power has to be recycled, or the
EN pin is toggled to HI and back to LO.
Applications Information
Power-On Reset (POR)
The ISL9220, ISL9220A resets itself as the input voltage rises
above the POR rising threshold. The internal oscillator starts to
oscillate, the internal timer is reset, and the charger begins to
charge the battery. The STAT1/2 pins will indicate the operating
condition according to Table 1.
Trickle Charge
If the battery voltage is below the trickle charge threshold, the
ISL9220, ISL9220A delivers a small current to charge the battery
until the battery voltage reaches the fast charge threshold value.
There are two trickle charge thresholds. The first threshold,
VPCHG1, is to pre-charge a deeply discharged battery or short
circuit. The second threshold, VPCHG2 is for batteries discharged
to a voltage range from 2.5V to 3V. When VBAT is below VPCHG1,
the ISL9220, ISL9220A operates as a linear regulator, providing
a 50mA constant current to output. When VBAT reaches VPCHG2,
the ISL9220, ISL9220A starts to operate as a switching charger.
The trickle charge current is programmable by RISET2.
Charge Cycle
A charge cycle consists of three charge modes: trickle mode,
constant current (CC) mode, and constant voltage (CV) mode. The
charge cycle always starts with the trickle mode until the battery
voltage stays above VMIN (3.0V typical). If the battery voltage
stays below VMIN, the charger stays in the trickle mode. The
charger operates in CC mode after the battery voltage is above
VMIN. As the battery-pack terminal voltage rises to the final
charge voltage, the CV mode operation begins. Since the battery
terminal voltage is regulated at the constant output voltage in
the CV mode, the charge current begins to drop. After the charge
current drops below the end-of-charge level, which is
programmed by RISET2. The ISL9220, ISL9220A indicates the
end-of-charge (EOC) with STAT1 and STAT2 and terminates the
charge. The following events initiate a new charge cycle:
•
•
•
•
POR
A new battery being inserted (detected by RTH pin)
Recovery from an battery over-temperature fault
The EN pin is toggled from HI-to-LO
Recharge
After a charge cycle completes at a timeout event, charging is
prohibited until the recharge condition (VBAT < VRECHG) is met,
then the charging restarts with the timer reset to zero.
11
Inductor and Output Capacitor Selection
To achieve better steady state and transient response, ISL9220,
ISL9220A typically uses a 10µH inductor. The peak-to-peak inductor
current ripple can be expressed in Equation 9:
V BAT⎞
⎛
V BAT • ⎜ 1 – -------------⎟
V IN ⎠
⎝
ΔI = ----------------------------------------------L • fS
(EQ. 9)
In Equation 9, usually the typical values can be used but to have
a more conservative estimation, the inductance should consider
the value with worst case tolerance; and for switching frequency
fS, the minimum fS from the “Electrical Specifications” table on
page 3 can be used. A worst case for charge current ripple is
when battery voltage is half of the input voltage.
To select the inductor, its saturation current rating should be at
least higher than the sum of the maximum output current and
half of the delta calculated from Equation 9. Another more
conservative approach is to select the inductor with the current
rating higher than the peak current limit.
Another consideration is the inductor DC resistance since it
directly affects the efficiency of the converter. Ideally, the
inductor with the lower DC resistance should be considered to
achieve higher efficiency.
Inductor specifications could be different from different
manufacturers so please check with each manufacturer if
additional information is needed.
For the output capacitor, a ceramic capacitor can be used
because of the low ESR values, which helps to minimize the
output voltage ripple. A typical value of 10µF/10V ceramic
capacitor should be enough for most of the applications and the
capacitor should be X5R or X7R.
Board Layout Recommendations
The ISL9220, ISL9220A is a high frequency switching charger
and hence the PCB layout is a very important design practice to
ensure a satisfactory performance.
The power loop is composed of the output inductor L, the output
capacitor COUT, the SW pin and the PGND pin. It is important to
make the power loop as small as possible and the connecting
traces among them should be direct, short and wide; the same
practice should be applied to the connection of the VIN pin, the
input capacitor CIN and PGND.
The switching node of the converter, the SW pin, and the traces
connected to this node are very noisy, so keep the voltage
feedback trace and other noise sensitive traces away from these
noisy traces.
The input capacitor should be placed as close as possible to the
VIN pin. The ground of the input and output capacitors should be
connected as close as possible as well. In addition, a solid ground
plane is helpful for a good EMI performance.
The ISL9220, ISL9220A employs a thermal enhanced QFN
package with an exposed pad. In order to maximize the current
capability, it is very important that the exposed pad under the
package is properly soldered to the board and is connected to
other layers through thermal vias. More thermal vias and more
FN6936.3
February 16, 2012
ISL9220, ISL9220A
copper attached to the exposed pad usually results in better
thermal performance. The exposed pad is big enough for 5 vias
as shown in Figure 8.
FIGURE 8. EXPOSED PAD
Charging Flow Chart
The charging flow chart is shown in Figure 9 The charging starts
with the trickle mode, the ISL9220, ISL9220A charges the
battery in a trickle current. If VBAT reaches VPCHG2 before the
trickle charge timeout interval, the operation will change to CC
mode. When the output voltage reaches the 4.2V final voltage,
the operation will change to CV mode, where the battery is
charged at a constant voltage. If the end-of-charge current is
reached before the timeout interval is elapsed, the operation will
come to charge complete state. The charging is terminated. After
the termination, if the output voltage drops below the recharge
threshold, a recharge starts and the timer is reset to zero.
In the event that the timeout condition is reached before EOC,
the fault mode is entered. The fault mode can also be triggered
by a VBAT OVP event. To exit the fault mode, the input power has
to be removed and re-applied, or the EN pin is toggled to HI and
back to LO, then a new cycle starts.
12
FN6936.3
February 16, 2012
VIN>VOVP
FROM ANY STATE
ISL9220, ISL9220A
POR
VBAT > VOUT_OVP
FROM ANY STATE
POR or EN
TOGGLED
EN = 0?
YES
VPOR<VIN<VOV
VBAT > Vpchg1
?
RESET
SAFETY TIMER
NO
YES
SUSPEND
CHGR = OFF
HALT TIMER
STAT1 = H
STAT2 = H
BATT
CONNECETD
?
NO
TEMP OK
?
YES
RESUME TIMER
IF STOPPED
YES
NO
TEMP OK?
VBAT > Vpchg2
?
YES
CHGR = ON
ISET2 SETS
CURRENT
NO
YES
RESUME TIMER
IF STOPPED
RESET
SAFETY TIMER
SUSPEND
CHGR = OFF
HALT TIMER
STAT1 = H
STAT2 = H
FOR ISL9220:
RESUME TIMER IF
STOPPED
NO
CHGR = ON
(FAST CHARGE)
YES
FOR ISL9220A:
RESET TIMER
RESET
SAFETY TIMER
NO
SUSPEND
CHGR = OFF
HALT TIMER
STAT1 = H
STAT2 = H
TEMP OK
?
VBAT >
VRECHG
?
NO
YES
IBAT < I_EOC
(> 25ms)
?
YES
YES
CHGR = OFF
(FULL)
VBAT < VRECHG
(> 25ms)
?
NO
NO
PRE-CHARGE
SUSPEND
CHGR = OFF
HALT TIMER
STAT1 = H
STAT2 = H
CHGR = ON
50mA TYP.
(LDO MODE)
NO
BUMP START FOR BATTERY IN UV FAULT
NO
TEMP OK
?
FAST-CHARGE
SUSPEND
CHGR = OFF
STAT1 = H
STAT2 = H
TIMEOUT BEFORE EOC
FAULT
CHGR = OFF
STAT1 = H
STAT2 = L
YES
RESUME TIMER
IF STOPPED
FIGURE 9. CHARGING FLOW CHART
13
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
December 16, 2011
October 3, 2011
August 11, 2010
July 1, 2010
June 30, 2010
REVISION
CHANGE
FN6936.3 Moved the 10µF capacitor at the SW to the VBAT pin in “1-Cell Application” and “2-Cell Application” on page 6.
Added AN1589 to “Related Literature” on page 1.
Changed Eval board names in “Ordering information” on page 2 from ISL9220EVAL1Z, ISL9220AEVAL1Z TO
ISL9220IRTZEVAL1Z, ISL9220AIRTZEVAL1Z.
In the “Pin Descriptions” on page 2:
Pin 12, VHI. Changed "Connect a Schottky diode from VBIAS to this pin, and a 0.1mF capacitor to AGND, as shown
in the Typical Application Circuits." to "Connect the anode of a Schottky diode to VBIAS pin and the cathode to VHI
pin. Connect a 0.1µF capacitor from VHI pin to SW pin. See “Typical Application Diagrams” on page 6.
Pin 17, VBIAS. Changed "Connect a 1µF ceramic capacitor from this pin to AGND." to "Connect a 0.1µF ~ 4.7µF
ceramic capacitor from this pin to AGND. A typical 1µF ceramic capacitor is recommended"
FN6936.2 Added “Number of Cells” column to “Ordering Information” on page 2.
Corrected input voltage in “2-Cell Application” on page 6 from “4.5V to 14V” to “9V to 14V”
FN6936.1 Changed minimum limit for “IPCHG1” on page 4 from 30 to 25mA.
On page 4, changed "Minimum On-Time" with typical 20ns to “Minimum Duty Cycle” with typical of 0%.
Changed minimum limit for “VPCHG1” on page 4 from 4.85 to 4.80V for only the "A option"
Changed maximum limit for “VPCHG1” on page 4 from 5.25 to 5.3V for only the "A option"
Changed minimum limit for “VPCHG2” on page 4 from 5.80V to 5.75V for only the "A option"
Changed maximum limit for “VPCHG2” on page 4 from 6.2V to 6.25V for only the "A option"
Changed minimum limit for “VRECHG” on page 4 from 7.80V to 7.75V for only the "A option"
Changed maximum limit for “VRECHG” on page 4 from 8.20 to 8.25V for only the "A option"
FN6936.0 Initial Release.
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products
address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks.
Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a
complete list of Intersil product families.
For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on
intersil.com: ISL9220, ISL9220A
To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
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14
FN6936.3
February 16, 2012
ISL9220, ISL9220A
Package Outline Drawing
L20.4x4E
20 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 4/10
4X 2.00
4.00
16X 0.50
A
B
16
6
PIN 1
INDEX AREA
6
PIN #1
INDEX AREA
20
1
4.00
15
2 . 60
11
5
(4X)
0.15
6
10
TOP VIEW
0.10 M C A B
20X 0 . 40 ±0.10
4 0.23 +0.07/- 0.05
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0.75
C
BASE PLANE
SEATING PLANE
0.08 C
SIDE VIEW
(3.8 TYP) (
( 16X 0 . 50 )
2 . 60 )
C
( 20X 0 . 23 )
0 . 2 REF
5
( 20 X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5.
Tiebar shown (if present) is a non-functional feature.
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
7.
JEDEC reference drawing: MO-229.
either a mold or mark feature.
15
FN6936.3
February 16, 2012