Maxim MAXQ610 16-bit microcontroller with infrared module Datasheet

19-4715; Rev 3; 7/09
KIT
ATION
EVALU
E
L
B
A
AVAIL
16-Bit Microcontroller with Infrared Module
The MAXQ610 is a low-power, 16-bit MAXQ® microcontroller designed for low-power applications including universal remote controls, consumer electronics,
and white goods. The MAXQ610 combines a powerful
16-bit RISC microcontroller and integrated peripherals
including two USARTs and an SPI™ master/slave communications port, along with an IR module with carrier
frequency generation and flexible port I/O capable of
multiplexed keypad control.
The MAXQ610 includes 64KB of flash memory and 2KB
of data SRAM. Intellectual property (IP) protection is
provided by a secure MMU that supports multiple
application privilege levels and protects code against
copying and reverse engineering. Privilege levels
enable vendors to provide libraries and applications to
execute on the MAXQ610, while limiting access to only
data and code allowed by their privilege level.
For the ultimate in low-power battery-operated performance, the MAXQ610 includes an ultra-low-power stop
mode (0.2µA, typ). In this mode, the minimum amount
of circuitry is powered. Wake-up sources include external interrupts, the power-fail interrupt, and a timer interrupt. The microcontroller runs from a wide 1.70V to 3.6V
operating voltage.
Applications
Remote Controls
Battery-Powered Portable Equipment
Consumer Electronics
♦ Dedicated Pointer for Direct Read from Code
Space
MAXQ610
General Description
♦ 16-Bit Instruction Word, 16-Bit Data Bus
♦ 16 x 16-Bit General-Purpose Working Registers
♦ Secure MMU for Application Partitioning and IP
Protection
♦ Memory Features
64KB Flash:
512 Byte Sectors
20,000 Erase/Write Cycles per Sector
Masked ROM Available
2KB Data SRAM
♦ Additional Peripherals
Power-Fail Warning
Power-On Reset/Brownout Reset
Automatic IR Carrier Frequency Generation and
Modulation
Two 16-Bit, Programmable Timers/Counters with
Prescaler and Capture/Compare
SPI and Two USART Communication Ports
Programmable Watchdog Timer
8kHz Nanopower Ring Oscillator Wake-Up Timer
Up to 24 (MAXQ610A) or 32 (MAXQ610B)
General-Purpose I/Os
♦ Low-Power Consumption
0.2µA (typ), 2.0µA (max) in Stop Mode
TA = +25°C, Power-Fail Monitor Disabled
3.75mA (typ) at 12MHz in Active Mode
Home Appliances
Ordering Information
White Goods
Features
♦ High-Performance, Low-Power 16-Bit RISC Core
♦ DC to 12MHz Operation Across Entire Operating
Range
♦ 1.70V to 3.6V Operating Voltage Range
♦ 33 Total Instructions for Simplified Programming
♦ Three Independent Data Pointers Accelerate Data
Movement with Automatic Increment/Decrement
PART
TEMP RANGE
PIN-PACKAGE
MAXQ610A-0000+*
0°C to +70°C
32 TQFN-EP
MAXQ610B-0000+
0°C to +70°C
40 TQFN-EP
MAXQ610X-0000+**
0°C to +70°C
Bare die
Note: Contact factory for information about masked ROM devices.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
**Contact factory for availability.
Pin Configurations and Selector Guide appear at end of
data sheet.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
SPI is a trademark of Motorola, Inc.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
simultaneously available through various sales channels. For information about device errata, go to: www.maxim-ic.com/errata.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAXQ610
16-Bit Microcontroller with Infrared Module
TABLE OF CONTENTS
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
SPI Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Detailed Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Stack Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Utility ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
IR Carrier Generation and Modulation Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Carrier Generation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IR Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
IR Transmit—Independent External Carrier and Modulator Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
IR Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Carrier Burst-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
16-Bit Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
ROM Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Loading Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
In-Application Flash Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
In-Circuit Debug and JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Power-Fail Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Grounds and Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Differences for ROM Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Additional Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Development and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Selector Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
2
_______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Figure 3. IR Transmission Waveform (IRCFME = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Figure 4. External IRTXM (Modulator) Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 5. IR Capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Figure 6. Receive Burst-Count Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Figure 7. SPI Master Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 8. SPI Slave Communication Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Figure 9. On-Chip Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Figure 10. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Figure 11. Power-Fail Detection During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . .23
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
LIST OF TABLES
Table 1. Memory Areas and Associated Maximum Privilege Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Table 3. USART Mode Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Table 4. Power-Fail Detection States During Normal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled . . . . . . . . . . . . . . . . . . . . . . . . . .24
_______________________________________________________________________________________
3
MAXQ610
LIST OF FIGURES
MAXQ610
16-Bit Microcontroller with Infrared Module
ABSOLUTE MAXIMUM RATINGS
Storage Temperature Range .............................-65°C to +150°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Voltage Range on VDD with Respect to GND .......-0.3V to +3.6V
Voltage Range on Any Lead with Respect
to GND except VDD .....................................-0.3V to (VDD + 0.5V)
Operating Temperature Range...............................0°C to +70°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VDD = VRST to 3.6V, TA = 0°C to +70°C.) (Note 1)
PARAMETER
Supply Voltage
1.8V Internal Regulator
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
VDD
VRST
3.6
V
VREG18
1.62
1.8
1.98
V
Power-Fail Warning Voltage for
Supply (Notes 2, 3)
VPFW
Monitors VDD
1.75
1.8
1.85
V
Power-Fail Reset Voltage
(Note 4)
VRST
Monitors VDD
1.64
1.67
1.70
V
Power-On Reset Voltage
VPOR
Monitors VDD
1.0
RAM Data-Retention Voltage
VDRV
(Note 5)
1.0
Active Current (Note 6)
IDD_1
Sysclk = 12MHz
I S1
Power-Fail Off
Stop-Mode Current
I S2
Power-Fail On
Current Consumption During
Power-Fail
I PFR
(Notes 5, 7)
Power Consumption During
Power-On Reset
I POR
(Note 8)
Stop-Mode Resume Time
Power-Fail Monitor Startup Time
Power-Fail Warning Detection
Time
t ON
t PRM_ON
t PFW
1.42
3.75
5.1
TA = +25°C
0.2
2.0
TA = 0°C to +70°C
0.2
12
TA = +25°C
22
29.5
27.6
42
TA = 0°C to +70°C
mA
μA
[(3 x I S2) + ((PCI - 3) x
(IS1 + INANO))]/PCI
μA
100
nA
375 + 8192tHFXIN
(Note 5)
(Notes 5, 9)
V
V
150
10
μs
μs
μs
Input Low Voltage for IRTX,
IRRX, RESET, and All Port Pins
VIL
GND
0.3 x
VDD
V
Input High Voltage for IRTX,
IRRX, RESET, and All Port Pins
VIH
0.7 x
VDD
VDD
V
Input Hysteresis (Schmitt)
Input Low Voltage for HFXIN
4
VIHYS
VIL_HFXIN
300
GND
_______________________________________________________________________________________
mV
0.3 x
VDD
V
16-Bit Microcontroller with Infrared Module
(VDD = VRST to 3.6V, TA = 0°C to +70°C.) (Note 1)
PARAMETER
SYMBOL
Input High Voltage for HFXIN
VIH_HFXIN
IRRX Input Filter Pulse-Width
Reject
t IRRX_R
IRRX Input Filter Pulse-Width
Accept
t IRRX_A
Otuput Low Voltage for IRTX
VOL_IRTX
Output Low Voltage for RESET
and All Port Pins (Note 10)
VOL
CONDITIONS
VDD
V
50
ns
ns
1.0
VDD = 1.85V, I OL = 4.5mA
1.0
1.0
VDD = 3.6V, I OL = 11mA (Note 5)
VDD = 2.35V, I OL = 8mA (Note 5)
0.4
0.5
0.4
0.5
VDD = 1.85V, I OL = 4.5mA
0.4
0.5
Input/Output Pin Capacitance for
All Port Pins
CIO
(Note 5)
RPU
UNITS
VDD = 3.6V, I OL = 25mA (Note 5)
VDD = 2.35V, I OL = 10mA (Note 5)
I OH = -2mA
IL
MAX
300
VOH
Input Pullup Resistor for RESET,
IRTX, IRRX, and All Port Pins
TYP
0.7 x
VDD
Output High Voltage for IRTX and
All Port Pins
Input Leakage Current
MIN
Internal pullup disabled
VDD 0.5
-100
V
V
VDD
V
15
pF
+100
nA
VDD = 3.0V, VOL = 0.4V (Note 5)
16
28
39
VDD = 2.0V, VOL = 0.4V
17
30
41
k
EXTERNAL CRYSTAL/RESONATOR
Crystal/Resonator
fHFXIN
Crystal/Resonator Period
DC
tHFXIN
Crystal/Resonator Warmup Time
t XTAL_RDY
Oscillator Feedback Resistor
R OSCF
From initial oscillation
(Note 5)
0.5
12
MHz
1/fHFXIN
ns
8192 x tHFXIN
ms
1.0
1.5
M
12
MHz
EXTERNAL CLOCK INPUT
External Clock Frequency
f XCLK
External Clock Period
t XCLK
External Clock Duty Cycle
DC
1/f XCLK
t XCLK_DUTY
System Clock Frequency
fCK
System Clock Period
tCK
45
ns
55
fHFIN
HFXOUT = GND
%
MHz
f XCLK
1/fCK
MHz
NANOPOWER RING OSCILLATOR
TA = +25°C
3.0
8.0
TA = +25°C, VDD = POR voltage (Note 5)
1.7
2.4
tNANO
(Note 5)
40
INANO
Typical at VDD = 1.64V, TA = +25°C
(Note 5)
Nanopower Ring Oscillator
Frequency
fNANO
Nanopower Ring Oscillator Duty
Cycle
Nanopower Ring Oscillator
Current
40
20.0
kHz
60
%
400
nA
_______________________________________________________________________________________
5
MAXQ610
RECOMMENDED DC OPERATING CONDITIONS (continued)
MAXQ610
16-Bit Microcontroller with Infrared Module
RECOMMENDED DC OPERATING CONDITIONS (continued)
(VDD = VRST to 3.6V, TA = 0°C to +70°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
65,535/
fNANO
s
WAKE-UP TIMER
Wake-Up Timer Interval
tWAKEUP
1/fNANO
fFPSYSCLK
5
FLASH MEMORY
System Clock During Flash
Programming/Erase
Flash Erase Time
Flash Programming Time per
Word
MHz
tME
Mass erase
20
40
t ERASE
Page erase
20
40
t PROG
(Note 11)
20
100
Write/Erase Cycles
Data Retention
TA = +25°C
ms
μs
20,000
Cycles
100
Years
IR
Carrier Frequency
f IR
(Note 5)
fCK/2
Hz
Specifications to 0°C are guaranteed by design and are not production tested.
It is not recommended to write to flash memory when the supply voltage drops below the power-fail warning levels as
there is uncertainty in the duration of continuous power supply. The user application should check the status of the powerfail warning flag before writing to flash to ensure complete write operations.
Note 3: The power-fail warning monitor and the power-fail reset monitor track each other with a minimum delta between the two of
0.11V.
Note 4: The power-fail reset and power-on-reset (POR) detectors operate in tandem to ensure that one or both signals are active
at all times when VDD < VRST. Doing so ensures the device maintains the reset state until the minimum operating voltage is
achieved.
Note 5: Guaranteed by design and not production tested.
Note 6: Measured on the VDD pin and the part not in reset. All inputs are connected to GND or VDD. Outputs do not source/sink
any current. Part is executing code from flash memory.
Note 7: The power-check interval (PCI) can be set to always on, 1024, 2048, or 4096 nanopower ring oscillator clock cycles.
Note 8: Current consumption during POR when powering up while VDD < VPOR.
Note 9: The minimum amount of time that VDD must be below VPFW before a power-fail event is detected.
Note 10: The maximum total current, IOH (max) and IOL (max), for all listed outputs combined should not exceed 32mA to satisfy
the maximum specified voltage drop. This does not include the IRTX output.
Note 11: Programming time does not include overhead associated with utility ROM interface.
Note 1:
Note 2:
6
_______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
(VDD = VRST to 3.6V, TA = 0°C to +70°C. AC electrical specifications are guaranteed by design and are not production tested.)
PARAMETER
SYMBOL
SPI Master Operating Frequency
1/tMCK
SPI Slave Operating Frequency
1/t SCK
SPI I/O Rise/Fall Time
t SPI_RF
SCLK Output Pulse-Width
High/Low
CONDITIONS
CL = 15pF, pullup = 560
MIN
TYP
8.3
MAX
UNITS
fCK/2
MHz
fCK/4
MHz
23.6
ns
tMCH, tMCL
tMCK/2 t SPI_RF
ns
MOSI Output Hold Time After
SCLK Sample Edge
tMOH
tMCK/2 t SPI_RF
ns
MOSI Output Valid to Sample
Edge
tMOV
tMCK/2 t SPI_RF
ns
MISO Input Valid to SCLK
Sample Edge Rise/Fall Setup
tMIS
25
ns
MISO Input to SCLK Sample
Edge Rise/Fall Hold
tMIH
0
ns
SCLK Inactive to MOSI Inactive
tMLH
tMCK/2 t SPI_RF
ns
SCLK Input Pulse-Width
High/Low
t SCH, t SCL
t SCK/2
ns
SSEL Active to First Shift Edge
t SSE
t SPI_RF
ns
MOSI Input to SCLK Sample
Edge Rise/Fall Setup
t SIS
t SPI_RF
ns
MOSI Input from SCLK Sample
Edge Transition Hold
t SIH
t SPI_RF
ns
MISO Output Valid After SCLK
Shift Edge Transition
t SOV
SSEL Inactive
t SSH
tCK +
t SPI_RF
ns
SCLK Inactive to SSEL Rising
t SD
t SPI_RF
ns
MISO Output Disabled After
SSEL Edge Rise
t SLH
2t SPI_RF
2tCK +
2t SPI_RF
ns
ns
_______________________________________________________________________________________
7
MAXQ610
SPI ELECTRICAL CHARACTERISTICS
16-Bit Microcontroller with Infrared Module
MAXQ610
Pin Description
PIN
32 TQFN
40 TQFN
NAME
FUNCTION
POWER PINS
14, 30
18, 38
VDD
Supply Voltage
13
17
REGOUT
Regulator Capacitor. This pin must be connected to ground through a 1.0μF external
ceramic-chip capacitor in series with a 2 to 10 resistor. The capacitor must be
placed as close to this pin as possible. No other external devices other than the
capacitor should be connected to this pin.
EP
EP
GND
Ground. The GND contact is through the exposed paddle located on the underside of
the package. It must be directly connected to the ground plane.
RESET
Digital, Active-Low, Reset Input/Output. The CPU is held in reset when this pin is low
and begins executing from the reset vector when released. The pin includes pullup
current source and should be driven by an open-drain, external source capable of
sinking in excess of 4mA. This pin is driven low as an output when an internal reset
condition occurs.
RESET PINS
29
37
CLOCK PINS
17
21
HFXIN
18
22
HFXOUT
High-Frequency Crystal Input. Connect external crystal or resonator between HFXIN
and HFXOUT as the high-frequency system clock. Alternatively, HFXIN is the input
for an external, high-frequency clock source when HFXOUT is floating.
IR FUNCTION PINS
31
39
IRTX
IR Transmit Output. IR transmit pin capable of sinking 25mA. This pin defaults to
high-impedance input with the weak pullup disabled during all forms of reset.
Software must configure this pin after release from reset to remove the highimpedance input condition.
32
40
IRRX
IR Receive Input. IR receive pin. This pin defaults to high-impedance input with the
weak pullup disabled during all forms of reset. Software must configure this pin after
release from reset to remove the high-impedance input condition.
GENERAL-PURPOSE I/O AND SPECIAL FUNCTION PINS
General-Purpose, Digital, I/O, Type-C Port. These port pins function as bidirectional
I/O pins. All port pins default to high-impedance mode after a reset. Software must
configure these pins after release from reset to remove the high-impedance input
condition. All alternate functions must be enabled from software.
1–8
8
1, 3, 5–10
P0.0–P0.7;
IRTXM, RX0,
TX0, RX1,
TX1, TBA0/
TBA1,
TBB0/
TBB1
32 TQFN
40 TQFN
PORT
SPECIAL FUNCTION
1
1
P0.0
IRTXM
2
3
P0.1
RX0
3
5
P0.2
TX0
4
6
P0.3
RX1
5
7
P0.4
TX1
6
8
P0.5
TBA0/TBA1
7
9
P0.6
TBB0
8
10
P0.7
TBB1
_______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
PIN
32 TQFN
40 TQFN
9–12, 15,
16, 19, 20
11–14, 19,
20, 23, 24
21–28
25, 26, 29–
32, 35, 36
—
2, 4, 15, 16,
27, 28, 33,
34
NAME
FUNCTION
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt.
These port pins function as bidirectional I/O pins or as interrupts. All port pins default
to high-impedance mode after a reset. Software must configure these pins after
release from reset to remove the high-impedance input condition. All interrupt
functions must be enabled from software.
32 TQFN
40 TQFN
PORT
SPECIAL FUNCTION
P1.0–P1.7;
9
11
P1.0
INT0
INT0–INT7
10
12
P1.1
INT1
11
13
P1.2
INT2
12
14
P1.3
INT3
15
19
P1.4
INT4
16
20
P1.5
INT5
19
23
P1.6
INT6
20
24
P1.7
INT7
General-Purpose, Digital, I/O, Type-C Port. These port pins function as bidirectional
I/O pins. P2.0–P2.3 default to high-impedance mode after a reset. Software must
configure these pins after release from reset to remove the high-impedance input
condition. All alternate functions must be enabled from software. Enabling the pin’s
special function disables the general-purpose I/O on the pin.
The JTAG pins (P2.4–P2.7) default to their JTAG function with weak pullups enabled
after a reset. The JTAG function can be disabled using the TAP bit in the SC register.
P2.0–P2.7; P2.7 functions as the JTAG test-data output on reset and defaults to an input with a
MOSI, MISO, weak pullup. The output function of the test data is only enabled during the TAP’s
SCLK, SSEL, Shift_IR or Shift_DR states.
TCK, TDI,
32 TQFN
40 TQFN
PORT
SPECIAL FUNCTION
TMS, TDO
21
25
P2.0
MOSI
22
26
P2.1
MISO
23
29
P2.2
SCLK
24
30
P2.3
SSEL
25
31
P2.4
TCK
26
32
P2.5
TDI
27
35
P2.6
TMS
28
36
P2.7
TDO
General-Purpose, Digital, I/O, Type-D Port; External Edge-Selectable Interrupt.
These port pins function as bidirectional I/O pins or as interrupts. All port pins default
to high-impedance mode after a reset. Software must configure these pins after
release from reset to remove the high-impedance input condition. All interrupt
functions must be enabled from software.
32 TQFN
40 TQFN
PORT
SPECIAL FUNCTION
P3.0–P3.7;
—
2
P3.0
INT8
INT8–INT15
—
4
P3.1
INT9
—
15
P3.2
INT10
—
16
P3.3
INT11
—
27
P3.4
INT12
—
28
P3.5
INT13
—
33
P3.6
INT14
—
34
P3.7
INT15
_______________________________________________________________________________________
9
MAXQ610
Pin Description (continued)
16-Bit Microcontroller with Infrared Module
MAXQ610
Block Diagram
MAXQ610
REGULATOR
VOLTAGE
MONITOR
GPIO
16-BIT TIMER
16-BIT MAXQ
RISC CPU
4KB ROM
SECURE MMU
CLOCK
64KB FLASH
WATCHDOG
2KB SRAM
16-BIT TIMER
8kHz NANO
RING
IR DRIVER
IR TIMER
SPI
USART0
USART1
Detailed Description
The MAXQ610 microcontroller provides integrated, lowcost solutions that simplify the design of IR communications equipment such as universal remote controls.
Standard features include the highly optimized, singlecycle, MAXQ 16-bit RISC core, 64KB of flash memory,
2KB data RAM, a soft stack, 16 general-purpose registers, and three data pointers. The MAXQ core offers the
industry’s best MIPS/mA rating, allowing developers to
achieve the same performance as competing microcontrollers at substantially lower clock rates. Combining
lower active-mode current with the MAXQ610 stopmode current (0.2µA typical) results in increased battery life. Application-specific peripherals include
flexible timers for generating IR carrier frequencies and
modulation, a high-current IR drive pin capable of sinking up to 25mA current, and output pins capable of
sinking up to 5mA ideal for IR applications, generalpurpose I/O pins ideal for keypad matrix input, and a
power-fail-detection circuit to notify the application
when the supply voltage is nearing the minimum operating voltage of the microcontroller.
At the heart of the MAXQ610 is the MAXQ 16-bit RISC
core. The MAXQ610 operates from DC to 12MHz and
almost all instructions execute in a single clock cycle
(83.3ns at 12MHz), enabling nearly 12MIPS true code
operation. When active device operation is not
required, an ultra-low-power stop mode can be invoked
from software resulting in quiescent current consumption of less than 0.2µA typical and 2.0µA maximum. The
combination of high-performance instructions and ultralow stop-mode current increases battery life over com-
10
peting microcontrollers. An integrated POR circuit with
brownout support resets the device to a known condition following a power-up cycle or brownout condition.
Additionally, a power-fail warning flag is set and a
power-fail interrupt can be generated when the system
voltage falls below the power-fail warning voltage,
VPFW. The power-fail warning feature allows the application to notify the user that the system supply is low
and appropriate action should be taken.
Microprocessor
The MAXQ610 is based on Maxim’s MAXQ core. The
MAXQ is a low-power implementation of the new 16-bit
MAXQ family of RISC cores. The core supports the
Harvard memory architecture with separate 16-bit program and data address buses. A fixed 16-bit instruction
word is standard, but data can be arranged in 8 or 16
bits. The MAXQ core in the MAXQ610 family is implemented as a pipelined processor with performance
approaching 1MIPS per MHz. The 16-bit data path is
implemented around register modules, and each register module contributes specific functions to the core.
The accumulator module consists of sixteen 16-bit registers and is tightly coupled with the arithmetic logic unit
(ALU). A configurable soft stack supports program flow.
Execution of instructions is triggered by data transfer
between functional register modules or between a functional register module and memory. Because data
movement involves only source and destination modules, circuit-switching activities are limited to active
modules only. For power-conscious applications, this
approach localizes power dissipation and minimizes
switching noise. The modular architecture also provides
a maximum of flexibility and reusability that is important
for a microprocessor used in embedded applications.
The MAXQ instruction set is highly orthogonal. All arithmetical and logical operations can use any register in
conjunction with the accumulator. Data movement is
supported from any register to any other register.
Memory is accessed through specific data-pointer registers with automatic increment/decrement support.
Memory
The MAXQ610 incorporates several memory types that
include the following:
• 64KB program flash
• 2KB SRAM data memory
• 5.25KB utility ROM
• Soft stack
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
AREA
PAGE ADDRESS
MAXIMUM PRIVILEGE LEVEL
System
0 to ULDR-1
High
User Loader
ULDR to UAPP-1
Medium
User Application
UAPP to top
Low
Utility ROM
N/A
High
Other (RAM)
N/A
Low
Memory Protection
The optional memory-protection feature separates code
memory into three areas: system, user loader, and user
application. Code in the system area can be kept confidential. Code in the user areas can be prevented from
reading and writing system code. The user loader can
also be protected from user application code.
Memory protection is implemented using privilege levels for code. Each area has an associated privilege
level. RAM/ROM are assigned privilege levels as well.
Refer to the MAXQ Family User's Guide: MAXQ610
Supplement for a more thorough explanation of the
topic. See Table 1.
Stack Memory
A 16-bit-wide internal stack provides storage for program
return addresses and can also be used general-purpose
data storage. The stack is used automatically by the
processor when the CALL, RET, and RETI instructions
are executed and when an interrupt is serviced. An
application can also store values in the stack explicitly by
using the PUSH, POP, and POPI instructions.
On reset, the stack pointer, SP, initializes to the top of
the stack (0Fh). The CALL, PUSH, and interrupt-vectoring operations increment SP, then store a value at the
location pointed to by SP. The RET, RETI, POP, and
POPI operations retrieve the value at SP and then
decrement SP.
Utility ROM
The utility ROM is a 5.25KB block of internal ROM memory that defaults to a starting address of 8000h. The utility ROM consists of subroutines that can be called from
application software. These include the following:
• In-system programming (bootstrap loader) using
JTAG interface
• In-circuit debug routines
• Test routines (internal memory tests, memory loader,
etc.)
• User-callable routines for in-application flash programming and fast table lookup
MAXQ610
Table 1. Memory Areas and Associated Maximum Privilege Levels
Following any reset, execution begins in the utility ROM.
The ROM software determines whether the program
execution should immediately jump to location 0000h,
the start of system code, or to one of the special routines mentioned. Routines within the utility ROM are
user accessible and can be called as subroutines by
the application software. More information on the utility
ROM functions is contained in the MAXQ Family User’s
Guide: MAXQ610 Supplement.
Some applications require protection against unauthorized viewing of program code memory. For these
applications, access to in-system programming, inapplication programming, or in-circuit debugging functions is prohibited until a password has been supplied.
The password is defined as the 16 words of physical
program memory at addresses 0010h to 001Fh.
Three password locks are provided for protection of up to
three different program memory segments. When the
PWL is set to 1 (POR default) and the contents of the
memory at addresses 0010h to 001Fh are any value other
than FFh or 00h, the password is required to access the
utility ROM, including in-circuit debug and in-system programming routines that allow reading or writing of internal
memory. When PWL is cleared to 0, these utilities are
fully accessible without password. The password is
automatically set to all ones following a mass erase.
Watchdog Timer
An internal watchdog timer greatly increases system
reliability. The timer resets the device if software execution is disturbed. The watchdog timer is a free-running
counter designed to be periodically reset by the application software. If software is operating correctly, the
counter is periodically reset and never reaches its maximum count. However, if software operation is interrupted, the timer does not reset, triggering a system reset
and optionally a watchdog timer interrupt. This protects
the system against electrical noise or ESD upsets that
could cause uncontrolled processor operation. The
internal watchdog timer is an upgrade to older designs
with external watchdog devices, reducing system cost
and simultaneously increasing reliability.
______________________________________________________________________________________
11
MAXQ610
16-Bit Microcontroller with Infrared Module
Table 2. Watchdog Interrupt Timeout (Sysclk = 12MHz, CD[1:0] = 00)
WATCHDOG INTERRUPT TIMEOUT
WATCHDOG RESET AFTER
WATCHDOG INTERRUPT (μs)
Sysclk/215
2.7ms
42.7
01
Sysclk/218
21.9ms
42.7
10
Sysclk/221
174.7ms
42.7
11
Sysclk/224
1.4s
42.7
WD[1:0]
WATCHDOG CLOCK
00
The watchdog timer functions as the source of both the
watchdog-timer timeout and the watchdog-timer reset.
The timeout period can be programmed in a range of
215 to 224 system clock cycles. An interrupt is generated when the timeout period expires if the interrupt is
enabled. All watchdog-timer resets follow the programmed interrupt timeouts by 512 system clock
cycles. If the watchdog timer is not restarted for another
full interval in this time period, a system reset occurs
when the reset timeout expires. See Table 2.
IR Carrier Generation and
Modulation Timer
The dedicated IR timer/counter module simplifies lowspeed IR communication. The IR timer implements two
pins (IRTX and IRRX) for supporting IR transmit and
receive, respectively. The IRTX pin has no corresponding port pin designation, so the standard PD, PO, and
PI port control status bits are not present. However, the
IRTX pin output can be manipulated high or low using
the PWCN.IRTXOUT and PWCN.IRTXOE bits when the
IR timer is not enabled (i.e., IREN = 0).
The IR timer is composed of two separate timing entities: a carrier generator and a carrier modulator. The
carrier generation module uses the 16-bit IR Carrier
register (IRCA) to define the high and low time of the
carrier through the IR carrier high byte (IRCAH) and IR
carrier low byte (IRCAL). The carrier modulator uses the
IR data bit (IRDATA) and IR Modulator Time register
(IRMT) to determine whether the carrier or the idle condition is present on IRTX.
The IR timer is enabled when the IR enable bit (IREN) is
set to 1. The IR Value register (IRV) defines the beginning value for the carrier modulator. During transmission, the IRV register is initially loaded with the IRMT
value and begins down counting towards 0000h,
whereas in receive mode it counts upward from the initial IRV register value. During the receive operation, the
IRV register can be configured to reload with 0000h
when capture occurs on detection of selected edges or
12
can be allowed to continue free-running throughout the
receive operation. An overflow occurs when the IR timer
value rolls over from 0FFFFh to 0000h. The IR overflow
flag (IROV) is set to 1 and an interrupt is generated if
enabled (IRIE = 1).
Carrier Generation Module
The IRCAH byte defines the carrier high time in terms of
the number of IR input clocks, whereas the IRCAL byte
defines the carrier low time.
IR Input Clock (fIRCLK) = fSYS/2IRDIV[1:0]
Carrier Frequency (fCARRIER) =
fIRCLK/(IRCAH + IRCAL + 2)
Carrier High Time = IRCAH + 1
Carrier Low Time = IRCAL + 1
Carrier Duty Cycle = (IRCAH + 1)/(IRCAH + IRCAL + 2)
During transmission, the IRCA register is latched for
each IRV downcount interval and is sampled along with
the IRTXPOL and IRDATA bits at the beginning of each
new IRV downcount interval so that duty-cycle variation
and frequency shifting is possible from one interval to
the next, which is illustrated in Figure 1.
Figure 2 illustrates the basic carrier generation and its
path to the IRTX output pin. The IR transmit polarity bit
(IRTXPOL) defines the starting/idle state and the carrier
polarity of the IRTX pin when the IR timer is enabled.
IR Transmission
During IR transmission (IRMODE = 1), the carrier generator creates the appropriate carrier waveform, while the
carrier modulator performs the modulation. The carrier
modulation can be performed as a function of carrier
cycles or IRCLK cycles dependent on the setting of the
IRCFME bit. When IRCFME = 0, the IRV downcounter is
clocked by the carrier frequency and thus the modulation is a function of carrier cycles. When IRCFME = 1,
the IRV downcounter is clocked by IRCLK, allowing carrier modulation timing with IRCLK resolution.
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
IRCA = 0202h
IRCA = 0002h
IRMT
IRMT = 3
IRMT = 5
MAXQ610
IRCA
IRCA, IRMT, IRDATA SAMPLED AT END OF IRV
DOWNCOUNT INTERVAL
3
2
1
0
5
4
3
2
1
0
CARRIER OUTPUT
(IRV)
IRDATA
0
1
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
Figure 1. IR Transmit Frequency Shifting Example (IRCFME = 0)
IRTXPOL
0
CARRIER GENERATION
IRCLK
IRTX PIN
1
CARRIER
IRCAH + 1
IRCAL + 1
IRCFME
0
1
IRDATA
IRMT
SAMPLE
IRDATA ON
IRV = 0000h
IR INTERRUPT
CARRIER MODULATION
Figure 2. IR Transmit Carrier Generation and Carrier Modulator Control
______________________________________________________________________________________
13
MAXQ610
16-Bit Microcontroller with Infrared Module
The IRTXPOL bit defines the starting/idle state as well
as the carrier polarity for the IRTX pin. If IRTXPOL = 1,
the IRTX pin is set to a logic-high when the IR timer
module is enabled. If IRTXPOL = 0, the IRTX pin is set
to a logic-low when the IR timer is enabled.
A separate register bit, IR data (IRDATA), is used to
determine whether the carrier generator output is output to the IRTX pin for the next IRMT carrier cycles.
When IRDATA = 1, the carrier waveform (or inversion of
this waveform if IRTXPOL = 1) is output on the IRTX pin
during the next IRMT cycles. When IRDATA = 0, the
idle condition, as defined by IRTXPOL, is output on the
IRTX pin during the next IRMT cycles.
The IR timer acts as a downcounter in transmit mode.
An IR transmission starts when 1) the IREN bit is set to
1 when IRMODE = 1, 2) the IRMODE bit is set to 1
when IREN = 1, or 3) when IREN and IRMODE are both
set to 1 in the same instruction. The IRMT and IRCA
registers, along with the IRDATA and IRTXPOL bits, are
sampled at the beginning of the transmit process and
every time the IR timer value reloads its value. When
the IRV reaches 0000h value, on the next carrier clock,
it does the following:
3) Generates IRTX accordingly.
4) Sets IRIF to 1.
5) Generates an interrupt to the CPU if enabled (IRIE = 1).
To terminate the current transmission, the user can
switch to receive mode (IRMODE = 0) or clear IREN to 0.
Carrier Modulation Time = IRMT + 1 carrier cycles
IR Transmit—Independent External Carrier
and Modulator Outputs
The normal transmit mode modulates the carrier based
upon the IRDATA bit. However, the user has the option
to input the modulator (envelope) on an external pin if
desired. If the IRENV[1:0] bits are configured to 01b or
10b, the modulator/envelope is output to the IRTXM pin.
The IRDATA bit is output directly to the IRTXM pin (if
IRTXPOL = 0) on each IRV downcount interval boundary just as if it were being used to internally modulate
the carrier frequency. If IRTXPOL = 1, the inverse of the
IRDATA bit is output to the IRTXM pin on the IRV interval downcount boundaries. The envelope output is illustrated in Figure 4. When the envelope mode is enabled,
it is possible to output either the modulated (IRENV[1:0]
= 01b) or unmodulated (IRENV[1:0] = 10b) carrier to
the IRTX pin.
1) Reloads IRV with IRMT.
2) Samples IRCA, IRDATA, and IRTXPOL.
IRMT = 3
CARRIER OUTPUT
(IRV)
3
2
1
0
3
2
1
0
IRDATA
0
1
0
IR INTERRUPT
IRTX
IRTXPOL = 1
IRTX
IRTXPOL = 0
Figure 3. IR Transmission Waveform (IRCFME = 0)
14
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
MAXQ610
IRTXM
IRTXPOL = 1
IRTXM
IRTXPOL = 0
IRDATA
1
0
1
0
1
0
1
0
IR INTERRUPT
IRV INTERVAL
IRMT
IRMT
IRMT
IRMT
Figure 4. External IRTXM (Modulator) Output
CARRIER GENERATION
CARRIER MODULATION
IRCLK
0
IRCAH + 1
IR TIMER OVERFLOW
IRCAL + 1
1
IRCFME
INTERRUPT TO CPU
0000h
IRV
IR INTERRUPT
COPY IRV TO IRMT
ON EDGE DETECT
IRXRL
IRRX PIN
RESET IRV TO 0000h
EDGE DETECT
IRDATA
Figure 5. IR Capture
IR Receive
When configured in receive mode (IRMODE = 0), the IR
hardware supports the IRRX capture function. The
IRRXSEL[1:0] bits define which edge(s) of the IRRX pin
should trigger IR timer capture function.
The IR module starts operating in the receive mode
when IRMODE = 0 and IREN = 1. Once started, the IR
timer (IRV) starts up counting from 0000h when a quali-
fied capture event as defined by IRRXSEL happens.
The IRV register is, by default, counting carrier cycles
as defined by the IRCA register. However, the IR carrier
frequency detect (IRCFME) bit can be set to 1 to allow
clocking of the IRV register directly with the IRCLK for
finer resolution. When IRCFME = 0, the IRCA defined
carrier is counted by IRV. When IRCFME = 1, the
IRCLK clocks the IRV register.
______________________________________________________________________________________
15
MAXQ610
16-Bit Microcontroller with Infrared Module
On the next qualified event, the IR module does the
following:
1) Captures the IRRX pin state and transfers its value to
IRDATA. If a falling edge occurs, IRDATA = 0. If a
rising edge occurs, IRDATA = 1.
2) Transfers its current IRV value to the IRMT.
3) Resets IRV content to 0000h (if IRXRL = 1).
4) Continues counting again until the next qualified
event.
If the IR timer value rolls over from 0FFFFh to 0000h
before a qualified event happens, the IR timer overflow
(IROV) flag is set to 1 and an interrupt generated if
enabled. The IR module continues to operate in receive
CARRIER FREQUENCY
CALCULATION
mode until it is stopped by switching into transmit mode
(IRMODE = 1) or clearing IREN = 0.
Carrier Burst-Count Mode
A special mode reduces the CPU processing burden
when performing IR learning functions. Typically, when
operating in an IR learning capacity, some number of
carrier cycles are examined for frequency determination. Once the frequency has been determined, the IR
receive function can be reduced to counting the number
of carrier pulses in the burst and the duration of the
combined mark-space time within the burst. To simplify
this process, the receive burst-count mode (as enabled
by the RXBCNT bit) can be used. When RXBCNT = 0,
the standard IR receive capture functionality is in place.
IRMT = PULSE COUNTING
IRMT = PULSE COUNTING
IRV = CARRIER CYCLE COUNTING
IRRX
IRV
IRMT
1
2
3
4
6
7
8
5
1 TO 4
CAPTURE INTERRUPT (IRIF = 1).
IRV ≥ IRMT.
IRV = 0 (IF IRXRL = 1).
5
SOFTWARE SETS IRCA = CARRIER FREQUENCY.
SOFTWARE SETS RXBCNT = 1 (WHICH CLEARS IRMT = 0001 IN HARDWARE).
SOFTWARE CLEARS IRCFME = 0 SO THAT IRV COUNTS CARRIER CYCLES. IRV IS RESET TO 0 ON QUALIFIED EDGE DETECTION IF IRXRL = 1.
SOFTWARE ADDS TO IRMT THE NUMBER OF PULSES USED FOR CARRIER MEASUREMENT.
IRCA x 2x COUNTER FOR SPACE CAN BEGIN IMMEDIATELY (QUALIFIED EDGE RESETS).
6
QUALIFIED EDGE DETECTED: IRMT++
IRV RESET TO 0 IF IRXRL = 1.
7
IRCA x 2 PERIOD ELAPSES: IRIF = 1; CARRIER ABSENCE = SPACE.
BURST MARK = IRMT PULSES.
SOFTWARE CLEARS RXBCNT = 0 SO THAT WE CAPTURE ON THE NEXT QUALIFIED EDGE.
8
QUALIFIED EDGE DETECTED: IRIF = 1, CAPTURE IRV ≥ IRMT AS THE BURST SPACE (PLUS UP TO ONE CARRIER CYCLE).
9
SOFTWARE SET RXBCNT = 1 AS IN (5).
CONTINUE (5) TO (8) UNTIL LEARNING SPACE EXCEEDS SOME DURATION. IRV ROLLOVERS CAN BE USED.
Figure 6. Receive Burst-Count Example
16
______________________________________________________________________________________
9
16-Bit Microcontroller with Infrared Module
USART
The USART units are implemented with the following
characteristics:
• 2-wire interface
• Full-duplex operation for asynchronous data transfers
• Half-duplex operation for synchronous data transfers
• Programmable interrupt for receive and transmit
16-Bit Timers/Counters
The MAXQ610 provides two timers/counters that support the following functions:
• 16-bit timer/counter
• Independent baud-rate generator
• Programmable 9th bit parity support
• 16-bit up/down autoreload
• Counter function of external pulse
• 16-bit timer with capture
• Start/stop bit support
Serial Peripheral Interface (SPI)
• 16-bit timer with compare
• Input/output enhancements for pulse-width modulation
• Set/reset/toggle output state on comparator match
The integrated SPI provides an independent serial
communication channel that communicates synchronously with peripheral devices in a multiple master or
multiple slave system. The interface allows access to a
4-wire, full-duplex serial bus, and can be operated in
either master mode or slave mode. Collision detection
is provided when two or more masters attempt a data
transfer at the same time.
The maximum SPI master transfer rate is Sysclk/2.
When operating as an SPI slave, the MAXQ610 can
support up to a Sysclk/4 SPI transfer rate. Data is transferred as an 8-bit or 16-bit value, MSB first. In addition,
the SPI module supports configuration of active SSEL
state through the slave active select.
• Prescaler with 2n divider (for n = 0, 2, 4, 6, 8, 10)
General-Purpose I/O
The MAXQ610 provides port pins for general-purpose
I/Os that have the following features:
• CMOS output drivers
• Schmitt trigger inputs
• Optional weak pullup to VDD when operating in input
mode
Table 3. USART Mode Details
MODE
TYPE
START BITS
DATA BITS
STOP BITS
Mode 0
Synchronous
N/A
8
N/A
Mode 1
Asynchronous
1
8
1
Mode 2
Asynchronous
1
8+1
1
Mode 3
Asynchronous
1
8+1
1
______________________________________________________________________________________
17
MAXQ610
While the microcontroller is in a reset state, all port pins
become high impedance with weak pullups disabled,
unless otherwise noted.
From a software perspective, each port appears as a
group of peripheral registers with unique addresses.
Special function pins can also be used as general-purpose I/O pins when the special functions are disabled.
For a detailed description of the special functions available for each pin, refer to the part-specific user manual.
The MAXQ Family User’s Guide: MAXQ610 Supplement
describes all special functions available on the
MAXQ610.
When RXBCNT = 1, the IRV capture operation is disabled and the interrupt flag associated with the capture
no longer denotes a capture. In the carrier burst-count
mode, the IRMT register is now used only to count qualified edges. The IRIF interrupt flag (normally used to signal a capture when RXBCNT = 0) now becomes set if
ever two IRCA cycles elapse without getting a qualified
edge. The IRIF interrupt flag thus denotes absence of
the carrier and the beginning of a space in the receive
signal. When the RXBCNT bit is changed from 0 to 1,
the IRMT register is set to 0001h. The IRCFME bit is still
used to define whether the IRV register is counting system IRCLK clocks or IRCA-defined carrier cycles. The
IRXRL bit is still used to define whether the IRV register
is reloaded with 0000h on detection of a qualified edge
(per the IRXSEL[1:0] bits). Figure 6 and the descriptive
sequence embedded in the figure illustrate the expected usage of the receive burst-count mode.
MAXQ610
16-Bit Microcontroller with Infrared Module
SHIFT
SAMPLE
SHIFT
SAMPLE
SSEL
tMCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tMCH
tMCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tMOH
tMOV
MSB
MOSI
tRF
LSB
MSB-1
tMIS
tMIH
MSB
MISO
tMLH
MSB-1
LSB
Figure 7. SPI Master Communication Timing
SHIFT
SSEL
SAMPLE
SHIFT
SAMPLE
tSSH
tSSE
tSD
tSCK
SCLK
CKPOL/CKPHA
0/1 OR 1/0
tSCH
tSCL
SCLK
CKPOL/CKPHA
0/0 OR 1/1
tSIS
MOSI
tSIH
MSB
MSB-1
tSOV
MISO
MSB
LSB
tRF
MSB-1
tSLH
LSB
Figure 8. SPI Slave Communication Timing
18
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
ty is not required, a commercial gang programmer can
be used for mass programming. Activating the JTAG
interface and loading the test access port (TAP) with
the system programming instruction invokes the bootstrap loader. Setting the SPE bit to 1 during reset
through the JTAG interface executes the bootstraploader-mode program that resides in the utility ROM.
When programming is complete, the bootstrap loader
can clear the SPE bit and reset the device, allowing the
device to bypass the utility ROM and begin execution
of the application software.
An external quartz crystal or a ceramic resonator can
be connected between HFXIN and HFXOUT on the
MAXQ610, as illustrated in Figure 9.
Noise at HFXIN and HFXOUT can adversely affect onchip clock timing. It is good design practice to place
the crystal and capacitors near the oscillator circuitry
and connect HFXIN and HFXOUT to ground with a
direct short trace. The typical values of external capacitors vary with the type of crystal to be used and should
be initially selected based on the load capacitance as
suggested by the crystal manufacturer.
In addition, the ROM loader also enforces the memoryprotection policies. 16-word passwords are required to
access the ROM loader interface.
Loading memory is not possible for ROM-only versions
of the MAXQ610 family.
ROM Loader
The MAXQ610 includes a ROM loader. The loader
denies access to the system, user loader, or user-application memories unless an area-specific password is
provided. The ROM loader is not available in ROM-only
versions of the MAXQ610.
In-Application Flash
Programming
From user-application code, flash can be programmed
using the ROM utility functions from either C or assembly language. The function declarations that follow
show examples of some of the ROM utility functions
provided for in-application flash programming.
Loading Flash Memory
An internal bootstrap loader allows the device to be
reloaded over a simple JTAG interface. As a result,
software can be upgraded in-system, eliminating the
need for a costly hardware retrofit when updates are
required. Remote software uploads are possible that
enable physically inaccessible applications to be frequently updated. The interface hardware can be a
JTAG connection to another microcontroller, or a connection to a PC serial port using a serial-to-JTAG converter, such as the MAXQJTAG-001 available from
Maxim Integrated Products. If in-system programmabili-
/* Write one 16-bit word to code address 'dest'.
* Dest must be aligned to 16 bits.
* Returns 0 = failure, 1 = OK.
*/
int flash_write (uint16_t dest, uint16_t data);
VDD
HFXIN
CLOCK CIRCUIT
STOP
RF
C1
MAXQ610
HFXOUT
C2
RF = 1MΩ ± 50%
C1 = C2 = 30pF
Figure 9. On-Chip Oscillator
______________________________________________________________________________________
19
MAXQ610
On-Chip Oscillator
MAXQ610
16-Bit Microcontroller with Infrared Module
To erase, the following function would be used:
1) Background Mode
/* Erase the given Flash page
* addr: Flash offset (anywhere within page)
*/
• CPU is executing the normal user program.
• Allows the host to configure and set up the in-circuit debugger.
2) Debug Mode
int flash_erasepage(uint16_t addr);
The in-application flash programming must call ROM
utility functions to erase and program any of the flash
memory. Memory protection is enforced by the ROM
utilty functions.
In-application programming is not available in ROMonly versions of the MAXQ610 family.
In-Circuit Debug and JTAG
Interface
Embedded debug hardware and software are developed and integrated into the MAXQ610 to provide full
in-circuit debugging capability in a user application
environment. These hardware and software features
include:
• A debug engine.
• A set of registers providing the ability to set breakpoints on register, code, or data using debug service
routines stored in ROM.
Collectively, these hardware and software features support two modes of in-circuit debug functionality:
MAXQ610
• The debugger takes over the control of the CPU.
• Read/write accesses to internal registers and
memory.
• Single-step of the CPU for trace operation.
The interface to the debug engine is the TAP controller.
The interface allows for communication with a bus master that can either be automatic test equipment or a
component that interfaces to a higher level test bus as
part of a complete system. The communication operates across a 4-wire serial interface from a dedicated
TAP that is compatible to the JTAG IEEE Std 1149. The
TAP provides an independent serial channel to communicate synchronously with the host system.
To prevent unauthorized access of the protected memory regions through the JTAG interface, the debug
engine prevents modification of the privilege registers
and disallows all access to system memory, unless
memory protection is disabled. In addition, all services
(such as register display or modification) are denied
when code is executing inside the system area.
The debugger is not available for ROM-only versions of
the MAXQ610 family.
DEBUG
SERVICE
ROUTINES
(UTILITY ROM)
CPU
DEBUG
ENGINE
TMS
TCK
TDI
TDO
TAP
CONTROLLER
CONTROL
BREAKPOINT
ADDRESS
DATA
Figure 10. In-Circuit Debugger
20
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
The lowest power mode of operation for the MAXQ610
is stop mode. In this mode, CPU state and memories
are preserved, but the CPU is not actively running.
Wake-up sources include external I/O interrupts, the
power-fail warning interrupt, or a power-fail reset. Any
time the microcontroller is in a state where code does
not need to be executed, the user software can put the
MAXQ610 into stop mode. The nanopower ring oscillator is an internal ultra-low-power (400nA), 8kHz ring
oscillator that can be used to drive a wake-up timer that
exits stop mode. The wake-up timer is programmable
by software in steps of 125µs up to approximately 8s.
The power-fail monitor is always on during normal operation. However, it can be selectively disabled during
stop mode to minimize power consumption. This feature is enabled using the power-fail monitor disable
VDD
t < tPFW
t ≥ tPFW
(PFD) bit in the PWCN register. The reset default state
for the PFD bit is 1, which disables the power-fail monitor function during stop mode. If power-fail monitoring
is disabled (PFD = 1) during stop mode, the circuitry
responsible for generating a power-fail warning or reset
is shut down and neither condition is detected. Thus,
the VDD < VRST condition does not invoke a reset state.
However, in the event that VDD falls below the POR
level, a POR is generated. The power-fail monitor is
enabled prior to stop mode exit and before code execution begins. If a power-fail warning condition (VDD <
VPFW) is then detected, the power-fail interrupt flag is
set on stop mode exit. If a power-fail condition is
detected (VDD < VRST), the CPU goes into reset.
Power-Fail Detection
Figures 11, 12, and 13 show the power-fail detection
and response during normal and stop mode operation.
t ≥ tPFW
t ≥ tPFW
C
VPFW
G
VRST
E
F
B
H
D
VPOR
I
A
INTERNAL RESET
(ACTIVE HIGH)
Figure 11. Power-Fail Detection During Normal Operation
______________________________________________________________________________________
21
MAXQ610
Operating Modes
MAXQ610
16-Bit Microcontroller with Infrared Module
Table 4. Power-Fail Detection States During Normal Operation
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
On
Off
Off
—
VDD < V POR.
B
On
On
On
—
VPOR < VDD < VRST.
Crystal warmup time, t XTAL_RDY.
CPU held in reset.
C
On
On
On
—
VDD > VRST.
CPU normal operation.
D
On
On
On
—
Power drop too short.
Power-fail not detected.
—
VRST < VDD < V PFW.
PFI is set when VRST < VDD < VPFW and maintains
this state for at least t PFW, at which time a powerfail interrupt is generated (if enabled).
CPU continues normal operation.
On
On
E
On
F
On
(Periodically)
Off
Off
Yes
G
On
On
On
—
VDD > VRST.
Crystal warmup time, t XTAL_RDY.
CPU resumes normal operation from 8000h.
H
On
(Periodically)
Off
Off
Yes
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor is turned on periodically.
I
Off
Off
Off
—
If a reset is caused by a power-fail, the power-fail monitor can be set to one of the following intervals:
• Always on—continuous monitoring
• 211 nanopower ring oscillator clocks (~256ms)
• 212 nanopower ring oscillator clocks (~512ms)
• 213 nanopower ring oscillator clocks (~1.024s)
In the case where the power-fail circuitry is periodically
turned on, the power-fail detection is turned on for two
nanopower ring oscillator cycles. If VDD > VRST during
22
COMMENTS
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor turns on periodically.
VDD < V POR.
Device held in reset.
No operation allowed.
detection, VDD is monitored for an additional nanopower ring oscillator period. If VDD remains above VRST for
the third nanopower ring period, the CPU exits the reset
state and resumes normal operation from utility ROM at
8000h after satisfying the crystal warmup period.
If a reset is generated by any other event, such as the
RESET pin being driven low externally or the watchdog
timer, the power-fail, internal regulator, and crystal
remain on during the CPU reset. In these cases, the
CPU exits the reset state in less than 20 crystal cycles
after the reset source is removed.
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
t < tPFW
A
t ≥ tPFW
MAXQ610
VDD
t ≥ tPFW
VPFW
D
VRST
B
C
E
VPOR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
Figure 12. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
Table 5. Stop Mode Power-Fail Detection States with Power-Fail Monitor Enabled
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
On
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
B
On
Off
Off
Yes
Power drop too short.
Power-fail not detected.
COMMENTS
C
On
On
On
Yes
VRST < VDD < V PFW.
Power-fail warning detected.
Turn on regulator and crystal.
Crystal warmup time, t XTAL_RDY.
Exit stop mode.
D
On
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
E
On
(Periodically)
Off
Off
Yes
VPOR < VDD < VRST.
Power-fail detected.
CPU goes into reset.
Power-fail monitor is turned on periodically.
F
Off
Off
Off
—
VDD < V POR.
Device held in reset. No operation allowed.
______________________________________________________________________________________
23
MAXQ610
16-Bit Microcontroller with Infrared Module
VDD
A
D
VPFW
B
VRST
C
E
VPOR
F
STOP
INTERNAL RESET
(ACTIVE HIGH)
INTERRUPT
Figure 13. Stop Mode Power-Fail Detection with Power-Fail Monitor Disabled
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
A
Off
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
B
Off
Off
Off
Yes
VDD < V PFW.
Power-fail not detected because power-fail
monitor is disabled.
Yes
VRST < VDD < V PFW.
An interrupt occurs that causes the CPU to exit
stop mode.
Power-fail monitor is turned on, detects a powerfail warning, and sets the power-fail interrupt flag.
Turn on regulator and crystal.
Crystal warmup time, t XTAL_RDY.
On stop mode exit, CPU vectors to the higher
priority of power-fail and the interrupt that causes
stop mode exit.
C
24
On
On
On
COMMENTS
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
STATE
POWER-FAIL
INTERNAL
REGULATOR
CRYSTAL
OSCILLATOR
SRAM
RETENTION
D
Off
Off
Off
Yes
Application enters stop mode.
VDD > VRST.
CPU in stop mode.
VPOR < VDD < VRST.
An interrupt occurs that causes the CPU to exit
stop mode.
Power-fail monitor is turned on, detects a powerfail, puts CPU in reset.
Power-fail monitor is turned on periodically.
E
On
(Periodically)
Off
Off
Yes
F
Off
Off
Off
—
COMMENTS
VDD < V POR
Device held in reset. No operation allowed.
Applications Information
Differences for ROM Versions
The low-power, high-performance RISC architecture of
this device makes it an excellent fit for many portable or
battery-powered applications. It is ideally suited for
applications such as universal remote controls that
require the cost-effective integration of IR transmit/
receive capability.
The ROM-only versions of the MAXQ610 family devices
operate in the same manner as their flash counterparts
with the following exceptions:
• The ROM loader is not available in the ROM version.
• Loading memory and in-application programming
are not supported.
Grounds and Bypassing
Careful PCB layout significantly minimizes system-level
digital noise that could interact with the microcontroller
or peripheral components. The area under any digital
components should be a continuous ground plane if
possible. Keep any bypass capacitor leads short for
best noise rejection and place the capacitors as close
to the leads of the devices as possible.
CMOS design guidelines for any semiconductor require
that no pin be taken above V DD or below GND.
Violation of this guideline can result in a hard failure
(damage to the silicon inside the device) or a soft failure (unintentional modification of memory contents).
Voltage spikes above or below the device’s absolute
maximum ratings can potentially cause a devastating
IC latchup.
Microcontrollers commonly experience negative voltage spikes through either their power pins or generalpurpose I/O pins. Negative voltage spikes on power
pins are especially problematic as they directly couple
to the internal power buses. Devices such as keypads
can conduct electrostatic discharges directly into the
microcontroller and seriously damage the device.
System designers must protect components against
these transients that can corrupt system memory.
• The debugger is not available in the ROM version.
Additional Documentation
Designers must have the following documents to fully
use all the features of this device. This data sheet contains pin descriptions, feature overviews, and electrical
specifications. Errata sheets contain deviations from
published specifications. The user’s guides offer
detailed information about device features and operation. The following documents can be downloaded from
www.maxim-ic.com/microcontrollers.
• This MAXQ610 data sheet, which contains electrical/
timing specifications and pin descriptions.
• The MAXQ610 revision-specific errata sheet
(www.maxim-ic.com/errata).
• The MAXQ Family User's Guide , which contains
detailed information on core features and operation,
including programming.
• The MAXQ Family User's Guide: MAXQ610
Supplement, which contains detailed information on
features specific to the MAXQ610.
______________________________________________________________________________________
25
MAXQ610
Table 6. Stop Mode Power-Fail Detection States with Power-Fail Monitor Disabled (continued)
Development and Technical
Support
Maxim and third-party suppliers provide a variety of
highly versatile, affordably priced development tools for
this microcontroller, including the following:
• Compilers
• In-circuit emulators
• Integrated Development Environments (IDEs)
• JTAG-to-serial converters for programming and
debugging
A partial list of development tool vendors can be found
at www.maxim-ic.com/MAXQ_tools.
Technical support is available at www.maximic.com/support.
15
13
REGOUT
4
5
6
7
8
P0.2/TX0
P0.3/RX1
P0.4/TX1
P0.5/TBA0/TBA1
P0.6/TBB0
P0.7/TBB1
17 REGOUT
16 P3.3/INT11
P2.6/TMS 35
12
P1.3/INT3
11
P1.2/INT2
10
P1.1/INT1
VDD 38
9
P1.0/INT0
IRTX 39
12 P1.1/INT1
IRRX 40
11 P1.0/INT0
MAXQ610
P2.7/TDO 36
15 P3.2/INT10
14 P1.3/INT3
RESET 37
1
2
3
4
5
6
7
8
THIN QFN
(6mm × 6mm)
THIN QFN
(5mm × 5mm)
*EXPOSED PAD = GND.
13 P1.2/INT2
*EP
+
9
10
P0.7/TBB1
3
P3.7/INT15 34
P0.6/TBB0
2
18 VDD
P0.5/TBA0/TAB1
1
P0.1/RX0
IRRX 32
P3.6/INT14 33
P0.4/TX1
*EP
+
HFXIN
19 P1.4/INT4
P2.7/TDO 28
IRTX 31
HFXOUT
P1.4/INT4
VDD
VDD 30
P1.6/INT6
20 P1.5/INT5
P2.5/TDI 32
14
MAXQ610
P1.7/INT7
P2.4/TCK 31
P2.6/TMS 27
RESET 29
P2.0/MOSI
P1.5/INT5
P0.3/RX1
P2.5/TDI 26
P3.4/INT12
30 29 28 27 26 25 24 23 22 21
16
P2.4/TCK 25
P2.1/MISO
17
P0.2/TX0
18
P3.5/INT13
HFXIN
19
P0.1/RX0
HFXOUT
20
P3.1/INT9
P1.6/INT6
21
P2.2/SCLK
P1.7/INT7
22
P2.3/SSEL
P2.0/MOSI
23
P3.0/INT8
P2.1/MISO
24
TOP VIEW
P0.0/IRTXM
P2.2/SCLK
TOP VIEW
P2.3/SSEL
Pin Configurations
P0.0/IRTXM
MAXQ610
16-Bit Microcontroller with Infrared Module
*EXPOSED PAD = GND.
Selector Guide
OPERATING VOLTAGE
(V)
PROGRAM MEMORY
(KB)
DATA MEMORY
(KB)
MAXQ610A-0000+
1.70 to 3.6
64 Flash
2
32 TQFN-EP
MAXQ610B-0000+
1.70 to 3.6
64 Flash
2
40 TQFN-EP
MAXQ610X-0000+
1.70 to 3.6
64 Flash
2
Bare die
PART
PIN-PACKAGE
Note: Contact factory for information about masked ROM devices.
26
______________________________________________________________________________________
16-Bit Microcontroller with Infrared Module
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
32 TQFN-EP
T3255+3
21-0140
40 TQFN-EP
T4066+2
21-0141
______________________________________________________________________________________
27
MAXQ610
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
MAXQ610
16-Bit Microcontroller with Infrared Module
Revision History
REVISION
NUMBER
REVISION
DATE
0
10/08
1
2
3
11/08
1/09
7/09
DESCRIPTION
Initial release.
PAGES
CHANGED
—
Removed the Sysclk = 1MHz condition for the Active Current parameter,
changed the RPU min values from 18k and 19k to 16k and 17k, and
changed the fNANO TA = +25°C min and max values from 4.2kHz and 14.0kHz
to 3.0kHz and 20.0kHz, respectively, in the Recommended DC Operating
Conditions table.
4, 5
Added the sentence “Software must configure this pin after release from reset to
remove the high-impedance input condition.” to the IRRX, P0.x, P1.x, P2.x, and
P3.x descriptions in the Pin Description table.
8, 9
Added future status to the 32 TQFN package in the Ordering Information table.
1
In the Pin Description table, changed the REGOUT pin series resistance from
1 to 2 to 10.
8
Changed the t IRRX_A minimum spec from 200ns to 300ns in the Recommended
DC Operating Conditions table.
5
Removed the statement about the use of multilayer boards from the Grounds
and Bypassing section.
25
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.