Continuous Rate 10 Mb/s to 1.25 Gb/s Clock and Data Recovery IC ADN2815 FEATURES GENERAL DESCRIPTION Serial data input: 10 Mb/s to 1.25 Gb/s Exceeds SONET requirements for jitter transfer/ generation/tolerance Patented clock recovery architecture No reference clock required Loss-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.3 V Low power: 390 mW typical 5 mm × 5 mm 32-lead LFCSP, Pb free The ADN2815 provides the receiver functions of quantization and clock and data recovery for continuous data rates from 10 Mb/s to 1.25 Gb/s. The ADN2815 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are met, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. The ADN2815 is available in a compact 5 mm × 5 mm 32-lead LFCSP. APPLICATIONS SONET OC-1/-3/-12 and all associated FEC rates Fibre Channel, GbE, HDTVs WDM transponders Regenerators/repeaters Test equipment Broadband crossconnects and routers FUNCTIONAL BLOCK DIAGRAM REFCLKP/REFCLKN (OPTIONAL) LOL CF1 CF2 FREQUENCY DETECT LOOP FILTER PHASE DETECT LOOP FILTER VCC VEE PIN NIN BUFFER PHASE SHIFTER VCO VREF 2 2 DATAOUTP/ DATAOUTN CLKOUTP/ CLKOUTN ADN2815 DRVCC DRVEE DVCC DVEE 04952-0-001 DATA RE-TIMING Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADN2815 TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 12 Applications....................................................................................... 1 Functional Description.................................................................. 14 General Description ......................................................................... 1 Frequency Acquisition............................................................... 14 Functional Block Diagram .............................................................. 1 Input Buffer................................................................................. 14 Revision History ............................................................................... 2 Lock Detector Operation .......................................................... 14 Specifications..................................................................................... 3 Harmonic Detector .................................................................... 15 Jitter Specifications....................................................................... 4 SQUELCH Mode........................................................................ 15 Output and Timing Specifications ............................................. 5 I2C Interface ................................................................................ 15 Absolute Maximum Ratings............................................................ 6 Reference Clock (Optional) ...................................................... 16 Thermal Characteristics .............................................................. 6 Applications Information .............................................................. 19 ESD Caution.................................................................................. 6 PCB Design Guidelines ............................................................. 19 Timing Characteristics..................................................................... 7 Coarse Data Rate Readback Look-Up Table............................... 22 Pin Configuration and Function Descriptions............................. 8 Outline Dimensions ....................................................................... 24 I2C Interface Timing and Internal Register Description............. 9 Ordering Guide .......................................................................... 24 Jitter Specifications ......................................................................... 11 REVISION HISTORY 9/05—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADN2815 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 1. Parameter QUANTIZER—DC CHARACTERISTICS Input Voltage Range Peak-to-Peak Differential Input Input Common-Mode Level QUANTIZER—AC CHARACTERISTICS Data Rate S11 Input Resistance Input Capacitance LOSS-OF-LOCK (LOL) DETECT VCO Frequency Error for LOL Assert VCO Frequency Error for LOL Deassert LOL Response Time ACQUISITION TIME Lock-to-Data Mode Optional Lock to REFCLK Mode DATA RATE READBACK ACCURACY Coarse Readback Fine Readback POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT OPERATING TEMPERATURE RANGE Conditions Min @ PIN or NIN, dc-coupled PIN − NIN DC-coupled 1.8 0.2 2.3 Typ Max Unit 2.5 2.8 2.0 2.8 V V V 1250 @ 2.5 GHz Differential 10 −15 100 0.65 Mb/s dB Ω pF With respect to nominal With respect to nominal 10 Mb/s OC-12 GbE 1000 250 4 200 200 ppm ppm ms μs μs GbE OC-12 OC-3 OC-1 10 Mb/s 1.5 2.0 3.4 9.8 40.0 20.0 ms ms ms ms ms ms See Table 13 In addition to REFCLK accuracy Data rate ≤ 20 Mb/s Data rate > 20 Mb/s 10 % 3.0 Locked to 1.25 Gb/s –40 Rev. 0 | Page 3 of 24 3.3 118 200 100 3.6 131 +85 ppm ppm V mA °C ADN2815 JITTER SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1, unless otherwise noted. Table 2. Parameter PHASE-LOCKED LOOP CHARACTERISTICS Jitter Transfer BW Jitter Peaking Jitter Generation Conditions Min OC-12 OC-3 OC-12 OC-3 OC-12, 12 kHz to 5 MHz OC-3, 12 kHz to 1.3 MHz Jitter Tolerance 1 GbE, IEEE 802.3 637 kHz OC-12, 223 − 1 PRBS 30 Hz 1 300 Hz1 25 kHz 250 kHz1 OC-3, 223 − 1 PRBS 30 Hz1 300 Hz1 6500 Hz 65 kHz1 Max Unit 75 26 0 0 0.001 0.011 0.001 0.005 130 42 0.03 0.03 0.003 0.026 0.002 0.010 kHz kHz dB dB UI rms UI p-p UI rms UI p-p 0.749 UI p-p 100 44 2.5 1.0 UI p-p UI p-p UI p-p UI p-p 50 24 3.5 1.0 UI p-p UI p-p UI p-p UI p-p Jitter tolerance of the ADN2815 at these jitter frequencies is better than what the test equipment is able to measure. Rev. 0 | Page 4 of 24 Typ ADN2815 OUTPUT AND TIMING SPECIFICATIONS Table 3. Parameter LVDS OUTPUT CHARACTERISTICS (CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN) Output Voltage High Output Voltage Low Differential Output Swing Differential Output Swing Output Offset Voltage Output Impedance LVDS Outputs Timing Rise Time Fall Time Setup Time Hold Time I2C INTERFACE DC CHARACTERISTICS Input High Voltage Input Low Voltage Input Current Output Low Voltage I2C INTERFACE TIMING SCK Clock Frequency SCK Pulse Width High SCK Pulse Width Low Start Condition Hold Time Start Condition Setup Time Data Setup Time Data Hold Time SCK/SDA Rise/Fall Time Stop Condition Setup Time Bus Free Time Between a Stop and a Start REFCLK CHARACTERISTICS Input Voltage Range Minimum Differential Input Drive Reference Frequency Required Accuracy LVTTL DC INPUT CHARACTERISTICS Input High Voltage Input Low Voltage Input High Current Input Low Current LVTTL DC OUTPUT CHARACTERISTICS Output High Voltage Output Low Voltage 1 Conditions Min VOH (see Figure 3), 655 Mb/s VOL (see Figure 3), 655 Mb/s VOD (see Figure 3), 655 Mb/s VOD (see Figure 3), 1.25 Gb/s VOS (see Figure 3) Differential 925 250 240 1125 20% to 80% 80% to 20% TS (see Figure 2), GbE TH (see Figure 2), GbE LVCMOS VIH VIL VIN = 0.1 VCC or VIN = 0.9 VCC VOL, IOL = 3.0 mA See Figure 10 360 360 Typ Max Unit 1475 mV mV mV mV mV Ω 320 300 1200 100 400 400 1275 115 115 400 400 220 220 440 440 ps ps ps ps 0.3 VCC +10.0 0.4 V V μA V 0.7 VCC −10.0 400 tHIGH tLOW tHD;STA tSU;STA tSU;DAT tHD;DAT TR/TF tSU;STO tBUF Optional lock to REFCLK mode @ REFCLKP or REFCLKN VIL VIH 600 1300 600 600 100 300 20 + 0.1 Cb 1 600 1300 300 0 VCC 100 10 160 100 VIH VIL IIH, VIN = 2.4 V IIL, VIN = 0.4 V 2.0 VOH, IOH = −2.0 mA VOL, IOL = 2.0 mA 2.4 Cb = total capacitance of one bus line in pF. If mixed with Hs-mode devices, faster fall-times are allowed. Rev. 0 | Page 5 of 24 0.8 5 −5 0.4 kHz ns ns ns ns ns ns ns ns ns V V mV p-p MHz ppm V V μA μA V V ADN2815 ABSOLUTE MAXIMUM RATINGS TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted. Table 4. Parameter Supply Voltage (VCC) Minimum Input Voltage (All Inputs) Maximum Input Voltage (All Inputs) Maximum Junction Temperature Storage Temperature Range Rating 4.2 V VEE − 0.4 V VCC + 0.4 V 125°C −65°C to +150°C Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICS Thermal Resistance 32-LFCSP, 4-layer board with exposed paddle soldered to VEE, θJA = 28°C/W. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 24 ADN2815 TIMING CHARACTERISTICS CLKOUTP TH 04952-0-002 TS DATAOUTP/ DATAOUTN Figure 2. Output Timing DIFFERENTIAL CLKOUTP/N, DATAOUTP/N VOH VOS 04952-0-032 |VOD| VOL Figure 3. Differential Output Specifications 5mA RLOAD 100Ω VDIFF 100Ω SIMPLIFIED LVDS OUTPUT STAGE Figure 4. Differential Output Stage Rev. 0 | Page 7 of 24 04952-0-033 5mA ADN2815 32 TEST2 31 VCC 30 VEE 29 DATAOUTP 28 DATAOUTN 27 SQUELCH 26 CLKOUTP 25 CLKOUTN PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADN2815* TOP VIEW (Not to Scale) 24 VCC 23 VEE 22 NC 21 SDA 20 SCK 19 SADDR5 18 VCC 17 VEE 04952-0-004 PIN 1 INDICATOR NC 9 REFCLKP 10 REFCLKN 11 VCC 12 VEE 13 CF2 14 CF1 15 LOL 16 TEST1 1 VCC 2 VREF 3 NIN 4 PIN 5 NC 6 NC 7 VEE 8 * THERE IS AN EXPOSED PAD ON THE BOTTOM OF THE PACKAGE THAT MUST BE CONNECTED TO GND. Figure 5. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3 4 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Exposed Pad 1 Mnemonic TEST1 VCC VREF NIN PIN NC VEE NC REFCLKP REFCLKN VCC VEE CF2 CF1 LOL VEE VCC SADDR5 SCK SDA NC VEE VCC CLKOUTN CLKOUTP SQUELCH DATAOUTN DATAOUTP VEE VCC TEST2 Pad Type 1 P AO AI AI P DI DI P P AO AO DO P P DI DI DI P P DO DO DI DO DO P P P Description Connect to VCC. Power for Limiting Amplifier, LOS. Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor. Differential Data Input. CML. Differential Data Input. CML. No Connect. GND for Limiting Amplifier, LOS. No Connect. Differential REFCLK Input. 10 MHz to 160 MHz. Differential REFCLK Input. 10 MHz to 160 MHz. VCO Power. VCO GND. Frequency Loop Capacitor. Frequency Loop Capacitor. Loss-of-Lock Indicator. LVTTL active high. FLL Detector GND. FLL Detector Power. Slave Address Bit 5. I2C Clock Input. I2C Data Input. No Connect. Output Buffer, I2C GND. Output Buffer, I2C Power. Differential Recovered Clock Output. LVDS. Differential Recovered Clock Output. LVDS. Disable Clock and Data Outputs. Active high. LVTTL. Differential Recovered Data Output. LVDS. Differential Recovered Data Output. LVDS. Phase Detector, Phase Shifter GND. Phase Detector, Phase Shifter Power. Connect to VCC. Connect to GND. Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output. Rev. 0 | Page 8 of 24 ADN2815 I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION 1 A5 MSB = 1 SET BY PIN 19 0 0 0 0 0 X 0 = WR 1 = RD 04952-0-007 R/W CTRL. SLAVE ADDRESS [6...0] S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S) DATA A(S) P 04952-0-008 Figure 6. Slave Address Configuration 2 S SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR S = START BIT A(S) = ACKNOWLEDGE BY SLAVE A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA A(M) DATA A(M) P P = STOP BIT A(M) = LACK OF ACKNOWLEDGE BY MASTER A(M) = ACKNOWLEDGE BY MASTER 04952-0-009 Figure 7. I C Write Data Transfer Figure 8. I2C Read Data Transfer SDA SLAVE ADDRESS A6 SUB ADDRESS A5 A7 STOP BIT DATA A0 D7 D0 SCK S WR ACK ACK SLADDR[4...0] SUB ADDR[6...1] ACK DATA[6...1] Figure 9. I2C Data Transfer Timing tF tSU;DAT tHD;STA tBUF SDA tR tR tSU;STO tF tLOW tHIGH tHD;STA S tSU;STA S tHD;DAT Figure 10. I2C Port Timing Diagram Rev. 0 | Page 9 of 24 P S 04952-0-011 SCK P 04952-0-010 START BIT ADN2815 Table 6. Internal Register Map 1 Reg Name FREQ0 FREQ1 FREQ2 RATE MISC R/W R R R R R Address 0x0 0x1 0x2 0x3 0x4 D7 D6 D5 MSB MSB 0 MSB COARSE_RD[8] MSB x x x CTRLA CTRLB W W 0x8 0x9 CTRLC W 0x11 FREF Range Config Reset LOL MISC[4] 0 0 1 D4 D3 D2 D1 Coarse Data Rate Readback Static LOL Data Rate LOL Status Measure Complete Data Rate/DIV_FREF Ratio 0 System 0 Reset Reset MISC[2] 0 0 0 0 D0 LSB LSB LSB COARSE_RD[1] COARSE_RD[0] LSB x Measure Data Rate 0 Lock to Reference 0 SQUELCH Mode Output Boost All writeable registers default to 0x00. Table 7. Miscellaneous Register, MISC D7 x D6 x D5 x Static LOL D4 0 = Waiting for next LOL 1 = Static LOL until reset LOL Status D3 0 = Locked 1 = Acquiring Data Rate Measurement Complete D2 0 = Measuring data rate 1 = Measurement complete D1 x Coarse Rate Readback LSB D0 COARSE_RD[0] Table 8. Control Register, CTRLA 1 FREF Range D7 D6 0 0 0 1 1 0 1 1 1 Data Rate/Div_FREF Ratio D5 D4 D3 D2 0 0 0 0 0 0 0 1 0 0 1 0 n 1 0 0 0 10 MHz to 20 MHz 20 MHz to 40 MHz 40 MHz to 80 MHz 80 MHz to 160 MHz 1 2 4 2n 256 Measure Data Rate D1 Set to 1 to measure data rate Lock to Reference D0 0 = Lock to input data 1 = Lock to reference clock Where DIV_FREF is the divided down reference referred to the 10 MHz to 20 MHz band (see the Reference Clock (Optional) section). Table 9. Control Register, CTRLB Config LOL D7 0 = LOL pin normal operation 1 = LOL pin is static LOL Reset MISC[4] D6 Write a 1 followed by 0 to reset MISC[4] System Reset D5 Write a 1 followed by 0 to reset ADN2815 D4 Set to 0 Reset MISC[2] D3 Write a 1 followed by 0 to reset MISC[2] D2 Set to 0 D1 Set to 0 D0 Set to 0 Table 10. Control Register, CTRLC D7 Set to 0 D6 Set to 0 D5 Set to 0 D4 Set to 0 D3 Set to 0 D2 Set to 0 SQUELCH Mode D1 0 = SQUELCH CLK and DATA 1 = SQUELCH CLK or DATA Rev. 0 | Page 10 of 24 Output Boost D0 0 = Default output swing 1 = Boost output swing ADN2815 JITTER SPECIFICATIONS Jitter Transfer The jitter transfer function is the ratio of the jitter on the output signal to the jitter applied on the input signal vs. the frequency. This parameter measures the limited amount of the jitter on an input signal that can be transferred to the output signal (see Figure 11). fC JITTER FREQUENCY (kHz) Figure 11. Jitter Transfer Curve Jitter Tolerance The jitter tolerance is defined as the peak-to-peak amplitude of the sinusoidal jitter applied on the input signal, which causes a 1 dB power penalty. This is a stress test intended to ensure that no additional penalty is incurred under the operating conditions (see Figure 12). 15.00 SLOPE = –20dB/DECADE 1.50 0.15 f0 f1 f2 f3 JITTER FREQUENCY (kHz) Figure 12. SONET Jitter Tolerance Mask Rev. 0 | Page 11 of 24 f4 04952-0-016 Jitter Generation The jitter generation specification limits the amount of jitter that can be generated by the device with no jitter and wander applied at the input. For SONET devices, the jitter generated must be less than 0.01 UI rms, and must be less than 0.1 UI p-p. SLOPE = –20dB/DECADE ACCEPTABLE RANGE 04952-0-015 The following sections briefly summarize the specifications of jitter generation, transfer, and tolerance in accordance with the Telcordia document (GR-253-CORE, Issue 3, September 2000) for the optical interface at the equipment level and the ADN2815 performance with respect to those specifications. JITTER GAIN (dB) Jitter is the dynamic displacement of digital signal edges from their long-term average positions, measured in unit intervals (UI), where 1 UI = 1 bit period. Jitter on the input data can cause dynamic phase errors on the recovered clock sampling edge. Jitter on the recovered clock causes jitter on the retimed data. 0.1 INPUT JITTER AMPLITUDE (UI p-p) The ADN2815 CDR is designed to achieve the best bit-errorrate (BER) performance and exceeds the jitter transfer, generation, and tolerance specifications proposed for SONET/SDH equipment defined in the Telcordia Technologies specification. ADN2815 THEORY OF OPERATION Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second-order phase-locked loop, and this zero is placed in the feedback path and, thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second-order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. Because this circuit has no zero in the closed-loop transfer, jitter peaking is minimized. INPUT DATA X(s) e(s) d/sc o/s 1/n Z(s) RECOVERED CLOCK d = PHASE DETECTOR GAIN o = VCO GAIN c = LOOP INTEGRATOR psh = PHASE SHIFTER GAIN n = DIVIDE RATIO JITTER TRANSFER FUNCTION Z(s) 1 = cn n psh X(s) s2 +s +1 do o 04952-0-017 TRACKING ERROR TRANSFER FUNCTION e(s) s2 = d psh do X(s) 2 s +s + c cn Figure 13. ADN2815 PLL/DLL Architecture JITTER PEAKING IN ORDINARY PLL ADN2815 Z(s) X(s) o n psh d psh c 04952-0-018 The delay and phase loops together track the phase of the input data signal. For example, when the clock lags input data, the phase detector drives the VCO to a higher frequency and increases the delay through the phase shifter; both of these actions serve to reduce the phase error between the clock and data. The faster clock picks up phase, while the delayed data loses phase. Because the loop filter is an integrator, the static phase error is driven to zero. psh JITTER GAIN (dB) The ADN2815 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops that share a common control voltage. A high speed delay-locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter. A separate phase control loop, comprised of the VCO, tracks the low frequency components of input jitter. The initial frequency of the VCO is set by yet a third loop, which compares the VCO frequency with the input data frequency and sets the coarse tuning voltage. The jitter tracking phase-locked loop (PLL) controls the VCO by the fine-tuning control. FREQUENCY (kHz) The delay and phase loops together simultaneously provide wideband jitter accommodation and narrow-band jitter filtering. The linearized block diagram in Figure 13 shows that the jitter transfer function, Z(s)/X(s), is a second-order low-pass providing excellent filtering. Note that the jitter transfer has no zero, unlike an ordinary second-order phase-locked loop. This means that the main PLL has virtually zero jitter peaking (see Figure 14). This makes this circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. The error transfer, e(s)/X(s), has the same high-pass form as an ordinary phase-locked loop. This transfer function is free to be optimized to give excellent wideband jitter accommodation, because the jitter transfer function, Z(s)/X(s), provides the narrow-band jitter filtering. Figure 14. ADN2815 Jitter Response vs. Conventional PLL The delay and phase loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. In this case, the VCO is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. The amount of low frequency jitter that can be tracked is a function of the VCO tuning range. A wider tuning range gives larger accommodation of low frequency jitter. The internal loop control voltage remains small for small phase errors; therefore, the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation. Rev. 0 | Page 12 of 24 ADN2815 At medium jitter frequencies, the gain and tuning range of the VCO are not large enough to track input jitter. In this case, the VCO control voltage becomes large and saturates, and the VCO frequency dwells at one extreme of its tuning range or at the other. The size of the VCO tuning range, therefore, has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and therefore the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve. The phase shifter has a minimum range of 2 UI at all data rates. The gain of the loop integrator is small for high jitter frequencies; therefore, larger phase differences are needed to make the loop control voltage large enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region, the gain of the integrator determines the jitter accommodation. Because the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5 UI in this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 1.5 MHz at 1.25 Gb/s. Rev. 0 | Page 13 of 24 ADN2815 FUNCTIONAL DESCRIPTION FREQUENCY ACQUISITION Once LOL is deasserted, the frequency-locked loop is turned off. The PLL/DLL pulls in the VCO frequency the rest of the way until the VCO frequency equals the data frequency. The frequency loop requires a single external capacitor between CF1 and CF2, Pin 14 and Pin 15. A 0.47 μF ± 20%, X7R ceramic chip capacitor with < 10 nA leakage current is recommended. Leakage current of the capacitor can be calculated by dividing the maximum voltage across the 0.47 μF capacitor, ~3 V, by the insulation resistance of the capacitor. The insulation resistance of the 0.47 μF capacitor should be greater than 300 MΩ. INPUT BUFFER The input buffer has differential inputs (PIN/NIN), which are internally terminated with 50 Ω to an on-chip voltage reference (VREF = 2.5 V typically). The minimum differential input level required to achieve a BER of 10−10 is 200 mV p-p. LOCK DETECTOR OPERATION The lock detector on the ADN2815 has three modes of operation: normal mode, REFCLK mode, and static LOL mode. Normal Mode In normal mode, the ADN2815 is a continuous rate CDR that locks onto any data rate from 10 Mb/s to 1.25 Gb/s without the use of a reference clock as an acquisition aid. In this mode, the lock detector monitors the frequency difference between the VCO and the input data frequency, and deasserts the loss-oflock signal, which appears on Pin 16 (LOL), when the VCO is within 250 ppm of the data frequency. This enables the D/PLL, which pulls the VCO frequency in the remaining amount and acquires phase lock. Once locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss-of-lock signal is reasserted and control returns to the frequency loop, which begins a new frequency acquisition starting at the lowest point in the VCO operating range, 10 MHz. The LOL pin remains asserted until the VCO locks onto a valid input data stream to within 250 ppm frequency error. This hysteresis is shown in Figure 15. LOL 1 –1000 –250 0 250 1000 fVCO ERROR (ppm) 04952-0-020 The ADN2815 acquires frequency from the data over a range of data frequencies from 10 Mb/s to 1.25 Gb/s. The lock detector circuit compares the frequency of the VCO and the frequency of the incoming data. When these frequencies differ by more than 1000 ppm, LOL is asserted. This initiates a frequency acquisition cycle. The VCO frequency is reset to the bottom of its range, which is 10 MHz. The frequency detector then compares this VCO frequency and the incoming data frequency and increments the VCO frequency, if necessary. Initially, the VCO frequency is incremented in large steps to aid fast acquisition. As the VCO frequency approaches the data frequency, the step size is reduced until the VCO frequency is within 250 ppm of the data frequency, at which point LOL is deasserted. Figure 15. Transfer Function of LOL LOL Detector Operation Using a Reference Clock In REFCLK mode, a reference clock is used as an acquisition aid to lock the ADN2815 VCO. Lock-to-reference mode is enabled by setting CTRLA[0] to 1. The user also needs to write to the CTRLA[7:6] and CTRLA[5:2] bits to set the reference frequency range and the divide ratio of the data rate with respect to the reference frequency. For more details, see the Reference Clock (Optional) section. In this mode, the lock detector monitors the difference in frequency between the divided down VCO and the divided down reference clock. The loss-of-lock signal, which appears on Pin 16 (LOL), is deasserted when the VCO is within 250 ppm of the desired frequency. This enables the D/PLL, which pulls the VCO frequency in the remaining amount with respect to the input data and acquires phase lock. Once locked, if the input frequency error exceeds 1000 ppm (0.1%), the loss-of-lock signal is reasserted and control returns to the frequency loop, which reacquires with respect to the reference clock. The LOL pin remains asserted until the VCO frequency is within 250 ppm of the desired frequency. This hysteresis is shown in Figure 15. Static LOL Mode The ADN2815 implements a static LOL feature, which indicates if a loss-of-lock condition has ever occurred and remains asserted, even if the ADN2815 regains lock, until the static LOL bit is manually reset. The I2C register bit, MISC[4], is the static LOL bit. If there is ever an occurrence of a loss-of-lock condition, this bit is internally asserted to logic high. The MISC[4] bit remains high even after the ADN2815 has reacquired lock to a new data rate. This bit can be reset by writing a 1 followed by 0 to I2C Register Bit CTRLB[6]. Once reset, the MISC[4] bit remains deasserted until another loss-oflock condition occurs. Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin, Pin 16, to become a static LOL indicator. In this mode, the LOL pin mirrors the contents of the MISC[4] bit and has the functionality described in the previous paragraph. Rev. 0 | Page 14 of 24 ADN2815 The CTRLB[7] bit defaults to 0. In this mode, the LOL pin operates in the normal operating mode, that is, it is asserted only when the ADN2815 is in acquisition mode and deasserts when the ADN2815 has reacquired lock. HARMONIC DETECTOR The ADN2815 provides a harmonic detector, which detects whether or not the input data has changed to a lower harmonic of the data rate that the VCO is currently locked onto. For example, if the input data instantaneously changes from OC-12, 622.08Mb/s to an OC-3, 155.52 Mb/s bit stream, this could be perceived as a valid OC-12 bit stream, because the OC-3 data pattern is exactly 4× slower than the OC-12 pattern. Therefore, if the change in data rate is instantaneous, a 101 pattern at OC-3 would be perceived by the ADN2815 as a 111100001111 pattern at OC-12. If the change to a lower harmonic is instantaneous, a typical CDR could remain locked at the higher data rate. The ADN2815 implements a harmonic detector that automatically identifies whether or not the input data has switched to a lower harmonic of the data rate that the VCO is currently locked onto. When a harmonic is identified, the LOL pin is asserted and a new frequency acquisition is initiated. The ADN2815 automatically locks onto the new data rate, and the LOL pin is deasserted. However, the harmonic detector does not detect higher harmonics of the data rate. If the input data rate switches to a higher harmonic of the data rate, then the VCO is currently locked onto, the VCO loses lock, the LOL pin is asserted, and a new frequency acquisition is initiated. The ADN2815 automatically locks onto the new data rate. The time to detect lock to harmonic is 216 × (Td/ρ) where: 1/Td is the new data rate. For example, if the data rate is switched from OC-12 to OC-3, then Td = 1/155.52 MHz. ρ is the data transition density. Most coding schemes seek to ensure that ρ = 0.5, for example, PRBS, 8B/10B. When the ADN2815 is placed in lock to reference mode, the harmonic detector is disabled. SQUELCH MODE Two SQUELCH modes are available with the ADN2815. SQUELCH DATAOUT and CLKOUT mode is selected when CTRLC[1] = 0 (default mode). In this mode, when the SQUELCH input, Pin 27, is driven to a TTL high state, both the clock and data outputs are set to the zero state to suppress downstream processing. If the SQUELCH function is not required, Pin 27 should be tied to VEE. SQUELCH DATAOUT or CLKOUT mode is selected when CTRLC[1] is 1. In this mode, when the SQUELCH input is driven to a high state, the DATAOUTN/DATAOUTP pins are squelched. When the SQUELCH input is driven to a low state, the CLKOUT pins are squelched. This is especially useful in repeater applications, where the recovered clock may not be needed. I2C INTERFACE The ADN2815 supports a 2-wire, I2C compatible, serial bus driving multiple peripherals. Two inputs, serial data (SDA) and serial clock (SCK), carry information between any devices connected to the bus. Each slave device is recognized by a unique address. The ADN2815 has two possible 7-bit slave addresses for both read and write operations. The MSB of the 7-bit slave address is factory programmed to 1. B5 of the slave address is set by Pin 19, SADDR5. Slave Address Bits [4:0] are defaulted to all 0s. The slave address consists of the 7 MSBs of an 8-bit word. The LSB of the word either sets a read or write operation (see Figure 6). Logic 1 corresponds to a read operation, while Logic 0 corresponds to a write operation. To control the device on the bus, the following protocol must be followed. First, the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on SDA while SCK remains high. This indicates that an address/ data stream follows. All peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the R/W bit). The bits are transferred from MSB to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCK lines waiting for the start condition and correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means that the master writes information to the peripheral. Logic 1 on the LSB of the first byte means that the master reads information from the peripheral. The ADN2815 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses, plus the R/W bit. The ADN2815 has eight subaddresses to enable the user-accessible internal registers (see Table 6 through Table 10). It, therefore, interprets the first byte as the device address and the second byte as the starting subaddress. Autoincrement mode is supported, allowing data to be read from or written to the starting subaddress and each subsequent address without manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all registers. Rev. 0 | Page 15 of 24 ADN2815 REFERENCE CLOCK (OPTIONAL) A reference clock is not required to perform clock and data recovery with the ADN2815. However, support for an optional reference clock is provided. The reference clock can be driven differentially or single-ended. If the reference clock is not being used, then REFCLKP should be tied to VCC, and REFCLKN can be left floating or tied to VEE (the inputs are internally terminated to VCC/2). See Figure 16 through Figure 18 for sample configurations. The REFCLK input buffer accepts any differential signal with a peak-to-peak differential amplitude of greater than 100 mV (for example, LVPECL or LVDS) or a standard single-ended low voltage TTL input, providing maximum system flexibility. Phase noise and duty cycle of the reference clock are not critical and 100 ppm accuracy is sufficient. REFCLKP 10 BUFFER REFCLKN 100kΩ VCC/2 04952-0-021 11 REFCLKP ADN2815 NC 11 REFCLKN 100kΩ 100kΩ VCC/2 Figure 18. No REFCLK Configuration The two uses of the reference clock are mutually exclusive. The reference clock can be used either as an acquisition aid for the ADN2815 to lock onto data or to measure the frequency of the incoming data to within 0.01%. (There is the capability to measure the data rate to approximately ±10% without the use of a reference clock.) The modes are mutually exclusive because, in the first use, the user knows exactly what the data rate is and wants to force the part to lock onto only that data rate; in the second use, the user does not know what the data rate is and wants to measure it. Lock-to-reference mode is enabled by writing a 1 to I2C Register Bit CTRLA[0]. Fine data rate readback mode is enabled by writing a 1 to I2C Register Bit CTRLA[1]. Writing a 1 to both of these bits at the same time causes an indeterminate state and is not supported. Using the Reference Clock to Lock onto Data In this mode, the ADN2815 locks onto a frequency derived from the reference clock according to Data Rate/2CTRLA[5:2] = REFCLK/2CTRLA[7:6] Table 11. CTRLA Settings OUT BUFFER REFCLKN 100kΩ 100kΩ VCC/2 04952-0-022 CLK OSC BUFFER The reference clock can be anywhere between 10 MHz and 160 MHz. By default, the ADN2815 expects a reference clock of between 10 MHz and 20 MHz. If it is between 20 MHz and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs to configure the ADN2815 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Figure 16. Differential REFCLK Configuration VCC ADN2815 10 REFCLKP The user must know exactly what the data rate is and provide a reference clock that is a function of this rate. The ADN2815 can still be used as a continuous rate device in this configuration, provided that the user has the ability to provide a reference clock that has a variable frequency (see Application Note AN-632). ADN2815 100kΩ VCC 04952-0-023 Stop and start conditions can be detected at any stage of the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCK high period, the user should issue one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADN2815 does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while reading back in autoincrement mode, then the highest subaddress register contents continue to be output until the master device issues a no-acknowledge. This indicates the end of a read. In a no-acknowledge condition, the SDATA line is not pulled low on the ninth pulse. See Figure 7 and Figure 8 for sample read and write data transfers and Figure 9 for a more detailed timing diagram. CTRLA[7:6] 00 01 10 11 Figure 17. Single-Ended REFCLK Configuration Rev. 0 | Page 16 of 24 Range (MHz) 10 to 20 20 to 40 40 to 80 80 to 160 CTRLA[5:2] 0000 0001 n 1000 Ratio 1 2 2n 256 ADN2815 The user can specify a fixed integer multiple of the reference clock to lock onto using CTRLA[5:2], where CTRLA should be set to the data rate/DIV_FREF, where DIV_FREF represents the divided-down reference referred to the 10 MHz to 20 MHz band. For example, if the reference clock frequency is 38.88 MHz and the input data rate is 622.08 Mb/s, then CTRLA[7:6] is set to [01] to give a divided-down reference clock of 19.44 MHz. CTRLA[5:2] is set to [0101], that is, 5, because 622.08 Mb/s/19.44 MHz = 25 In this mode, if the ADN2815 loses lock for any reason, it relocks onto the reference clock and continues to output a stable clock. While the ADN2815 is operating in lock-to-reference mode, if the user ever changes the reference frequency, the FREF range (CTRLA[7:6]) or the FREF ratio (CTRLA[5:2]), this must be followed by writing a 0 to 1 transition into the CTRLA[0] bit to initiate a new lock-to-reference command. Prior to reading back the data rate using the reference clock, the CTRLA[7:6] bits must be set to the appropriate frequency range with respect to the reference clock being used. A fine data rate readback is then executed as follows: 1. Write a 1 to CTRLA[1]. This enables the fine data rate measurement capability of the ADN2815. This bit is level sensitive and does not need to be reset to perform subsequent frequency measurements. 2. Reset MISC[2] by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. 3. Read back MISC[2]. If it is 0, the measurement is not complete. If it is 1, the measurement is complete and the data rate can be read back on FREQ[22:0]. The time for a data rate measurement is typically 80 ms. 4. Read back the data rate from Registers FREQ2[6:0], FREQ1[7:0], and FREQ0[7:0]. The data rate can be determined by Using the Reference Clock to Measure Data Frequency The user can also provide a reference clock to measure the recovered data frequency. In this case, the user provides a reference clock, and the ADN2815 compares the frequency of the incoming data to the incoming reference clock and returns a ratio of the two frequencies to 0.01% (100 ppm). The accuracy error of the reference clock is added to the accuracy of the ADN2815 data rate measurement. For example, if a 100 ppm accuracy reference clock is used, the total accuracy of the measurement is within 200 ppm. f DATARATE = (FREQ [22..0] × f REFCLK )/ 2(14 + SEL _ RATE) where: FREQ[22:0] is the reading from FREQ2[6:0] MSByte, FREQ1[7:0], and FREQ0[7:0] LSByte. fDATARATE is the data rate (Mb/s). fREFCLK is the REFCLK frequency (MHz). SEL_RATE is the setting from CTRLA[7:6]. The reference clock can range from 10 MHz and 160 MHz. The ADN2815 expects a reference clock between 10 MHz and 20 MHz by default. If it is between 20 MHz and 40 MHz, 40 MHz and 80 MHz, or 80 MHz and 160 MHz, the user needs to configure the ADN2815 to use the correct reference frequency range by setting two bits of the CTRLA register, CTRLA[7:6]. Using the reference clock to determine the frequency of the incoming data does not affect the manner in which the part locks onto data. In this mode, the reference clock is used only to determine the frequency of the data. For this reason, the user does not need to know the data rate to use the reference clock in this manner. For example, if the reference clock frequency is 32 MHz, SEL_RATE = 1, since the CTRLA[7:6] setting is [01], because the reference frequency falls into the 20 MHz to 40 MHz range. Assume for this example that the input data rate is 1.25 Gb/s (GbE). After following Step 1 through Step 4, the value that is read back on FREQ[22:0] = 0x138800, which is equal to 128 × 106. Plugging this value into the equation yields 128e6 × 32e6/2(14+1) = 1.25 Gb/s If subsequent frequency measurements are required, CTRLA[1] should remain set to 1. It does not need to be reset. The measurement process is reset by writing a 1 followed by a 0 to CTRLB[3]. This initiates a new data rate measurement. Follow Step 2 through Step 4 to read back the new data rate. Note that a data rate readback is valid only if LOL is low. If LOL is high, the data rate readback is invalid. Table 12. D22 D21...D17 FREQ2[6:0] D16 D15 D14...D9 FREQ1[7:0] Rev. 0 | Page 17 of 24 D8 D7 D6...D1 FREQ0[7:0] D0 ADN2815 Additional Features Available via the I2C Interface Coarse Data Rate Readback System Reset The data rate can be read back over the I2C interface to approximately ±10% without the need of an external reference clock. A 9-bit register, COARSE_RD[8:0], can be read back when LOL is deasserted. The eight MSBs of this register are the contents of the RATE[7:0] register. The LSB of the COARSE_RD register is Bit MISC[0]. A frequency acquisition can be initiated by writing a 1 followed by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new frequency acquisition while keeping the ADN2815 in the operating mode that it was previously programmed to in Registers CTRL[A], CTRL[B], and CTRL[C]. Table 13 provides coarse data rate readback to within ±10%. Rev. 0 | Page 18 of 24 ADN2815 APPLICATIONS INFORMATION PCB DESIGN GUIDELINES Proper RF PCB design techniques must be used for optimal performance. If connections to the supply and ground are made through vias, the use of multiple vias in parallel helps to reduce series inductance, especially on Pin 24, which supplies power to the high speed CLKOUTP/CLKOUTN and DATAOUTP/ DATAOUTN output buffers. Refer to Figure 19 for the recommended connections. Power Supply Connections and Ground Planes Use of one low impedance ground plane is recommended. The VEE pins should be soldered directly to the ground plane to reduce series inductance. If the ground plane is an internal plane and connections to the ground plane are made through vias, multiple vias can be used in parallel to reduce the series inductance, especially on Pin 23, which is the ground return for the output buffers. The exposed pad should be connected to the GND plane using plugged vias so that solder does not leak through the vias during reflow. By using adjacent power supply and GND planes, excellent high frequency decoupling can be realized by using close spacing between the planes. This capacitance is given by CPLANE = 0.88εr A/d (pF) where: εr is the dielectric constant of the PCB material. A is the area of the overlap of power and GND planes (cm2). d is the separation between planes (mm). Use of a 22 μF electrolytic capacitor between VCC and VEE is recommended at the location where the 3.3 V supply enters the PCB. When using 0.1 μF and 1 nF ceramic chip capacitors, they should be placed between the IC power supply VCC and VEE, as close as possible to the ADN2815 VCC pins. For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2. 50Ω TRANSMISSION LINES VCC DATAOUTP + 22μF 0.1μF DATAOUTN 1nF CLKOUTP TEST2 VCC VEE DATAOUTP DATAOUTN SQUELCH CLKOUTP CLKOUTN CLKOUTN 0.1μF 32 31 30 29 28 27 26 25 50Ω REFCLKP REFCLKN NC VCC VEE CF2 CF1 LOL OPTICAL TRANSCEIVER MODULE 24 EXPOSED PAD 23 TIED OFF TO 22 VEE PLANE 21 20 WITH VIAS 19 18 17 0.1μF I2C CONTROLLER I2C CONTROLLER VCC 0.1μF μC NC 50Ω 1nF VCC VEE NC SDA SCK SADDR5 VCC VEE 1nF 0.47μF ±20% >300MΩ INSULATION RESISTANCE VCC 0.1μF 1nF Figure 19. Typical ADN2815 Applications Circuit Rev. 0 | Page 19 of 24 04952-0-031 1nF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 0.1μF TEST1 VCC VREF NIN PIN NC NC VEE VCC ADN2815 Transmission Lines Choosing AC Coupling Capacitors Use of 50 Ω transmission lines is required for all high frequency input and output signals to minimize reflections: PIN, NIN, CLKOUTP, CLKOUTN, DATAOUTP and DATAOUTN (also REFCLKP and REFCLKN, if a high frequency reference clock is used, such as 155 MHz). It is also necessary for the PIN/NIN input traces to be matched in length, and the CLKOUTP/ CLKOUTN and DATAOUTP/DATAOUTN output traces to be matched in length to avoid skew between the differential traces. AC coupling capacitors at the input (PIN, NIN) and output (DATAOUTP, DATAOUTN) of the ADN2815 must be chosen such that the device works properly over the full range of data rates used in the application. When choosing the capacitors, the time constant formed with the two 50 Ω resistors in the signal path must be considered. When a large number of consecutive identical digits (CIDs) are applied, the capacitor voltage can droop due to baseline wander (see Figure 21), causing patterndependent jitter (PDJ). The high speed inputs, PIN and NIN, are internally terminated with 50 Ω to an internal reference voltage (see Figure 20). A 0.1 μF is recommended between VREF, Pin 3, and GND to provide an ac ground for the inputs. As with any high speed mixed-signal design, take care to keep all high speed digital traces away from sensitive analog nodes. The user must determine how much droop is tolerable and choose an ac coupling capacitor based on that amount of droop. The amount of PDJ can then be approximated based on the capacitor selection. The actual capacitor value selection can require some trade-offs between droop and PDJ. For example, assuming 2% droop can be tolerated, then the maximum differential droop is 4%. Normalizing to V p-p: VCC ADN2815 50Ω CIN Droop = Δ V = 0.04 V = 0.5 V p-p (1 − e–t/τ); therefore, τ = 12t PIN where: TIA CIN τ is the RC time constant (C is the ac coupling capacitor, R = 100 Ω seen by C). NIN 50Ω 50Ω 2.5V 0.1μF VREF 3kΩ 04952-0-026 50Ω Figure 20. ADN2815 AC-Coupled Input Configuration t is the total discharge time, which is equal to nT. n is the number of CIDs. T is the bit period. Soldering Guidelines for Lead Frame Chip Scale Package The lands on the 32-lead LFCSP are rectangular. The printed circuit board (PCB) pad for these should be 0.1 mm longer than the package land length and 0.05 mm wider than the package land width. The land should be centered on the pad. This ensures that the solder joint size is maximized. The bottom of the chip scale package has a central exposed pad. The pad on the PCB should be at least as large as this exposed pad. The user must connect the exposed pad to VEE using plugged vias so that solder does not leak through the vias during reflow. This ensures a solid connection from the exposed pad to VEE. The capacitor value can then be calculated by combining the equations for τ and t: C = 12 nT/R Once the capacitor value is selected, the PDJ can be approximated as ( ) PDJ pspp = 0.5t r 1 − e ( −nT/RC ) / 0.6 where: PDJpspp is the amount of pattern-dependent jitter allowed; < 0.01 UI p-p typical. tr is the rise time, which is equal to 0.22/BW, where BW ~ 0.7 (bit rate). Note that this expression for tr is accurate only for the inputs. The output rise time for the ADN2815 is ~100 ps, regardless of data rate. Rev. 0 | Page 20 of 24 ADN2815 VCC V1 CIN ADN2815 V2 PIN COUT + DATAOUTP 50Ω TIA V1b CIN V2b VREF CDR BUFFER DATAOUTN 50Ω COUT – NIN V1 1 2 3 4 V1b V2 VREF V2b VTH VDIFF NOTES: 1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO. 2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS. 3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES, EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1 AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER DOES NOT RECOGNIZE THIS AS A VALID STATE. 4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2815. THE QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT. Figure 21. Example of Baseline Wander Rev. 0 | Page 21 of 24 04952-0-027 VDIFF = V2–V2b VTH = ADN2815 QUANTIZER THRESHOLD ADN2815 COARSE DATA RATE READBACK LOOK-UP TABLE Code is the 9-bit value read back from COARSE_RD[8:0]. Table 13. Look-Up Table Code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 FMID 5.3745e+06 5.3741e+06 5.4793e+06 5.5912e+06 5.7111e+06 5.8391e+06 5.9760e+06 6.1215e+06 6.2780e+06 6.4565e+06 6.6391e+06 6.8372e+06 7.0520e+06 7.2868e+06 7.5424e+06 7.8220e+06 7.6663e+06 7.6659e+06 7.8217e+06 7.9880e+06 8.1667e+06 8.3570e+06 8.5616e+06 8.7805e+06 9.0166e+06 9.2849e+06 9.5608e+06 9.8591e+06 1.0183e+07 1.0535e+07 1.0918e+07 1.1332e+07 1.0749e+07 1.0748e+07 1.0959e+07 1.1182e+07 1.1422e+07 1.1678e+07 1.1952e+07 1.2243e+07 1.2556e+07 1.2913e+07 1.3278e+07 1.3674e+07 1.4104e+07 1.4574e+07 1.5085e+07 1.5644e+07 Code 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 FMID 1.5333e+07 1.5332e+07 1.5643e+07 1.5976e+07 1.6333e+07 1.6714e+07 1.7123e+07 1.7561e+07 1.8033e+07 1.8570e+07 1.9122e+07 1.9718e+07 2.0367e+07 2.1070e+07 2.1835e+07 2.2664e+07 2.1498e+07 2.1496e+07 2.1917e+07 2.2365e+07 2.2844e+07 2.3357e+07 2.3904e+07 2.4486e+07 2.5112e+07 2.5826e+07 2.6556e+07 2.7349e+07 2.8208e+07 2.9147e+07 3.0170e+07 3.1288e+07 3.0665e+07 3.0664e+07 3.1287e+07 3.1952e+07 3.2667e+07 3.3428e+07 3.4246e+07 3.5122e+07 3.6066e+07 3.7140e+07 3.8243e+07 3.9436e+07 4.0733e+07 4.2140e+07 4.3671e+07 4.5328e+07 Code 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 Rev. 0 | Page 22 of 24 FMID 4.2996e+07 4.2993e+07 4.3834e+07 4.4729e+07 4.5688e+07 4.6713e+07 4.7808e+07 4.8972e+07 5.0224e+07 5.1652e+07 5.3113e+07 5.4698e+07 5.6416e+07 5.8295e+07 6.0339e+07 6.2576e+07 6.1331e+07 6.1328e+07 6.2574e+07 6.3904e+07 6.5334e+07 6.6856e+07 6.8493e+07 7.0244e+07 7.2133e+07 7.4279e+07 7.6486e+07 7.8872e+07 8.1467e+07 8.4279e+07 8.7341e+07 9.0657e+07 8.5991e+07 8.5986e+07 8.7668e+07 8.9458e+07 9.1377e+07 9.3426e+07 9.5616e+07 9.7944e+07 1.0045e+08 1.0330e+08 1.0623e+08 1.0940e+08 1.1283e+08 1.1659e+08 1.2068e+08 1.2515e+08 Code 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 FMID 1.2266e+08 1.2266e+08 1.2515e+08 1.2781e+08 1.3067e+08 1.3371e+08 1.3699e+08 1.4049e+08 1.4427e+08 1.4856e+08 1.5297e+08 1.5774e+08 1.6293e+08 1.6856e+08 1.7468e+08 1.8131e+08 1.7198e+08 1.7197e+08 1.7534e+08 1.7892e+08 1.8275e+08 1.8685e+08 1.9123e+08 1.9589e+08 2.0089e+08 2.0661e+08 2.1245e+08 2.1879e+08 2.2566e+08 2.3318e+08 2.4136e+08 2.5030e+08 2.4532e+08 2.4531e+08 2.5029e+08 2.5562e+08 2.6134e+08 2.6742e+08 2.7397e+08 2.8098e+08 2.8853e+08 2.9712e+08 3.0594e+08 3.1549e+08 3.2587e+08 3.3712e+08 3.4936e+08 3.6263e+08 ADN2815 Code 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 FMID 3.4397e+08 3.4394e+08 3.5067e+08 3.5783e+08 3.6551e+08 3.7370e+08 3.8247e+08 3.9177e+08 4.0179e+08 4.1322e+08 4.2490e+08 4.3758e+08 4.5133e+08 4.6636e+08 4.8272e+08 5.0061e+08 Code 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 FMID 4.9064e+08 4.9062e+08 5.0059e+08 5.1123e+08 5.2267e+08 5.3485e+08 5.4794e+08 5.6195e+08 5.7706e+08 5.9423e+08 6.1189e+08 6.3098e+08 6.5173e+08 6.7423e+08 6.9873e+08 7.2525e+08 Code 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 Rev. 0 | Page 23 of 24 FMID 6.8793e+08 6.8789e+08 7.0135e+08 7.1567e+08 7.3102e+08 7.4741e+08 7.6493e+08 7.8355e+08 8.0358e+08 8.2643e+08 8.4981e+08 8.7516e+08 9.0266e+08 9.3272e+08 9.6543e+08 1.0012e+09 Code 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 FMID 9.8129e+08 9.8124e+08 1.0012e+09 1.0225e+09 1.0453e+09 1.0697e+09 1.0959e+09 1.1239e+09 1.1541e+09 1.1885e+09 1.2238e+09 1.2620e+09 1.3035e+09 1.3485e+09 1.3975e+09 1.4505e+09 ADN2815 OUTLINE DIMENSIONS 0.60 MAX 5.00 BSC SQ 0.60 MAX 25 24 PIN 1 INDICATOR TOP VIEW 0.50 BSC 4.75 BSC SQ 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 32 1 EXPOSED PAD (BOTTOM VIEW) 17 16 3.45 3.30 SQ 3.15 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 22. 32-Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters ORDERING GUIDE Model ADN2815ACPZ 1 ADN2815ACPZ-500RL71 ADN2815ACPZ-RL71 EVAL-ADN2815EB 1 Temperature Range −40°C to 85°C −40°C to 85°C −40°C to 85°C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ, Tape-Reel, 500 pieces 32-Lead LFCSP_VQ, Tape-Reel, 1,500 pieces Evaluation Board Package Option CP-32-3 CP-32-3 CP-32-3 Z = Pb-free part. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04952–0–9/05(0) T T Rev. 0 | Page 24 of 24