SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 SN54ALS373A, . . . J OR W PACKAGE SN54AS373 . . . J PACKAGE SN74ALS373A, SN74AS373 . . . DW, N, OR NS PACKAGE (TOP VIEW) OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND description These octal transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without interface or pullup components. 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q LE 1D 1Q SN54ALS373A, SN54AS373 . . . FK PACKAGE (TOP VIEW) 2D 2Q 3Q 3D 4D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND LE 5Q 5D While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. 1 8Q Eight Latches in a Single Package 3-State Bus-Driving True Outputs Full Parallel Access for Loading Buffered Control Inputs pnp Inputs Reduce dc Loading on Data Lines OE VCC D D D D D OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are off. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 ORDERING INFORMATION PDIP – N 0°C to 70°C Tube SOIC – DW SOP – NS –55°C to 125°C ORDERABLE PART NUMBER PACKAGE† TA SN74ALS373AN SN74ALS373AN SN74AS373N SN74AS373N Tube SN74ALS373ADW Tape and reel SN74ALS373ADWR Tube SN74AS373DW Tape and reel SN74AS373DWR Tape and reel CDIP – J Tube CFP – W Tube LCCC – FK TOP-SIDE MARKING Tube ALS373A AS373 SN74ALS373ANSR ALS373A SN74AS373NSR 74AS373 SNJ54ALS373AJ SNJ54ALS373AJ SNJ54AS373J SNJ54AS373J SNJ54ALS373AW SNJ54ALS373AW SNJ54ALS373AFK SNJ54ALS373AFK SNJ54AS373FK SNJ54AS373FK † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each latch) INPUTS OE LE D OUTPUT Q L H H H L H L L L L X Q0 H X X Z logic diagram (positive logic) OE LE 1 11 C1 1D 3 1D To Seven Other Channels 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 1Q SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 absolute maximum ratings over operating free-air temperature range (SN54ALS373A, SN74ALS373A) (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to any output in the high state or power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions SN54ALS373A SN74ALS373A MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.7 0.8 V High-level output current –1 –2.6 mA IOL TA Low-level output current 24 mA 70 °C High-level input voltage 2 2 V 12 Operating free-air temperature –55 125 V 0 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54ALS373A MIN MAX SN74ALS373A MIN MAX UNIT fclock tw Clock frequency Pulse duration, LE high 12 10 MHz ns tsu th Setup time, data before LE↓ 10 10 ns 7 7 ns Hold time, data after LE↓ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –0.4 mA 5V VCC = 4 4.5 IOH = –1 mA IOH = –2.6 mA VOL VCC = 4 4.5 5V IOL = 12 mA IOL = 24 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VOH ICC SN54ALS373A TYP† MAX TEST CONDITIONS VCC = 5.5 V MIN SN74ALS373A TYP† MAX MIN –1.5 VCC–2 2.4 –1.5 UNIT V VCC–2 V 3.3 2.4 0.25 –20 0.4 3.2 0.25 0.4 0.35 0.5 V 20 20 µA –20 –20 µA 0.1 0.1 mA 20 20 µA –0.1 –0.1 mA –112 mA –112 –30 Outputs high 9 16 9 16 Outputs low 16 25 16 25 mA Outputs disabled 17 27 17 27 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ SN54ALS373A tPLH tPHL D Q tPLH tPHL LE A Q Any tPZH tPZL OE A Q Any tPHZ tPLZ OE Any Q SN74ALS373A MIN MAX MIN MAX 2 17 2 12 1 19 4 16 6 29 6 22 1 27 7 23 6 22 1 18 5 24 5 20 2 16 1 10 2 24 2 12 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 absolute maximum ratings over operating free-air temperature range (SN54AS373, SN74AS373) (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage applied to any output in the high state or power-off state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Package thermal impedance, θJA (see Note 1): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 2: The package thermal impedance is calculated in accordance with JESD 51-7. recommended operating conditions SN54AS373 SN74AS373 MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 UNIT VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –12 –15 mA IOL TA Low-level output current 48 mA 70 °C High-level input voltage 2 2 V 32 Operating free-air temperature –55 125 V 0 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 1) SN54AS373 MIN fclock tw Clock frequency tsu th MAX SN74AS373 MIN MAX UNIT MHz Pulse duration, LE high 5.5* 4.5* ns Setup time, data before LE↓ 2* 2* ns Hold time, data after LE↓ 3* 3* ns * On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = –18 mA IOH = –2 mA 5V VCC = 4 4.5 IOH = –12 mA IOH = –15 mA VOL VCC = 4 4.5 5V IOL = 32 mA IOL = 48 mA IOZH IOZL VCC = 5.5 V, VCC = 5.5 V, VO = 2.7 V VO = 0.4 V II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO‡ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V VOH ICC SN54AS373 TYP† MAX TEST CONDITIONS VCC = 5.5 V MIN SN74AS373 TYP† MAX MIN –1.2 VCC–2 2.4 –1.2 UNIT V VCC–2 V 3.2 2.4 0.27 3.3 0.5 0.32 –0.02 –30 0.5 V 50 50 µA –50 –50 µA 0.1 0.1 mA 20 20 µA –0.5 mA –112 mA –0.5 –112 –0.02 –30 Outputs high 55 90 55 90 Outputs low 55 85 55 85 mA Outputs disabled 65 100 65 100 † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, R1 = 500 Ω, R2 = 500 Ω, TA = MIN to MAX§ SN54AS373 tPLH tPHL D Q tPLH tPHL LE A Q Any tPZH tPZL OE A Q Any tPHZ tPLZ OE Any Q SN74AS373 MIN MAX MIN MAX 3 9 3.5 6 3 8 3.5 6 6.5 14.5 6.5 11.5 5 9 5 7.5 2 7.5 2 6.5 4.5 10.5 4.5 9.5 3 10 3 6.5 3 8 3 7 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT ns ns ns ns SN54ALS373A, SN54AS373, SN74ALS373A, SN74AS373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SDAS083C – APRIL 1982 – REVISED MARCH 2002 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ tPHZ 1.3 V 1.3 V 0.3 V tPHL ≈3.5 V tPLH VOL 0.3 V VOH 1.3 V 3.5 V Input 1.3 V tPZH Waveform 2 S1 Open (see Note B) 1.3 V 0.3 V ≈0 V VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) 83020012A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC 8302001RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC 8302001SA ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC JM38510/37203B2A ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC JM38510/37203BRA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC SN54ALS373AJ ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC SN54AS373J ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC SN74ALS373ADBLE OBSOLETE SSOP DB 20 None Call TI Call TI SN74ALS373ADBR ACTIVE SSOP DB 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74ALS373ADW ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74ALS373ADWR ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74ALS373AN ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74ALS373AN3 OBSOLETE PDIP N 20 None Call TI SN74ALS373ANSR ACTIVE SO NS 20 2000 Pb-Free (RoHS) CU NIPDAU Call TI Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SN74AS373DW ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74AS373DWR ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM SN74AS373N ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC SN74AS373N3 OBSOLETE PDIP N 20 None Call TI SN74AS373NSR ACTIVE SO NS 20 2000 Pb-Free (RoHS) CU NIPDAU Call TI SNJ54ALS373AFK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC Level-2-260C-1 YEAR/ Level-1-235C-UNLIM SNJ54ALS373AJ ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC SNJ54ALS373AW ACTIVE CFP W 20 1 None Call TI Level-NC-NC-NC SNJ54AS373FK ACTIVE LCCC FK 20 1 None Call TI Level-NC-NC-NC SNJ54AS373J ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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