ISL84541, ISL84542, ISL84543, ISL84544 ® Data Sheet September 2003 Low-Voltage, Single Supply, Dual SPST, SPDT Analog Switches The Intersil ISL84541–ISL84544 devices are precision, dual analog switches designed to operate from a single +2.7V to +12V supply. Targeted applications include battery powered equipment that benefit from the devices’ low power consumption (5µW), low leakage currents (100pA max), and fast switching speeds (tON = 35ns, tOFF = 25ns). Cell phones, for example, often face ASIC functionality limitations. The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance. This family of parts may be used to “mux-in” additional functionality while reducing ASIC design risk. Some of the smallest packages are available alleviating board space limitations, and making Intersil’s newest line of low-voltage switches an ideal solution. The ISL84541/ISL84542/ISL84543 are dual singlepole/single-throw (SPST) devices. The ISL84541 has two normally open (NO) switches; the ISL84542 has two normally closed (NC) switches; the ISL84543 has one NO and one NC switch and can be used as an SPDT. The ISL84544 is a committed SPDT, which is perfect for use in 2-to-1 multiplexer applications. Table 1 summarizes the performance of this family. For higher performance, pin compatible versions, see the ISL43120 - 22 and ISL43210 datasheet. FN6016.6 Features • Pb-free Available as an Option • Drop-in Replacements for MAX4541 - MAX4544, DG9461, DG9262 - DG9263 • Fully Specified at 3.3V and 5V Supplies • Pin Compatible with MAX323 - MAX325 • ON Resistance (RON) . . . . . . . . . . . . . . . . . . . . . . . . 30Ω • RON Matching Between Channels. . . . . . . . . . . . . . . . . . <1Ω • Low Charge Injection . . . . . . . . . . . . . . . . . . . . . . 5pC (Max) • Single Supply Operation. . . . . . . . . . . . . . . . . +2.7V to +12V • Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . . .<5µW • Low Leakage Current (Max at 85oC) . . . . . . . . . . . . 10nA • Fast Switching Action - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns • Guaranteed Break-Before-Make (ISL84543/ISL84544 only) • Minimum 2000V ESD Protection per Method 3015.7 • TTL, CMOS Compatible • Available in SOT-23 Packaging Applications TABLE 1. FEATURES AT A GLANCE ISL84541 ISL84542 ISL84543 ISL84544 NUMBER OF SWITCHES 2 2 2 1 SW 1 / SW 2 NO / NO NC / NC NO / NC SPDT 3.3V RON 50Ω 50Ω 50Ω 50Ω 3.3V tON / tOFF 50 / 20ns 5V RON 30Ω 5V tON / tOFF 35 / 25ns 35 / 25ns 35 / 25ns 35 / 25ns 8 Ld PDIP, 8 Ld SOIC, 8 Ld SOT-23, 8 Ld MSOP 8 Ld PDIP, 8 Ld SOIC, 8 Ld SOT-23 8 Ld PDIP, 8 Ld SOIC, 6 Ld SOT-23 PACKAGES 50 / 20ns 50 / 20ns 30Ω 30Ω 50 / 20ns 30Ω • Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Communications Systems - Military Radios - PBX, PABX • Test Equipment - Ultrasound - Electrocardiograph • Heads-Up Displays • Audio and Video Switching Related Literature Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” 1 • Various Circuits - +3V/+5V DACs and ADCs - Sample and Hold Circuits - Digital Filters - Operational Amplifier Gain Switching Networks - High Frequency Analog Switching - High Speed Multiplexing - Integrator Reset Circuits CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001-2004. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL84541, ISL84542, ISL84543, ISL84544 Pinouts (Note 1) ISL84541 (PDIP, SOIC, MSOP) TOP VIEW ISL84541 (SOT-23) TOP VIEW NO1 1 8 V+ COM1 2 7 IN1 V+ 2 7 IN1 6 COM2 IN2 3 6 GND COM2 4 5 NO2 IN2 3 5 NO2 GND 4 ISL84542 (PDIP, SOIC) TOP VIEW NC1 1 COM1 2 ISL84542 (SOT-23) TOP VIEW NC1 1 7 IN1 V+ 2 7 IN1 IN2 3 6 GND COM2 4 5 NC2 5 NC2 GND 4 8 COM1 8 V+ 6 COM2 IN2 3 8 COM1 NO1 1 ISL84543 (PDIP, SOIC) TOP VIEW ISL84543 (SOT-23) TOP VIEW NO1 1 8 V+ NO1 1 COM1 2 7 IN1 V+ 2 7 IN1 IN2 3 6 GND COM2 4 5 NC2 6 COM2 IN2 3 5 NC2 GND 4 ISL84544 (PDIP, SOIC) TOP VIEW 8 COM1 ISL84544 (SOT-23) TOP VIEW NO 1 8 V+ IN 1 6 NO COM 2 7 IN V+ 2 5 COM NC 3 6 NC GND 4 5 NC 4 NC GND 3 NOTE: 1. Switches Shown for Logic “0” Input. Truth Table Pin Descriptions ISL84541 ISL84542 ISL84543 ISL84544 PIN PIN NC PIN NO V+ FUNCTION System Power Supply Input (+2.7V to +12V) LOGIC SW 1, 2 SW 1, 2 SW 1 SW 2 0 OFF ON OFF ON ON OFF GND Ground Connection 1 ON OFF ON OFF OFF ON IN Digital Control Input NOTE: Logic “0” ≤ 0.8V. Logic “1” ≥ 2.4V. 2 COM Analog Switch Common Pin NO Analog Switch Normally Open Pin NC Analog Switch Normally Closed Pin N.C. No Internal Connection ISL84541, ISL84542, ISL84543, ISL84544 Ordering Information PART NO. (BRAND) TEMP. RANGE (oC) Ordering Information PACKAGE PKG. DWG. # ISL84541CP 0 to 70 8 Ld PDIP E8.3 ISL84541CPZ (See Note 2) 0 to 70 8 Ld PDIP (Pb-free) E8.3 ISL84541CB 0 to 70 8 Ld SOIC M8.15 ISL84541CB-T ISL84541CBZ (See Note 2) ISL84541CBZ-T (See Note 2) 8 Ld SOIC Tape and Reel 0 to 70 M8.15 E8.3 8 Ld PDIP (Pb-free) E8.3 ISL84543CB 0 to 70 8 Ld SOIC M8.15 ISL84543CBZ (See Note 2) ISL84543CBZ-T (See Note 2) -40 to 85 8 Ld PDIP (Pb-free) E8.3 ISL84541IBZ (See Note 2) 8 Ld PDIP 0 to 70 ISL84543CB-T ISL84541IPZ (See Note 2) ISL84541IB-T 0 to 70 ISL84543CPZ (See Note 2) M8.15 E8.3 8 Ld SOIC M8.15 8 Ld SOIC Tape and Reel -40 to 85 M8.15 0 to 70 M8.15 8 Ld SOIC (Pb-free) M8.15 8 Ld SOIC Tape and Reel (Pb-free) M8.15 -40 to 85 8 Ld PDIP E8.3 ISL84543IPZ (See Note 2) -40 to 85 8 Ld PDIP (Pb-free) E8.3 -40 to 85 8 Ld SOIC M8.15 8 Ld SOIC Tape and Reel M8.15 ISL84543IB M8.15 ISL84541IBZ-T (See Note 2) 8 Ld SOIC Tape and Reel (Pb-free) M8.15 ISL84543IBZ (See Note 2) ISL84541IH-T (541I) 8 Ld SOT-23 Tape and Reel P8.064 ISL84541IHZ-T 8 Ld SOT-23 Tape and Reel (541I) (See Note 2) (Pb-free) ISL84541IU-T (541I) 8 Ld SOIC Tape and Reel ISL84543IP 8 Ld SOIC (Pb-free) ISL84541IU (541I) -40 to 85 PKG. DWG. # ISL84543CP 8 Ld SOIC Tape and Reel (Pb-free) 8 Ld PDIP PACKAGE P8.064 M8.15 -40 to 85 TEMP. RANGE (oC) ISL84542IHZ-T 8 Ld SOT-23 Tape and Reel (542I) (See Note 2) (Pb-free) 8 Ld SOIC (Pb-free) ISL84541IP ISL84541IB PART NO. (BRAND) ISL84543IB-T 8 Ld SOIC (Pb-free) M8.15 ISL84543IBZ-T (See Note 2) 8 Ld SOIC Tape and Reel (Pb-free) M8.15 P8.064 ISL84543IH-T (543I) 8 Ld SOT-23 Tape and Reel P8.064 8 Ld MSOP M8.118 M8.118 ISL84543IHZ-T 8 Ld SOT-23 Tape and Reel (543I) (See Note 2) (Pb-free) P8.064 8 Ld MSOP Tape and Reel -40 to 85 -40 to 85 ISL84544CP 0 to 70 8 Ld PDIP E8.3 8 Ld MSOP (Pb-free) M8.118 ISL84544CPZ (See Note 2) 0 to 70 8 Ld PDIP (Pb-free) E8.3 ISL84541IUZ-T 8 Ld MSOP Tape and Reel (541I) (See Note 2) (Pb-free) M8.118 ISL84544CB 0 to 70 8 Ld SOIC M8.15 ISL84542CP 0 to 70 8 Ld PDIP E8.3 ISL84542CPZ (See Note 2) 0 to 70 8 Ld PDIP (Pb-free) E8.3 ISL84544CBZ (See Note 2) ISL84542CB 0 to 70 8 Ld SOIC M8.15 ISL84544CBZ-T (See Note 2) 8 Ld SOIC Tape and Reel M8.15 ISL84544IP -40 to 85 8 Ld PDIP E8.3 8 Ld SOIC (Pb-free) M8.15 ISL84544IPZ (See Note 2) -40 to 85 8 Ld PDIP (Pb-free) E8.3 8 Ld SOIC Tape and Reel (Pb-free) M8.15 ISL84544IB -40 to 85 8 Ld SOIC M8.15 8 Ld SOIC Tape and Reel M8.15 ISL84541IUZ (541I) (See Note 2) ISL84542CB-T ISL84542CBZ (See Note 2) ISL84542CBZ-T (See Note 2) -40 to 85 0 to 70 ISL84544CB-T ISL84544IB-T ISL84542IP -40 to 85 8 Ld PDIP E8.3 ISL84542IPZ (See Note 2) -40 to 85 8 Ld PDIP (Pb-free) E8.3 ISL84544IBZ (See Note 2) ISL84542IB -40 to 85 8 Ld SOIC M8.15 ISL84542IB-T ISL84542IBZ (See Note 2) 8 Ld SOIC Tape and Reel -40 to 85 M8.15 8 Ld SOIC (Pb-free) M8.15 ISL84542IBZ-T (See Note 2) 8 Ld SOIC Tape and Reel (Pb-free) M8.15 ISL84542IH-T (542I) 8 Ld SOT-23 Tape and Reel P8.064 3 8 Ld SOIC Tape and Reel 0 to 70 M8.15 8 Ld SOIC (Pb-free) M8.15 8 Ld SOIC Tape and Reel (Pb-free) M8.15 -40 to 85 8 Ld SOIC (Pb-free) M8.15 ISL84544IBZ-T (See Note 2) 8 Ld SOIC Tape and Reel (Pb-free) M8.15 ISL84544IH-T (544I) 6 Ld SOT-23 Tape and Reel P6.064 ISL84544IHZ-T 6 Ld SOT-23 Tape and Reel (544I) (See Note 2) (Pb-free) P6.064 NOTE: 2. Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which is compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J Std-020B. ISL84541, ISL84542, ISL84543, ISL84544 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to15V Input Voltages IN (Note 3). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) NO, NC (Note 3) . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Output Voltages COM (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to ((V+) + 0.3V) Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 10mA Peak Current, IN, NO, NC, or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 20mA ESD Rating (Per MIL-STD-883 Method 3015). . . . . . . . . . . . . .>2kV Thermal Resistance (Typical, Note 4) Operating Conditions Temperature Range ISL8454XCX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC ISL8454XIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC θJA (oC/W) 6 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 230 8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . 215 8 Ld MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . 210 8 LD SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . 170 8 LD PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . 140 Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC Moisture Sensitivity (See Technical Brief TB363) All Other Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1 8 Ld SOT-23 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 2 Maximum Storage Temperature Range . . . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC, MSOP and SOT-23 - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 3. Signals on NC, NO, COM, or IN exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 4. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications - 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 6) TYP Full 0 - V+ V 25 - 30 60 Ω Full - - 75 Ω 25 - 0.8 2 Ω Full - - 4 Ω MAX (NOTE 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 4.5V, ICOM = 1.0mA, VNO or VNC = 3.5V, See Figure 5 RON Matching Between Channels, ∆RON V+ = 5V, ICOM = 1.0mA, VNO or VNC= 3.5V RON Flatness, RFLAT(ON) V+ = 5V, ICOM = 1.0mA, VNO or VNC = 1V, 2V, 3V Full - 7 8 Ω NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 5.5V, VCOM = 1V, 4.5V, VNO or VNC = 4.5V, 1V, Note 7 25 -0.1 0.01 0.1 nA Full -5 - 5 nA 25 -0.1 - 0.1 nA Full -5 - 5 nA 25 -0.2 - 0.2 nA Full -10 - 10 nA COM OFF Leakage Current, ICOM(OFF) V+ = 5.5V, VCOM = 4.5V, 1V, VNO or VNC = 1V, 4.5V, Note 7 COM ON Leakage Current, ICOM(ON) V+ = 5.5V, VCOM = 1V, 4.5V, or VNO or VNC = 1V, 4.5V, or Floating, Note 7 4 ISL84541, ISL84542, ISL84543, ISL84544 Electrical Specifications - 5V Supply PARAMETER Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (oC) MIN (NOTE 6) TYP 25 - 35 100 ns Full - - 240 ns 25 - 25 75 ns Full - - 150 ns MAX (NOTE 6) UNITS DYNAMIC CHARACTERISTICS Turn-ON Time, tON VNO or VNC = 3V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V, See Figure 1 VNO or VNC = 3V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V, See Figure 1 Turn-OFF Time, tOFF Break-Before-Make Time Delay (ISL84543, ISL84544), tD RL = 300Ω, CL = 35pF, VNO = VNC = 3V, VIN = 0 to 3V, See Figure 3 Full 2 10 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, See Figure 2 25 - 1 5 pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz, See Figure 4 25 - 76 - dB Crosstalk (Channel-to-Channel) RL = 50Ω, CL = 5pF, f = 1MHz, See Figure 6 25 - -90 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 8 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7 25 - 8 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7, ISL84541/2/3 25 - 13 - pF f = 1MHz, VNO or VNC = VCOM = 0V, See Figure 7, ISL84544 25 - 20 - pF Full 2.7 12 V Full -1 0.0001 1 µA Input Voltage Low, VINL Full - - 0.8 V Input Voltage High, VINH Full 2.4 - - V POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 5.5V, VIN = 0V or V+, all channels on or off Positive Supply Current, I+ DIGITAL INPUT CHARACTERISTICS NOTES: 5. VIN = input voltage to perform proper function. 6. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 7. Leakage parameter is 100% tested at high temp, and guaranteed by correlation at 25oC. 5 ISL84541, ISL84542, ISL84543, ISL84544 Electrical Specifications - 3.3V Supply PARAMETER Test Conditions: V+ = +3.0V to +3.6V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Note 5), Unless Otherwise Specified TEST CONDITIONS TEMP (oC) MIN (NOTE 6) TYP Full 0 - V+ V 25 - 50 80 Ω Full - - 140 Ω 25 - 0.8 2 Ω Full - - 4 Ω 25 - 6 10 Ω Full - 7 12 Ω 25 -0.1 0.01 0.1 nA Full -5 - 5 nA 25 -0.1 0.01 0.1 nA Full -5 - 5 nA 25 -0.2 - 0.2 nA Full -10 - 10 nA 25 - 50 120 ns 200 ns MAX (NOTE 6) UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3V, ICOM = 1.0mA, VNO or VNC = 1.5V RON Matching Between Channels, ∆RON V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 1.5V RON Flatness, RFLAT(ON) V+ = 3.3V, ICOM = 1.0mA, VNO or VNC = 0.5V, 1V, 1.5V NO or NC OFF Leakage Current, INO(OFF) or INC(OFF) V+ = 3.6V, VCOM = 1V, 3V, VNO or VNC = 3V, 1V, Note 7 COM OFF Leakage Current, ICOM(OFF) V+ = 3.6V, VCOM = 3V, 1V, VNO or VNC = 1V, 3V, Note 7 COM ON Leakage Current, ICOM(ON) V+ = 3.6V, VCOM = 1V, 3V, or VNO or VNC = 1V, 3V, or floating, Note 7 DYNAMIC CHARACTERISTICS Turn-ON Time, tON VNO or VNC = 1.5V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V Full Turn-OFF Time, tOFF VNO or VNC = 1.5V, RL =1kΩ, CL = 35pF, VIN = 0 to 3V 25 - 20 50 ns Full - - 120 ns Break-Before-Make Time Delay (ISL84543, ISL84544), tD RL = 300Ω, CL = 35pF, VNO or VNC = 1.5V, VIN = 0 to 3V Full 3 30 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω 25 - 1 5 pC OFF Isolation RL = 50Ω, CL = 5pF, f = 1MHz 25 - 76 - dB Crosstalk (Channel-to-Channel) 25 - -90 - dB NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM OFF Capacitance, CCOM(OFF) f = 1MHz, VNO or VNC = VCOM = 0V 25 - 8 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VNO or VNC = VCOM = 0V, ISL84541/2/3 25 - 13 - pF f = 1MHz, VNO or VNC = VCOM = 0V, ISL84544 25 - 20 - pF Full -1 - 1 µA Input Voltage Low, VINL Full - - 0.8 V Input Voltage High, VINH Full 2.4 - - V Full -1 - 1 µA POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = 3.6V, VIN = 0V or V+, all channels on or off DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL V+ = 3.6V, VIN = 0V or V+ 6 ISL84541, ISL84542, ISL84543, ISL84544 Test Circuits and Waveforms 3V LOGIC INPUT V+ tr < 20ns tf < 20ns 50% 0V tOFF VOUT NO or NC SWITCH INPUT SWITCH INPUT VNO COM VOUT IN 90% SWITCH OUTPUT C 90% LOGIC INPUT 0V CL 35pF RL 1kΩ GND tON Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for all switches. CL includes fixture and stray capacitance. RL V OUT = V (NO or NC) -----------------------------R L + R ( ON ) FIGURE 1A. MEASUREMENT POINTS FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT VOUT ∆VOUT RG C VOUT COM NO or NC V+ LOGIC INPUT ON ON VG OFF GND IN 0V CL LOGIC INPUT Q = ∆VOUT x CL FIGURE 2A. MEASUREMENT POINTS FIGURE 2B. TEST CIRCUIT FIGURE 2. CHARGE INJECTION V+ 3V C LOGIC INPUT 0V VNX SWITCH OUTPUT VOUT1 SWITCH OUTPUT VOUT2 COM1 VOUT2 RL1 300Ω NC2 90% COM2 0V IN1 tD tD RL2 300Ω IN2 90% 0V VOUT1 NO1 LOGIC INPUT CL2 35pF GND CL includes fixture and stray capacitance. FIGURE 3A. MEASUREMENT POINTS (ISL84543 ONLY) 7 FIGURE 3B. TEST CIRCUIT (ISL84543 ONLY) CL1 35pF ISL84541, ISL84542, ISL84543, ISL84544 Test Circuits and Waveforms (Continued) V+ C 3V LOGIC INPUT 0V NO VNX VOUT COM NC 90% SWITCH OUTPUT VOUT RL 300Ω IN GND LOGIC INPUT 0V tD CL 35pF CL includes fixture and stray capacitance. FIGURE 3D. TEST CIRCUIT (ISL84544 ONLY) FIGURE 3C. MEASUREMENT POINTS (ISL84544 ONLY) FIGURE 3. BREAK-BEFORE-MAKE TIME V+ V+ C C RON = V1/1mA SIGNAL GENERATOR NO or NC NO or NC VNX INX 0V or 2.4V 1mA 0.8V or 2.4V COM COM ANALYZER IN V1 GND GND RL FIGURE 5. RON TEST CIRCUIT FIGURE 4. OFF ISOLATION TEST CIRCUIT V+ C V+ C SIGNAL GENERATOR NO1 or NC1 COM1 50Ω NO or NC IN1 0V or 2.4V COM2 ANALYZER INX IN2 0V or 2.4V NO2 or NC2 GND 0V or 2.4V IMPEDANCE ANALYZER COM NC GND RL FIGURE 6. CROSSTALK TEST CIRCUIT 8 FIGURE 7. CAPACITANCE TEST CIRCUIT ISL84541, ISL84542, ISL84543, ISL84544 Detailed Description The ISL84541–ISL84544 dual analog switches offer precise switching capability from a single 2.7V to 12V supply with low on-resistance (30Ω) and high speed operation (tON = 35ns, tOFF = 25ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (2.7V), low power consumption (5µW), low leakage currents (100pA max), and the tiny SOT-23 packaging. High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. Supply Sequencing And Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then one of the following two protection methods should be employed. Logic inputs can easily be protected by adding a 1kΩ resistor in series with the input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the sub-microamp input current produces an insignificant voltage drop during normal operation. Adding a series resistor to the switch input defeats the purpose of using a low RON switch, so two small signal diodes can be added in series with the supply pins to provide overvoltage protection for all pins (see Figure 8). These additional diodes limit the analog signal from 1V below V+ to 1V above GND. The low leakage current performance is unaffected by this approach, but the switch resistance may increase, especially at low supply voltages. OPTIONAL PROTECTION DIODE V+ OPTIONAL PROTECTION RESISTOR INX VNO or NC VCOM GND OPTIONAL PROTECTION DIODE their analog voltage limits. Unlike switches with a 13V maximum supply voltage, the ISL8454X 15V maximum supply voltage provides plenty of room for the 10% tolerance of 12V supplies, as well as room for overshoot and noise spikes. The minimum recommended supply voltage is 2.7V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance curves for details. V+ and GND also power the internal logic and level shifters. The level shifters convert the logic levels to switched V+ and GND signals to drive the analog switch gate terminals. This family of switches cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds This switch family is TTL compatible (0.8V and 2.4V) over a supply range of 3V to 11V (see Figure 15). At 12V the VIH level is about 2.5V. This is still below the TTL guaranteed high output minimum level of 2.8V, but noise margin is reduced. For best results with a 12V supply, use a logic family the provides a VOH greater than 3V. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. High-Frequency Performance In 50Ω systems, signal response is reasonably flat even past 300MHz (see Figure 16). Figure 16 also illustrates that the frequency response is very consistent over a wide V+ range, and for varying analog signal levels. An off switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch’s input to its output. Off Isolation is the resistance to this feedthrough, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 17 details the high Off Isolation and Crosstalk rejection provided by this family. At 10MHz, off isolation is about 50dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Power-Supply Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. The ISL8454X construction is typical of most CMOS analog switches, except that they have only two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, FIGURE 8. OVERVOLTAGE PROTECTION 9 ISL84541, ISL84542, ISL84543, ISL84544 they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog-signal paths and V+ or GND. Typical Performance Curves TA = 25oC, Unless Otherwise Specified 45 40 V+ = 3.3V 40 35 35 30 30 RON (Ω) RON (Ω) 25oC 20 25 20 25oC 15 85oC 25 85oC -40oC 15 30 25 V+ = 5V 85oC 25oC -40oC 20 15 -40oC 10 20 10 85oC 15 5 3 4 5 6 7 8 V+ (V) 9 10 11 12 10 13 -40oC 5 0 4 6 VCOM (V) 8 10 12 V+ = 3.3V 60 25oC 50 0.2 85oC 0.1 0 0.25 0.2 0.15 40 -40oC 30 V+ = 5V 25oC 0.1 Q (pC) ∆RON (Ω) 2 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE 0.5 0.4 0.3 V+ = 12V 25oC 85oC 85oC 0.05 0 0.15 20 V+ = 5V V+ = 12V 10 V+ = 3.3V -40oC 0 V+ = 12V 25oC 0.1 -40oC 0.05 85oC 25oC -40oC 2 4 6 8 10 VCOM (V) FIGURE 11. RON MATCH vs SWITCH VOLTAGE 10 -20 0 0 0 -10 12 2 4 6 VCOM (V) 8 10 FIGURE 12. CHARGE INJECTION vs SWITCH VOLTAGE 12 ISL84541, ISL84542, ISL84543, ISL84544 Typical Performance Curves TA = 25oC, Unless Otherwise Specified (Continued) 100 35 90 80 30 85oC tOFF (ns) tON (ns) 70 60 85oC 25 -40oC 50 -40oC 40 20 -40oC 25oC 30 25oC 20 15 3 4 5 6 7 V+ (V) 8 9 10 11 12 2 3.0 2.5 VINH AND VINL (V) VINH -40oC 2.0 85oC 5 6 7 V+ (V) 8 9 10 11 12 V+ = 3.3V to 12V 0 GAIN -3 -6 0 PHASE 20 25oC 1.5 85oC 40 -40oC 60 25oC 1.0 RL = 50Ω VIN = 0.2VP-P to 2.5VP-P (V+ = 3.3V) VIN = 0.2VP-P to 4VP-P (V+ = 5V) VIN = 0.2VP-P to 5VP-P (V+ = 12V) VINL 85oC 0.5 2 3 4 5 6 7 8 V+ (V) 9 10 11 12 13 1 10 80 100 100 FREQUENCY (MHz) FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE -10 FIGURE 16. FREQUENCY RESPONSE 10 V+ = 3V to 13V -20 20 Die Characteristics -30 30 SUBSTRATE POTENTIAL (POWERED UP): -40 40 -50 50 -60 60 ISOLATION -70 70 -80 80 -90 90 CROSSTALK -100 -110 1k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 17. CROSSTALK AND OFF ISOLATION 11 TRANSISTOR COUNT: ISL84541: 66 ISL84542: 66 ISL84543: 66 ISL84544: 58 PROCESS: Si Gate CMOS 100 10k GND OFF ISOLATION (dB) CROSSTALK (dB) 4 FIGURE 14. TURN - OFF TIME vs SUPPLY VOLTAGE NORMALIZED GAIN (dB) FIGURE 13. TURN - ON TIME vs SUPPLY VOLTAGE 3 600 PHASE (DEGREES) 2 ISL84541, ISL84542, ISL84543, ISL84544 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) N 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- A2 SEATING PLANE A L D1 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - C L B1 0.045 0.070 1.15 1.77 8, 10 eA C 0.008 0.014 0.204 C D 0.355 0.400 9.01 eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC eA 0.300 BSC 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. eB - L 0.115 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 12 5 D1 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 0.355 10.16 N 8 2.54 BSC 7.62 BSC 0.430 - 0.150 2.93 10.92 3.81 8 6 7 4 9 Rev. 0 12/93 ISL84541, ISL84542, ISL84543, ISL84544 Mini Small Outline Plastic Packages (MSOP) N M8.118 (JEDEC MO-187AA) 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 INCHES E -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE SEATING PLANE -CA 4X θ A2 A1 b -H- 0.10 (0.004) L SEATING PLANE C MAX MIN MAX NOTES 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 0.026 BSC 0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (0.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only. 13 0.65 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 0.037 REF N -A- 10. Datums -A -H- . MIN A L1 e D SYMBOL e L1 MILLIMETERS 0.95 REF 8 R 0.003 R1 0 α - 8 - 0.07 0.003 - 5o 15o 0o 6o 7 - - 0.07 - - 5o 15o - 0o 6o Rev. 2 01/03 ISL84541, ISL84542, ISL84543, ISL84544 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) N INDEX AREA 0.25(0.010) M H 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M E INCHES -B- 1 2 SYMBOL 3 L SEATING PLANE -A- h x 45o A D -C- e µα A1 B 0.25(0.010) M C C A M B S 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 14 MILLIMETERS MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N NOTES: MAX A1 e 0.10(0.004) MIN α 8 0o 8 7 8o Rev. 0 12/93 ISL84541, ISL84542, ISL84543, ISL84544 Small Outline Transistor Plastic Packages (SOT23-6) 0.20 (0.008) M P6.064 VIEW C C 6 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE CL INCHES e b SYMBOL 6 5 4 CL CL E1 E 1 2 3 e1 C D CL A A2 SEATING PLANE A1 -C- WITH b PLATING b1 c c1 MILLIMETERS MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - A1 0.000 0.0059 0.00 0.15 - A2 0.036 0.051 0.90 1.30 - b 0.012 0.020 0.30 0.50 - b1 0.012 0.018 0.30 0.45 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 D 0.111 0.118 2.80 3.00 3 E 0.103 0.118 2.60 E1 0.060 0.068 1.50 3.00 - 1.75 3 e 0.0374 Ref 0.95 Ref - e1 0.0748 Ref 1.90 Ref - L 0.10 (0.004) C MIN 0.014 0.022 0.35 0.55 L1 0.024 Ref. 0.60 Ref. L2 0.010 Ref. 0.25 Ref. N 6 6 4 5 R 0.004 - 0.10 - R1 0.004 0.010 0.10 0.25 α 0o 8o 0o 8o Rev. 3 9/03 BASE METAL NOTES: 1. Dimensioning and tolerance per ASME Y14.5M-1994. 4X θ1 2. Package conforms to EIAJ SC-74 and JEDEC MO178AB. 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. R1 4. Footlength L measured at reference to gauge plane. R 5. “N” is the number of terminal positions. GAUGE PLANE SEATING PLANE L C L1 4X θ1 VIEW C 15 α L2 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only ISL84541, ISL84542, ISL84543, ISL84544 Small Outline Transistor Plastic Packages (SOT23-8) 0.20 (0.008) M CL P8.064 C VIEW C 8 LEAD SMALL OUTLINE TRANSISTOR PLASTIC PACKAGE e b INCHES SYMBOL 8 6 7 5 CL CL E 1 2 3 E1 MILLIMETERS MAX MIN MAX NOTES A 0.036 0.057 0.90 1.45 - A1 0.000 0.0059 0.00 0.15 - A2 0.036 0.051 0.90 1.30 - b 0.009 0.015 0.22 0.38 - b1 0.009 0.013 0.22 0.33 c 0.003 0.009 0.08 0.22 6 4 e1 C D CL A MIN A2 A1 SEATING PLANE -C- c1 0.003 0.008 0.08 0.20 6 D 0.111 0.118 2.80 3.00 3 E 0.103 0.118 2.60 3.00 - E1 0.060 0.067 1.50 1.70 3 e 0.0256 Ref 0.65 Ref - e1 0.0768 Ref 1.95 Ref - L 0.10 (0.004) C 0.014 0.022 0.35 0.55 L1 0.024 Ref. 0.60 Ref. L2 0.010 Ref. 0.25 Ref. N 8 8 5 WITH b R 0.004 - 0.10 - PLATING b1 R1 0.004 0.010 0.10 0.25 α 0o 8o 0o 8o c c1 4 Rev. 2 9/03 NOTES: BASE METAL 1. Dimensioning and tolerance per ASME Y14.5M-1994. 2. Package conforms to EIAJ SC-74 and JEDEC MO178BA. 4X θ1 3. Dimensions D and E1 are exclusive of mold flash, protrusions, or gate burrs. 4. Footlength L measured at reference to gauge plane. R1 5. “N” is the number of terminal positions. R GAUGE PLANE SEATING PLANE L C L1 α 6. These Dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only L2 4X θ1 VIEW C All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16