TI1 MSP430FR2310IPW16R Mixed-signal microcontroller Datasheet

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MSP430FR2311, MSP430FR2310
SLASE58 – FEBRUARY 2016
MSP430FR231x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
(1)
1
Operation voltage is restricted by SVS levels (see VSVSH- and
VSVSH+ in Table 5-1)
•
•
•
•
•
•
•
•
Multiple Input Selections
Configurable High-Power and Low-Power
Modes
– Transimpedance Amplifier (TIA)
• Current-to-Voltage Conversion
• Half-Rail Input
• Low-Leakage Negative Input Down to 50 pA
• Rail-to-Rail Output
• Multiple Input Selections
• Configurable High-Power and Low-Power
Modes
Clock System (CS)
– On-Chip 32-kHz RC Oscillator (REFO)
– On-Chip 16-MHz Digitally Controlled Oscillator
(DCO) With Frequency Locked Loop (FLL)
• ±1% Accuracy With On-Chip Reference at
Room Temperature
– On-Chip Very Low-Frequency 10-kHz Oscillator
(VLO)
– On-Chip High-Frequency Modulation Oscillator
(MODOSC)
– External 32-kHz Crystal Oscillator (LFXT)
– External High-Frequency Crystal Oscillator up to
16 MHz (HFXT)
– Programmable MCLK Prescalar of 1 to 128
– SMCLK Derived From MCLK With
Programmable Prescalar of 1, 2, 4, or 8
General Input/Output and Pin Functionality
– 16 I/Os on 20-Pin Package
– 12 Interrupt Pins (8 Pins of P1 and 4 Pins of P2)
Can Wake MCU From LPMs
– All I/Os are Capacitive Touch I/Os
Development Tools and Software
– Free Professional Development Environments
– Development Kit (TBD)
Family Members (Also See Section 3)
– MSP430FR2311: 3.75KB of Program FRAM +
1KB of RAM
– MSP430FR2310: 2KB of Program FRAM + 1KB
of RAM
Package Options
– 20-Pin: TSSOP (PW20)
– 16-Pin: TSSOP (PW16)
– 16-Pin: QFN (RGY16)
For Complete Module Descriptions, See the
MSP430FR4xx and MSP430FR2xx Family User's
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCT PREVIEW Information. Product in design phase of
development. Subject to change or discontinuance without notice.
PRODUCT PREVIEW
• Embedded Microcontroller
– 16-Bit RISC Architecture up to 16 MHz
– Wide Supply Voltage Range From 1.8 V to
3.6 V (1)
• Optimized Low-Power Modes (at 3 V)
– Active Mode: 126 µA/MHz
– Standby:
• LPM3.5 With VLO: 1 µA
• Real-Time Clock (RTC) Counter (LPM3.5
With 32768-Hz Crystal): 1 µA
– Shutdown (LPM4.5): 25 nA with SVS
• Low-Power Ferroelectric RAM (FRAM)
– Up to 3.75KB of Nonvolatile Memory
– Built-In Error Correction Code (ECC)
– Configurable Write Protection
– Unified Memory of Program, Constants, and
Storage
– 1015 Write Cycle Endurance
– Radiation Resistant and Nonmagnetic
• Intelligent Digital Peripherals
– IR Modulation Logic
– Two 16-Bit Timers With Three Capture/Compare
Registers Each (Timer_B3)
– One 16-Bit Counter-Only RTC Counter
– 16-Bit Cyclic Redundancy Checker (CRC)
• Enhanced Serial Communications
– Enhanced USCI A (eUSCI_A) Supports UART,
IrDA, and SPI
– Enhanced USCI B (eUSCI_B) Supports SPI and
I2C
• High-Performance Analog
– 8-Channel 10-Bit Analog-to-Digital Converter
(ADC)
• Internal 1.5-V Reference
• Sample-and-Hold 200 ksps
– Enhanced Comparator (eCOMP)
• Integrated 6-Bit Digital-to-Analog Converter
(DAC) as Reference Voltage
• Programmable Hysteresis
• Configurable High-Power and Low-Power
Modes
– Smart Analog Combo (SAC-L1)
• Supports General-Purpose OA
• Rail-to-Rail Input and Output
MSP430FR2311, MSP430FR2310
SLASE58 – FEBRUARY 2016
www.ti.com
Guide (SLAU445)
1.2
•
•
•
Applications
Smoke Detectors
Power Banks
Portable Health and Fitness
1.3
•
•
Power Monitoring
Personal Electronics
Description
The ultra-low-power MSP430FR231x FRAM microcontroller (MCU) family consists of several devices that
feature embedded nonvolatile FRAM and different sets of peripherals targeted for various sensing and
measurement applications. The architecture, FRAM, and peripherals, combined with extensive low-power
modes, are optimized to achieve extended battery life in portable and wireless sensing applications.
FRAM is a new nonvolatile memory that combines the speed, flexibility, and endurance of SRAM with the
stability and reliability of flash, all at lower total power consumption.
PRODUCT PREVIEW
The MSP430FR231x FRAM MCU is the world's first microcontroller with a configurable low-leakage
current sense amplifier and features a powerful 16-bit RISC CPU, 16-bit registers, and constant
generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) also allows
the device to wake from low-power modes to active mode typically in less than 10 μs. Additionally,
developers can reduce PCB real estate by up to 75 percent with integrated analog, EEPROM, crystal, and
MCU functionality in a 3.5 mm × 4 mm package. The feature set of this microcontroller is ideal for
applications ranging from smoke detectors to portable health and fitness accessories.
Device Information (1)
PART NUMBER
MSP430FR2311IPW20
MSP430FR2310IPW20
MSP430FR2311IPW16
MSP430FR2310IPW16
MSP430FR2311IRGY
MSP430FR2310IRGY
(1)
(2)
PACKAGE
BODY SIZE (2)
TSSOP (20)
6.5 mm × 4.4 mm
TSSOP (16)
5 mm × 4.4 mm
QFN (16)
4 mm × 3.5 mm
For the most current part, package, and ordering information, see the Package Option Addendum in
Section 9, or see the TI website at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the
Mechanical Data in Section 9.
CAUTION
System-level ESD protection must be applied in compliance with the devicelevel ESD specification to prevent electrical overstress or disturbing of data or
code memory. See MSP430™ System-Level ESD Considerations (SLAA530)
for more information.
2
Device Overview
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1.4
SLASE58 – FEBRUARY 2016
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
P1.x/P2.x
XOUT
XIN
Cap Touch I/O
XT1
DVCC
Clock
System
Control
Power
Management
Module
DVSS
ADC
FRAM
RAM
SAC0
TRI0
eCOMP0
8-ch
Single-end
10-bit
200ksps
3.75KB
2KB
1KB
GP only
TransImpedance
Amplifier
with 6-bit
DAC
CRC16
TB0
TB1
eUSCI_A0
16-bit
Cyclic
Redundancy
Check
Timer_B
3 CC
Registers
Timer_B
3 CC
Registers
(UART,
IrDA, SPI)
I/O Ports
P1(1×8 IOs)
P2(1×4 IOs)
Interrupt
& Wakeup
PA(P1/P2)
1×16 IOs
RST/NMI
MAB
16-MHZ CPU
inc.
16 Registers
MDB
TCK
TMS
TDI/TCLK
TDO
SBWTCK
SBWTDIO
SYS
JTAG
SBW
•
•
•
•
•
Watchdog
eUSCI_B0
(SPI, I2C)
RTC
Counter
BAKMEM
16-bit
Real-Time
Clock
32 Bytes
Backup
Memory
LPM3.5 Domain
Figure 1-1. Functional Block Diagram
The MCU has one main power pair of DVCC and DVSS that supplies digital and analog modules.
Recommended bypass and decoupling capacitors are 4.7 µF to 10 µF and 0.1 µF, respectively, with
±5% accuracy.
All 8 pins of P1 and 4 pins of P2 feature the pin-interrupt function and can wake the MCU from all
LPMs, including LPM4, LPM3.5, and LPM4.5.
Each Timer_B3 has three capture/compare registers. Only CCR1 and CCR2 are externally connected.
CCR0 registers can be used only for internal period timing and interrupt generation.
In LPM3.5, the RTC counter and Backup memory can be functional while the rest of peripherals are
off.
All general-purpose I/Os can be configured as capacitive touch I/Os.
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Device Overview
3
PRODUCT PREVIEW
EEM
MSP430FR2311, MSP430FR2310
SLASE58 – FEBRUARY 2016
www.ti.com
Table of Contents
1
2
3
4
Device Overview ......................................... 1
5.12
Thermal Packaging Characteristics ................. 18
1.1
Features .............................................. 1
5.13
Timing and Switching Characteristics ............... 19
1.2
Applications ........................................... 2
1.3
Description ............................................ 2
1.4
Functional Block Diagram ............................ 3
Revision History ......................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions .............. 6
4.1
Pin Diagrams ......................................... 6
4.2
Pin Attributes ......................................... 9
4.3
Signal Descriptions .................................. 11
.....................................
4.5
Buffer Type ..........................................
4.6
Connection of Unused Pins .........................
Specifications ...........................................
5.1
Absolute Maximum Ratings ........................
5.2
ESD Ratings ........................................
5.3
Recommended Operating Conditions ...............
4.4
5
6
Pin Multiplexing
PRODUCT PREVIEW
5.4
13
13
13
14
14
14
14
7
Active Mode Supply Current Into VCC Excluding
External Current ..................................... 15
Active Mode Supply Current Per MHz .............. 15
Low-Power Mode LPM0 Supply Currents Into VCC
Excluding External Current.......................... 15
Low-Power Mode LPM3 and LPM4 Supply Currents
(Into VCC) Excluding External Current .............. 16
5.5
5.6
5.7
5.8
5.9
5.10
5.11
8
Detailed Description ................................... 42
............................................
.................................................
6.3
Operating Modes ....................................
6.4
Interrupt Vector Addresses..........................
6.5
Memory Organization ...............................
6.6
Bootloader (BSL) ....................................
6.7
JTAG Standard Interface............................
6.8
Spy-Bi-Wire Interface (SBW)........................
6.9
FRAM................................................
6.10 Memory Protection ..................................
6.11 Peripherals ..........................................
6.12 Input/Output Schematics ............................
6.13 Device Descriptors (TLV) ...........................
6.14 Identification .........................................
Applications, Implementation, and Layout........
7.1
Device Connection and Layout Fundamentals ......
6.1
Overview
6.2
CPU
42
42
42
43
45
45
46
46
46
46
47
62
66
67
68
7.2
68
Peripheral- and Interface-Specific Design
Information .......................................... 71
7.3
Typical Applications ................................. 72
Device and Documentation Support ............... 73
8.1
Device Support ...................................... 73
Production Distribution of LPM3 Supply Currents .. 17
Low-Power Mode LPMx.5 Supply Currents (Into
VCC) Excluding External Current .................... 17
8.2
Documentation Support ............................. 75
8.3
Trademarks.......................................... 77
8.4
Electrostatic Discharge Caution ..................... 77
Production Distribution of LPMx.5 Supply Currents 18
Typical Characteristics – Current Consumption Per
Module .............................................. 18
8.5
Glossary ............................................. 77
9
Mechanical, Packaging, and Orderable
Information .............................................. 78
9.1
Packaging Information
..............................
78
2 Revision History
4
DATE
REVISION
NOTES
February 2016
*
Initial Release
Revision History
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SLASE58 – FEBRUARY 2016
3 Device Comparison
Table 3-1 summarizes the features of the available family members.
Table 3-1. Device Comparison (1)
DEVICE
PROGRAM
FRAM (KB)
SRAM
(Bytes)
TB0, TB1
eUSCI_A
eUSCI_B
MSP430FR2311IPW20
3.75
1024
3 × CCR (3)
1
1
8
MSP430FR2310IPW20
2
1024
3 × CCR (3)
1
1
MSP430FR2311IPW16
3.75
1024
1
MSP430FR2310IPW16
2
1024
(4)
MSP430FR2311IRGY
3.75
1024
MSP430FR2310IRGY
2
1024
(2)
(3)
(4)
10-BIT ADC
SAC0(OA)
CHANNELS
TRI0
eCOMP0
I/O
PACKAGE
1
1
1
16
20 PW
(TSSOP)
8
1
1
1
16
20 PW
(TSSOP)
1
8
1
1
1
11
16 PW
(TSSOP)
1
1
8
1
1
1
11
16 PW
(TSSOP)
3 × CCR (3)
1
1
8
1
1
1
12
16 RGY
(QFN)
3 × CCR (3)
1
1
8
1
1
1
12
16 RGY
(QFN)
3 × CCR (3)
(4)
3 × CCR (3)
For the most current device, package, and ordering information, see the Package Option Addendum in Section 9, or see the TI website
at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging
A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM
outputs.
TB1 only can provide one externally connection (TB1.1) on this package type
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Device Comparison
PRODUCT PREVIEW
(1)
(2)
5
MSP430FR2311, MSP430FR2310
SLASE58 – FEBRUARY 2016
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4 Terminal Configuration and Functions
4.1
Pin Diagrams
Figure 4-1 shows the pinout of the 20-pin PW package.
P1.1/UCB0CLK/ACLK/C1/A1
1
20
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.0/UCB0STE/SMCLK/C0/A0/Veref+
2
19
P1.3/UCB0SOMI/UCB0SCL/OA0O/A3
TEST/SBWTCK
3
18
P1.4/UCA0STE/TCK/OA0+/A4
RST/NMI/SBWTDIO
4
17
P1.5/UCA0CLK/TMS/TRI0O/A5
DVCC
5
16
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/TRI0-/A6
MSP430FR2311IPW20
MSP430FR2310IPW20
DVSS
6
15
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
P2.7/TB0CLK/XIN
7
14
P2.0/TB1.1/COUT
P2.6/MCLK/XOUT
8
13
P2.1/TB1.2
P2.5/UCB0SOMI/UCB0SCL
9
12
P2.2/UCB0STE/TB1CLK
P2.4/UCB0SIMO/UCB0SDA
10
11
P2.3/UCB0CLK/TB1TRG
PRODUCT PREVIEW
Figure 4-1. 20-Pin PW (TSSOP) (Top View)
6
Terminal Configuration and Functions
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SLASE58 – FEBRUARY 2016
P2.0/TB1.1/COUT
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
P1.5/UCA0CLK/TMS/TRI0O/A5
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/TRI0-/A6
P1.3/UCB0SOMI/UCB0SCL/OA0O/A3
P1.4/UCA0STE/TCK/OA0+/A4
Figure 4-2 shows the pinout of the 16-pin RGY package.
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
16
9
P2.1/TB1.2
8
P2.6/MCLK/XOUT
PRODUCT PREVIEW
15 14 13 12 11 10
MSP430FR2311IRGY
MSP430FR2310IRGY
4
5
RST/NMI/SBWTDIO
DVCC
6
7
DVSS
3
P2.7/TB0CLK/XIN
2
TEST/SBWTCK
1
P1.0/UCB0STE/SMCLK/C0/A0/Veref+
P1.1/UCB0CLK/ACLK/C1/A1
Figure 4-2. 16-Pin RGY (QFN) (Top View)
Terminal Configuration and Functions
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Figure 4-3 shows the pinout of the 16-pin PW package.
P1.1/UCB0CLK/ACLK/C1/A1
1
16
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/Veref-
P1.0/UCB0STE/SMCLK/C0/A0/Veref+
2
15
P1.3/UCB0SOMI/UCB0SCL/OA0O/A3
TEST/SBWTCK
3
14
P1.4/UCA0STE/TCK/OA0+/A4
RST/NMI/SBWTDIO
4
13
P1.5/UCA0CLK/TMS/TRI0O/A5
DVCC
5
12
TRI0-
MSP430FR2311IPW16
MSP430FR2310IPW16
DVSS
6
11
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/A6
P2.7/TB0CLK/XIN
7
10
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
P2.6/MCLK/XOUT
8
9
P2.0/TB1.1/COUT
Figure 4-3. 16-Pin PW (TSSOP) (Top View)
PRODUCT PREVIEW
8
Terminal Configuration and Functions
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4.2
SLASE58 – FEBRUARY 2016
Pin Attributes
Table 4-1 lists the attributes of all pins.
PIN NUMBER
PW20
1
RGY
1
PW16
1
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE
RESET STATE
AFTER BOR (5)
P1.1 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
I/O
LVCMOS
DVCC
N/A
ACLK
O
LVCMOS
DVCC
N/A
C1
I
Analog
DVCC
N/A
SIGNAL NAME (1)
A1
2
3
4
2
3
4
2
3
4
I
Analog
DVCC
N/A
P1.0 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
I/O
LVCMOS
DVCC
N/A
SMCLK
O
LVCMOS
DVCC
N/A
C0
I
Analog
DVCC
N/A
A0
I
Analog
DVCC
N/A
Veref+
I
Power
DVCC
N/A
TEST (RD)
I
LVCMOS
DVCC
OFF
SBWTCK
I
LVCMOS
DVCC
N/A
RST (RD)
I/O
LVCMOS
DVCC
OFF
NMI
SBWTDIO
I
LVCMOS
DVCC
N/A
I/O
LVCMOS
DVCC
N/A
5
5
5
DVCC
P
Power
DVCC
N/A
6
6
6
DVSS
P
Power
DVCC
N/A
7
7
7
P2.7 (RD)
8
9
10
11
12
13
(1)
(2)
(3)
(4)
(5)
(2)
8
–
–
–
–
9
8
–
–
–
–
–
I/O
LVCMOS
DVCC
OFF
TB0CLK
I
LVCMOS
DVCC
N/A
XIN
I
LVCMOS
DVCC
N/A
P2.6 (RD)
I/O
LVCMOS
DVCC
OFF
MCLK
O
LVCMOS
DVCC
N/A
XOUT
O
LVCMOS
DVCC
N/A
P2.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
N/A
UCB0SCL
I/O
LVCMOS
DVCC
N/A
P2.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
N/A
UCB0SDA
I/O
LVCMOS
DVCC
N/A
P2.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0CLK
N/A
I/O
LVCMOS
DVCC
TB1TRG
I
LVCMOS
DVCC
N/A
P2.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0STE
N/A
I/O
LVCMOS
DVCC
TB1CLK
I
LVCMOS
DVCC
N/A
P2.1(RD)
I/O
LVCMOS
DVCC
OFF
TB1.2
I/O
LVCMOS
DVCC
N/A
PRODUCT PREVIEW
Table 4-1. Pin Attributes
Signals names with (RD) denote the reset default pin name.
To determine the pin mux encodings for each pin, see Section 6.12, Input/Output Schematics.
Signal Types: I = Input, O = Output, I/O = Input or Output.
Buffer Types: LVCMOS, Analog, or Power
Reset States:
OFF = High-impedance input with pullup or pulldown disabled (if available)
N/A = Not applicable
Terminal Configuration and Functions
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Table 4-1. Pin Attributes (continued)
PIN NUMBER
PW20
RGY
PW16
14
10
9
15
PRODUCT PREVIEW
16
–
17
18
19
20
(6)
10
11
12
–
13
14
15
16
10
11
12
13
14
15
16
SIGNAL
TYPE (3)
BUFFER TYPE (4)
POWER SOURCE
RESET STATE
AFTER BOR (5)
P2.0 (RD)
I/O
LVCMOS
DVCC
OFF
TB1.1
I/O
LVCMOS
DVCC
N/A
COUT
O
LVCMOS
DVCC
N/A
P1.7 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0TXD
O
LVCMOS
DVCC
N/A
UCA0SIMO
I/O
LVCMOS
DVCC
N/A
TB0.2
I/O
LVCMOS
DVCC
N/A
TDO
O
LVCMOS
DVCC
N/A
TRI0+
I
Analog
DVCC
N/A
A7
I
Analog
DVCC
N/A
SIGNAL NAME (1)
(2)
VREF+
O
Power
DVCC
N/A
P1.6 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0RXD
I
LVCMOS
DVCC
N/A
UCA0SOMI
I/O
LVCMOS
DVCC
N/A
TB0.1
I/O
LVCMOS
DVCC
N/A
TDI
I
LVCMOS
DVCC
N/A
TCLK
I
LVCMOS
DVCC
N/A
TRI0- (6)
I
Analog
DVCC
N/A
A6
I
Analog
DVCC
N/A
TRI0-
I
Analog
DVCC
N/A
P1.5 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0CLK
I/O
LVCMOS
DVCC
N/A
TMS
I
LVCMOS
DVCC
N/A
TRI0O
O
Analog
DVCC
N/A
A5
I
Analog
DVCC
N/A
P1.4 (RD)
I/O
LVCMOS
DVCC
OFF
UCA0STE
I/O
LVCMOS
DVCC
N/A
TCK
I
LVCMOS
DVCC
N/A
OA0+
I
Analog
DVCC
N/A
A4
I
Analog
DVCC
N/A
P1.3 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SOMI
I/O
LVCMOS
DVCC
N/A
UCB0SCL
I/O
LVCMOS
DVCC
N/A
OA0O
O
Analog
DVCC
N/A
A3
I
Analog
DVCC
N/A
P1.2 (RD)
I/O
LVCMOS
DVCC
OFF
UCB0SIMO
I/O
LVCMOS
DVCC
N/A
UCB0SDA
I/O
LVCMOS
DVCC
N/A
TB0TRG
I
LVCMOS
DVCC
N/A
OA0-
I
Analog
DVCC
N/A
A2
I
Analog
DVCC
N/A
Veref-
I
Power
DVCC
N/A
Not available on TSSOP-16 package
Terminal Configuration and Functions
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4.3
SLASE58 – FEBRUARY 2016
Signal Descriptions
Table 4-2 describes the signals for all device variants and package options.
Table 4-2. Signal Descriptions
FUNCTION
SIGNAL NAME
A0
eCOMP0
TRI0
SAC0
Clock
Debug
System
Power
PIN TYPE
DESCRIPTION
RGY
PW16
2
2
2
I
Analog input A0
A1
1
1
1
I
Analog input A1
A2
20
16
16
I
Analog input A2
A3
19
15
15
I
Analog input A3
A4
18
14
14
I
Analog input A4
A5
17
13
13
I
Analog input A5
A6
16
12
11
I
Analog input A6
A7
15
11
10
I
Analog input A7
Veref+
2
2
2
I
ADC positive reference
Veref-
20
16
16
I
ADC negative reference
C0
2
2
2
I
Comparator input channel C0
C1
1
1
1
I
Comparator input channel C1
COUT
14
10
9
O
Comparator output channel COUT
TRI0+
15
11
10
I
TRI0 positive input
TRI0-
16
12
12
I
TRI0 negative input
TRI0O
17
13
13
O
TRI0 output
OA0+
18
14
14
I
SAC0, OA positive input
OA0-
20
16
16
I
SAC0, OA negative input
OA0O
19
15
15
O
SAC0, OA output
ACLK
1
1
1
O
ACLK output
MCLK
8
8
8
O
MCLK output
SMCLK
2
2
2
O
SMCLK output
XIN
7
7
7
I
Input terminal for crystal oscillator
XOUT
8
8
8
O
Output terminal for crystal oscillator
SBWTCK
3
3
3
I
Spy-Bi-Wire input clock
SBWTDIO
4
4
4
I/O
TCK
18
14
14
I
Test clock
TCLK
16
12
11
I
Test clock input
TDI
16
12
11
I
Test data input
TDO
15
11
10
O
Test data output
TMS
17
13
13
I
Test mode select
TEST
3
3
3
I
Test Mode pin – selected digital I/O on JTAG pins
NMI
4
4
4
I
Nonmaskable interrupt input
RST
4
4
4
I/O
DVCC
5
5
5
P
Power supply
DVSS
6
6
6
P
Power ground
VREF+
15
11
10
P
Output of positive reference voltage with ground as reference
Spy-Bi-Wire data input/output
Reset input, active-low
Terminal Configuration and Functions
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PRODUCT PREVIEW
ADC
PIN NUMBER
PW20
11
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SLASE58 – FEBRUARY 2016
www.ti.com
Table 4-2. Signal Descriptions (continued)
FUNCTION
GPIO
SIGNAL NAME
PRODUCT PREVIEW
(2)
12
DESCRIPTION
1
1
1
I/O
General-purpose I/O
16
16
I/O
General-purpose I/O
P1.3
19
12
15
I/O
General-purpose I/O
P1.4
18
14
14
I/O
General-purpose I/O
(1)
(1)
P1.5
17
13
13
I/O
General-purpose I/O
P1.6
16
12
11
I/O
General-purpose I/O (1)
P1.7
15
11
10
I/O
General-purpose I/O (1)
P2.0
14
10
9
I/O
General-purpose I/O
P2.1
13
9
–
I/O
General-purpose I/O
P2.2
12
–
–
I/O
General-purpose I/O
P2.3
11
–
–
I/O
General-purpose I/O
P2.4
10
–
–
I/O
General-purpose I/O
P2.5
9
–
–
I/O
General-purpose I/O
P2.6
8
8
8
I/O
General-purpose I/O
P2.7
7
7
7
I/O
General-purpose I/O
UCB0SCL
19
15
15
I/O
eUSCI_B0 I2C clock
20
16
16
I/O
eUSCI_B0 I2C data
(2)
9
–
–
I/O
eUSCI_B0 I2C clock
(2)
10
–
–
I/O
eUSCI_B0 I2C data
UCA0STE
18
14
14
I/O
eUSCI_A0 SPI slave transmit enable
UCA0CLK
17
13
13
I/O
eUSCI_A0 SPI clock input/output
UCA0SOMI
16
12
11
I/O
eUSCI_A0 SPI slave out/master in
UCA0SIMO
15
11
10
I/O
eUSCI_A0 SPI slave in/master out
UCB0STE
2
2
2
I/O
eUSCI_B0 slave transmit enable
UCB0CLK
1
1
1
I/O
eUSCI_B0 clock input/output
UCB0SIMO
20
16
16
I/O
eUSCI_B0 SPI slave in/master out
UCB0SOMI
19
15
15
I/O
eUSCI_B0 SPI slave out/master in
UCB0STE (2)
12
–
–
I/O
eUSCI_B0 slave transmit enable
UCB0CLK (2)
11
–
–
I/O
eUSCI_B0 clock input/output
UCB0SIMO (2)
10
–
–
I/O
eUSCI_B0 SPI slave in/master out
eUSCI_B0 SPI slave out/master in
UCB0SOMI
(1)
PIN TYPE
20
UCB0SDA
Timer_B
PW16
P1.2
UCB0SCL
UART
RGY
P1.1
UCB0SDA
I2C
PIN NUMBER
PW20
(2)
9
–
–
I/O
UCA0RXD
16
12
11
I
eUSCI_A0 UART receive data
UCA0TXD
15
11
10
O
eUSCI_A0 UART transmit data
TB0.1
16
12
11
I/O
Timer TB0 CCR1 capture: CCI1A input, compare: Out1
outputs
TB0.2
15
11
10
I/O
Timer TB0 CCR2 capture: CCI2A input, compare: Out2
outputs
TB0CLK
7
7
7
I
Timer clock input TBCLK for TB0
TB0TRG
20
16
16
I
TB0 external trigger input for TB0OUTH
TB1.1
14
10
9
I/O
Timer TB1 CCR1 capture: CCI1A input, compare: Out1
outputs
TB1.2
13
9
–
I/O
Timer TB1 CCR2 capture: CCI2A input, compare: Out2
outputs
TB1CLK
12
–
–
I
Timer clock input TBCLK for TB1
TB1TRG
11
–
–
I
TB1 external trigger input for TB1OUTH
Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to
prevent collisions.
This is the remapped functionality controlled by USCIBRMP bit on SYSCFG2 register, only one of selected port is valid at the same
time.
Terminal Configuration and Functions
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Table 4-2. Signal Descriptions (continued)
FUNCTION
QFN Pad
SIGNAL NAME
PIN NUMBER
PW20
RGY
PW16
–
Pad
–
QFN Thermal pad
PIN TYPE
DESCRIPTION
QFN package exposed thermal pad. TI recommends
connection to VSS.
NOTE
Functions shared with the four JTAG pins cannot be debugged if 4-wire JTAG is used for
debug.
4.4
Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.12.
4.5
Buffer Type
Table 4-3. Buffer Type
PU OR PD
NOMINAL
PU OR PD
STRENGTH
(µA)
OUTPUT
DRIVE
STRENGTH
(mA)
Y (1)
Programmable
See
Section 5.13.4
See
Section 5.13.4.1
3.0 V
N
N
N/A
N/A
See analog modules in
Section 5 for details.
Power (DVCC)
3.0 V
N
N
N/A
N/A
SVS enables hysteresis on
DVCC.
Power (AVCC)
3.0 V
N
N
N/A
N/A
BUFFER TYPE
(STANDARD)
NOMINAL
VOLTAGE
HYSTERESIS
LVCMOS
3.0 V
Analog
(1)
4.6
OTHER
CHARACTERISTICS
Only for input pins.
Connection of Unused Pins
Table 4-4 shows the correct termination of unused pins.
Table 4-4. Connection of Unused Pins (1)
(1)
(2)
PIN
POTENTIAL
Px.0 to Px.7
Open
Set to port function, output direction (PxDIR.n = 1)
COMMENT
RST/NMI
DVCC
47-kΩ pullup or internal pullup selected with 10-nF (or 1.1-nF (2)) pulldown
TEST
Open
This pin always has an internal pulldown enabled.
TRI0-
Open
This pin is a high-impedance output.
Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection
guidelines.
The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like
FET interfaces or GANG programmers.
Terminal Configuration and Functions
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13
PRODUCT PREVIEW
Table 4-3 defines the pin buffer types that are listed in Table 4-1.
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
Voltage applied at DVCC pin to VSS
–0.3
4.1
UNIT
V
Voltage applied to any pin (2)
–0.3
VCC + 0.3
(4.1 V Max)
V
Diode current at any device pin
±2
mA
Maximum junction temperature, TJ
85
°C
125
°C
Storage temperature, Tstg
(1)
(2)
(3)
(3)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.
Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
5.2
ESD Ratings
VALUE
PRODUCT PREVIEW
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
UNIT
±1000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions. Pins listed as ±1000 V may actually have higher performance.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions. Pins listed as ±250 V may actually have higher performance.
5.3
Recommended Operating Conditions
VCC
Supply voltage applied at DVCC pin (1) (2) (3)
VSS
Supply voltage applied at DVSS pin
TA
Operating free-air temperature
–40
85
TJ
Operating junction temperature
–40
85
CDVCC
Recommended capacitor at DVCC (4)
4.7
MIN
fSYSTEM
Processor frequency (maximum MCLK frequency)
fACLK
Maximum ACLK frequency
fSMCLK
Maximum SMCLK frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
14
NOM
1.8
MAX
3.6
0
(3) (5)
UNIT
V
V
10
°C
°C
µF
No FRAM wait states
(NWAITSx = 0)
0
8
With FRAM wait states
(NWAITSx = 1) (6)
0
16 (7)
MHz
40
kHz
16 (7)
MHz
Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset even within the recommended supply voltage range.
Modules may have a different supply voltage range specification. See the specification of the respective module in this data sheet.
The minimum supply voltage is defined by the SVS levels. Refer to the SVS threshold parameters in Table 5-1.
A capacitor tolerance of ±20% or better is required.
Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
Wait states only occur on actual FRAM accesses (that is, on FRAM cache misses). RAM and peripheral accesses are always executed
without wait states.
If clock sources such as HF crystals or the DCO with frequencies >16 MHz are used, the clock must be divided in the clock system to
comply with this operating condition.
Specifications
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SLASE58 – FEBRUARY 2016
Active Mode Supply Current Into VCC Excluding External Current (1)
5.4
FREQUENCY (fMCLK = fSMCLK)
PARAMETER
EXECUTION
MEMORY
TEST
CONDITIONS
1 MHz
0 WAIT STATES
(NWAITSx = 0)
TYP
TYP
MAX
TYP
3.0 V, 25°C
474
2461
2772
3.0 V, 85°C
493
2256
2703
FRAM(100%)
FRAM
100% cache hit ratio
3.0 V, 25°C
196
585
958
3.0 V, 85°C
205
598
974
(2)
RAM
3.0 V, 25°C
219
750
1250
FRAM(0%)
IAM,
IAM,
RAM
(2)
MAX
16 MHz
1 WAIT STATE
(NWAITSx = 1)
FRAM
0% cache hit ratio
IAM,
(1)
8 MHz
0 WAIT STATES
(NWAITSx = 0)
UNIT
MAX
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. Characterized with program executing typical data
processing.
fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO at specified frequency
Program and data entirely reside in FRAM. All execution is from FRAM.
Program and data reside entirely in RAM. All execution is from RAM. No access to FRAM.
5.5
Active Mode Supply Current Per MHz
VCC = 3.0 V, TA = 25°C (unless otherwise noted)
dIAM,FRAM/df
(1)
TEST CONDITIONS
MIN
TYP
(IAM, 75% cache hit rate at 8 MHz –
IAM, 75% cache hit rate at 1 MHz) / 7 MHz
MAX
UNIT
126
µA/MHz
All peripherals are turned on in default settings.
5.6
Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
VCC = 3.0 V, TA = 25°C (unless otherwise noted) (1)
(2)
FREQUENCY (fSMCLK)
PARAMETER
VCC
1 MHz
TYP
ILPM0
(1)
(2)
MAX
8 MHz
TYP
MAX
16 MHz
TYP
2.0 V
158
307
415
3.0 V
169
318
427
UNIT
MAX
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for watchdog timer clocked by SMCLK included.
fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK at specified frequency.
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Specifications
15
PRODUCT PREVIEW
PARAMETER
Active mode current consumption per
MHz, execution from FRAM, no wait
states (1)
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SLASE58 – FEBRUARY 2016
5.7
www.ti.com
Low-Power Mode LPM3 and LPM4 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
VCC
ILPM3,XT1
Low-power mode 3, includes SVS (2)
(3) (4)
ILPM3,VLO
Low-power mode 3, VLO, excludes SVS (5)
ILPM3,
RTC
Low-power mode 3, RTC, excludes SVS (6)
ILPM4,
SVS
Low-power mode 4, includes SVS
–40°C
TYP
25°C
MAX
TYP
85°C
MAX
TYP
MAX
5.25
3.0 V
1.01
1.16
2.53
2.0 V
0.99
1.13
2.49
3.0 V
0.88
1.02
2.39
2.0 V
0.86
1.00
2.35
3.0 V
0.96
1.11
2.49
2.0 V
0.94
1.09
2.45
3.0 V
0.50
0.60
1.93
2.0 V
0.48
0.59
1.91
3.0 V
0.34
0.45
1.77
2.0 V
0.34
0.44
1.75
ILPM4
Low-power mode 4, excludes SVS
ILPM4, RTC, VLO
Low-power mode 4, RTC is soured from VLO,
excludes SVS (7)
3.0 V
0.48
0.59
1.91
2.0 V
0.48
0.58
1.89
ILPM4, RTC, XT1
Low-power mode 4, RTC is soured from XT1,
excludes SVS (8)
3.0 V
0.89
1.04
2.41
2.0 V
0.88
1.02
2.38
PRODUCT PREVIEW
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
16
5.06
UNIT
µA
µA
µA
µA
µA
µA
µA
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current
Not applicable for devices with HF crystal oscillator only.
Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3, includes SVS test conditions:
Current for watchdog timer clocked by ACLK and RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 3, VLO, excludes SVS test conditions:
Current for watchdog timer clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 0 (LPM3),
fXT1 = 32768 Hz, fMCLK = fSMCLK = 0 MHz
RTC periodically wakes up every second with external 32768-Hz as source.
Low-power mode 4, VLO, excludes SVS test conditions:
Current for RTC clocked by VLO included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4, XT1, excludes SVS test conditions:
Current for RTC clocked by XT1 included. RTC disabled. Current for brownout included. SVS disabled (SVSHE = 0).
CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPM4),
fXT1 = 32768 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Specifications
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5.8
SLASE58 – FEBRUARY 2016
Production Distribution of LPM3 Supply Currents
10
LPM3 Supply Current (µA)
9
8
7
6
5
4
3
2
1
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
0
LPM3
RTC Enabled
DVCC = 3 V
SVS Disabled
Figure 5-1. Low-Power Mode 3 Supply Current vs Temperature
5.9
Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VCC
ILPM3.5,
XT1
Low-power mode 3.5, includes SVS (1)
(also see Figure 5-2)
ILPM4.5,
SVS
Low-power mode 4.5, includes SVS (4)
ILPM4.5
(1)
(2)
(3)
(4)
(5)
Low-power mode 4.5, excludes SVS (5)
(2) (3)
–40°C
TYP
MAX
25°C
TYP
85°C
MAX
TYP
MAX
1.23
3.0 V
0.64
0.71
0.86
2.0 V
0.61
0.69
0.83
3.0 V
0.23
0.25
0.30
2.0 V
0.21
0.24
0.29
3.0 V
0.020
0.032
0.071
2.0 V
0.022
0.034
0.068
0.45
0.120
UNIT
µA
µA
µA
Not applicable for devices with HF crystal oscillator only.
Characterized with a Seiko Crystal SC-32S crystal with a load capacitance chosen to closely match the required load.
Low-power mode 3.5, includes SVS test conditions:
Current for RTC clocked by XT1 included. Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 32768 Hz, fACLK = fXT1, fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, includes SVS test conditions:
Current for brownout and SVS included (SVSHE = 1). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
Low-power mode 4.5, excludes SVS test conditions:
Current for brownout included. SVS disabled (SVSHE = 0). Core regulator disabled.
PMMREGOFF = 1, CPUOFF = 1, SCG0 = 1 SCG1 = 1, OSCOFF = 1 (LPMx.5),
fXT1 = 0 Hz, fACLK = fMCLK = fSMCLK = 0 MHz
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Specifications
17
PRODUCT PREVIEW
Temperature (°C)
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5.10 Production Distribution of LPMx.5 Supply Currents
3.0
0.50
LPM4.5 Supply Current (µA)
LPM3.5 Supply Current (µA)
0.45
2.5
2.0
1.5
1.0
0.5
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.0
-40
-35
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
0.00
-40
-30
-20
-10
0
Temperature (°C)
LPM3.5
DVCC = 3 V
10
20
30
40
50
60
70
80
Temperature (°C)
DVCC = 3 V
LPM4.5
SVS Enabled
XT1 Enabled SVS Disabled
PRODUCT PREVIEW
Figure 5-2. LPM3.5 Supply Current vs Temperature
Figure 5-3. LPM4.5 Supply Current vs Temperature
5.11 Typical Characteristics – Current Consumption Per Module
MODULE
TEST CONDITIONS
Timer_B
REFERENCE CLOCK
MIN
TYP
MAX
UNIT
Module input clock
5
µA/MHz
eUSCI_A
UART mode
Module input clock
7
µA/MHz
eUSCI_A
SPI mode
Module input clock
5
µA/MHz
eUSCI_B
SPI mode
Module input clock
5
µA/MHz
eUSCI_B
I2C mode, 100 kbaud
Module input clock
5
µA/MHz
RTC
CRC
From start to end of operation
32 kHz
85
nA
MCLK
8.5
µA/MHz
5.12 Thermal Packaging Characteristics
VALUE
QFN 16 pin (RGY)
θJA
θJC
θJB
(1)
(2)
(3)
18
Junction-to-ambient thermal resistance, still air (1)
Junction-to-case (top) thermal resistance (2)
Junction-to-board thermal resistance (3)
UNIT
41.8
TSSOP 20 pin (PW20)
92.6
TSSOP 16 pin (PW16)
104.1
QFN 16 pin (RGY)
49.1
TSSOP 20 pin (PW20)
26.1
TSSOP 16 pin (PW16)
38.5
QFN 16 pin (RGY)
18.5
TSSOP 20 pin (PW20)
45.0
TSSOP 16 pin (PW16)
49.1
ºC/W
ºC/W
ºC/W
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
Specifications
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5.13 Timing and Switching Characteristics
5.13.1 Power Supply Sequencing
Table 5-1 lists the characteristics of the SVS and BOR.
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-4)
TEST CONDITIONS
MIN
Safe BOR power-down level (1)
TYP
MAX
(2)
V
tBOR, safe
Safe BOR reset delay
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
ISVSH,LPM
SVSH current consumption, low-power modes
VCC = 3.6 V
VSVSH-
SVSH power-down level
1.71
1.80
1.87
VSVSH+
SVSH power-up level
1.76
1.88
1.99
VSVSH_hys
SVSH hysteresis
tPD,SVSH, AM
SVSH propagation delay, active mode
tPD,SVSH, LPM
SVSH propagation delay, low-power modes
(1)
(2)
UNIT
0.1
10
ms
1.5
µA
240
nA
80
V
V
mV
10
µs
100
µs
A safe BOR is correctly generated only if DVCC drops below this voltage before it rises.
When an BOR occurs, a safe BOR is correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+.
Figure 5-4 shows the reset conditions.
V
Power Cycle Reset
V SVS+
SVS Reset
BOR Reset
V SVS–
V BOR
t BOR
t
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
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19
PRODUCT PREVIEW
PARAMETER
VBOR, safe
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5.13.2 Reset Timing
Table 5-2 lists the wake-up times from low-power modes and reset.
Table 5-2. Wake-up Times From Low-Power Modes and Reset
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tWAKE-UP FRAM
(Additional) wake-up time to activate the FRAM
in AM if previously disabled through the FRAM
controller or from a LPM if immediate activation
is selected for wakeup (1)
tWAKE-UP LPM0
Wake-up time from LPM0 to active mode
(1)
3V
tWAKE-UP LPM3
Wake-up time from LPM3 to active mode
(1)
3V
10
µs
tWAKE-UP LPM4
Wake-up time from LPM4 to active mode
(2)
3V
10
µs
µs
tWAKE-UP LPM3.5 Wake-up time from LPM3.5 to active mode
tWAKE-UP LPM4.5 Wake-up time from LPM4.5 to active mode
(2)
(2)
PRODUCT PREVIEW
tWAKE-UP-RESET
Wake-up time from RST or BOR event to active
mode (2)
tRESET
Pulse duration required at RST/NMI pin to
accept a reset
(1)
(2)
20
3V
10
µs
200 ns +
2.5 / fDCO
3V
350
SVSHE = 1
3V
350
µs
SVSHE = 0
3V
1
ms
3V
1
ms
2
µs
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) to the first
externally observable MCLK clock edge.
The wake-up time is measured from the edge of an external wake-up signal (for example, port interrupt or wake-up event) until the first
instruction of the user program is executed.
Specifications
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5.13.3 Clock Specifications
Table 5-3 lists the characteristics of the XT1 crystal oscillator (low frequency).
Table 5-3. XT1 Crystal Oscillator (Low Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
TEST CONDITIONS
fXT1, LF
XT1 oscillator crystal, low
frequency
LFXTBYPASS = 0
DCXT1, LF
XT1 oscillator LF duty cycle
Measured at MCLK,
fLFXT = 32768 Hz
fXT1,SW
XT1 oscillator logic-level squarewave input frequency
LFXTBYPASS = 1
DCXT1, SW
LFXT oscillator logic-level squarewave input duty cycle
LFXTBYPASS = 1
OALFXT
Oscillation allowance for
LF crystals (4)
LFXTBYPASS = 0, LFXTDRIVE = {3},
fLFXT = 32768 Hz, CL,eff = 12.5 pF
CL,eff
Integrated effective load
capacitance (5)
tSTART,LFXT
Start-up time
fFault,LFXT
Oscillator fault frequency
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
VCC
MIN
(8)
MAX
32768
30%
(2) (3)
XTS = 0 (9)
70%
40%
0
UNIT
Hz
32768
fOSC = 32768 Hz
LFXTBYPASS = 0, LFXTDRIVE = {3},
TA = 25°C, CL,eff = 12.5 pF
(7)
TYP
Hz
60%
200
kΩ
(6)
1
pF
1000
ms
3500
Hz
To improve EMI on the LFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
When LFXTBYPASS is set, LFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics
defined in the Schmitt-trigger inputs section of this data sheet. Duty cycle requirements are defined by DCLFXT, SW.
Maximum frequency of operation of the entire device cannot be exceeded.
Oscillation allowance is based on a safety factor of 5 for recommended crystals. The oscillation allowance is a function of the
LFXTDRIVE settings and the effective load. In general, comparable oscillator allowance can be achieved based on the following
guidelines, but should be evaluated based on the actual crystal selected for the application:
• For LFXTDRIVE = {0}, CL,eff = 3.7 pF.
• For LFXTDRIVE = {1}, 6 pF ≤ CL,eff ≤ 9 pF.
• For LFXTDRIVE = {2}, 6 pF ≤ CL,eff ≤ 10 pF.
• For LFXTDRIVE = {3}, 6 pF ≤ CL,eff ≤ 12 pF.
Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Requires external capacitors at both terminals. Values are specified by crystal manufacturers.
Includes start-up counter of 1024 clock cycles.
Frequencies above the MAX specification do not set the fault flag. Frequencies in between the MIN and MAX specification may set the
flag. A static condition or stuck at fault condition sets the flag.
Measured with logic-level input frequency but also applies to operation with crystals.
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Specifications
21
PRODUCT PREVIEW
PARAMETER
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Table 5-4 lists the characteristics of the XT1 crystal oscillator (high frequency).
Table 5-4. XT1 Crystal Oscillator (High Frequency)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
HFXT oscillator crystal
frequency, crystal mode
fHFXT
VCC
MIN
TYP
MAX
XT1BYPASS = 0, XTS = 1, XT1HFFREQ = 00
1
XT1BYPASS = 0, XTS = 1, XT1HFFREQ = 01
4.01
6
XT1BYPASS = 0, XTS = 1, XT1HFFREQ = 10
6.01
16
1
16
fHFXT,SW
HFXT oscillator logic-level
square-wave input frequency,
bypass mode
XT1BYPASS = 1, XTS = 1
DCHFXT
HFXT oscillator duty cycle
Measured at ACLK, fHFXT,HF = 4 MHz (4)
40%
60%
DCHFXT,
HFXT oscillator logic-level
square-wave input duty cycle
XT1BYPASS = 1
40%
60%
Oscillation allowance for
HFXT crystals (5)
XT1BYPASS = 0, XT1HFSEL = 1,
fHFXT,HF = 16 MHz, CL,eff = 18 pF
2.4
fOSC = 4 MHz, XTS = 1 (4),
XT1BYPASS = 0, XT1HFFREQ = 00,
XT1DRIVE = 3, TA = 25°C, CL,eff = 18 pF
1.6
fOSC = 16 MHz, XTS = 1 (4),
XT1BYPASS = 0, XT1HFFREQ = 00,
XT1DRIVE = 3, TA = 25°C, CL,eff = 18 pF
1.1
SW
OAHFXT
tSTART,HFXT Start-up time
(6)
PRODUCT PREVIEW
CL,eff
Integrated effective load
capacitance (7) (8)
fFault,HFXT
Oscillator fault frequency (9)
(2) (3)
UNIT
4
MHz
MHz
kΩ
ms
1
(10)
0
pF
800
kHz
(1)
To improve EMI on the HFXT oscillator, the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and techniques that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
(2) When XT1BYPASS is set, HFXT circuits are automatically powered down. Input signal is a digital square wave with parametrics defined
in the Schmitt-trigger Inputs section of this datasheet. Duty cycle requirements are defined by DCHFXT, SW.
(3) Maximum frequency of operation of the entire device cannot be exceeded.
(4) 4-MHz crystal used for lab characterization: Abracon HC49/U AB-4.000MHZ-B2
16-MHz crystal used for lab characterization: Abracon HC49/U AB-16.000MHZ-B2
(5) Oscillation allowance is based on a safety factor of 5 for recommended crystals.
(6) Includes start-up counter of 4096 clock cycles.
(7) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Because the PCB adds additional capacitance, TI recommends verifying the correct load by measuring the oscillator frequency through
MCLK or SMCLK. For a correct setup, the effective load capacitance should always match the specification of the used crystal.
(8) Requires external capacitors at both terminals. Values are specified by crystal manufacturers. Recommended values supported are
14 pF, 16 pF, and 18 pF. Maximum shunt capacitance of 7 pF.
(9) Frequencies above the MAX specification do not set the fault flag. Frequencies between the MIN and MAX might set the flag. A static
condition or stuck at fault condition sets the flag.
(10) Measured with logic-level input frequency but also applies to operation with crystals.
22
Specifications
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Table 5-5 lists the characteristics of the DCO FLL.
Table 5-5. DCO FLL
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
FLL lock frequency, 16 MHz, 25°C
fDCO,
FLL lock frequency, 16 MHz, –40°C to 85°C
VCC
Measured at MCLK, Internal
trimmed REFO as reference
3.0 V
Measured at MCLK, XT1 crystal
as reference
3.0 V
MIN
TYP
MAX
–1.0%
1.0%
–2.0%
2.0%
–0.5%
0.5%
UNIT
FLL
FLL lock frequency, 16 MHz, –40°C to 85°C
fDUTY
Duty cycle
Jittercc
Cycle-to-cycle jitter, 16 MHz
Jitterlong
Long term Jitter, 16 MHz
tFLL, lock
FLL lock time
40%
Measured at MCLK, XT1 crystal
as reference
50%
60%
0.25%
3.0 V
0.022%
200
ms
Table 5-6 lists the characteristics of the DCO frequency.
Table 5-6. DCO Frequency
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-5)
fDCO,
fDCO,
fDCO,
fDCO,
16MHz
12MHz
8MHz
4MHz
TEST CONDITIONS
DCO frequency, 16 MHz
DCO frequency, 12 MHz
DCO frequency, 8 MHz
DCO frequency, 4 MHz
MIN
TYP
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
7.8
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
12.5
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
18
DCORSEL = 101b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
30
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
6
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
9.5
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
13.5
DCORSEL = 100b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
22
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
3.8
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
6.5
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
9.5
DCORSEL = 011b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
16
DCORSEL = 010b,, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
2
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
3.2
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
4.8
DCORSEL = 010b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
8
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MAX
UNIT
PRODUCT PREVIEW
PARAMETER
MHz
MHz
MHz
MHz
Specifications
23
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DCO Frequency (continued)
over recommended operating free-air temperature (unless otherwise noted) (see Figure 5-5)
PARAMETER
fDCO,
fDCO,
2MHz
1MHz
TEST CONDITIONS
DCO frequency, 2 MHz
DCO frequency, 1 MHz
MIN
TYP
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
1
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
1.7
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
2.5
DCORSEL = 001b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
4.2
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 0
0.5
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 000b, DCO = 511
0.85
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 0
1.2
DCORSEL = 000b, DISMOD = 1b,
DCOFTRIM = 111b, DCO = 511
2.1
MAX
UNIT
MHz
MHz
PRODUCT PREVIEW
30
DCOFTRIM = 7
25
DCOFTRIM = 7
Frequency (MHz)
20
DCOFTRIM = 7
15
10
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 7
5
DCOFTRIM = 0
DCOFTRIM = 7
DCOFTRIM = 0
DCOFTRIM = 0
0
DCO
DCORSEL
DCOFTRIM = 0
DCOFTRIM = 0
0
511
0
511
0
511
0
1
511
0
2
3
511
0
511
0
4
5
Figure 5-5. Typical DCO Frequency
Table 5-7 lists the characteristics of the REFO.
Table 5-7. REFO
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
IREFO
TEST CONDITIONS
VCC
REFO oscillator current consumption
TA = 25°C
REFO calibrated frequency
Measured at MCLK
REFO absolute calibrated tolerance
–40°C to 85°C
dfREFO/dT
REFO frequency temperature drift
Measured at MCLK (1)
3.0 V
dfREFO/
dVCC
REFO frequency supply voltage drift
Measured at MCLK at
25°C (2)
1.8 V to 3.6 V
fDC
REFO duty cycle
Measured at MCLK
1.8 V to 3.6 V
tSTART
REFO start-up time
40% to 60% duty cycle
fREFO
(1)
(2)
24
MIN
3.0 V
MAX
15
3.0 V
1.8 V to 3.6 V
TYP
µA
32768
–3.5%
40%
UNIT
Hz
+3.5%
0.01
%/°C
1
%/V
50%
50
60%
µs
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
Specifications
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Table 5-8 lists the characteristics of the internal very-low-power low-frequency oscillator (VLO).
Table 5-8. Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fVLO
TEST CONDITIONS
VLO frequency
dfVLO/dT
Measured at MCLK
VLO frequency temperature drift
Measured at MCLK
(1)
dfVLO/dVCC VLO frequency supply voltage drift
Measured at MCLK (2)
fVLO,DC
Measured at MCLK
(1)
(2)
Duty cycle
VCC
MIN
TYP
MAX
UNIT
3.0 V
10
kHz
3.0 V
0.5
%/°C
4
%/V
1.8 V to 3.6 V
3.0 V
50%
Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V)
NOTE
The VLO clock frequency is reduced by 15% (typical) when the device switches from active
mode or LPM0 to LPM3 or LPM4, because the reference changes. This lower frequency is
not a violation of the VLO specifications (see Table 5-8).
Table 5-9. Module Oscillator (MODOSC)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
fMODOSC
MODOSC frequency
fMODOSC/dT
MODOSC frequency temperature drift
fMODOSC/dVCC
MODOSC frequency supply voltage drift
fMODOSC,DC
Duty cycle
TEST
CONDITIONS
VCC
MIN
TYP
MAX
UNIT
3.0 V
3.8
4.8
5.8
MHz
3.0 V
0.102
1.8 V to 3.6 V
1.02
3.0 V
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40%
50%
%/℃
%/V
60%
Specifications
25
PRODUCT PREVIEW
Table 5-9 lists the characteristics of the module oscillator (MODOSC).
MSP430FR2311, MSP430FR2310
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5.13.4 Digital I/Os
Table 5-10 lists the characteristics of the digital inputs.
Table 5-10. Digital Inputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
2V
0.90
1.50
3V
1.35
2.25
2V
0.50
1.10
3V
0.75
1.65
2V
0.3
0.8
3V
0.4
1.2
UNIT
PRODUCT PREVIEW
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT–)
RPull
Pullup or pulldown resistor
For pullup: VIN = VSS
For pulldown: VIN = VCC
CI,dig
Input capacitance, digital only port pins
VIN = VSS or VCC
3
pF
CI,ana
Input capacitance, port pins with shared analog
functions
VIN = VSS or VCC
5
pF
Ilkg(Px.y)
High-impedance leakage current (also see
(2)
)
t(int)
External interrupt timing (External trigger pulse
duration to set interrupt flag) (3)
(1)
(2)
(3)
(1)
and
Ports with interrupt capability
(see block diagram and
terminal function descriptions)
20
2 V, 3 V
–20
2 V, 3 V
50
35
50
+20
V
V
V
kΩ
nA
ns
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is
disabled.
An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. The interrupt flag may be set by
trigger signals shorter than t(int).
Table 5-11 lists the characteristics of the digital outputs.
Table 5-11. Digital Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
(1)
2.0 V
1.4
2.0
I(OHmax) = –5 mA (1)
3.0 V
2.4
3.0
I(OLmax) = 3 mA (1)
2.0 V
0.0
0.60
(1)
3.0 V
0.0
0.60
2.0 V
16
3.0 V
16
I(OHmax) = –3 mA
VOH
High-level output voltage
VOL
Low-level output voltage
fPort_CLK
Clock output frequency
CL = 20 pF (2)
trise,dig
Port output rise time, digital only port pins
CL = 20 pF
tfall,dig
Port output fall time, digital only port pins
CL = 20 pF
(1)
(2)
26
I(OLmax) = 5 mA
TYP
MAX
UNIT
V
V
MHz
2.0 V
10
3.0 V
7
2.0 V
10
3.0 V
5
ns
ns
The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop
specified.
The port can output frequencies at least up to the specified limit and might support higher frequencies.
Specifications
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5.13.4.1 Digital I/O Typical Characteristics
10
Low-Level Output Current (mA)
20
15
10
5
T A = 85°C
T A = 25°C
0
T A = -40°C
-5
7.5
5
T A = 85°C
2.5
T A = 25°C
T A = -40°C
0
0
0.5
1
1.5
2
2.5
3
0
0.25
0.5
Low-Level Output Voltage (V)
DVCC = 3 V
1
1.25
1.5
1.75
2
DVCC = 2 V
Figure 5-6. Typical Low-Level Output Current
vs
Low-Level Output Voltage
Figure 5-7. Typical Low-Level Output Current
vs
Low-Level Output Voltage
5
0
T A = 85°C
High-Level Output Current (mA)
High-Level Output Current (mA)
0.75
Low-Level Output Voltage (V)
0
T A = 25°C
-5
T A = -40°C
-10
-15
-20
-25
T A = 85°C
T A = 25°C
-2.5
T A = -40°C
-5
-7.5
-10
-30
0
0.5
1
1.5
2
2.5
High-Level Output Voltage (V)
3
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
High-Level Output Voltage (V)
DVCC = 2 V
DVCC = 3 V
Figure 5-8. Typical High-Level Output Current
vs
High-Level Output Voltage
Figure 5-9. Typical High-Level Output Current
vs
High-Level Output Voltage
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27
PRODUCT PREVIEW
Low-Level Output Current (mA)
25
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5.13.5 VREF+ Built-in Reference
Table 5-12 lists the characteristics of the VREF+.
Table 5-12. VREF+
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VREF+
Positive built-in reference voltage
EXTREFEN = 1 with 1-mA load
current to ground
TCREF+
Temperature coefficient of built-in
reference voltage
EXTREFEN = 1 with 1-mA load
current
VCC
MIN
TYP
MAX
UNIT
2.0 V, 3.0 V
1.15
1.19
1.23
V
30
µV/°C
5.13.6 Timer_B
Table 5-13 lists the characteristics of the Timer_B clock frequency.
Table 5-13. Timer_B Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
PRODUCT PREVIEW
fTB
28
TEST CONDITIONS
Timer_B input clock frequency
Specifications
Internal: SMCLK, ACLK
External: TBCLK
Duty cycle = 50% ±10%
VCC
2.0 V,
3.0 V
MIN
TYP
MAX
UNIT
16
MHz
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5.13.7 eUSCI
Table 5-14 lists the characteristics of the eUSCI (UART mode) clock frequency.
Table 5-14. eUSCI (UART Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fBITCLK
BITCLK clock frequency
(equals baud rate in Mbaud)
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
VCC
MIN
TYP
MAX
UNIT
2.0 V,
3.0 V
16
MHz
2.0 V,
3.0 V
5
MHz
MAX
UNIT
Table 5-15 lists the switching characteristics of the eUSCI (UART mode).
Table 5-15. eUSCI (UART Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
VCC
MIN
TYP
UCGLITx = 0
tt
UART receive deglitch time
(1)
UCGLITx = 1
UCGLITx = 2
12
40
2.0 V,
3.0 V
UCGLITx = 3
(1)
ns
68
110
Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are
correctly recognized, their duration must exceed the maximum specification of the deglitch time.
Table 5-16 lists the characteristics of the eUSCI (SPI master mode) clock frequency.
Table 5-16. eUSCI (SPI Master Mode) Clock Frequency
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
feUSCI
CONDITIONS
VCC
MIN
TYP
Internal: SMCLK, MODCLK
Duty cycle = 50% ±10%
eUSCI input clock frequency
MAX
UNIT
8
MHz
Table 5-17 lists the switching characteristics of the eUSCI (SPI master mode).
Table 5-17. eUSCI (SPI Master Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
tSTE,LEAD
STE lead time, STE active to clock
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
tSTE,LAG
STE lag time, Last clock to STE
inactive
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCLK
cycles
tSU,MI
SOMI input data setup time
tHD,MI
SOMI input data hold time
tVALID,MO
SIMO output data valid time (2)
UCLK edge to SIMO valid,
CL = 20 pF
tHD,MO
SIMO output data hold time (3)
CL = 20 pF
(1)
(2)
(3)
2.0 V
47
3.0 V
35
2.0 V
0
3.0 V
0
ns
ns
2.0 V
20
3.0 V
20
2.0 V
0
3.0 V
0
ns
ns
fUCxCLK = 1/2tLO/HI with tLO/HI = max(tVALID,MO(eUSCI) + tSU,SI(Slave), tSU,MI(eUSCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-10 and Figure 5-11.
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-10 and Figure 5-11.
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PRODUCT PREVIEW
PARAMETER
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1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tSU,MI
tHD,MI
SOMI
tVALID,MO
SIMO
Figure 5-10. SPI Master Mode, CKPH = 0
1/fUCxCLK
CKPL = 0
PRODUCT PREVIEW
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,MI
tSU,MI
SOMI
tVALID,MO
SIMO
Figure 5-11. SPI Master Mode, CKPH = 1
30
Specifications
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Table 5-18 lists the switching characteristics of the eUSCI (SPI slave mode).
Table 5-18. eUSCI (SPI Slave Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1)
TEST CONDITIONS
tSTE,LEAD
STE lead time, STE active to clock
tSTE,LAG
STE lag time, Last clock to STE inactive
tSTE,ACC
STE access time, STE active to SOMI data out
tSTE,DIS
STE disable time, STE inactive to SOMI high
impedance
tSU,SI
SIMO input data setup time
tHD,SI
SIMO input data hold time
tVALID,SO
SOMI output data valid time (2)
tHD,SO
SOMI output data hold time
(1)
(2)
(3)
(3)
UCLK edge to SOMI valid,
CL = 20 pF
CL = 20 pF
VCC
MIN
2.0 V
55
3.0 V
45
2.0 V
20
3.0 V
20
TYP
MAX
ns
ns
2.0 V
65
3.0 V
40
2.0 V
40
3.0 V
35
2.0 V
8
3.0 V
6
2.0 V
12
3.0 V
12
65
30
3.0 V
5
ns
ns
3.0 V
5
ns
ns
2.0 V
2.0 V
UNIT
ns
PRODUCT PREVIEW
PARAMETER
ns
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(eUSCI), tSU,MI(Master) + tVALID,SO(eUSCI)).
For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.
Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-12 and Figure 5-13.
Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. Refer to the timing diagrams in
Figure 5-12 and Figure 5-13.
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tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tSU,SIMO
tLOW/HIGH
tHD,SIMO
SIMO
tACC
tDIS
tVALID,SOMI
SOMI
Figure 5-12. SPI Slave Mode, CKPH = 0
PRODUCT PREVIEW
tSTE,LAG
tSTE,LEAD
STE
1/fUCxCLK
CKPL = 0
UCLK
CKPL = 1
tLOW/HIGH
tLOW/HIGH
tHD,SI
tSU,SI
SIMO
tACC
tDIS
tVALID,SO
SOMI
Figure 5-13. SPI Slave Mode, CKPH = 1
32
Specifications
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Table 5-19 lists the switching characteristics of the eUSCI (I2C mode).
Table 5-19. eUSCI (I2C Mode) Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-14)
TEST CONDITIONS
feUSCI
eUSCI input clock frequency
fSCL
SCL clock frequency
VCC
MIN
TYP
Internal: SMCLK, MODCLK
External: UCLK
Duty cycle = 50% ±10%
2.0 V, 3.0 V
fSCL = 100 kHz
UNIT
16
MHz
400
kHz
4.0
tHD,STA
Hold time (repeated) START
tSU,STA
Setup time for a repeated START
tHD,DAT
Data hold time
2.0 V, 3.0 V
0
ns
tSU,DAT
Data setup time
2.0 V, 3.0 V
250
ns
tSU,STO
fSCL > 100 kHz
fSCL = 100 kHz
fSCL > 100 kHz
fSCL = 100 kHz
Setup time for STOP
fSCL > 100 kHz
Pulse duration of spikes suppressed by
input filter
tSP
2.0 V, 3.0 V
0
MAX
2.0 V, 3.0 V
2.0 V, 3.0 V
µs
0.6
4.7
µs
0.6
4.0
µs
0.6
UCGLITx = 0
50
600
UCGLITx = 1
25
300
12.5
150
UCGLITx = 2
2.0 V, 3.0 V
UCGLITx = 3
6.3
75
UCCLTOx = 1
tTIMEOUT
Clock low time-out
UCCLTOx = 2
27
2.0 V, 3.0 V
30
UCCLTOx = 3
tSU,STA
tHD,STA
ns
PRODUCT PREVIEW
PARAMETER
ms
33
tHD,STA
tBUF
SDA
tLOW
tHIGH
tSP
SCL
tSU,DAT
tSU,STO
tHD,DAT
Figure 5-14. I2C Mode Timing
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5.13.8 ADC
Table 5-20 lists the characteristics of the ADC power supply and input range conditions.
Table 5-20. ADC, Power Supply and Input Range Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
DVCC
ADC supply voltage
V(Ax)
Analog input voltage range
IADC
Operating supply current into
DVCC terminal, reference
current not included, repeatsingle-channel mode
fADCCLK = 5 MHz, ADCON = 1,
REFON = 0, SHT0 = 0, SHT1 = 0,
ADCDIV = 0, ADCCONSEQx = 10b
CI
Input capacitance
Only one terminal Ax can be selected at one
time from the pad to the ADC capacitor array,
including wiring and pad
RI
Input MUX ON resistance
DVCC = 2 V, 0 V = VAx = DVCC
VCC
All ADC pins
MIN
TYP
MAX
UNIT
2.0
3.6
V
0
DVCC
V
2V
185
3V
207
2.2 V
2.5
µA
3.5
pF
2
kΩ
Table 5-21 lists the ADC 10-bit timing parameters.
Table 5-21. ADC, 10-Bit Timing Parameters
PRODUCT PREVIEW
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
For specified performance of ADC linearity
parameters
2 V to
3.6 V
0.45
5
5.5
MHz
Internal ADC oscillator
(MODOSC)
ADCDIV = 0, fADCCLK = fADCOSC
2 V to
3.6 V
3.8
4.8
5.8
MHz
2 V to
3.6 V
2.18
Conversion time
REFON = 0, Internal oscillator,
10 ADCCLK cycles, 10-bit mode,
fADCOSC = 4.5 MHz to 5.5 MHz
External fADCCLK from ACLK, MCLK, or SMCLK,
ADCSSEL ≠ 0
2 V to
3.6 V
fADCCLK
fADCOSC
tCONVERT
tADCON
tSample
(1)
34
(1)
TEST CONDITIONS
Turn on settling time of
the ADC
The error in a conversion started after tADCON is less
than ±0.5 LSB,
Reference and input signal already settled
Sampling time
RS = 1000 Ω, RI = 36000 Ω, CI = 3.5 pF,
Approximately 8 Tau (t) are required for an error of
less than ±0.5 LSB
2.67
µs
100
2V
1.5
3V
2.0
ns
µs
12 × ADCDIV × 1 / fADCCLK
Specifications
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Table 5-22 lists the ADC 10-bit linearity parameters.
Table 5-22. ADC, 10-Bit Linearity Parameters
over operating free-air temperature range (unless otherwise noted)
TEST CONDITIONS
EI
Integral linearity error (8-bit mode)
Differential linearity error (10-bit mode)
ED
Differential linearity error (8-bit mode)
Offset error (10-bit mode)
EO
Veref+ as reference
Gain error (10-bit mode)
Internal 1.5-V reference
EG
Veref+ as reference
Gain error (8-bit mode)
Internal 1.5-V reference
Total unadjusted error (10-bit mode)
ET
Total unadjusted error (8-bit mode)
TCSENSOR
tSENSOR
(sample)
(1)
(2)
(3)
Veref+ reference
Veref+ reference
Offset error (8-bit mode)
VSENSOR
Veref+ reference
Veref+ as reference
Internal 1.5-V reference
Veref+ as reference
Internal 1.5-V reference
VCC
MIN
TYP
MAX
2.4 V to 3.6 V
–2
2
2.0 V to 3.6 V
–2
2
2.4 V to 3.6 V
–1
1
2.0 V to 3.6 V
–1
1
2.4 V to 3.6 V
–6.5
6.5
2.0 V to 3.6 V
–6.5
6.5
2.4 V to 3.6 V
2.0 V to 3.6 V
2.4 V to 3.6 V
2.0 V to 3.6 V
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
–2.0
2.0
–3.0%
3.0%
UNIT
LSB
LSB
mV
LSB
LSB
LSB
LSB
See
(1)
ADCON = 1, INCH = 0Ch,
TA = 0℃
3V
913
mV
See
(2)
ADCON = 1, INCH = 0Ch
3V
3.35
mV/℃
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB,
AM and all LPMs above LPM3
3V
ADCON = 1, INCH = 0Ch,
Error of conversion result
≤1 LSB, LPM3
3V
Sample time required if channel 12 is
selected (3)
30
µs
100
The temperature sensor offset can vary significantly. TI recommends a single-point calibration to minimize the offset error of the built-in
temperature sensor.
The device descriptor structure contains calibration values for 30℃ ±3℃ and 85 ±3℃ for each of the available reference voltage levels.
The sensor voltage can be computed as VSENSE = TCSENSOR × (Temperature, ℃) + VSENSOR, where TCSENSOR and VSENSOR can be
computed from the calibration values for higher accuracy.
The typical equivalent impedance of the sensor is 700 kΩ. The sample time required includes the sensor on time, tSENSOR(on).
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PRODUCT PREVIEW
PARAMETER
Integral linearity error (10-bit mode)
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5.13.9 Enhanced Comparator (eCOMP)
Table 5-23 lists the characteristics of eCOMP0.
Table 5-23. eCOMP0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
Supply voltage
VIC
Common mode input range
VHYS
DC input hysteresis
MIN
Input offset voltage
ICOMP
Quiescent current draw from
VCC, only comparator
CIN
Input channel capacitance (1)
PRODUCT PREVIEW
RIN
3.6
V
VCC
V
CPEN = 1, CPHSEL = 00
0
CPEN = 1, CPHSEL = 01
10
CPEN = 1, CPHSEL = 10
20
tEN_CP
Comparator enable time
tEN_CP_DAC
tFDLY
mV
30
CPEN = 1, CPMSEL = 0
–30
+30
CPEN = 1, CPMSEL = 1
–40
+40
VIC = VCC / 2, CPEN = 1, CPMSEL = 0
24
35
VIC = VCC / 2, CPEN = 1, CPMSEL = 1
1.6
5
On (switch closed)
10
Off (switch open)
µA
kΩ
MΩ
1
CPMSEL = 1, CPFLT = 0, Overdrive = 20 mV
3.2
CPEN = 0→1, CPMSEL = 0, V+ and V- from pads,
Overdrive = 20 mV
8.5
CPEN = 0→1, CPMSEL = 1, V+ and V- from pads,
Overdrive = 20 mV
1.4
µs
µs
CPEN = 0→1, CPDACEN = 0→1, CPMSEL = 0,
CPDACREFS = 1, CPDACBUF1 = 0F,
Comparator with reference DAC Overdrive = 20 mV
enable time
CPEN = 0→1, CPDACEN = 0→1, CPMSEL = 1,
CPDACREFS = 1, CPDACBUF1 = 0F,
Overdrive = 20 mV
Propagation delay with analog
filter active
mV
pF
20
50
CPMSEL = 0, CPFLT = 0, Overdrive = 20 mV
Propagation delay, response
time
UNIT
0
1
Input channel series resistance
tPD
MAX
2.0
CPEN = 1, CPHSEL = 11
VOFFSET
TYP
8.5
µs
101
CPMSEL = 0, CPFLTDY = 00, Overdrive = 20 mV,
CPFLT = 1
0.7
CPMSEL = 0, CPFLTDY = 01, Overdrive = 20 mV,
CPFLT = 1
1.1
CPMSEL = 0, CPFLTDY = 10, Overdrive = 20 mV,
CPFLT = 1
1.9
CPMSEL = 0, CPFLTDY = 11, Overdrive = 20 mV,
CPFLT = 1
3.4
µs
INL
Integral nonlinearity
–0.5
0.5
LSB
DNL
Differential nonlinearity
–0.5
0.5
LSB
(1)
eCOMP CIN, model, see Figure 5-15 for details.
MSP430
RS
RI
VI
VC
Cpext
CPAD
CIN
VI = External source voltage
RS = External source resistance
RI = Internal MUX-on input resistance
CIN = Input capacitance
CPAD = PAD capacitance
CPext = Parasitic capacitance, external
VC = Capacitance-charging voltage
Figure 5-15. eCOMP Input Circuit
36
Specifications
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5.13.10 Smart Analog Combo (SAC)
Table 5-24 lists the characteristics of SAC0 (SAC-L1, OA).
Table 5-24. SAC0 (SAC-L1, OA)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
VCC
Supply voltage
2.0
3.6
VOS
Input offset voltage
–5
5
dVOS /dT
Offset drift
IB
Input bias current
VCM
Input voltage range
IIDD
ENI
OAPM = 0
3
OAPM = 1
5
Quiescent current
350
OAPM = 1
120
Input noise voltage, f = 0.1 Hz to 10 Hz
Vin = VCC / 2, OAPM = 0
40
Input noise voltage density, f = 1 kHz
Vin = VCC / 2, OAPM = 0
40
Input noise voltage, f = 10 kHz
Vin = VCC / 2, OAPM = 0
20
OAPM = 0
70
OAPM = 1
80
OAPM = 0
70
OAPM = 1
80
CMRR
Common-mode rejection ratio
PSRR
Power supply rejection ratio
GBW
Gain bandwidth
AOL
Open-loop voltage gain
φM
Phase margin
Positive slew rate
OAPM = 0
4
OAPM = 1
1.4
OAPM = 0
100
OAPM = 1
100
CL = 50 pF , RL = 2 kΩ
65
CL = 50 pF, OAPM = 0
3
CL = 50 pF, OAPM = 1
1
Cin
Input capacitance
Common mode
VO
Voltage output swing from supply rails
RL = 10 kΩ
tST
OA settling time
1
To 0.1% final value, G = +1, 1-V setup,
CL = 50 pF, OAPM = 1
4.5
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V
µA
µV
µV/Hz
dB
dB
MHz
dB
deg
V/us
2
40
To 0.1% final value, G = +1, 1-V setup,
CL = 50 pF, OAPM = 0
Copyright © 2016, Texas Instruments Incorporated
nA
VCC + 0.1
OAPM = 0
V
mV
µV/℃
5
–0.1
UNIT
PRODUCT PREVIEW
PARAMETER
pF
100
mV
µs
Specifications
37
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5.13.11 Transimpedance Amplifier (TIA)
Table 5-25 lists the characteristics of TRI0.
Table 5-25. TRI0
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
VCC
Supply voltage
2.0
3.6
VOS
Input offset voltage
–5
5
dVOS /dT
Offset drift
IB
Input bias current
TRIPM = 0
3
TRIPM = 1
5
VB = 0 V, TSSOP-16 package with OAdedicated pin input (see Figure 4-3)
TSSOP-20 and QFN-16 packages
VCM
IIDD
ENI
Input voltage range
µV/℃
pA
5
nA
VCC / 2
TRIPM = 0
350
TRIPM = 1
120
V
µA
PRODUCT PREVIEW
Input noise voltage, f = 0.1 Hz to 10 Hz
Vin = VCC / 2, TRIPM = 0
40
µV
Input noise voltage density, f = 1 kHz
Vin = VCC / 2, TRIPM = 0
40
µV/Hz
Input noise voltage, f = 10 kHz
Vin = VCC / 2, TRIPM = 0
16
TRIPM = 0
70
TRIPM = 1
70
TRIPM = 0
70
TRIPM = 1
70
CMRR
Common-mode rejection ratio
PSRR
Power supply rejection ratio
GBW
Gain bandwidth
AOL
Open-loop voltage gain
φM
Phase margin
Positive slew rate
TRIPM = 0
5
TRIPM = 1
1.8
TRIPM = 0
100
TRIPM = 1
100
CL = 50 pF , RL = 2 kΩ, TRIPM = 0
40
CL = 50 pF , RL = 2 kΩ, TRIPM = 1
70
CL = 50 pF, TRIPM = 0
4
CL = 50 pF, TRIPM = 1
1
Cin
Input capacitance
Common mode
VO
Voltage output swing from supply rails
RL = 10 kΩ
tST
TRI settling time
38
V
mV
50
–0.1
Quiescent current
UNIT
Specifications
dB
dB
MHz
dB
deg
V/µs
7
40
To 0.1% final value, G = +1, 1-V setup,
CL = 50 pF, TRIPM = 0
3
To 0.1% final value, G = +1, 1-V setup,
CL = 50 pF, TRIPM = 1
5
pF
100
mV
µs
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5.13.12 FRAM
Table 5-26 lists the characteristics of the FRAM.
Table 5-26. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
Current to write into FRAM
IERASE
Erase current
tWRITE
Write time
IREAD
(1)
(2)
(3)
(4)
MAX
10
Data retention duration
IWRITE
TYP
15
Read and write endurance
tRetention
MIN
TJ = 25°C
100
TJ= 70°C
40
TJ= 85°C
10
cycles
years
IREAD (1)
nA
N/A (2)
nA
tREAD (3)
ns
NWAITSx = 0
1/fSYSTEM (4
)
NWAITSx = 1
2/fSYSTEM (4
Read time
UNIT
ns
)
Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current IREAD is included in the active mode current consumption numbers IAM, FRAM.
FRAM does not require a special erase sequence.
Writing into FRAM is as fast as reading.
The maximum read (and write) speed is specified by fSYSTEM using the appropriate wait state settings (NWAITSx).
5.13.13 Emulation and Debug
Table 5-27 lists the characteristics of the JTAG Spy-Bi-Wire interface.
Table 5-27. JTAG, Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-16)
MAX
UNIT
fSBW
Spy-Bi-Wire input frequency
PARAMETER
2.0 V, 3.0 V
0
8
MHz
tSBW,Low
Spy-Bi-Wire low clock pulse duration
2.0 V, 3.0 V
0.028
15
µs
tSU,SBWTDIO
SBWTDIO setup time (before falling edge of SBWTCK in TMS and TDI
slot Spy-Bi-Wire )
2.0 V, 3.0 V
4
ns
tHD,SBWTDIO
SBWTDIO hold time (after rising edge of SBWTCK in TMS and TDI slot
Spy-Bi-Wire )
2.0 V, 3.0 V
19
ns
tValid,SBWTDIO
SBWTDIO data valid time (after falling edge of SBWTCK in TDO slot
Spy-Bi-Wire )
2.0 V, 3.0 V
31
ns
2.0 V, 3.0 V
110
µs
tSBW, En
Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge)
tSBW,Ret
Spy-Bi-Wire return to normal operation time
Rinternal
Internal pulldown resistance on TEST
(1)
(2)
VCC
(1)
(2)
MIN
TYP
15
2.0 V, 3.0 V
20
35
100
µs
50
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
Maximum tSBW,Rst time after pulling or releasing the TEST/SBWTCK pin low, the Spy-Bi-Wire pins revert from their Spy-Bi-Wire function
to their application function. This time applies only if the Spy-Bi-Wire mode was selected.
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PRODUCT PREVIEW
PARAMETER
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tSBW,EN
1/fSBW
tSBW,Low
tSBW,High
tSBW,Ret
TEST/SBWTCK
tEN,SBWTDIO
tValid,SBWTDIO
RST/NMI/SBWTDIO
tSU,SBWTDIO
tHD,SBWTDIO
Figure 5-16. JTAG Spy-Bi-Wire Timing
Table 5-28 lists the characteristics of the JTAG 4-wire interface.
Table 5-28. JTAG, 4-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 5-17)
PRODUCT PREVIEW
PARAMETER
(1)
VCC
MIN
TYP
MAX
UNIT
10
MHz
fTCK
TCK input frequency
2.0 V, 3.0 V
0
tTCK,Low
Spy-Bi-Wire low clock pulse duration
2.0 V, 3.0 V
15
ns
tTCK,high
Spy-Bi-Wire high clock pulse duration
2.0 V, 3.0 V
15
ns
tSU,TMS
TMS setup time (before rising edge of TCK )
2.0 V, 3.0 V
11
ns
tHD,TMS
TMS hold time (after rising edge of TCK )
2.0 V, 3.0 V
3
ns
tSU,TDI
TDI setup time (before rising edge of TCK )
2.0 V, 3.0 V
13
ns
tHD,TDI
TDI hold time (after rising edge of TCK )
2.0 V, 3.0 V
5
ns
tz-Valid,TDO
TDO high impedance to valid output time (after falling edge of TCK )
2.0 V, 3.0 V
26
ns
tValid,TDO
TDO to new valid output time (after falling edge of TCK )
2.0 V, 3.0 V
26
ns
tValid-Z,TDO
TDO valid to high impedance output time (after falling edge of TCK )
2.0 V, 3.0 V
26
ns
tJTAG,Ret
Spy-Bi-Wire return to normal operation time
Rinternal
Internal pulldown resistance on TEST
(1)
40
15
2.0 V, 3.0 V
20
35
100
µs
50
kΩ
Tools that access the Spy-Bi-Wire interface must wait for the tSBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
Specifications
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1/fTCK
tTCK,Low
tTCK,High
TCK
TMS
tSU,TMS
tHD,TMS
TDI
(or TDO as TDI)
tSU,TDI
tHD,TDI
TDO
tValid,TDO
tValid-Z,TDO
PRODUCT PREVIEW
tZ-Valid,TDO
tJTAG,Ret
TEST
Figure 5-17. JTAG 4-Wire Timing
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6 Detailed Description
6.1
Overview
The MSP430FR231x FRAM MCU features a powerful 16-bit RISC CPU, 16-bit registers, and constant
generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) also allows
the device to wake up from low-power modes to active mode typically in less than 10 µs. The feature set
of this microcontroller is ideal for applications ranging from smoke detectors to portable health and fitness
accessories.
6.2
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter (PC), stack pointer (SP), status register
(SR), and constant generator (CG), respectively. The remaining registers are general-purpose registers.
PRODUCT PREVIEW
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
6.3
Operating Modes
The MSP430 has one active mode and several software selectable low-power modes of operation (see
Table 6-1). An interrupt event can wake up the device from low-power mode LPM0, LPM3 or LPM4,
service the request, and restore back to the low-power mode on return from the interrupt program. Lowpower modes LPM3.5 and LPM4.5 disable the core supply to minimize power consumption.
Table 6-1. Operating Modes
AM
MODE
Maximum System Clock
Power Consumption at 25°C, 3 V
Wake-up time
Wake-up events
Power
42
Detailed Description
LPM0
LPM4
LPM3.5
LPM4.5
STANDBY
OFF
ONLY RTC
COUNTER
SHUTDOWN
16 MHz
40 kHz
0
40 kHz
0
126 µA/MHz
40 µA/MHz
1.11 µA with
RTC counter
only in LFXT
0.45 µA
without SVS
0.71 µA with
RTC counter
only in LFXT
32 nA
without SVS
N/A
instant
10 µs
10 µs
350 µs
350 µs
I/O
RTC Counter
I/O
I/O
ACTIVE
MODE
CPU OFF
16 MHz
LPM3
N/A
All
All
Regulator
Full
Regulation
Full
Regulation
SVS
On
On
Optional
Optional
Optional
Optional
Brown Out
On
On
On
On
On
On
Partial Power Partial Power Partial Power
Down
Down
Down
Power Down
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Table 6-1. Operating Modes (continued)
Clock (1)
Core
Peripherals
I/O
(1)
(2)
(3)
ACTIVE
MODE
LPM0
LPM3
LPM4
LPM3.5
LPM4.5
SHUTDOWN
CPU OFF
STANDBY
OFF
ONLY RTC
COUNTER
MCLK
Active
Off
Off
Off
Off
Off
SMCLK
Optional
Optional
Off
Off
Off
Off
FLL
Optional
Optional
Off
Off
Off
Off
DCO
Optional
Optional
Off
Off
Off
Off
MODCLK
Optional
Optional
Off
Off
Off
Off
REFO
Optional
Optional
Optional
Off
Off
Off
ACLK
Optional
Optional
Optional
Off
Off
Off
XT1HFCLK (2)
Optional
Optional
Off
Off
Off
Off
XT1LFCLK
Optional
Optional
Optional
Off
Optional
Off
VLOCLK
Optional
Optional
Optional
Off
Optional
Off
CPU
On
Off
Off
Off
Off
Off
FRAM
On
On
Off
Off
Off
Off
RAM
On
On
On
On
Off
Off
Backup Memory (3)
On
On
On
On
On
Off
Timer0_B3
Optional
Optional
Optional
Off
Off
Off
Timer1_B3
Optional
Optional
Optional
Off
Off
Off
WDT
Optional
Optional
Optional
Off
Off
Off
eUSCI_A0
Optional
Optional
Off
Off
Off
Off
eUSCI_B0
Optional
Optional
Off
Off
Off
Off
CRC
Optional
Optional
Off
Off
Off
Off
ADC
Optional
Optional
Optional
Off
Off
Off
eCOMP
Optional
Optional
Optional
Optional
Off
Off
TRI
Optional
Optional
Optional
Optional
Off
Off
SAC0
Optional
Optional
Optional
Optional
Off
Off
RTC Counter
Optional
Optional
Optional
Off
Optional
Off
General Digital
Input/Output
On
Optional
State Held
State Held
State Held
State Held
Capacitive Touch I/O
Optional
Optional
Optional
Off
Off
Off
PRODUCT PREVIEW
AM
MODE
The status shown for LPM4 applies to internal clocks only.
HFXT must be disabled before entering into LPM3, LPM4 or LPMx.5 mode.
Backup memory contains one 32-byte register in the peripheral memory space. Refer to Table 6-23 and Table 6-38 for its memory
allocation.
NOTE
XT1CLK and VLOCLK can be active during LPM4 if requested by low-frequency peripherals.
6.4
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are in the address range 0FFFFh to 0FF80h (see
Table 6-2). The vector contains the 16-bit address of the appropriate interrupt-handler instruction
sequence
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Table 6-2. Interrupt Sources, Flags, and Vectors
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Reset
FFFEh
63, Highest
Nonmaskable
FFFCh
62
NMIIFG
OFIFG
Nonmaskable
FFFAh
61
Timer0_B3
TB0CCR0 CCIFG0
Maskable
FFF8h
60
Timer0_B3
TB0CCR1 CCIFG1, TB0CCR2
CCIFG2, TB0IFG (TB0IV)
Maskable
FFF6h
59
Timer1_B3
TB1CCR0 CCIFG0
Maskable
FFF4h
58
Timer1_B3
TB1CCR1 CCIFG1, TB1CCR2
CCIFG2, TB1IFG (TB1IV)
Maskable
FFF2h
57
INTERRUPT SOURCE
INTERRUPT FLAG
System Reset
Power-up, Brownout, Supply Supervisor
External Reset RST
Watchdog Time-out, Key Violation
FRAM uncorrectable bit error detection
Software POR, BOR
FLL unlock error
SVSHIFG
PMMRSTIFG
WDTIFG
PMMPORIFG, PMMBORIFG
SYSRSTIV
FLLULPUC
System NMI
Vacant Memory Access
JTAG Mailbox
FRAM access time error
FRAM bit error detection
User NMI
External NMI
Oscillator Fault
PRODUCT PREVIEW
RTC Counter
RTCIFG
Maskable
FFF0h
56
Watchdog Timer Interval mode
WDTIFG
Maskable
FFEEh
55
eUSCI_A0 Receive or Transmit
UCTXCPTIFG, UCSTTIFG,
UCRXIFG, UCTXIFG (UART
mode)
UCRXIFG, UCTXIFG (SPI
mode)
(UCA0IV))
Maskable
FFECh
54
eUSCI_B0 Receive or Transmit
UCB0RXIFG, UCB0TXIFG (SPI
mode)
UCALIFG, UCNACKIFG,
UCSTTIFG, UCSTPIFG,
UCRXIFG0, UCTXIFG0,
UCRXIFG1, UCTXIFG1,
UCRXIFG2, UCTXIFG2,
UCRXIFG3, UCTXIFG3,
UCCNTIFG,
UCBIT9IFG,UCCLTOIFG(I2C
mode)
(UCB0IV)
Maskable
FFEAh
53
ADC
ADCIFG0, ADCINIFG,
ADCLOIFG, ADCHIIFG,
ADCTOVIFG, ADCOVIFG
(ADCIV)
Maskable
FFE8h
52
P1
P1IFG.0 to P1IFG.7 (P1IV)
Maskable
FFE6h
51
P2
P2IFG.0 to P2IFG.7 (P2IV) (1)
Maskable
FFE4h
50
eCOMP
CPIIFG, CPIFG (CPIV)
Maskable
FFE2h
49
Reserved
Reserved
Maskable
FFE0h–FF88h
Signatures
(1)
44
VMAIFG
JMBINIFG, JMBOUTIFG
CBDIFG, UBDIFG
BSL Signature 2
0FF86h
BSL Signature 1
0FF84h
JTAG Signature 2
0FF82h
JTAG Signature 1
0FF80h
P2.0, P2.1, P2.6, and P2.7 support both pin and software interrupts. Others ports support software interrupts only.
Detailed Description
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6.5
SLASE58 – FEBRUARY 2016
Memory Organization
Table 6-3 shows the memory organization of the MSP430FR231x devices.
Table 6-3. Memory Organization
ACCESS
MSP430FR2311
MSP430FR2310
Read/Write
(Optional Write Protect) (1)
3.75KB
FFFFh–FF80h
FFFFh–F100h
2KB
FFFFh–FF80h
FFFFh–F800h
RAM
Read/Write
1KB
23FFh–2000h
1KB
23FFh–2000h
Bootloader (BSL1) Memory (ROM) (TI
Internal Use)
Read only
2KB
17FFh–1000h
2KB
17FFh–1000h
Bootloader (BSL2) Memory (ROM) (TI
Internal Use)
Read only
1KB
F FFFFh-F FC00h
1KB
F FFFFh-F FC00h
Peripherals
Read/Write
4KB
0FFFh–0000h
4KB
0FFFh–0000h
Memory (FRAM)
Main: interrupt vectors and signatures
Main: code memory
6.6
The Program FRAM can be write protected by setting PFWP bit in SYSCFG0 register. See SYS chapter in MSP430FR4xx and
MSP430FR2xx Family User's Guide (SLAU445) for more details
Bootloader (BSL)
The BSL enables users to program the FRAM or RAM using a UART or I2C serial interface. Access to the
device memory through the BSL is protected by an user-defined password. Use of the BSL requires four
pins (see Table 6-4 and Table 6-5). BSL entry requires a specific entry sequence on the
RST/NMI/SBWTDIO and TEST/SBWTCK pins. For complete description of the features of the BSL and its
implementation, see MSP430 Programming With the Bootloader (BSL) (SLAU319). For the complete
description of feature of the I2C BSL, see the MSP430 I2C Bootloader (BSL) User's Guide (SLAU557).
Table 6-4. UART BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.7
Data transmit
P1.6
Data receive
VCC
Power supply
VSS
Ground supply
Table 6-5. I2C BSL Pin Requirements and Functions
DEVICE SIGNAL
BSL FUNCTION
RST/NMI/SBWTDIO
Entry sequence signal
TEST/SBWTCK
Entry sequence signal
P1.2
Data receive and transmit
P1.3
Clock
VCC
Power supply
VSS
Ground supply
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Detailed Description
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PRODUCT PREVIEW
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6.7
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JTAG Standard Interface
The MSP430 family supports the standard JTAG interface which requires four signals for sending and
receiving data. The JTAG signals are shared with general-purpose I/O. The TEST/SBWTCK pin enables
the JTAG signals. In addition to these signals, the RST/NMI/SBWTDIO pin interfaces with MSP430
development tools and device programmers. Table 6-6 lists the JTAG pin requirements. For further details
on interfacing to development tools and device programmers, see the MSP430 Hardware Tools User's
Guide (SLAU278).
Table 6-6. JTAG Pin Requirements and Function
PRODUCT PREVIEW
6.8
DEVICE SIGNAL
DIRECTION
P1.4/UCA0STE/TCK/OA0+/A4
IN
JTAG FUNCTION
JTAG clock input
P1.5/UCA0CLK/TMS/TRI0O/A5
IN
JTAG state control
JTAG data input and TCLK input
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/TRI0-/A6
IN
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
OUT
JTAG data output
TEST/SBWTCK
IN
Enable JTAG pins
RST/NMI/SBWTDIO
IN
External reset
VCC
Power supply
VSS
Ground supply
Spy-Bi-Wire Interface (SBW)
The MSP430 family supports the 2-wire Spy-Bi-Wire interface. Spy-Bi-Wire can be used to interface with
MSP430 development tools and device programmers. Table 6-7 lists the Spy-Bi-Wire interface pin
requirements. For further details on interfacing to development tools and device programmers, see the
MSP430 Hardware Tools User's Guide (SLAU278).
Table 6-7. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
6.9
DIRECTION
SBW FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RST/NMI/SBWTDIO
IN, OUT
Spy-Bi-Wire data input and output
VCC
–
Power supply
VSS
–
Ground supply
FRAM
The FRAM can be programmed using the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. Features of the FRAM include:
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
6.10 Memory Protection
The device features memory protection of user access authority and write protection include:
• Securing the whole memory map to prevent unauthorized access from JTAG port or BSL, by writing
JTAG and BSL signatures using the JTAG port, SBW, the BSL, or in system by the CPU.
• Write protection enabled to prevent unwanted write operation to FRAM contents by setting the control
bits with accordingly password in System Configuration register 0. For more detailed information, see
the SYS chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
46
Detailed Description
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6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses. All peripherals can be
handled by using all instructions in the memory map. For complete module description, see the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
6.11.1 Power Management Module (PMM) and On-chip Reference Voltages
The PMM includes an integrated voltage regulator that supplies the core voltage to the device. The PMM
also includes supply voltage supervisor (SVS) and brownout protection. The brownout reset circuit (BOR)
is implemented to provide the proper internal reset signal to the device during power-on and power-off.
The SVS circuitry detects if the supply voltage drops below a user-selectable safe level. SVS circuitry is
available on the primary supply.
The device contains two on-chip reference: 1.5 V for internal reference and 1.2 V for external reference.
The 1.5-V reference is internally connected to ADC channel 13. DVCC is internally connected to ADC
channel 15. When DVCC is set as the reference voltage for ADC conversion, the DVCC can be easily
represent as Equation 1 by using ADC sampling 1.5-V reference without any external components
support.
(1)
The 1.5-V reference is also internally connected to Comparator built-in DAC as reference voltage. DVCC
is internally connected to another source of DAC reference, both are controlled by CPDACREFS bit, For
more detailed information, see the Comparator chapter of the MSP430FR4xx and MSP430FR2xx Family
User's Guide (SLAU445).
A
1.2-V
reference
voltage
can
be
buffered
and
output
to
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+, when EXTREFEN = 1 on PMMCTL2 register,
meanwhile the ADC channel 7 can also be selected to monitor this voltage. For more detailed information,
see the MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
6.11.2 Clock System (CS) and Clock Distribution
The clock system includes a 32-kHz low-frequency or up to a 16-MHz high-frequency crystal oscillator
(XT1), an internal very low-power low-frequency oscillator (VLO), an integrated 32-kHz RC oscillator
(REFO), an integrated internal digitally controlled oscillator (DCO) that may use frequency-locked loop
(FLL) locking with internal or external 32-kHz reference clock, and on-chip asynchronous high-speed clock
(MODOSC). The clock system is designed to target cost-effective designs with minimal external
components. A fail-safe mechanism is designed for XT1. The clock system module offers the following
clock signals.
• Main Clock (MCLK): system clock used by the CPU and all relevant peripherals accessed by the bus.
All clock sources except MODOSC can be selected as the source with a predivider of 1, 2, 4, 8, 16,
32, 64, or 128.
• Sub-Main Clock (SMCLK): subsystem clock used by the peripheral modules. SMCLK derives from the
MCLK with a predivider of 1, 2, 4, or 8. This means SMCLK is always equal to or less than MCLK.
• Auxiliary Clock (ACLK): derived from the external XT1 clock or internal REFO clock up to 40 kHz
All peripherals may have one or several clock sources depending on specific functionality. Table 6-8 and
Table 6-9 show the clock distribution used in this device.
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PRODUCT PREVIEW
DVCC = (1023 × 1.5 V) ÷ 1.5-V reference ADC result
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Table 6-8. Clock Distribution
CLOCK
SOURCE
SELECT
BITS (1)
Frequency
Range
MCLK
SMCLK
ACLK
MODCLK
VLOCLK
EXTERNAL PIN
DC to 16 MHz
DC to 16 MHz
DC to 40 kHz
5 MHz ±10%
10 kHz ±50%
–
CPU
N/A
Default
–
–
–
–
–
FRAM
N/A
Default
–
–
–
–
–
RAM
N/A
Default
–
–
–
–
–
CRC
N/A
Default
–
–
–
–
–
I/O
N/A
Default
–
–
–
–
TB0
TBSSEL
–
10b
01b
–
–
TB1
TBSSEL
–
10b
01b
–
–
00b (TB1CLK pin)
eUSCI_A0
UCSSEL
–
10b or 11b
01b
–
–
00b (UCA0CLK pin)
eUSCI_B0
00b (TB0CLK pin)
UCSSEL
–
10b or 11b
01b
–
–
00b (UCB0CLK pin)
WDT
WDTSSEL
–
00b
01b
–
10b
–
ADC
ADCSSEL
–
10b or 11b
01b
00b
–
–
RTC
RTCSS
–
01b
01b
–
11b
–
PRODUCT PREVIEW
(1)
N/A = not applicable
Table 6-9. XTCLK Distribution
OPERATION
MODE
CLOCK SOURCE
SELECT BITS
XTHFCLK
XTLFCLK
XTLFCLK
(LPMx.5)
AM TO LPM0
AM TO LPM3
AM TO LPM3.5
SELMS
10b
10b
10b
SMCLK
SELMS
10b
10b
10b
REFO
SELREF
0b
0b
0b
ACLK
SELA
0b
0b
0b
RTC
RTCSS
–
10b
10b
MCLK
6.11.3 General-Purpose Input/Output Port (I/O)
There are up to 16 I/O ports implemented.
• P1 and P2 are full 8-bit ports.
• All individual I/O bits are independently programmable.
• Any combination of input and output is possible for P1 and P2. All inputs of P1 and four inputs of P2
(P2.0, P2.1, P2.6, P2.7) can be configured for interrupt input.
• Programmable pullup or pulldown on all ports.
• All inputs of P1 and four inputs of P2 (P2.0, P2.1, P2.6, P2.7) can be configured for edge-selectable
interrupt and for LPM3.5, LPM4, and LPM4.5 wake-up input capability.
• Read and write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive Touch I/O functionality is supported on all pins.
48
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NOTE
Configuration of digital I/Os after BOR reset
To prevent any cross currents during start-up of the device, all port pins are high-impedance
with Schmitt triggers and module functions disabled. To enable the I/O functions after a BOR
reset, the ports must be configured first and then the LOCKLPM5 bit must be cleared. For
details, see the Configuration After Reset section in the Digital I/O chapter of the
MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
6.11.4 Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as interval timer and can generate interrupts at
selected time intervals.
WDTSSEL
NORMAL OPERATION
(WATCHDOG AND INTERVAL TIMER MODE)
00
SMCLK
01
ACLK
10
VLOCLK
11
Reserved
6.11.5 System Module (SYS)
The SYS module handles many of the system functions within the device. These include power-on reset
(POR) and power-up clear (PUC) handling, NMI source selection and management, reset interrupt vector
generators, bootloader entry mechanisms, and configuration management (device descriptors) (see
Table 6-11). SYS also includes a data exchange mechanism through SBW called a JTAG mailbox that
can be used in the application.
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PRODUCT PREVIEW
Table 6-10. WDT Clocks
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Table 6-11. System Module Interrupt Vector Registers
INTERRUPT VECTOR
REGISTER
SYSRSTIV, System Reset
PRODUCT PREVIEW
SYSSNIV, System NMI
SYSUNIV, User NMI
ADDRESS
015Eh
INTERRUPT EVENT
VALUE
No interrupt pending
00h
Brownout (BOR)
02h
RSTIFG RST/NMI (BOR)
04h
PMMSWBOR software BOR (BOR)
06h
LPMx.5 wakeup (BOR)
08h
Security violation (BOR)
0Ah
Reserved
0Ch
SVSHIFG SVSH event (BOR)
0Eh
Reserved
10h
Reserved
12h
PMMSWPOR software POR (POR)
14h
WDTIFG watchdog time-out (PUC)
16h
WDTPW password violation (PUC)
18h
FRCTLPW password violation (PUC)
1Ah
Uncorrectable FRAM bit error detection
1Ch
Peripheral area fetch (PUC)
1Eh
PMMPW PMM password violation (PUC)
20h
Reserved
22h
FLL unlock (PUC)
24h
Reserved
26h to 3Eh
No interrupt pending
00h
SVS low-power reset entry
02h
Uncorrectable FRAM bit error detection
04h
Reserved
06h
Reserved
08h
Reserved
0Ah
Reserved
0Ch
Reserved
0Eh
Reserved
10h
VMAIFG Vacant memory access
12h
JMBINIFG JTAG mailbox input
14h
JMBOUTIFG JTAG mailbox output
16h
015Ch
Correctable FRAM bit error detection
18h
Reserved
1Ah to 1Eh
No interrupt pending
00h
NMIIFG NMI pin or SVSH event
02h
OFIFG oscillator fault
04h
Reserved
06h to 1Eh
015Ah
PRIORITY
Highest
Lowest
Highest
Lowest
Highest
Lowest
6.11.6 Cyclic Redundancy Check (CRC)
The 16-bit cyclic redundancy check (CRC) module produces a signature based on a sequence of data
values and can be used for data checking purposes. The CRC generation polynomial is compliant with
CRC-16-CCITT standard of x16 + x12 + x5 + 1.
50
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6.11.7 Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
The eUSCI modules are used for serial data communications. The eUSCI_A module supports either
UART or SPI communications. The eUSCI_B module supports either SPI or I2C communications. In
addition, the eUSCI_A module supports automatic baud-rate detection and IrDA.. The eUSCI_B module is
connected either from P1 port or P2 port, it can be selected from the USCIBRMAP bit of the SYSCFG2
register (see Table 6-12).
PIN
UART
SPI
P1.7
TXD
SIMO
P1.6
RXD
SOMI
P1.5
–
SCLK
P1.4
–
STE
PIN (USCIBRMP = 0)
I2C
SPI
P1.0
–
STE
P1.1
–
SCLK
P1.2
SDA
SIMO
P1.3
SCL
SOMI
eUSCI_A0
eUSCI_B0
PIN (USCIBRMP = 1)
2
I C
SPI
P2.2
–
STE
P2.3
–
SCLK
P2.4
SDA
SIMO
P2.5
SCL
SOMI
6.11.8 Timers (Timer0_B3, Timer1_B3)
The Timer0_B3 and Timer1_B3 modules are 16-bit timers and counters with three capture/compare
registers each (see Table 6-13 and Table 6-14). Each can support multiple captures or compares, PWM
outputs, and interval timing. Each has extensive interrupt capabilities. Interrupts may be generated from
the counter on overflow conditions and from each of the capture/compare registers. The CCR0 registers
on both TB0 and TB1 are not externally connected and can only be used for hardware period timing and
interrupt generation. In Up Mode, they can set the overflow value of the counter.
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PRODUCT PREVIEW
Table 6-12. eUSCI Pin Configurations
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Table 6-13. Timer0_B3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
P2.7
TB0CLK
TBCLK
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
From Capacitive
Touch I/O (internal)
INCLK
From RTC (internal)
CCI0A
ACLK (internal)
CCI0B
DVSS
GND
MODULE BLOCK
MODULE OUTPUT
SIGNAL
DEVICE OUTPUT
SIGNAL
Timer
N/A
CCR0
TB0
Timer1_B3 CCI0B
input
TB1
DVCC
VCC
TB0.1
CCI1A
TB0.1
From eCOMP
(internal)
CCI1B
Timer1_B3 CCI1B
input
DVSS
GND
P1.6
CCR1
DVCC
VCC
TB0.2
CCI2A
TB0.2
From Capacitive
Touch I/O (internal)
CCI2B
Timer1_B3 INCLK
Timer1_B3 CCI2B
input,
IR Input
DVSS
GND
DVCC
VCC
P1.7
PRODUCT PREVIEW
CCR2
TB2
Table 6-14. Timer1_B3 Signal Connections
PORT PIN
DEVICE INPUT
SIGNAL
MODULE INPUT
NAME
TB1CLK
TBCLK
P2.2
ACLK (internal)
ACLK
SMCLK (internal)
SMCLK
Timer0_B3 CCR2B
output (internal)
INCLK
DVSS
CCI0A
Timer0_B3 CCR0B
output (internal)
CCI0B
DVSS
GND
DVCC
VCC
TB1.1
CCI1A
Timer0_B3 CCR1B
output (internal)
CCI1B
DVSS
GND
P2.0
DVCC
VCC
TB1.2
CCI2A
Timer0_B3 CCR2B
output (internal)
CCI2B
DVSS
GND
DVCC
VCC
P2.1
52
Detailed Description
MODULE BLOCK
MODULE OUTPUT
SIGNAL
Timer
N/A
CCR0
TB0
DEVICE OUTPUT
SIGNAL
TB1.1
CCR1
TB1
to ADC trigger
TB1.2
CCR2
TB2
IR Input
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The interconnection of Timer0_B3 and Timer1_B3 can modulate the eUSCI_A pin of
UCA0TXD/UCA0SIMO in either ASK or FSK mode, with which a user can easily acquire a modulated
infrared command for directly driving an external IR diode. The IR functions are fully controlled by the SYS
configuration registers including IREN (enable), IRPSEL (polarity select), IRMSEL (mode select), IRDSEL
(data select), and IRDATA (data) bits. For more information, see the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide (SLAU445).
The Timer_B module includes a feature that puts all Timer_B outputs into a high-impedance state when
the selected source is triggered. The source can be selected from an external pin or an internal signal,
and it is controlled by TBxTRG in SYS. For more information, see the SYS chapter in the MSP430FR4xx
and MSP430FR2xx Family User's Guide (SLAU445).
Table 6-15 lists the Timer_B high-impedance trigger source selections.
Table 6-15. TBxOUTH
TBxOUTH TRIGGER SOURCE
SELECTION
TB0TRGSEL = 0
eCOMP0 output (internal)
TB0TRGSEL= 1
P1.2
TB1TRGSEL = 0
eCOMP0 output (internal)
TB1TRGSEL = 1
P2.3
Timer_B PAD OUTPUT HIGH
IMPEDANCE
P1.6, P1.7
P2.0, P2.1
6.11.9 Backup Memory (BAKMEM)
The BAKMEM supports data retention during LPM3.5 mode. This device provides up to 32 bytes that are
retained during LPM3.5.
6.11.10 Real-Time Clock (RTC) Counter
The RTC counter is a 16-bit modulo counter that is functional in AM, LPM0, LPM3, LPM4, and LPM3.5.
This module may periodically wake up the CPU from LPM0, LPM3, LPM4, and LPM3.5 based on timing
from a low-power clock source such as the XT1, ACLK, or VLO clocks. In AM, RTC can be driven by
SMCLK to generate high-frequency timing events and interrupts. ACLK and SMCLK both can source to
the RTC, however only one of them can be selected simultaneously. The RTC overflow events trigger:
• Timer0_B3 CCI0A
• ADC conversion trigger when ADCSHSx bits are set as 01b
6.11.11 10-Bit Analog-to-Digital Converter (ADC)
The 10-bit ADC module supports fast 10-bit analog-to-digital conversions with single-ended input. The
module implements a 10-bit SAR core, sample select control, reference generator and a conversion result
buffer. A window comparator with a lower and upper limit allows CPU independent result monitoring with
three window comparator interrupt flags.
The ADC supports 10 external inputs and 4 internal inputs (see Table 6-16).
Table 6-16. ADC Channel Connections
ADCSHSx
ADC CHANNELS
EXTERNAL PIN
0
A0/Veref+
P1.0
1
A1/
P1.1
2
A2/Veref-
P1.2
3
A3
P1.3
4
A4
P1.4
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PRODUCT PREVIEW
TBxTRGSEL
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Table 6-16. ADC Channel Connections (continued)
ADCSHSx
ADC CHANNELS
EXTERNAL PIN
5
A5
P1.5
6
A6
P1.6
7
A7 (1)
P1.7
8
Not used
N/A
(1)
9
Not used
N/A
10
Not used
N/A
11
Not used
N/A
12
On-chip temperature
sensor
N/A
13
Reference voltage (1.5 V)
N/A
14
DVSS
N/A
15
DVCC
N/A
When A7 is used, the PMM 1.2-V reference voltage can be output to
this pin by setting the PMM control register. The 1.2-V voltage can
be measured by the A7 channel.
PRODUCT PREVIEW
The analog-to-digital conversion can be started by software or a hardware trigger. Table 6-17 lists the
trigger sources that are available.
Table 6-17. ADC Trigger Signal Connections
ADCSHSx
TRIGGER SOURCE
BINARY
DECIMAL
00
0
ADCSC bit (software trigger)
01
1
RTC event
10
2
TB1.1B
11
3
eCOMP0 COUT
6.11.12 eCOMP0
The enhanced comparator is an analog voltage comparator with built-in 6-bit DAC as an internal voltage
reference. The integrated 6-bit DAC can be set up to 64 steps for comparator reference voltage. This
module has 4-level programmable hysteresis and configurable power modes, high power or low power.
eCOMP0 supports external inputs and internal inputs (see Table 6-18) and outputs (see Table 6-19).
Table 6-18. eCOMP0 Input Channel Connections
CPPSEL, CPNSEL
eCOMP0 CHANNELS
EXTERNAL OR INTERNAL
CONNECTION
000
C0
P1.0
001
C1
P1.1
010
Not used
N/A
011
Not used
N/A
100
C4
SAC0 , OA0O on positive port
TRI0, TRI0O on negative port
101
Not used
N/A
110
C6
Built-in 6-bit DAC
BINARY
54
Detailed Description
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Table 6-19. eCOMP0 Output Channel Connections
eCOMP0 OUT
EXTERNAL PIN OUT, MODULE
1
P2.0
2
TB0.1B, TB0 (TB0OUTH), TB1 (TB1OUTH), ADC
6.11.13 SAC0
The Smart Analog Combo (SAC) integrates a high-performance low-power operational amplifier. SAC-L1
is integrated in FR231x. SAC-L1 supports only a general-purpose amplifier. For more information, see the
SAC chapter in the MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
SAC0 supports external inputs and internal inputs (see Table 6-20 and Table 6-21).
Table 6-20. SAC0 Positive Input Channel Connections
SAC0 CHANNELS
00
SAC0, OA0 positive channel 1
EXTERNAL PIN OUT, MODULE
P1.4
10
SAC0, OA0 positive channel 2
TRI0O
Table 6-21. SAC0 Negative Input Channel Connections
NSEL
SAC0 CHANNELS
EXTERNAL PIN OUT, MODULE
00
SAC0, OA0 negative channel 1
P1.2
10
Not used
N/A
6.11.14 TRI0
The Transimpedance Amplifier (TIA) is a high-performance low-power amplifier with rail-to-rail output. This
module is an amplifier that converts current to voltage. It has programmable power modes: high power or
low power. For more information, see the TRI chapter in the MSP430FR4xx and MSP430FR2xx Family
User's Guide (SLAU445).
The FR231x device in the TSSOP-16 package supports a dedicates low-leakage pad for TRI negative
input to support low-leakage performance. In other packages (TSSOP-20 and QFN-16), the TRI negative
port is shared with a GPIO to support the transimpedance amplifier function. For more information, see
Section 4 and Table 5-25
The TRI supports external input (see Table 6-22 and Section 4).
Table 6-22. TRI Input Channel Connections
TRIPSEL
TRI0 CHANNELS
EXTERNAL PIN OUT, MODULE
00
Positive input
P1.7
01
Not used
N/A
10
Not used
N/A
11
Not used
N/A
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PRODUCT PREVIEW
PSEL
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6.11.15 eCOMP0, SAC0, TRI0, and ADC in SOC Interconnection
Figure 6-1 shows how the high-performance analog modules are internally connected.
A6
P1.6
A5
–
TRI0–
P1.5/TRI0O
P1.7/TRI+
+
00
10
TRI
A7
A1
A0
A0
P1.0
A1
P1.1
A2
P1.2
A3
P1.3
A4
P1.4
A5
P1.5
A6
P1.6
A7
P1.7
00
Software Trigger
01
from RTC
10
ADC
Core
from TB1.1B
DAC
Core
11
A12
from eCOMP
HW Trigger
Selection
ADC
000
On-Chip Temperature Sensor
A13
1.5-V Reference Voltage
A14
DVSS
A15
DVCC
001
P1.1/C1
100
PRODUCT PREVIEW
110
–
Invert
Noninvert
Logic
+
P2.0/COUT
000
P1.0/C0
001
100
110
eCOMP
10
P1.4/OA0+
00
P1.2/OA0–
00
+
P1.3/OA0O
10
–
SAC-L1
A3
A4
A2
Figure 6-1. High-Performance Analog SOC Interconnection
6.11.16 Embedded Emulation Module (EEM)
The EEM supports real-time in-system debugging. The EEM on these devices has the following features:
• Three hardware triggers or breakpoints on memory access
• One hardware trigger or breakpoint on CPU register write access
• Up to four hardware triggers can be combined to form complex triggers or breakpoints
• One cycle counter
• Clock control on module level
56
Detailed Description
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6.11.17 Peripheral File Map
Table 6-23 lists the base address of the registers for each peripheral. Table 6-24 through Table 6-42 list
all of the available registers for each peripheral and their address offsets.
BASE ADDRESS
SIZE
Special Functions (See Table 6-24)
MODULE NAME
0100h
0010h
PMM (See Table 6-25)
0120h
0020h
SYS (See Table 6-26)
0140h
0040h
CS (See Table 6-27)
0180h
0020h
FRAM (See Table 6-28)
01A0h
0010h
CRC (See Table 6-29)
01C0h
0008h
WDT (See Table 6-30)
01CCh
0002h
Port P1, P2 (See Table 6-31)
0200h
0020h
Capacitive Touch I/O (See Table 6-32)
02E0h
0010h
RTC (See Table 6-33)
0300h
0010h
Timer0_B3 (See Table 6-34)
0380h
0030h
Timer1_B3 (See Table 6-35)
03C0h
0030h
eUSCI_A0 (See Table 6-36)
0500h
0020h
eUSCI_B0 (See Table 6-37)
0540h
0030h
Backup Memory (See Table 6-38)
0660h
0020h
ADC (See Table 6-39)
0700h
0040h
eCOMP0 (See Table 6-40)
08E0h
0020h
SAC0 (See Table 6-41)
0C80h
0010h
TRI0 (See Table 6-42)
0F00h
0010h
PRODUCT PREVIEW
Table 6-23. Peripherals Summary
Table 6-24. Special Function Registers (Base Address: 0100h)
REGISTER DESCRIPTION
SFR interrupt enable
SFR interrupt flag
SFR reset pin control
REGISTER
OFFSET
SFRIE1
00h
SFRIFG1
02h
SFRRPCR
04h
Table 6-25. PMM Registers (Base Address: 0120h)
REGISTER
OFFSET
PMM control 0
REGISTER DESCRIPTION
PMMCTL0
00h
PMM control 1
PMMCTL1
02h
PMM control 2
PMMCTL2
04h
PMM interrupt flags
PMMIFG
0Ah
PM5 control 0
PM5CTL0
10h
Table 6-26. SYS Registers (Base Address: 0140h)
REGISTER DESCRIPTION
REGISTER
OFFSET
SYSCTL
00h
Bootloader configuration area
SYSBSLC
02h
JTAG mailbox control
SYSJMBC
06h
JTAG mailbox input 0
SYSJMBI0
08h
JTAG mailbox input 1
SYSJMBI1
0Ah
JTAG mailbox output 0
SYSJMBO0
0Ch
System control
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Table 6-26. SYS Registers (Base Address: 0140h) (continued)
REGISTER
OFFSET
JTAG mailbox output 1
REGISTER DESCRIPTION
SYSJMBO1
0Eh
Bus error vector generator
SYSBERRIV
18h
User NMI vector generator
SYSUNIV
1Ah
System NMI vector generator
SYSSNIV
1Ch
Reset vector generator
SYSRSTIV
1Eh
System configuration 0
SYSCFG0
20h
System configuration 1
SYSCFG1
22h
System configuration 2
SYSCFG2
24h
Table 6-27. CS Registers (Base Address: 0180h)
REGISTER DESCRIPTION
PRODUCT PREVIEW
REGISTER
OFFSET
CS control 0
CSCTL0
00h
CS control 1
CSCTL1
02h
CS control 2
CSCTL2
04h
CS control 3
CSCTL3
06h
CS control 4
CSCTL4
08h
CS control 5
CSCTL5
0Ah
CS control 6
CSCTL6
0Ch
CS control 7
CSCTL7
0Eh
CS control 8
CSCTL8
10h
Table 6-28. FRAM Registers (Base Address: 01A0h)
REGISTER
OFFSET
FRAM control 0
REGISTER DESCRIPTION
FRCTL0
00h
General control 0
GCCTL0
04h
General control 1
GCCTL1
06h
Table 6-29. CRC Registers (Base Address: 01C0h)
REGISTER
OFFSET
CRC data input
REGISTER DESCRIPTION
CRC16DI
00h
CRC data input reverse byte
CRCDIRB
02h
CRC initialization and result
CRCINIRES
04h
CRC result reverse byte
CRCRESR
06h
Table 6-30. WDT Registers (Base Address: 01CCh)
REGISTER DESCRIPTION
Watchdog timer control
REGISTER
OFFSET
WDTCTL
00h
Table 6-31. Port P1, P2 Registers (Base Address: 0200h)
REGISTER DESCRIPTION
REGISTER
OFFSET
P1IN
00h
Port P1 output
P1OUT
02h
Port P1 direction
P1DIR
04h
Port P1 pulling enable
P1REN
06h
Port P1 selection 0
P1SEL0
0Ah
Port P1 selection 1
P1SEL1
0Ch
Port P1 input
58
Detailed Description
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Table 6-31. Port P1, P2 Registers (Base Address: 0200h) (continued)
REGISTER
OFFSET
Port P1 interrupt vector word
REGISTER DESCRIPTION
P1IV
0Eh
Port P1 interrupt edge select
P1IES
18h
P1IE
1Ah
P1IFG
1Ch
Port P1 interrupt enable
Port P1 interrupt flag
Port P2 input
P2IN
01h
Port P2 output
P2OUT
03h
Port P2 direction
P2DIR
05h
Port P2 pulling enable
P2REN
07h
Port P2 selection 0
P2SEL0
0Bh
Port P2 selection 1
P2SEL1
0Dh
Port P2 interrupt vector word
P2IV
1Eh
Port P2 interrupt edge select
P2IES
19h
P2IE
1Bh
P2IFG
1Dh
Port P2 interrupt enable
Port P2 interrupt flag
REGISTER DESCRIPTION
Capacitive touch I/O 0 control
REGISTER
OFFSET
CAPIO0CTL
0Eh
PRODUCT PREVIEW
Table 6-32. Capacitive Touch I/O Registers (Base Address: 02E0h)
Table 6-33. RTC Registers (Base Address: 0300h)
REGISTER DESCRIPTION
REGISTER
OFFSET
RTCCTL
00h
RTCIV
04h
RTC modulo
RTCMOD
08h
RTC counter
RTCCNT
0Ch
RTC control
RTC interrupt vector
Table 6-34. Timer0_B3 Registers (Base Address: 0380h)
REGISTER DESCRIPTION
REGISTER
OFFSET
TB0CTL
00h
Capture/compare control 0
TB0CCTL0
02h
Capture/compare control 1
TB0CCTL1
04h
Capture/compare control 2
TB0CCTL2
06h
TB0R
10h
Capture/compare 0
TB0CCR0
12h
Capture/compare 1
TB0CCR1
14h
Capture/compare 2
TB0CCR2
16h
TB0EX0
20h
TB0IV
2Eh
TB0 control
TB0 counter
TB0 expansion 0
TB0 interrupt vector
Table 6-35. Timer1_B3 Registers (Base Address: 03C0h)
REGISTER DESCRIPTION
TB1 control
REGISTER
OFFSET
TB1CTL
00h
Capture/compare control 0
TB1CCTL0
02h
Capture/compare control 1
TB1CCTL1
04h
Capture/compare control 2
TB1CCTL2
06h
TB1R
10h
TB1 counter
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Table 6-35. Timer1_B3 Registers (Base Address: 03C0h) (continued)
REGISTER
OFFSET
Capture/compare 0
REGISTER DESCRIPTION
TB1CCR0
12h
Capture/compare 1
TB1CCR1
14h
Capture/compare 2
TB1CCR2
16h
TB1EX0
20h
TB1IV
2Eh
TB1 expansion 0
TB1 interrupt vector
Table 6-36. eUSCI_A0 Registers (Base Address: 0500h)
REGISTER
OFFSET
eUSCI_A control word 0
REGISTER DESCRIPTION
UCA0CTLW0
00h
eUSCI_A control word 1
UCA0CTLW1
02h
eUSCI_A control rate 0
UCA0BR0
06h
UCA0BR1
07h
eUSCI_A control rate 1
eUSCI_A modulation control
UCA0MCTLW
08h
UCA0STAT
0Ah
eUSCI_A receive buffer
UCA0RXBUF
0Ch
eUSCI_A transmit buffer
UCA0TXBUF
0Eh
eUSCI_A LIN control
UCA0ABCTL
10h
eUSCI_A IrDA transmit control
lUCA0IRTCTL
12h
eUSCI_A IrDA receive control
IUCA0IRRCTL
13h
UCA0IE
1Ah
UCA0IFG
1Ch
UCA0IV
1Eh
eUSCI_A status
PRODUCT PREVIEW
eUSCI_A interrupt enable
eUSCI_A interrupt flags
eUSCI_A interrupt vector word
Table 6-37. eUSCI_B0 Registers (Base Address: 0540h)
REGISTER
OFFSET
eUSCI_B control word 0
REGISTER DESCRIPTION
UCB0CTLW0
00h
eUSCI_B control word 1
UCB0CTLW1
02h
eUSCI_B bit rate 0
UCB0BR0
06h
eUSCI_B bit rate 1
UCB0BR1
07h
eUSCI_B status word
UCB0STATW
08h
eUSCI_B byte counter threshold
UCB0TBCNT
0Ah
eUSCI_B receive buffer
UCB0RXBUF
0Ch
eUSCI_B transmit buffer
UCB0TXBUF
0Eh
eUSCI_B I2C own address 0
UCB0I2COA0
14h
eUSCI_B I2C own address 1
UCB0I2COA1
16h
eUSCI_B I2C own address 2
UCB0I2COA2
18h
eUSCI_B I2C own address 3
UCB0I2COA3
1Ah
UCB0ADDRX
1Ch
UCB0ADDMASK
1Eh
eUSCI_B receive address
eUSCI_B address mask
eUSCI_B I2C slave address
eUSCI_B interrupt enable
eUSCI_B interrupt flags
eUSCI_B interrupt vector word
60
Detailed Description
UCB0I2CSA
20h
UCB0IE
2Ah
UCB0IFG
2Ch
UCB0IV
2Eh
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REGISTER
OFFSET
Backup memory 0
REGISTER DESCRIPTION
BAKMEM0
00h
Backup memory 1
BAKMEM1
02h
Backup memory 2
BAKMEM2
04h
Backup memory 3
BAKMEM3
06h
Backup memory 4
BAKMEM4
08h
Backup memory 5
BAKMEM5
0Ah
Backup memory 6
BAKMEM6
0Ch
Backup memory 7
BAKMEM7
0Eh
Backup memory 8
BAKMEM8
10h
Backup memory 9
BAKMEM9
12h
Backup memory 10
BAKMEM10
14h
Backup memory 11
BAKMEM11
16h
Backup memory 12
BAKMEM12
18h
Backup memory 13
BAKMEM13
1Ah
Backup memory 14
BAKMEM14
1Ch
Backup memory 15
BAKMEM15
1Eh
PRODUCT PREVIEW
Table 6-38. Backup Memory Registers (Base Address: 0660h)
Table 6-39. ADC Registers (Base Address: 0700h)
REGISTER DESCRIPTION
REGISTER
OFFSET
ADC control 0
ADCCTL0
00h
ADC control 1
ADCCTL1
02h
ADC control 2
ADCCTL2
04h
ADCLO
06h
ADC window comparator low threshold
ADC window comparator high threshold
ADCHI
08h
ADC memory control 0
ADCMCTL0
0Ah
ADC conversion memory
ADCMEM0
12h
ADC interrupt enable
ADC interrupt flags
ADC interrupt vector word
ADCIE
1Ah
ADCIFG
1Ch
ADCIV
1Eh
Table 6-40. eCOMP0 Registers (Base Address: 08E0h)
REGISTER
OFFSET
Comparator control 0
REGISTER DESCRIPTION
CPCTL0
00h
Comparator control 1
CPCTL1
02h
Comparator interrupt
CPINT
06h
CPIV
08h
CPDACCTL
10h
CPDACDATA
12h
Comparator interrupt vector
Comparator built-in DAC control
Comparator built-in DAC data
Table 6-41. SAC0 Registers (Base Address: 0C80h)
REGISTER DESCRIPTION
SAC0 OA control
REGISTER
OFFSET
SAC0OA
00h
Table 6-42. TRI0 Registers (Base Address: 0F00h)
REGISTER DESCRIPTION
TRI control
REGISTER
OFFSET
TRICTL
00h
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6.12 Input/Output Schematics
6.12.1 Port P1 Input/Output With Schmitt Trigger
Figure 6-2 shows the port schematic. Table 6-43 summarizes the selection of the port functions.
A0..A7
OA0+,OA0-,OA0O
TRI0+,TRI0-,TRI0O
C0,C1
From analog module
P1REN.x
P1DIR.x
From Module1
00
01
10
11
2 bit
From Module2
PRODUCT PREVIEW
DVSS
0
DVCC
1
P1SEL.x= 11
00
01
10
11
P1OUT.x
From Module1
From Module2
DVSS
2 bit
P1SEL.x
EN
To module
D
P1IN.x
P1IE.x
P1 Interrupt
Q
D
Bus
Keeper
S
P1IFG.x
P1IES.x
From JTAG
P1.0/UCB0STE/SMCLK/C0/A0/Veref+
Edge
Select
P1.1/UCB0CLK/ACLK/C1/A1
P1.2/UCB0SIMO/UCB0SDA/TB0TRG/OA0-/A2/VerefP1.3/UCB0SOMI/UCB0SCL/OA0O/A3
P1.4/UCA0STE/TCK/OA0+/A4
P1.5/UCA0CLK/TMS/TRI0O/A5
To JTAG
P1.6/UCA0RXD/UCA0SOMI/TB0.1/TDI/TCLK/TRI0-/A6
P1.7/UCA0TXD/UCA0SIMO/TB0.2/TDO/TRI0+/A7/VREF+
Figure 6-2. Port P1 Input/Output With Schmitt Trigger
62
Detailed Description
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Table 6-43. Port P1 Pin Functions
P1.0/UCB0STE/SMCLK/
C0/A0/Veref+
P1.1/UCB0CLK/ACLK/
C1A1
x
0
1
FUNCTION
P1DIR.x
P1SELx
JTAG
P1.0 (I/O)
I: 0; O: 1
00
N/A
UCB0STE
X
01
N/A
SMCLK
1
VSS
0
10
N/A
C0, A0/Veref+
X
11
N/A
P1.1 (I/O)
I: 0; O: 1
0
N/A
UCB0CLK
X
01
N/A
ACLK
1
VSS
0
10
N/A
C1, A1
X
11
N/A
I: 0; O: 1
00
N/A
X
01
N/A
TB0TRG
0
10
N/A
OA0-, A2/Veref-
X
11
N/A
I: 0; O: 1
00
N/A
UCB0SOMI/UCB0SCL
X
01
N/A
OA0O, A3
X
11
N/A
P1.4 (I/O)
I: 0; O: 1
00
Disabled
UCA0STE
X
01
Disabled
OA0+, A4
X
11
Disabled
JTAG TCK
X
X
TCK
P1.5 (I/O)
I: 0; O: 1
00
Disabled
UCA0CLK
X
01
Disabled
TRI0O, A5
X
11
Disabled
JTAG TMS
X
X
TMS
P1.2 (I/O)
P1.2/UCB0SIMO/
UCB0SDA/TB0TRG/
OA0-/A2/Veref-
2
UCB0SIMO/UCB0SDA
P1.3 (I/O)
P1.3/UCB0SOMI/
UCB0SCL/OA0O/A3
P1.4/UCA0STE/TCK/
OA0+/A4
P1.5/UCA0CLK/TMS/
TRI0O/A5
3
4
5
P1.6 (I/O)
P1.6/UCA0RXD/
UCA0SOMI/TB0.1/TDI/
TCLK/TRI0-/A6
6
I: 0; O: 1
00
Disabled
UCA0RXD/UCA0SOMI
X
01
Disabled
TB0.CCI1A
0
TB0.1
1
10
Disabled
TRI0-, A6
X
11
Disabled
JTAG TDI/TCLK
X
X
TDI/TCLK
I: 0; O: 1
00
Disabled
UCA0TXD/UCA0SIMO
X
01
Disabled
TB0.CCI2A
0
TB0.2
1
10
Disabled
TRI0+, A7, VREF+
X
11
Disabled
JTAG TDO
X
X
TDO
P1.7 (I/O)
P1.7/UCA0TXD/
UCA0SIMO/TB0.2/TDO/
TRI0+/A7/VREF+
(1)
7
CONTROL BITS AND SIGNALS (1)
PRODUCT PREVIEW
PIN NAME (P1.x)
X = don't care
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6.12.2 Port P2 Input/Output With Schmitt Trigger
Figure 6-3 shows the port schematic. Table 6-44 summarizes the selection of the port functions.
P2REN.x
P2DIR.x
From Module1
00
01
10
11
2 bit
From Module2
DVSS
0
DVCC
1
PRODUCT PREVIEW
00
01
10
11
P2OUT.x
From Module1
From Module2
DVSS
2 bit
P2SEL.x
EN
To module
D
P2IN.x
P2IE.x
P2 Interrupt
Q
D
Bus
Keeper
S
P2IFG.x
P2IES.x
Edge
Select
P2.0/TB1.1/COUT
P2.1/TB1.2
P2.2/UCB0STE/TB1CLK
P2.3/UCB0CLK/TB1TRG
P2.4/UCB0SIMO/UCB0SDA
P2.5/UCB0SOMI/UCB0SCL
P2.6/MCLK/XOUT
P2.7/TB0CLK/XIN
Figure 6-3. Port P2 Input/Output With Schmitt Trigger
64
Detailed Description
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Table 6-44. Port P2 Pin Functions
x
FUNCTION
P2.0 (I/O)
P2.0/TB1.1/COUT
0
CONTROL BITS AND SIGNALS (1)
P2DIR.x
P2SELx
I: 0; O: 1
00
TB1.CCI1A
0
TB1.1
1
COUT
1
P2.1/TB1.2
P2.2/UCB0STE/TB1CLK
P2.3/UCB0CLK/TB1TRG
P2.4/UCB0SIMO/UCB0SDA
P2.5/UCB0SOMI/UCB0SCL
2
3
4
5
1
10
P2.1 (I/O)0
I: 0; O: 1
00
TB1.CCI2A
0
TB1.2
1
P2.7/TB0CLK/XIN
(1)
6
7
01
P2.2 (I/O)
I: 0; O: 1
00
UCB0STE
X
01
TB1CLK
0
VSS
1
10
P2.3 (I/O)
I: 0; O: 1
00
UCB0CLK
X
01
TB1TRG
0
10
P2.4 (I/O)
I: 0; O: 1
00
UCB0SIMO/UCB0SDA
P2.5 (I/O)
X
01
I: 0; O: 1
00
X
01
I: 0; O: 1
00
UCB0SOMI/UCB0SCL
P2.6 (I/O)
P2.6/MCLK/XOUT
01
MCLK
1
VSS
0
XOUT
X
10
P2.7 (I/O)
I: 0; O: 1
00
TB0CLK
0
VSS
1
XIN
X
PRODUCT PREVIEW
PIN NAME (P2.x)
01
01
10
X = don't care
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6.13 Device Descriptors (TLV)
Table 6-45 lists the Device IDs of the MSP430FR231x device variants. Table 6-46 lists the contents of the
device descriptor tag-length-value (TLV) structure for the devices.
Table 6-45. Device IDs
DEVICE ID
DEVICE
1A04h
1A05h
MSP430FR2311
F0
82
MSP430FR2310
F1
82
Table 6-46. Device Descriptors
DESCRIPTION
VALUE
Info length
1A00h
06h
CRC length
1A01h
06h
1A02h
per unit
1A03h
per unit
CRC value (1)
PRODUCT PREVIEW
Information block
1A04h
Device ID
1A05h
1A06h
per unit
Firmware revision
1A07h
per unit
Die record tag
1A08h
08h
Die record length
1A09h
0Ah
1A0Ah
per unit
1A0Bh
per unit
1A0Ch
per unit
1A0Dh
per unit
1A0Eh
per unit
1A0Fh
per unit
1A10h
per unit
1A11h
per unit
1A12h
per unit
1A13h
per unit
ADC calibration tag
1A14h
per unit
ADC calibration length
1A15h
per unit
1A16h
per unit
1A17h
per unit
1A18h
per unit
Die record
Die X position
Die Y position
Test result
ADC gain factor
ADC offset
ADC 1.5-V reference, temperature 30°C
ADC 1.5-V reference, temperature 85°C
(1)
66
See Table 6-45
Hardware revision
Lot wafer ID
ADC calibration
MSP430FR231x
ADDRESS
1A19h
per unit
1A1Ah
per unit
1A1Bh
per unit
1A1Ch
per unit
1A1Dh
per unit
CRC value covers the check sum from 0x1A04h to 0x1A77h by applying CRC-CCITT-16 polynomial of X16 + X12 + X5 + 1
Detailed Description
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Table 6-46. Device Descriptors (continued)
MSP430FR231x
DESCRIPTION
Reference and DCO
calibration
ADDRESS
VALUE
Calibration tag
1A1Eh
12h
Calibration length
1A1Fh
04h
1A20h
per unit
1A21h
per unit
1A22h
per unit
1A23h
per unit
1.5-V reference factor
DCO tap settings for 16 MHz, temperature 30°C
(2)
(2)
This value can be directly loaded into the DCO bits in the CSCTL0 register to get an accurate 16-MHz frequency at room temperature,
especially when MCU exits from LPM3 and below. TI also suggests using a predivider to decrease the frequency if the temperature drift
might result an overshoot above 16 MHz.
6.14 Identification
The device revision information is shown as part of the top-side marking on the device package. The
device-specific errata sheet describes these markings. For links to all of the errata sheets for the devices
in this data sheet, see Section 8.2.
The hardware revision is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Hardware Revision" entries in Section 6.13.
6.14.2 Device Identification
The device type can be identified from the top-side marking on the device package. The device-specific
errata sheet describes these markings. For links to all of the errata sheets for the devices in this data
sheet, see Section 8.2.
A device identification value is also stored in the Device Descriptor structure in the Info Block section. For
details on this value, see the "Device ID" entries in Section 6.13.
6.14.3 JTAG Identification
Programming through the JTAG interface, including reading and identifying the JTAG ID, is described in
detail in the MSP430 Programming Via the JTAG Interface User's Guide (SLAU320).
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7 Applications, Implementation, and Layout
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI's customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their implementation to confirm system functionality.
7.1
Device Connection and Layout Fundamentals
This section discusses the recommended guidelines when designing with the MSP430. These guidelines
are to make sure that the device has proper connections for powering, programming, debugging, and
optimum analog performance.
7.1.1
Power Supply Decoupling and Bulk Capacitors
TI recommends connecting a combination of a 10-µF plus a 100-nF low-ESR ceramic decoupling
capacitor to the DVCC pin. Higher-value capacitors may be used but can impact supply rail ramp-up time.
Decoupling capacitors must be placed as close as possible to the pins that they decouple (within a few
millimeters).
PRODUCT PREVIEW
DVCC
Digital
Power Supply
Decoupling
+
10 µF
100 nF
DVSS
Figure 7-1. Power Supply Decoupling
7.1.2
External Oscillator
Depending on the device variant (see Table 3-1), the device can support a low-frequency crystal (32 kHz)
on the LFXT pins, a high-frequency crystal on the HFXT pins, or both. External bypass capacitors for the
crystal oscillator pins are required.
It is also possible to apply digital clock signals to the LFXIN and HFXIN input pins that meet the
specifications of the respective oscillator if the appropriate LFXTBYPASS or HFXTBYPASS mode is
selected. In this case, the associated LFXOUT and HFXOUT pins can be used for other purposes. If they
are left unused, they must be terminated according to Section 4.6.
Figure 7-2 shows a typical connection diagram.
LFXIN
or
HFXIN
CL1
LFXOUT
or
HFXOUT
CL2
Figure 7-2. Typical Crystal Connection
68
Applications, Implementation, and Layout
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See MSP430 32-kHz Crystal Oscillators (SLAA322) for more information on selecting, testing, and
designing a crystal oscillator with the MSP430 devices.
7.1.3
JTAG
With the proper connections, the debugger and a hardware JTAG interface (such as the MSP-FET or
MSP-FET430UIF) can be used to program and debug code on the target board. In addition, the
connections also support the MSP-GANG production programmers, thus providing an easy way to
program prototype boards, if desired. Figure 7-3 shows the connections between the 14-pin JTAG
connector and the target device required to support in-system programming and debugging for 4-wire
JTAG communication. Figure 7-4 shows the connections for 2-wire JTAG mode (Spy-Bi-Wire).
For additional design information regarding the JTAG interface, see the MSP430 Hardware Tools User’s
Guide (SLAU278).
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kW
JTAG
VCC TOOL
VCC TARGET
TEST
2
RST/NMI/SBWTDIO
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
TDO/TDI
TDI
TDI
TMS
TCK
TMS
TCK
GND
RST
TEST/SBWTCK
C1
1 nF
(see Note B)
A.
B.
DVSS
If a local target power supply is used, make connection J1. If power from the debug or programming adapter is used,
make connection J2.
The upper limit for C1 is 1.1 nF when using TI tools.
Figure 7-3. Signal Connections for 4-Wire JTAG Communication
Applications, Implementation, and Layout
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PRODUCT PREVIEW
The connections for the MSP-FET and MSP-FET430UIF interface modules and the MSP-GANG are
identical. Both can supply VCC to the target board (through pin 2). In addition, the MSP-FET and MSPFET430UIF interface modules and MSP-GANG have a VCC sense feature that, if used, requires an
alternate connection (pin 4 instead of pin 2). The VCC-sense feature detects the local VCC present on the
target board (that is, a battery or other local power supply) and adjusts the output signals accordingly.
Figure 7-3 and Figure 7-4 show a jumper block that supports both scenarios of supplying VCC to the target
board. If this flexibility is not required, the desired VCC connections may be hard-wired to eliminate the
jumper block. Pins 2 and 4 must not be connected at the same time.
MSP430FR2311, MSP430FR2310
SLASE58 – FEBRUARY 2016
www.ti.com
VCC
Important to connect
MSP430FRxxx
J1 (see Note A)
DVCC
J2 (see Note A)
R1
47 kΩ
(see Note B)
JTAG
VCC TOOL
VCC TARGET
2
1
4
3
6
5
8
7
10
9
12
11
14
13
TDO/TDI
RST/NMI/SBWTDIO
TCK
GND
PRODUCT PREVIEW
TEST/SBWTCK
C1
1 nF
(see Note B)
A.
B.
DVSS
Make connection J1 if a local target power supply is used, or make connection J2 if the target is powered from the
debug or programming adapter.
The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 1.1 nF when using current TI tools.
Figure 7-4. Signal Connections for 2-Wire JTAG Communication (Spy-Bi-Wire)
7.1.4
Reset
The reset pin can be configured as a reset function (default) or as an NMI function in the Special Function
Register (SFR), SFRRPCR.
In reset mode, the RST/NMI pin is active low, and a pulse applied to this pin that meets the reset timing
specifications generates a BOR-type device reset.
Setting SYSNMI causes the RST/NMI pin to be configured as an external NMI source. The external NMI is
edge sensitive, and its edge is selectable by SYSNMIIES. Setting the NMIIE enables the interrupt of the
external NMI. When an external NMI event occurs, the NMIIFG is set.
The RST/NMI pin can have either a pullup or pulldown that is enabled or not. SYSRSTUP selects either
pullup or pulldown, and SYSRSTRE causes the pullup (default) or pulldown to be enabled (default) or not.
If the RST/NMI pin is unused, it is required either to select and enable the internal pullup or to connect an
external 47-kΩ pullup resistor to the RST/NMI pin with a 2.2-nF pulldown capacitor. The pulldown
capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or
in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
See the device family user’s guide (SLAU445) for more information on the referenced control registers
and bits.
7.1.5
Unused Pins
For details on the connection of unused pins, see Section 4.6.
70
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7.1.6
SLASE58 – FEBRUARY 2016
General Layout Recommendations
•
•
•
•
•
7.1.7
Proper grounding and short traces for external crystal to reduce parasitic capacitance. See MSP430
32-kHz Crystal Oscillators (SLAA322) for recommended layout guidelines.
Proper bypass capacitors on DVCC, AVCC, and reference pins if used.
Avoid routing any high-frequency signal close to an analog signal line. For example, keep digital
switching signals such as PWM or JTAG signals away from the oscillator circuit and ADC signals.
See Circuit Board Layout Techniques (SLOA089) for a detailed discussion of PCB layout
considerations. This document is written primarily about op amps, but the guidelines are generally
applicable for all mixed-signal applications.
Proper ESD level protection should be considered to protect the device from unintended high-voltage
electrostatic discharge. See MSP430 System-Level ESD Considerations (SLAA530) for guidelines.
Do's and Don'ts
During power up, power down, and device operation, the voltage difference between AVCC and DVCC
must not exceed the limits specified in the Absolute Maximum Ratings section. Exceeding the specified
limits may cause malfunction of the device including erroneous writes to RAM and FRAM.
Peripheral- and Interface-Specific Design Information
7.2.1
PRODUCT PREVIEW
7.2
ADC Peripheral
7.2.1.1
Partial Schematic
DVSS
Using an
External
Positive
Reference
Using an
External
Negative
Reference
VREF+/VEREF+
+
10 µF
100 nF
VEREF+
10 µF
100 nF
Figure 7-5. ADC Grounding and Noise Considerations
7.2.1.2
Design Requirements
As with any high-resolution ADC, appropriate printed-circuit-board layout and grounding techniques should
be followed to eliminate ground loops, unwanted parasitic effects, and noise.
Ground loops are formed when return current from the ADC flows through paths that are common with
other analog or digital circuitry. If care is not taken, this current can generate small unwanted offset
voltages that can add to or subtract from the reference or input voltages of the ADC. The general
guidelines in Section 7.1.1 combined with the connections shown in Figure 7-5 prevent this.
In addition to grounding, ripple and noise spikes on the power-supply lines that are caused by digital
switching or switching power supplies can corrupt the conversion result. TI recommends a noise-free
design using separate analog and digital ground planes with a single-point connection to achieve high
accuracy.
Figure 7-5 shows the recommended decoupling circuit when an external voltage reference is used. The
internal reference module has a maximum drive current as described in the sections ADC Pin Enable and
1.2-V Reference Settings of the MSP430FR4xx and MSP430FR2xx Family User's Guide (SLAU445).
Applications, Implementation, and Layout
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The reference voltage must be a stable voltage for accurate measurements. The capacitor values that are
selected in the general guidelines filter out the high- and low-frequency ripple before the reference voltage
enters the device. In this case, the 10-µF capacitor buffers the reference pin and filters any low-frequency
ripple. A bypass capacitor of 100 nF filters out any high-frequency noise.
7.2.1.3
Layout Guidelines
Components that are shown in the partial schematic (see Figure 7-5) should be placed as close as
possible to the respective device pins to avoid long traces, because they add additional parasitic
capacitance, inductance, and resistance on the signal.
Avoid routing analog input signals close to a high-frequency pin (for example, a high-frequency PWM),
because the high-frequency switching can be coupled into the analog signal.
7.3
Typical Applications
Table 7-1 lists several TI Designs that reflect the use of the MSP430FR231x family of devices in different
real-world application scenarios. Consult these designs for additional guidance regarding schematic,
layout, and software implementation.
Table 7-1. TI Designs
PRODUCT PREVIEW
DESIGN NAME
LINK
TIDM-FRAM-SMOKEDETECTOR
TBD
MSP430FR2311 LaunchPad Development Kit
TBD
72
Applications, Implementation, and Layout
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SLASE58 – FEBRUARY 2016
8 Device and Documentation Support
8.1
Device Support
8.1.1
Development Support
8.1.1.1
Getting Started and Next Steps
For more information on the MSP430™ family of devices and the tools and libraries that are available to
help with your development, visit the Getting Started page.
8.1.1.2
Development Tools Support
8.1.1.2.1 Hardware Features
MSP430
ARCHITECTURE
4-WIRE
JTAG
2-WIRE
JTAG
BREAKPOINTS
(N)
RANGE
BREAKPOINTS
CLOCK
CONTROL
STATE
SEQUENCER
TRACE
BUFFER
LPMx.5
DEBUGGING
SUPPORT
MSP430Xv2
Yes
Yes
8
Yes
Yes
Yes
Yes
No
8.1.1.2.2 Recommended Hardware Options
All MSP microcontrollers are supported by a wide variety of software and hardware development tools.
Tools are available from TI and various third parties. See them all at MSP Tools.
8.1.1.2.2.1 Target Socket Boards
The target socket boards allow easy programming and debugging of the device using JTAG. They also
feature header pin outs for prototyping. Target socket boards are orderable individually or as a kit with the
JTAG programmer and debugger included. The following table lists the compatible target boards and the
supported packages.
PACKAGE
TARGET BOARD AND PROGRAMMER BUNDLE
TARGET BOARD ONLY
20-pin TSSOP (PW)
MSP-FET430U20
MSP-TS430PW20
8.1.1.2.2.2 Experimenter Boards
Experimenter Boards and Evaluation kits are available for some MSP devices. These kits feature
additional hardware components and connectivity for full system evaluation and prototyping. See MSP
Tools for details.
8.1.1.2.2.3 Debugging and Programming Tools
Hardware programming and debugging tools are available from TI and from its third-party suppliers. See
the full list of available tools at MSP Tools.
8.1.1.2.2.4 Production Programmers
The production programmers expedite loading firmware to devices by programming several devices
simultaneously.
PART NUMBER
MSP-GANG
PC PORT
Serial and USB
FEATURES
Programs up to eight devices at a time.
Works with a PC or as a stand-alone programmer.
PROVIDER
Texas Instruments
Device and Documentation Support
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PRODUCT PREVIEW
See the Code Composer Studio for MSP430 User's Guide (SLAU157) for details on the available features.
MSP430FR2311, MSP430FR2310
SLASE58 – FEBRUARY 2016
www.ti.com
8.1.1.2.3 Recommended Software Options
8.1.1.2.3.1 Integrated Development Environments
Software development tools are available from TI or from third parties. Open source solutions are also
available.
This device is supported by Code Composer Studio™ IDE (CCS).
8.1.1.2.3.2 MSPWare
MSPWare is a collection of code examples, data sheets, and other design resources for all MSP430
devices delivered in a convenient package. In addition to providing a complete collection of existing
MSP430 design resources, MSPWare also includes a high-level API called MSP Driver Library. This
library makes it easy to program MSP hardware. MSPWare is available as a component of CCS or as a
stand-alone package.
8.1.1.2.3.3 Command-Line Programmer
MSP Flasher is an open-source shell-based interface for programming MSP microcontrollers through a
FET programmer or eZ430 using JTAG or Spy-Bi-Wire (SBW) communication. MSP Flasher can be used
to download binary files (.txt or .hex) files directly to the MSP microcontroller without the need for an IDE.
PRODUCT PREVIEW
8.1.2
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430FR2311). Texas Instruments recommends two
of three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent
evolutionary stages of product development from engineering prototypes (with XMS for devices and MSPX
for tools) through fully qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS devices and MSPX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PM) and temperature range (for example, T). Figure 8-1 provides a legend for
reading the complete device name for any family member.
74
Device and Documentation Support
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SLASE58 – FEBRUARY 2016
MSP 430 FR 2 311 I PW T
Processor Family
Platform
Series
Feature Set
Optional: Tape and Reel
Packaging
Optional: Temperature Range
Processor Family
MSP = Mixed-Signal Processor
XMS = Experimental Silicon
Platform
430 = MSP430 16-Bit Low-Power Microcontroller
Device Type
Memory Type
FR = FRAM
Series
4 = FRAM 4 Series, Up to 16 MHz With LCD
2 = FRAM 2 Series, Up to 16 MHz Without LCD
Feature Set
First and Second Digits –
SAC Level / ADC Channels / COMP / 16-bit Timers / I/O
31 = SAC-L1 / Up to 8 / 1 / 2 / Up to 16
Optional: Temperature Range
S = 0°C to 50°C
I = –40°C to 85°C
T = –40°C to 105°C
Packaging
http://www.ti.com/packaging
Optional: Distribution Format
T = Small Reel
R = Large Reel
No Marking = Tube or Tray
Third Digit –
FRAM (KB) / SRAM (KB)
1=4/1
0=2/1
Figure 8-1. Device Nomenclature
8.2
Documentation Support
The following documents describe the MSP430FR231x microcontrollers. Copies of these documents are
available on the Internet at www.ti.com.
SLAU445
MSP430FR4xx and MSP430FR2xx Family User's Guide. Detailed description of all
modules and peripherals available in this device family.
SLAZ679
MSP430FR2311 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this device.
SLAZ678
MSP430FR2310 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this device.
SLAU157
Code Composer Studio v6.1 for MSP430 User's Guide. This manual describes the use of
TI Code Composer Studio IDE v6.1 (CCS v6.1) with the MSP430 ultra-low-power
microcontrollers. This document applies only for the Windows version of the Code Composer
Studio IDE. The Linux version is similar and, therefore, is not described separately.
SLAU138
IAR Embedded Workbench Version 3+ for MSP430 User's Guide. This manual describes
the use of IAR Embedded Workbench (EW430) with the MSP430 ultra-low-power
microcontrollers.
Device and Documentation Support
Submit Documentation Feedback
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PRODUCT PREVIEW
Device Type
MSP430FR2311, MSP430FR2310
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PRODUCT PREVIEW
76
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SLAU319
MSP430 Programming With the Bootloader (BSL). The MSP430 bootloader (BSL,
formerly known as the bootstrap loader) allows users to communicate with embedded
memory in the MSP430 microcontroller during the prototyping phase, final production, and in
service. Both the programmable memory (flash memory) and the data memory (RAM) can
be modified as required. Do not confuse the bootloader with the bootstrap loader programs
found in some digital signal processors (DSPs) that automatically load program code (and
data) from external memory to the internal memory of the DSP.
SLAU557
MSP430 I2C Bootloader (BSL) User's Guide. Available Soon
SLAU320
MSP430 Programming Via the JTAG Interface. This document describes the functions that
are required to erase, program, and verify the memory module of the MSP430 flash-based
and FRAM-based microcontroller families using the JTAG communication port. In addition, it
describes how to program the JTAG access security fuse that is available on all MSP430
devices. This document describes device access using both the standard 4-wire JTAG
interface and the 2-wire JTAG interface, which is also referred to as Spy-Bi-Wire (SBW).
SLAU278
MSP430 Hardware Tools User's Guide. This manual describes the hardware of the TI
MSP-FET430 Flash Emulation Tool (FET). The FET is the program development tool for the
MSP430 ultra-low-power microcontroller. Both available interface types, the parallel port
interface and the USB interface, are described.
SLAA322
MSP430 32-kHz Crystal Oscillators. Selection of the right crystal, correct load circuit, and
proper board layout are important for a stable crystal oscillator. This application report
summarizes crystal oscillator function and explains the parameters to select the correct
crystal for MSP430 ultra-low-power operation. In addition, hints and examples for correct
board layout are given. The document also contains detailed information on the possible
oscillator tests to ensure stable oscillator operation in mass production.
SLAA530
MSP430 System-Level ESD Considerations. System-Level ESD has become increasingly
demanding with silicon technology scaling towards lower voltages and the need for designing
cost-effective and ultra-low-power components. This application report addresses three
different ESD topics to help board designers and OEMs understand and design robust
system-level designs: (1) Component-level ESD testing and system-level ESD testing, their
differences and why component-level ESD rating does not ensure system-level robustness.
(2) General design guidelines for system-level ESD protection at different levels including
enclosures, cables, PCB layout, and on-board ESD protection devices. (3) Introduction to
System Efficient ESD Design (SEED), a co-design methodology of on-board and on-chip
ESD protection to achieve system-level ESD robustness, with example simulations and test
results. A few real-world system-level ESD protection design examples and their results are
also discussed.
Device and Documentation Support
Copyright © 2016, Texas Instruments Incorporated
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8.2.1
SLASE58 – FEBRUARY 2016
Related Links
Table 8-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 8-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FR2311
Click here
Click here
Click here
Click here
Click here
MSP430FR2310
Click here
Click here
Click here
Click here
Click here
8.2.2
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
8.3
Trademarks
MSP430, Code Composer Studio, E2E are trademarks of Texas Instruments.
8.4
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.5
Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
Device and Documentation Support
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PRODUCT PREVIEW
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
MSP430FR2311, MSP430FR2310
SLASE58 – FEBRUARY 2016
www.ti.com
9 Mechanical, Packaging, and Orderable Information
9.1
Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the
most current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, see the left-hand navigation.
PRODUCT PREVIEW
78
Mechanical, Packaging, and Orderable Information
Copyright © 2016, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430FR2310IPW16
PREVIEW
TSSOP
PW
16
90
TBD
Call TI
Call TI
-40 to 85
MSP430FR2310IPW16R
PREVIEW
TSSOP
PW
16
2000
TBD
Call TI
Call TI
-40 to 85
MSP430FR2310IPW20
PREVIEW
TSSOP
PW
20
70
TBD
Call TI
Call TI
-40 to 85
MSP430FR2310IPW20R
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
MSP430FR2310IRGYR
PREVIEW
VQFN
RGY
16
3000
TBD
Call TI
Call TI
-40 to 85
MSP430FR2310IRGYT
PREVIEW
VQFN
RGY
16
250
TBD
Call TI
Call TI
-40 to 85
MSP430FR2311IPW16
PREVIEW
TSSOP
PW
16
90
TBD
Call TI
Call TI
-40 to 85
MSP430FR2311IPW16R
PREVIEW
TSSOP
PW
16
2000
TBD
Call TI
Call TI
-40 to 85
MSP430FR2311IPW20
PREVIEW
TSSOP
PW
20
70
TBD
Call TI
Call TI
-40 to 85
MSP430FR2311IPW20R
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
MSP430FR2311IRGYR
PREVIEW
VQFN
RGY
16
3000
TBD
Call TI
Call TI
-40 to 85
MSP430FR2311IRGYT
PREVIEW
VQFN
RGY
16
250
TBD
Call TI
Call TI
-40 to 85
XMS430FR2311IPW16R
PREVIEW
TSSOP
PW
16
2000
TBD
Call TI
Call TI
-40 to 85
XMS430FR2311IPW20R
PREVIEW
TSSOP
PW
20
2000
TBD
Call TI
Call TI
-40 to 85
XMS430FR2311IRGYR
PREVIEW
VQFN
RGY
16
3000
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
25-Feb-2016
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
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