AD ADV7120KP80 Cmos 80 mhz, triple 8-bit video dac Datasheet

a
FEATURES
80 MHz Pipelined Operation
Triple 8-Bit D/A Converters
RS-343A/RS-170 Compatible Outputs
TTL Compatible Inputs
+5 V CMOS Monolithic Construction
40-Pin DIP or 44-Pin PLCC and 48-Lead TQFP
APPLICATIONS
High Resolution Color Graphics
CAE/CAD/CAM Applications
Image Processing
Instrumentation
Video Signal Reconstruction
Desktop Publishing
Direct Digital Synthesis (DDS) and I/Q Modulation
SPEED GRADES*
80 MHz
50 MHz
30 MHz
CMOS
80 MHz, Triple 8-Bit Video DAC
ADV7120
FUNCTIONAL BLOCK DIAGRAM
FS
ADJUST
VAA
VREF
REFERENCE
AMPLIFIER
ADV7120
COMP
CLOCK
R0
R7
PIXEL
INPUT
PORT
G0
G7
B0
B7
8
RED
8
REGISTER
8
GREEN
REGISTER
8
8
BLUE
REGISTER
8
REF WHITE
CONTROL
REGISTER
BLANK
SYNC
DAC
IOR
DAC
IOG
DAC
IOB
SYNC
CONTROL
ISYNC
GND
GENERAL DESCRIPTION
The ADV7120 (ADV) is a digital to analog video converter on
a single monolithic chip. The part is specifically designed for
high resolution color graphics and video systems. It is also ideal
for any high speed communications type applications requiring
low cost, high speed DACs. It consists of three, high speed,
8-bit, video D/A converters (RGB); a standard TTL input interface and high impedance, analog output, current sources.
PRODUCT HIGHLIGHTS
1. Fast video refresh rate, 80 MHz.
2. Compatible with a wide variety of high resolution color
graphics video systems.
3. Guaranteed monotonic with a maximum differential nonlinearity of ± 0.5 LSB. Integral nonlinearity is guaranteed to
be a maximum of ± 1 LSB.
The ADV7120 has three separate, 8-bit, pixel input ports, one
each for red, green and blue video data. Additional video input
controls on the part include composite sync, blank and reference white. A single +5 V supply, an external 1.23 V reference
and pixel clock input are all that are required to make the part
operational.
The ADV7120 is capable of generating RGB video output signals, which are compatible with RS-343A and RS-170 video
standards, without requiring external buffering.
The ADV7120 is fabricated in a +5 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with low power dissipation. The part is packaged in both a 0.6",
40-pin plastic DIP and a 44-pin plastic leaded (J-lead) chip carrier, PLCC. The ADV7120 is also available in a very small 48lead Thin Quad Flatpack (TQFP).
ADV is a registered trademark of Analog Devices, Inc.
*Speed grades up to 140 MHz are also available upon special request.
Please contact Analog Devices or its representatives for further details.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
(VAA = +5 V 6 5%; VREF = +1.235 V; RL = 37.5 V, CL = 10 pF; RSET = 560 V.
1
SYNC connected to I0G. All Specifications TMIN to TMAX unless otherwise noted.)
ADV7120–SPECIFICATIONS I
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity, INL
Differential Nonlinearity, DNL
Gray Scale Error
Coding
DIGITAL INPUTS
Input High Voltage, V INH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN2
ANALOG OUTPUTS
Gray Scale Current Range
Output Current
White Level Relative to Blank
White Level Relative to Black
Black Level Relative to Blank
Blank Level on IOR, IOB
Blank Level on IOG
Sync Level on IOG
LSB Size
DAC to DAC Matching
Output Compliance, VOC
Output Impedance, ROUT2
Output Capacitance, COUT2
VOLTAGE REFERENCE
Voltage Reference Range, V REF
Input Current, IVREF
POWER REQUIREMENTS
VAA
IAA
Power Supply Rejection Ratio
Power Dissipation
DYNAMIC PERFORMANCE
Glitch Impulse2, 3
DAC Noise2, 3, 4
Analog Output Skew
All Versions
Units
Test Conditions/Comments
8
Bits
±1
± 0.5
±5
LSB max
LSB max
% Gray Scale max
Guaranteed Monotonic
Max Gray Scale Current: IOG = (VREF* 12,082/RSET) mA
IOR, IOB = (VREF* 8,627/RSET) mA
Binary
2
0.8
±1
10
V min
V max
µA max
pF max
15
22
mA min
mA max
17.69
20.40
16.74
18.50
0.95
1.90
0
50
6.29
9.5
0
50
69.1
5
–1
+1.4
100
30
mA min
mA max
mA min
mA max
mA min
mA max
µA min
µA max
mA min
mA max
µA min
µA max
µA typ
% max
V min
V max
kΩ typ
pF max
1.14/1.26
–5
V min/V max
mA typ
5
125
100
0.5
625
500
V nom
mA max
mA max
%/% max
mW max
mW max
Typically 80 mA: 80 MHz Parts
Typically 70 mA: 50 MHz & 35 MHz Parts
Typically 0.12%/%: f = 1 kHz, COMP = 0.1 µF
Typically 400 mW: 80 MHz Parts
Typically 350 mW: 50 MHz & 30 MHz Parts
50
200
2
pV secs typ
pV secs typ
ns max
Typically 1 ns
VIN = 0.4 V or 2.4 V
Typically 19.05 mA
Typically 17.62 mA
Typically 1.44 mA
Typically 5 µA
Typically 7.62 mA
Typically 5 µA
Typically 2%
IOUT = 0 mA
VREF = 1.235 V for Specified Performance
NOTES
1
Temperature range (T MIN to TMIN); 0°C to +70°C.
2
Sample tested at +25°C to ensure compliance.
3
TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and
outputs. See timing notes in Figure 1.
4
This includes effects due to clock and data feedthrough as well as RGB analog crosstalk.
Specifications subject to change without notice.
–2–
REV. B
ADV7120
TIMING CHARACTERISTICS1
(VAA = +5 V 6 5%; VREF = +1.235 V; RL = 37.5 V, CL = 10 pF; RSET = 560 V.
ISYNC connected to IOG. All Specifications TMIN to TMAX2 unless otherwise noted.)
Parameter
80 MHz Version
50 MHz Version
30 MHz Version
Units
Conditions/Comments
fMAX
tl
t2
t3
t4
t5
t6
80
3
2
12.5
4
4
30
20
3
12
50
6
2
20
7
7
30
20
3
15
30
8
2
33.3
9
9
30
20
3
15
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns typ
ns max
ns typ
Clock Rate
Data & Control Setup Time
Data & Control Hold Time
Clock Cycle Time
Clock Pulse Width High Time
Clock Pulse Width Low Time
Analog Output Delay
t7
t 83
Analog Output Rise/Fall Time
Analog Output Transition Time
NOTES
1
TTL input values are 0 to 3 volts, with input rise/fall times ≤3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs
and outputs. See timing notes in Figure 1.
2
Temperature range (T MIN to TMAX): 0°C to +70°C
3
Sample tested at +25°C to ensure compliance.
Specifications subject to change without notice.
t4
t5
CLOCK
t3
t1
DIGITAL INPUTS
(R0-R7, G0-G7, B0-B7;
SYNC, BLANK,
REF WHITE)
t2
DATA
t6
t8
ANALOG OUTPUTS
(IOR, IOG, IOB, I SYNC )
t7
NOTES
1. OUTPUT DELAY ( t ) MEASURED FROM THE 50% POINT OF THE RISING EDGE OF
6
CLOCK TO THE 50% POINT OF FULL-SCALE TRANSITION.
2. TRANSITION TIME ( t ) MEASURED FROM THE 50% POINT OF FULL-SCALE
8
TRANSITION TO WITHIN 2% OF THE FINAL OUTPUT VALUE.
3. OUTPUT RISE/FALL TIME (t ) MEASURED BETWEEN THE 10% AND 90% POINTS
7
OF FULL TRANSITION.
Figure 1. Video Input/Output Timing
REV. B
–3–
ADV7120
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Power Supply
Ambient Operating
Temperature
Output Load
Reference Voltage
Min
VAA
4.75
TA
RL
VREF
0
1.14
Typ
Max
5.00
37.5
1.235
ORDERING GUIDE
Model
Speed
Temperature
Range1
Package
Option2
ADV7120KN80
ADV7120KN50
ADV7120KN30
ADV7120KP80
ADV7120KP50
ADV7120KP30
ADV7120KST50
ADV7120KST30
80 MHz
50 MHz
30 MHz
80 MHz
50 MHz
30 MHz
50 MHz
30 MHz
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
N-40A
N-40A
N-40A
P-44A
P-44A
P-44A
ST-48
ST-48
Units
5.25
Volts
+70
°C
Ω
Volts
1.26
ABSOLUTE MAXIMUM RATINGS 1
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Voltage on Any Digital Pin . . . . . GND –0.5 V to VAA +0.5 V
Ambient Operating Temperature (TA) . . . . . . . . 0°C to +70°C
Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Soldering Temperature (10 secs) . . . . . . . . . . . . . . . . . . 300°C
Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . . . 220°C
IOR, IOB, IOG, ISYNC to GND2 . . . . . . . . . . . . . . 0 V to VAA
NOTES
1
Industrial temperature range (–40°C to +85°C) version available to special
request. Please consult your local Analog Device representative.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier.
NOTES
1
Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2
Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7120 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
TQFP
FS ADJUST
PLCC
DIP
35 VREF
G1
6
35 VREF
G1
8
38
G1 3
34 COMP
G2
7
34 COMP
G2
9
37 ISYNC
G2 4
33 IOR
G3
8
33 IOR
G3 5
G4
9
36 VAA
VREF
COMP
R2
R1
R0
R4
G4 6
G5 12
TOP VIEW
(Not to Scale)
34 VAA
G5 7
G6 13
33 IOB
G6 8
29 IOB
G7 14
32 GND
G7 9
28 GND
31 GND
BLANK 10
27 GND
SYNC 11
VAA 17
29 GND
VAA 12
GND
CLOCK
B6
21 B5
B7
22
REF WHITE
B3 19
B4 20
18 19 20 21 22 23 24 25 26 27 28
B5
B7
B6
REF WHITE
23
B4
24
B2 18
B3
B1 17
B2
CLOCK
B1
25
B0
B0 16
26 CLOCK
25 NC
13 14 15 16 17 18 19 20 21 22 23 24
NC
30 GND
B7
SYNC 16
B6
26 GND
30 VAA
B5
27 GND
15
B4
14
VAA
B3
SYNC
BLANK 15
31 VAA
TOP VIEW
(Not to Scale)
B2
28 GND
35 VAA
B1
13
IOB
ADV7120
B0
BLANK
29
32 IOG
ADV7120
G4 11
GND
32 IOG
ADV7120
NC
G7 12
R3
G3 10
IOG
36 FS ADJUST
GND
10
48 47 46 45 44 43 42 41 40 39 38 37
GND 1
31 ISYNC
TOP VIEW
G6 11 (Not to Scale) 30 VAA
G5
NC
G0 2
44 43 42 41 40
GND
39 IOR
1
GND
7
2
R0
G0
3
R1
36 FS ADJUST
4
R3
5
5
R2
G0
6
R5
37 R0
R4
4
R6
38 R1
R7
GND
3
R7
39 R2
R6
R5
40 R3
2
R6
1
R5
R7
R4
NC = NO CONNECT
NOTE
For the ADV7120 in TQFP package: The REF WHITE pin is not available.
The ISYNC pin is not available and is internally connected to the IOG pin.
–4–
REV. B
ADV7120
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
BLANK
Composite blank control input (TTL compatible). A logic zero on this control input drives the analog outputs, IOR, IOB and IOG, to the blanking level. The BLANK signal is latched on the rising edge of CLOCK.
While BLANK is a logical zero, the R0–R7, G0–G7, R0–R7 and REF WHITE pixel and control inputs are
ignored.
SYNC
Composite sync control input (TTL compatible). A logical zero on the SYNC input switches off a 40 IRE
current source on the ISYNC output. SYNC does not override any other control or data input; therefore, it
should only be asserted during the blanking interval. SYNC is latched on the rising edge of CLOCK.
CLOCK
Clock input (TTL compatible). The rising edge of CLOCK latches the R0–R7, G0–G7, B0–B7, SYNC,
BLANK and REF WHITE pixel and control inputs. It is typically the pixel clock rate of the video system.
CLOCK should be driven by a dedicated TTL buffer.
REF WHITE
Reference white control input (TTL compatible). A logical one on this input forces the IOR, IOG and IOB
outputs to the white level, regardless of the pixel input data (R0–R7, G0–G7 and B0–B7). REF WHITE is
latched on the rising edge of clock.
R0–R7,
G0–G7,
B0–B7
Red, green and blue pixel data inputs (TTL compatible). Pixel data is latched on the rising edge of CLOCK.
R0, G0 and B0 are the least significant data bits. Unused pixel data inputs should be connected to either the
regular PCB power or ground plane.
IOR, IOG, IOB
Red, green, and blue current outputs. These high impedance current sources are capable of directly driving
a doubly terminated 75 Ω coaxial cable. All three current outputs should have similar output loads whether
or not they are all being used.
ISYNC
Sync current output. This high impedance current source can be directly connected to the IOG output. This
allows sync information to be encoded onto the green channel. ISYNC does not output any current while
SYNC is at logical zero. The amount of current output at ISYNC while SYNC is at logical one is given by:
ISYNC (mA) = 3,455 × VREF (V)/ RSET (Ω)
If sync information is not required on the green channel, ISYNC should be connected to AGND.
FS ADJUST
Full-scale adjust control. A resistor (RSET) connected between this pin and GND, controls the magnitude of
the full-scale video signal. Note that the IRE relationships are maintained, regardless of the full-scale output
current.
The relationship between RSET and the full-scale output current on IOG (assuming ISYNC is connected to
IOG) is given by:
RSET (Ω) = 12,082 × VREF (V)/IOG (mA)
The relationship between RSET and the full-scale output current on IOR and IOB is given by:
IOR, IOB (mA) = 8,628 × VREF (V)/ RSET (Ω)
COMP
Compensation pin. This is a compensation pin for the internal reference amplifier. A 0.1 µF ceramic capacitor must be connected between COMP and VAA.
VREF
Voltage reference input. An external 1.2 V voltage reference must be connected to this pin. The use of an external resistor divider network is not recommended. A 0.1 µF decoupling ceramic capacitor should be connected between VREF and VAA.
VAA
Analog power supply (5 V ± 5%). All VAA pins on the ADV7120 must be connected.
GND
Ground. All GND pins must be connected.
REV. B
–5–
ADV7120
TERMINOLOGY
Blanking Level
Raster Scan
The most basic method of sweeping a CRT one line at a time to
generate and display images.
The level separating the SYNC portion from the video portion
of the waveform. Usually referred to as the front porch or back
porch. At 0 IRE units, it is the level which will shut off the picture tube, resulting in the blackest possible picture.
Reference Black Level
The maximum negative polarity amplitude of the video signal.
Reference White Level
Color Video (RGB)
The maximum positive polarity amplitude of the video signal.
This usually refers to the technique of combining the three primary colors of red, green and blue to produce color pictures
within the usual spectrum. In RGB monitors, three DACs are
required, one for each color.
Sync Level
The peak level of the SYNC signal.
Video Signal
That portion of the composite video signal which varies in gray
scale levels between reference white and reference black. Also
referred to as the picture signal, this is the portion which may be
visually observed.
Sync Signal (SYNC)
The position of the composite video signal which synchronizes
the scanning process.
Gray Scale
The discrete levels of video signal between reference black and
reference white levels. An 8-bit DAC contains 256 different levels while a 6-bit DAC contains 64.
The REF WHITE control input drives the RGB video outputs
to the white level. This function could be used to overlay a cursor or crosshair onto the RGB video output.
CIRCUIT DESCRIPTION AND OPERATION
The ADV7120 contains three 8-bit D/A converters, with three
input channels each containing an 8-bit register. Also integrated on board the part is a reference amplifier and CRT control functions BLANK, SYNC and REF WHITE.
Table I details the resultant effect on the analog outputs of
BLANK, SYNC and REF WHITE.
Digital Inputs
All these digital inputs are specified to accept TTL logic levels.
24-bits of pixel data (color information) R0–R7, G0–G7 and
B0–B7 are latched into the device on the rising edge of each
clock cycle. This data is presented to the three 8-bit DACs and
is then converted to three analog (RGB) output waveforms.
(See Figure 2.)
Clock Input
The CLOCK input of the ADV7120 is typically the pixel clock
rate of the system. It is also known as the dot rate. The dot rate,
and hence the required CLOCK frequency, will be determined
by the on-screen resolution, according to the following
equation:
Three other digital control signals are latched to the analog
video outputs in a similar fashion. BLANK, SYNC and REF
WHITE are each latched on the rising edge of CLOCK to
maintain synchronization with the pixel data stream.
Dot Rate = (Horiz: Res) × (Vert Res) × (Refresh Rate)/
(Retrace Factor)
The BLANK and SYNC functions allow for the encoding of
these video synchronization signals onto the RGB video output.
This is done by adding appropriately weighted current sources
to the analog outputs, as determined by the logic levels on the
BLANK and SYNC digital inputs. Figure 3 shows the analog
output, RGB video waveform of the ADV7120. The influence
of SYNC and BLANK on the analog video waveform is
illustrated.
Horiz Res
=
Number of pixels/line
Vert Res
=
Number of lines/frame
Refresh Rate
=
Horizontal scan rate. This is the rate at
which the screen must be refreshed, typically 60 Hz for a noninterlaced system or
30 Hz for an interlaced system.
Retrace Factor
=
Total blank time factor. This takes into account that the display is blanked for a certain fraction of the total duration of each
frame (e.g., 0.8).
CLOCK
DIGITAL INPUTS
(R0-R7, G0-G7, B0-B7;
SYNC, BLANK,
REF WHITE)
DATA
ANALOG OUTPUTS
(IOR, IOG, IOB, I SYNC )
Figure 2. Video Data Input/Output
–6–
REV. B
ADV7120
If we, therefore, have a graphics system with a 1024 × 1024
resolution, a noninterlaced 60 Hz refresh rate and a retrace factor of 0.8, then:
Dot Rate = 1024 × 1024 × 60/0.8
= 78.6 MHz
RED, BLUE
GREEN
mA
V
mA
V
19.05
0.714
26.67
1.000
The required CLOCK frequency is thus 78.6 MHz.
All video data and control inputs are latched into the ADV7120
on the rising edge of CLOCK, as previously described in the
“Digital Inputs” section. It is recommended that the CLOCK
input to the ADV7120 be driven by a TTL buffer (e.g.,
74F244).
WHITE LEVEL
92.5 IRE
1.44
0.054
9.05
BLACK LEVEL
0.340
7.5 IRE
0
0
7.62
0.286
BLANK LEVEL
40 IRE
0
0
SYNC LEVEL
NOTES
1. OUTPUTS CONNECTED TO A DOUBLY TERMINATED 75Ω LOAD.
2. V REF = 1.235V, RSET = 560Ω, I SYNC CONNECTED TO IOG.
3. RS-343A LEVELS AND TOLERANCES ASSUMED ON ALL LEVELS.
Figure 3. RGB Video Output Waveform
Table I. Video Output Truth Table
Description
IOG
(mA)l
IOR, IOB
(mA)
REF
WHITE
SYNC
BLANK
DAC
Input Data
WHITE LEVEL
WHITE LEVEL
VIDEO
VIDEO to BLANK
BLACK LEVEL
BLACK to BLANK
BLANK LEVEL
SYNC LEVEL
26.67
26.67
video + 9.05
video + 1.44
9.05
1.44
7.62
0
19.05
19.05
video + 1.44
video + 1.44
1.44
1.44
0
0
1
0
0
0
0
0
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
1
0
0
xxH
FFH
data
data
00H
00H
xxH
xxH
NOTE
Typical with full-scale IOG = 26.67 mA.
VREF = 1.235 V, RSET = 560 Ω, ISYNC connected to IOG.
Video Synchronization and Control
Reference Input
The ADV7120 has a single composite video sync (SYNC) input
control. Many graphics processors and CRT controllers have
the ability of generating horizontal sync (HSYNC), vertical sync
(VSYNC) and composite SYNC.
An external 1.23 V voltage reference is required to drive
the ADV7120. The AD589 from Analog Devices is an
ideal choice of reference. It is a two-terminal, low cost,
temperature compensated bandgap voltage reference which
provides a fixed 1.23 V output voltage for input currents
between 50 µA and 5 mA. Figure 4 shows a typical reference circuit connection diagram. The voltage reference gets
its current drive from the ADV7120’s VAA through an onboard 1 kΩ resistor to the VREF pin. A 0.1 µF ceramic capacitor is required between the COMP pin and VAA.
This is necessary so as to provide compensation for the
internal reference amplifier.
In a graphics system which does not automatically generate a
composite SYNC signal, the inclusion of some additional logic
circuitry will enable the generation of a composite SYNC signal.
The ISYNC current output is typically connected directly to the
IOG output, thus encoding video synchronization information
onto the green video channel. If it is not required to encode sync
information onto the ADV7120’s analog outputs, the SYNC input should be tied to logic low and the ISYNC should be connected to analog ground.
REV. B
–7–
ADV7120
as a doubly terminated 75 Ω coaxial cable. Figure 5a shows the
required configuration for each of the three RGB outputs connected into a doubly terminated 75 Ω load. This arrangement
will develop RS-343A video output voltage levels across a 75 Ω
monitor.
A resistance RSET connected between FS ADJUST and GND
determines the amplitude of the output video level according to
the following equations:
IOG (mA) = 12,082 × VREF (V)/RSET (Ω)
(1)
IOR, IOB (mA) = 8,628 × VREF (V)/RSET (Ω)
(2)
IOR, IOG, IOB
If SYNC is not being encoded onto the green channel, then
Equation 1 will be similar to Equation 2.
ZO = 75Ω
DACs
Using a variable value of RSET, as shown in Figure 4, allows for
accurate adjustment of the analog output video levels. Use of a
fixed 560 Ω RSET resistor yields the analog output levels as
quoted in the specification page. These values also correspond
to the RS-343A video waveform values as shown in Figure 3.
(CABLE)
ZS = 75Ω
(SOURCE
TERMINATION)
ZL = 75Ω
(MONITOR)
ANALOG POWER PLANE
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
+5V
0.1µF
COMP
Figure 5a. Analog Output Termination for RS-343A
VAA
One suggested method of driving RS-170 video levels into a 75 Ω
monitor is shown in Figure 5b. The output current levels of the
DACs remain unchanged but the source termination resistance,
ZS, on each of the three DACs is increased from 75 Ω to 150 Ω.
IREF ≈ 4mA
1kΩ
VREF
TO DACs
FS ADJUST
AD589
500Ω
RSET
560Ω
100Ω
IOR, IOG, IOB
(1.235V
VOLTAGE
REFERENCE)
ZO = 75Ω
DACs
(CABLE)
ADV7120*
GND
ZS = 150Ω
(SOURCE
TERMINATION)
*ADDITIONAL CIRCUITRY, INCLUDING
DECOUPLING COMPONENTS,
EXCLUDED FOR CLARITY
ZL = 75Ω
(MONITOR)
TERMINATION REPEATED THREE TIMES
FOR RED, GREEN AND BLUE DACs
Figure 4. Reference Circuit
Figure 5b. Analog Output Termination for RS-170
More detailed information regarding load terminations for various output configurations, including RS-343A and RS-170, is
available in an application note entitled “Video Formats & Required Load Terminations” available from Analog Devices,
publication number E1228-15-1/89.
D/A Converters
The ADV7120 contains three matched 8-bit D/A converters.
The DACs are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each
digital input are routed to either the analog output (bit = “1”)
or GND (bit = “0”) by a sophisticated decoding scheme. As all
this circuitry is on one monolithic device, matching between the
three DACs is optimized. As well as matching, the use of identical current sources in a monolithic design guarantees monotonicity and low glitch. The onboard operational amplifier
stabilizes the full-scale output current against temperature and
power supply variations.
Figure 3 shows the video waveforms associated with the three
RGB outputs driving the doubly terminated 75 Ω load of Figure
5a. As well as the gray scale levels, black level to white level, the
diagram also shows the contributions of SYNC and BLANK.
These control inputs add appropriately weighted currents to the
analog outputs, producing the specific output level requirements
for video applications. Table I details how the SYNC and
BLANK inputs modify the output levels.
Analog Outputs
The ADV7120 has three analog outputs, corresponding to the red,
green and blue video signals. A fourth analog output (ISYNC) can be
used if it is required to encode video synchronization information
onto the green signal. In this case, ISYNC is connected to IOG .
(See “Video Synchronization and Control” section.)
Gray Scale Operation
The ADV7120 can be used for stand-alone, gray scale (monochrome) or composite video applications (i.e., only one channel
used for video information). Any one of the three channels, red,
green or blue, can be used to input the digital video data. The
two unused video data channels should be tied to logical zero.
The red, green and blue analog outputs of the ADV7102 are
high impedance current sources. Each one of these three RGB
current outputs is capable of directly driving a 37.5 Ω load, such
–8–
REV. B
ADV7120
The unused analog outputs should be terminated with the same
load as that for the used channel. In other words, if the red
channel is used and IOR is terminated with a doubly terminated
75 Ω load (37.5 Ω), IOB and IOG should be terminated with
37.5 Ω resistors. (See Figure 6.)
VIDEO
INPUT
The ADV7120 is specified to drive transmission line loads,
which is what most monitors are rated as. The analog output
configurations to drive such loads are described in the Analog
Interface section and illustrated in Figure 5. However, in some
applications it may be required to drive long “transmission line”
cable lengths. Cable lengths greater than 10 meters can attenuate and distort high frequency analog output pulses. The inclusion of output buffers will compensate for some cable distortion.
Buffers with large full power bandwidths and gains between 2
and 4 will be required.
DOUBLY
TERMINATED
75Ω LOAD
IOR
R0
Video Output Buffers
R7
IOG
G0
These buffers will also need to be able to supply sufficient current over the complete output voltage swing. Analog Devices
produces a range of suitable op amps for such applications.
These include the AD84X series of monolithic op amps. In very
high frequency applications (80 MHz), the AD9617 is recommended. More information on line driver buffering circuits is
given in the relevant op amp data sheets.
37.5Ω
G7
B0
IOB
B7
37.5Ω
ADV7120
Use of buffer amplifiers also allows implementation of other
video standards besides RS-343A and RS-170. Altering the gain
components of the buffer circuit will result in any desired
video level.
GND
Figure 6. Input and Output Connections for Stand-Alone
Gray Scale or Composite Video
Z2
Z1
+VS
0.1µF
2
DACs
7
ZO = 75Ω
75Ω
IOR, IOG, IOB
AD848
3
4
6
(CABLE)
0.1µF
ZL = 75Ω
(MONITOR)
ZS = 75Ω
(SOURCE
TERMINATION)
–V S
GAIN (G) = 1 +
Z1
Z2
Figure 7. AD848 As an Output Buffer
REV. B
–9–
ADV7120
PC BOARD LAYOUT CONSIDERATIONS
Ground Planes
The ADV7120 is optimally designed for lowest noise performance, both radiated and conducted noise. To complement the
excellent noise performance of the ADV7120, it is imperative
that great care be given to the PC board layout. Figure 8 shows
a recommended connection diagram for the ADV7120.
The ADV7120 and associated analog circuitry, should have a
separate ground plane referred to as the analog ground plane.
This ground plane should connect to the regular PCB ground
plane at a single point through a ferrite bead, as illustrated in
Figure 8. This bead should be located as close as possible
(within 3 inches) to the ADV7120.
The layout should be optimized for lowest noise on the
ADV7120 power and ground lines. This can be achieved by
shielding the digital inputs and providing good decoupling. The
lead length between groups of VAA and GND pins should by
minimized so as to minimize inductive ringing.
The analog ground plane should encompass all ADV7120
ground pins, voltage reference circuitry, power supply bypass
circuitry, the analog output traces and any output amplifiers.
The regular PCB ground plane area should encompass all the
digital signal traces, excluding the ground pins, leading up to
the ADV7120.
COMP
C6
0.1µF
R0
R7
ANALOG POWER PLANE
VAA
VIDEO
DATA
INPUTS
G0
G7
L1 (FERRITE BEAD)
C3
0.1µF
C4
0.1µF
C5
0.1µF
+5V (VCC )
B0
B7
C2
10µF
VREF
C1
33µF
Z1 (AD589)
ADV7120
ANALOG GROUND PLANE
GROUND
GND
RSET
560Ω
R1
75Ω
R2
75Ω
R3
75Ω
L2 (FERRITE BEAD)
FS ADJUST
CLOCK
IOR
VIDEO
CONTROL
INPUTS
REF WHITE
RGB
VIDEO
OUTPUT
IOG
SYNC
ISYNC
IOB
BLANK
COMPONENT
C1
C2
C3, C4, C5, C6
L1, L2
R1, R2, R3
Rset
SET
Z1
DESCRIPTION
VENDOR PART NUMBER
33µF TANTALUM CAPACITOR
10µF TANTALUM CAPACITOR
0.1µF CERAMIC CAPACITOR
FERRITE BEAD
FAIR-RITE 274300111 OR MURATA BL01/02/03
75Ω 1% METAL FILM RESISTOR
560Ω 1% METAL FILM RESISTOR
DALE CMF-55C
DALE CMF-55C
1.235V VOLTAGE REFERENCE
ANALOG DEVICES AD589JH
Figure 8. ADV7120 Typical Connection Diagram and Component List
–10–
REV. B
ADV7120
Power Planes
The PC board layout should have two distinct power planes,
one for analog circuitry and one for digital circuitry. The analog
power plane should encompass the ADV7120 (VAA) and all associated analog circuitry. This power plane should be connected
to the regular PCB power plane (VCC) at a single point through
a ferrite bead, as illustrated in Figure 8. This bead should be located within three inches of the ADV7120.
The PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7120 power pins, voltage reference circuitry
and any output amplifiers.
The PCB power and ground planes should not overlay portions
of the analog power plane. Keeping the PCB power and ground
planes from overlaying the analog power plane will contribute to
a reduction in plane-to-plane noise coupling.
Supply Decoupling
Noise on the analog power plane can be further reduced by the
use of multiple decoupling capacitors. (See Figure 8.)
Optimum performance is achieved by the use of 0.1 µF ceramic
capacitors. Each of the two groups of VAA should be individually
decoupled to ground. This should be done by placing the capacitors as close as possible to the device with the capacitor
leads as short as possible, thus minimizing lead inductance.
It is important to note that while the ADV7120 contains circuitry to reject power supply noise, this rejection decreases with
frequency. If a high frequency switching power supply is used,
the designer should pay close attention to reducing power supply noise. A dc power supply filter (Murata BNX002) will provide EMI suppression between the switching power supply and
REV. B
the main PCB. Alternatively, consideration could be given to
using a three terminal voltage regulator.
Digital Signal Interconnect
The digital signal lines to the ADV7120 should be isolated as
much as possible from the analog outputs and other analog circuitry. Digital signal lines should not overlay the analog power
plane.
Due to the high clock rates used, long clock lines to the
ADV7120 should be avoided so as to minimize noise pickup.
Any active pull-up termination resistors for the digital inputs
should be connected to the regular PCB power plane (VCC), and
not the analog power plane.
Analog Signal Interconnect
The ADV7120 should be located as close as possible to the output connectors thus minimizing noise pickup and reflections
due to impedance mismatch.
The video output signals should overlay the ground plane, and
not the analog power plane, thereby maximizing the high frequency power supply rejection.
For optimum performance, the analog outputs should each have
a source termination resistance to ground of 75 Ω (doubly terminated 75 Ω configuration). This termination resistance should
be as close as possible to the ADV7120 so as to minimize
reflections.
Additional information on PCB design is available in an application note entitled “Design and Layout of a Video Graphics System for Reduced EMI.” This application note is available from
Analog Devices, publication number E1309-15-10/89.
–11–
ADV7120
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
44-Terminal Plastic Leaded Chip Carrier
(P-44A)
0.045
TYP
6
7
40
39
PIN 1
IDENTIFIER
C1379–24–4/90
0.045 TYP
0.045 TYP
0.050 ± 0.005
(1.27 ± 0.13) 0.630 (16.00)
0.045
TYP
0.590 (14.99)
0.021 (0.533)
TOP VIEW
0.013 (0.331)
(PINS DOWN)
0.032 (0.812)
17
0.026 (0.661)
29
28
18
0.656 (16.662)
0.650 (16.510)
0.020 MIN
SQ
0.120 (3.04)
0.090 (2.29)
0.695 (17.65)
SQ
0.685 (17.40)
0.180 (4.57)
0.165 (4.20)
R.020 MAX
3 PLCS
40-Pin Plastic DIP
(N-40A)
40
21
0.545 (13.843)
0.535 (13.589)
1
20
0.630 (16.0)
0.590 (15.0)
2.090 (53.0)
2.008 (51.0)
0.155 (3.937)
0.145 (3.683)
0.17
(4.32)
MAX
0.012 (0.305)
0.008 (0.203)
0.021 (0.533)
0.015 (0.381)
0.052 (1.32)
0.048 (1.219)
0.105 (2.67)
0.095 (2.42)
0.175 (4.45)
0.125 (3.18)
LEAD NO. 1 IDENTIFIED BY DOT, NOTCH OR "1."
LEADS ARE SOLDER PLATED KOVAR OR ALLOY 42.
15°
0°
0.354 ± 0.008
(9.00 ± 0.2)
0.059 +0.008 –0.004
(1.50 +0.2 –0.1)
0.02 ± 0.008
(0.5 ± 0.02)
0.276 ± 0.004
(7.0 ± 0.1)
0.055 ± 0.002
(1.40 ± 0.05)
37
36
48
1
0.276 ± 0.004
(7.0 ± 0.1)
0.354 ± 0.008
(9.00 ± 0.2)
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.004 ± 0.002
(0.1 ± 0.05)
0° MIN
(3.5° ± 3.5 °)
0.005 +0.002 –0.0008
(0.127 +0.05 –0.02)
PRINTED IN U.S.A.
48-Lead TQFP
(ST-48)
12
13
25
24
0.02 ± 0.003 0.007 ± 0.003 –0.001
(0.50 ± 0.08)
(0.18 ± 0.08 –0.03)
–12–
REV. B
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