TI LMP91050MMX Lmp91050 configurable afe for nondispersive infrared (ndir) sensing application Datasheet

LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
LMP91050 Configurable AFE for Nondispersive Infrared (NDIR) Sensing Applications
Check for Samples: LMP91050
FEATURES
DESCRIPTION
•
•
•
•
The LMP91050 is a programmable integrated Sensor
Analog Front End (AFE) optimized for thermopile
sensors, as typically used in NDIR applications. It
provides a complete signal path solution between a
sensor and microcontroller that generates an output
voltage proportional to the thermopile voltage. The
LMP91050's programmability enables it to support
multiple thermopile sensors with a single design as
opposed to the multiple discrete solutions.
1
2
Programmable Gain Amplifier
“Dark Signal” Offset Cancellation
Supports External Filtering
Common Mode Generator and 8 bit DAC
APPLICATIONS
•
•
•
•
•
•
•
NDIR Sensing
Demand Control Ventilation
Building Monitoring
CO2 Cabin Control — Automotive
Alcohol Detection — Automotive
Industrial Safety and Security
GHG & Freons Detection Platforms
KEY SPECIFICATIONS
•
•
•
•
•
Programmable gain 167 to 7986 V/V
Low noise (0.1 to 10 Hz) 0.1 μVRMS
Gain Drift 100 ppm/°C (max)
Phase Delay Drift 500 ns (max)
Power supply voltage range 2.7 to 5.5 V
The LMP91050 features a programmable gain
amplifier (PGA), “dark phase” offset cancellation, and
an adjustable common mode generator (1.15V or
2.59V) which increases output dynamic range. The
PGA offers a low gain range of 167V/V to 1335V/V
plus a high gain range of 1002V/V to 7986V/V which
enables the user to utilize thermopiles with different
sensitivities. The PGA is highlighted by low gain drift
(100 ppm/°C), output offset drift (1.2mV/°C at G =
1002 V/V), phase delay drift (500ns) and noise
specifications (0.1 μVRMS 0.1 to 10Hz) . The offset
cancellation circuitry compensates for the “dark
signal” by adding an equal and opposite offset to the
input of the second stage, thus removing the original
offset from the output signal. This offset cancellation
circuitry allows optimized usage of the ADC full scale
and relaxes ADC resolution requirements.
The LMP91050 allows extra signal filtering (high
pass, low pass or band pass) through dedicated pins
A0 and A1, in order to remove out of band noise. The
user can program through the on board SPI interface.
Available in a small form factor 10–pin package, the
LMP91050 operates from -40 to +105°C.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
www.ti.com
Block Diagram
CMOUT
VDD
A0
A1
LMP91050
G2=4,8,16,32
G1=250,42
IN
SPI
OUT
PGA2
PGA1
DAC
CMOUT
SPI
CM GEN
VREF
GND
CSB SCLK SDIO
Figure 1. Configurable AFE for NDIR
Typical Application
10 µF
6.8 nF
160 k
VDD
10 µF
CMOUT
10 nF
VDD
Thermopile
160 k
A0
A1
OUT
IN
1 kO
û ADC
10 nF
LMP91050
1 µF
CSB
CMOUT
SCLK
SDIO
10 nF
GND
Figure 2. Typical NDIR Sensing Application Circuit
2
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
Connection Diagram
VDD
IN
SDIO
CMOUT
A0
SCLK
LMP91050
A1
CSB
GND
OUT
Pin Descriptions
Pin
Symbol
Type
1
IN
Analog Input
Description
2
CMOUT
Analog Output
Common Mode Voltage Output
3
A0
Analog Output
First Stage Output
4
A1
Analog Input
5
GND
Power
6
OUT
Analog Output
7
CSB
Digital Input
Chip Select, active low
8
SCLK
Digital Input
Interface Clock
9
SDIO
Digital Input / Output
10
VDD
Power
Signal Input
Second Stage Input
Ground
Signal Output, reference to the same potential as
CMOUT
Serial Data Input / Output
Positive Supply
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance (3)
(1) (2)
Human Body Model
2500V
Machine Model
250V
Charged Device Model
Supply Voltage (VDD)
1250V
–0.3V to 6.0V
Voltage at Any Pin
– 0.3V to VDD + 0.3V
Input Current at Any Pin
5mA
Storage Temperature Range
-65°C to 150°C
Junction Temperature (4)
For soldering specifications:
see product folder at www.ti.com and
(1)
(2)
(3)
(4)
150°C
http://www.ti.com/lit/SNOA549.
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the
device is functional and the device should not be operated beyond such conditions.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field- Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
3
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
Operating Ratings
www.ti.com
(1)
Supply Voltage
2.7V to 5.5V
Junction Temperature Range
(2)
-40°C to 105°C
Package Thermal Resitance, θJA
10 Lead VSSOP
(1)
176 °C/W
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Operating Ratings is not implied. Operating Ratings indicate conditions at which the
device is functional and the device should not be operated beyond such conditions.
The maximum power dissipation is a function of TJ(MAX), θJA, and the ambient temperature, TA. The maximum allowable power
dissipation at any ambient temperature is PDMAX = (TJ(MAX) - TA)/ θJA All numbers apply for packages soldered directly onto a PC board.
(2)
Electrical Characteristics (1)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless otherwise
specified. All other limits apply to TA = TJ = +25°C.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
Power Supply
VDD
Supply Voltage
2.7
3.3
5.5
V
IDD
Supply Current
All analog block ON
3.1
3.7
4.2
mA
Power Down Supply Current
All analog block OFF
45
85
121
μA
Offset Cancellation (Offset DAC)
Resolution
LSB
256
All gains
33.8
DNL
-1
Error
Output referred offset error, all gains
Offset adjust Range
Output referred, all gains
steps
mV
2
±100
DAC settling time
mV
VDD –
0.2
0.2
LSB
V
μs
480
Programmable Gain Amplifier (PGA) 1st Stage, RL = 10kΩ, CL = 15pF
IBIAS
Bias Current
VINMAX
_HGM
Max input signal High gain
mode
VINMAX
_LGM
Max input signal Low gain
mode
VOS
Input Offset Voltage
-165
µV
G _HGM
Gain High gain mode
250
V/V
G_LGM
Gain Low gain mode
42
V/V
GE
Gain Error
VOUT
5
Referenced to CMOUT voltage, it refers to the
maximum voltage at the IN pin before clipping; It
includes dark voltage of the thermopile and
signal voltage.
Both HGM and LGM
Output Voltage Range
Phase Delay
TCPhDly
Phase Delay variation with
Temperature
1mV input step signal, HGM, Vout measured at
Vdd/2,
SSBW
Small Signal Bandwidth
Vin = 1mVpp, Gain = 250 V/V
Cin
Input Capacitance
(2)
(3)
4
mV
±12
mV
%
VDD –
0.5
0.5
PhDly
pA
±2
2.5
1mV input step signal, HGM, Vout measured at
Vdd/2
(1)
200
V
6
μs
416
ns
18
kHz
100
pF
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
Electrical Characteristics(1) (continued)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless otherwise
specified. All other limits apply to TA = TJ = +25°C.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
Programmable Gain Amplifier (PGA) 2nd Stage, RS = 1kΩ, CL = 1µF
VINMAX
Max input signal
VINMIN
Min input signal
GAIN = 4 V/V
1.65
V
G
Gain
Programmable in 4 steps
GE
Gain Error
Any gain
VOUT
Output Voltage Range
PhDly
Phase Delay
100mV input sine 35kHz signal, Gain = 8, VOUT
measured at 1.65V, RL = 10kΩ
1
µs
TCPhDly
Phase Delay variation with
Temperature
250mV input step signal, Gain = 8, Vout
measured at Vdd/2
84
ns
SSBW
Small Signal Bandwidth
Gain = 32 V/V
360
kHz
Cin
Input Capacitance
5
pF
CLOAD,
OUT
OUT Pin Load Capacitance
Series RC
1
µF
RLOAD,
OUT
OUT Pin Load Resistance
Series RC
1
kΩ
Combination of both current and voltage noise,
with a 86kΩ source impedance at 5Hz, Gain =
7986
30
nV/√Hz
Combination of both current and voltage noise,
Input-Referred Integrated Noise with a 86kΩ source impedance 0.1Hz to 10Hz,
Gain = 7986
0.1
0.82
4
V
32
V/V
2.5
%
VDD –
0.2
0.2
V
Combined Amplifier Chain Specification
en
Input-Referred Noise Density
G
Gain
GE
Gain Error
PGA1 GAIN = 42, PGA2 GAIN = 4
167
PGA1 GAIN = 42, PGA2 GAIN = 8
335
PGA1 GAIN = 42, PGA2 GAIN = 16
669
PGA1 GAIN = 42, PGA2 GAIN = 32
1335
PGA1 GAIN = 250, PGA2 GAIN = 4
1002
PGA1 GAIN = 250, PGA2 GAIN = 8
2004
PGA1 GAIN = 250, PGA2 GAIN = 16
4003
PGA1 GAIN = 250, PGA2 GAIN = 32
7986
Any gain
Gain Temp Coefficient
PSRR
Power Supply Rejection Ratio
DC, 3.0V to 3.6V supply, gain = 1002V/V
PhDly
Phase Delay
1mV input step signal, Gain = 1002, Vout
measured at Vdd/2
TCPhDly
Phase Delay variation with
Temperature (6)
1mV input step signal, Gain=1002, Vout
measured at Vdd/2
(4)
(5)
(6)
(4)
µVrms
V/V
5
(5)
TCCGE
0.12
%
100
90
ppm/°C
110
dB
9
µs
500
ns
Specified by design and characterization. Not tested on shipped production material.
TCCGE and TCVOS are calculated by taking the largest slope between -40°C and 25°C linear interpolation and 25°C and 85°C linear
interpolation.
TCPhDly is largest change in phase delay between -40°C and 25°C measurements and 25°C and 85°C measurements.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
5
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
www.ti.com
Electrical Characteristics(1) (continued)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, Bold values for TA = -40°C to +85°C unless otherwise
specified. All other limits apply to TA = TJ = +25°C.
Symbol
TCVOS
Parameter
Output Offset Voltage
Temperature Drift (5)
Conditions
Min
(2)
Typ
(3)
Max
(2)
Gain = 167 V/V
–0.525
0.525
Gain = 335 V/V
–0.60
0.60
Gain = 669 V/V
–0.90
0.90
Gain = 1335 V/V
–1.50
1.50
Gain = 1002 V/V
–1.20
1.20
Gain = 2004 V/V
–1.90
1.90
Gain = 4003 V/V
–3.70
3.70
Gain = 7986V/V
–7.10
7.10
Units
mV/°C
Common Mode Generator
VCM
Common Mode Voltage
CLOAD
1.15 or
2.59
Programmable, see Common Mode Generation
V
VCM accuracy
2
%
CMOut Load Capacitance
10
nF
SPI Interface (1)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
Symbol
Parameter
VIH
Logic Input High
VIL
Logic Input Low
VOH
Logic Output High
VOL
Logic Output Low
IIH/IIL
(1)
Conditions
Min
(2)
Typ
(3)
Max
Units
(2)
0.7
× VDD
V
0.8
2.6
V
–100
–200
Input Digital Leakage Current
V
0.4
V
100
200
nA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(2)
(3)
Timing Characteristics
(1)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
Symbol
Parameter
tWU
Wake up time
fSCLK
Serial Clock Frequency
(1)
(2)
(3)
6
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
10
MHz
1
ms
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
Timing Characteristics (1) (continued)
The following specifications apply for VDD = 3.3V, VCM = 1.15V, CL = 15pF, Bold values for TA = -40°C to +85°C unless
otherwise specified. All other limits apply to TA = TJ = +25°C.
Symbol
Parameter
Conditions
Min
(2)
Typ
(3)
Max
(2)
Units
tPH
SCLK Pulse Width High
0.4/fSCLK
ns
tPL
SCLK Pulse Width Low
0.4/fSCLK
ns
tCSS
CSB Setup Time
10
ns
tCSH
CSB Hold Time
10
ns
tSU
SDI Setup Time prior to rise
edge of SCLK
10
ns
tSH
SDI Hold Time prior to rise
edge of SCLK
10
ns
tDOD1
SDO Disable Time after rise
edge of CSB
45
ns
tDOD2
SDO Disable Time after 16th
rise edge of SCLK
45
ns
tDOE
SDO Enable Time from the fall
edge of 8th SCLK
35
ns
tDOA
SDO Access Time after the fall
edge of SCLK
35
ns
tDOH
SDO hold time after the fall
edge of SCLK
tDOR
SDO Rise time
5
ns
tDOF
SDO Fall time
5
ns
5
ns
Timing Diagrams
Figure 3. SPI Timing Diagram
tPL
tPH
16th clock
SCLK
tH
tSU
SDI
Valid Data
Valid Data
Figure 4. SPI Set-up Hold Time
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
7
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
www.ti.com
Figure 5. SDO disable time after 16th rise edge of SCLK
Figure 6. SDO access time (tDOA) and SDO hold time (tDOH) after the fall edge of SCLK
Figure 7. SDO Enable time from the fall edge of 8th SCLK
Figure 8. SDO disable time after rise edge of CSB
Figure 9. SDO rise and fall times
8
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
Typical Performance Characteristics
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Gain = 335 V/V vs. Temperature
336.0
168.3
335.9
168.2
335.8
GAIN (V/V)
GAIN (V/V)
Gain = 167 V/V vs. Temperature
168.4
168.1
168.0
335.7
335.6
167.9
335.5
167.8
-50
-25
0
25
50
75
TEMPERATURE (°C)
335.4
-50
100
-25
0
25
50
75
TEMPERATURE (°C)
Figure 10.
100
Figure 11.
Gain = 669 V/V vs. Temperature
Gain = 1002 V/V vs. Temperature
672.5
1011
672.4
GAIN (V/V)
GAIN (V/V)
672.3
672.2
672.1
672.0
1010
1009
671.9
671.8
671.7
-50
1008
-25
0
25
50
75
TEMPERATURE (°C)
100
-50
-25
0
25
50
75
TEMPERATURE (°C)
Figure 12.
Figure 13.
Phase Delay vs. Temperature
9.3
2013
9.2
PHASE DELAY ( s)
GAIN (V/V)
Gain = 2004 V/V vs. Temperature
2014
2012
2011
2010
2009
9.1
9.0
8.9
8.8
8.7
2008
-50
100
8.6
-25
0
25
50
75
TEMPERATURE (°C)
100
Figure 14.
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
Figure 15.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
9
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Output Offset vs. Temperature
Common Mode Voltage vs. Temperature
1.160
100
COMMON MODE VOLTAGE (V)
OUTPUT OFFSET (mV)
90
80
70
60
50
40
30
G = 1002 V/V
20
10
0
-50
-25
0
25
50
TEMPERATURE (°C)
75
1.158
1.156
1.154
1.152
1.150
-50
100
-25
0
25
50
75
TEMPERATURE (°C)
Figure 16.
Figure 17.
Input Bias Current vs. Temperature
Supply Current vs. Temperature
0
5
-1
4
IDD (mA)
IBIAS (pA)
100
-2
-3
3
2
G = 1002 V/V
-4
1
-5
0
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
-50
-25
0
25
50
TEMPERATURE (°C)
75
100
Figure 18.
Figure 19.
Supply Current vs. Supply Voltage
Power Down Supply Current vs. Supply Voltage
4.5
120
4.0
110
3.5
100
IDD ( A)
IDD (mA)
3.0
2.5
2.0
1.5
80
PGA ALL ON
PGA2 ON
PGA1 ON
1.0
0.5
0.0
2.5
70
60
3.0
3.5
4.0
4.5
VDD (V)
5.0
5.5
Figure 20.
10
90
2.5
3.0
3.5
4.0
4.5
VDD (V)
5.0
5.5
Figure 21.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
Typical Performance Characteristics (continued)
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
Output Offset vs. Supply Voltage
PGA1 Small Signal Bandwidth
60
65
G = 250 V/V
G = 42 V/V
50
G = 1002 V/V
40
GAIN (dB)
OUTPUT OFFSET (mV)
70
60
30
20
55
10
50
0
2.5
3.0
3.5
4.0
4.5
VDD (V)
5.0
5.5
1k
1M
Figure 22.
Figure 23.
PGA2 Small Signal Bandwidth
Power Supply Rejection Ratio vs. Frequency
40
120
G = 32 V/V
G = 16 V/V
G = 8 V/V
G = 4 V/V
20
G = 7986 V/V
G = 4003 V/V
G = 2004 V/V
G = 1002 V/V
110
PSRR (dB)
30
GAIN (dB)
10k
100k
FREQUENCY (Hz)
100
90
80
10
70
0
60
10k
100k
1M
FREQUENCY (Hz)
10M
10
100
FREQUENCY (Hz)
Figure 24.
Figure 25.
DAC DC Sweep
140
3.5
120
3.0
OUTPUT VOLTAGE (V)
NOISE DENSITY (nV/¥+])
Input-Referred Noise Density vs. Frequency
100
80
60
40
20
G = 1002 V/V
G = 2004 V/V
G = 4003 V/V
G = 7986 V/V
2.5
2.0
1.5
VDD = 3.3V
1.0
0.5
0.0
0
100m
1k
-0.5
1
10
100
1k
FREQUENCY (Hz)
10k
Figure 26.
0
50
100 150 200
DAC CODE
250
300
Figure 27.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
11
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
www.ti.com
Typical Performance Characteristics (continued)
VDD = +3.3V, VCM = 1.15V, and TA = 25°C unless otherwise noted
DAC DC Sweep
5.50
G = 1002 V/V
G = 2004 V/V
G = 4003 V/V
G = 7986 V/V
OUTPUT VOLTAGE (V)
4.75
4.00
3.25
2.50
VDD = 5V
1.75
1.00
0.25
-0.50
0
50
100 150 200
DAC CODE
250
300
Figure 28.
12
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
PROGRAMMABLE GAIN AMPLIFIER
The LMP91050 offers two programmable gain modes (low/high) with four programmable gain settings each. The
purpose of the gain mode is to enable thermopiles with larger dark voltage levels. All gain settings are accessible
through bits GAIN1 and GAIN2[1:0]. The low gain mode has a range of 167 V/V to 1335 V/V while the high gain
mode has a range of 1002 V/V to 7986 V/V. The PGA is referenced to the internally generated VCM. Input
signal, referenced to this VCM voltage, should be within +/-2mV (see VINMAX_HGM specification) in high gain
mode. In the low gain mode the first stage will provide a gain of 42 V/V instead of 250 V/V, thus allowing a larger
maximum input signal up to +/-12mV (VINMAX_LGM).
Table 1. Gain Modes
Bit Symbol
Gain
0: 250 (default)
GAIN1
1: 42
00: 4 (default)
01: 8
GAIN2 [1:0]
10: 16
11: 32
EXTERNAL FILTER
The LMP91050 offers two different measurement modes selectable through EXT_FILT bit. EXT_FILT bit is
present in the Device configuration register and is programmable through SPI.
Table 2. Measurement Modes
Bit Symbol
EXT_FILT
Measurement Mode
0: The signal from the thermopile is being processed by the internal PGAs, without
additional external decoupling or filtering (default).
1: The signal from the thermopile is being processed by the first internal PGA and fed to the A0
pin. An external low pass, high pass or band pass filter can be connected through pins A0, A1.
An external filter can be applied when EXT_FILT = 1. A typical band pass filter is shown in the picture below.
Resistor and capacitor can be connected to the CMOUT pin of the LMP91050 as shown. Discrete component
values have been added for reference.
10 µF
160 k
A1
A0
6.8 nF
160 k
CMOUT
Figure 29. Typical Bandpass Filter
OFFSET ADJUST
Procedure of the offset adjust is to first measure the “dark signal”, program the DAC to adjust, and then measure
in a second cycle the residual of the dark signal for further signal manipulation within the µC. The signal source
is expected to have an offset component (dark signal) larger than the actual signal. During the “dark phase”, the
time when no light is detected by the sensor, the µC can program LMP91050 internal DAC to compensate for a
measured offset. A low output offset voltage temperature drift (TCVOS) ensures system accuracy over
temperature. See Figure 30 below which plots the maximum TCVOS allowed over a given temperature drift in
order to achieve n bit system accuracy.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
13
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
www.ti.com
MAX TCVOS (mV/°C)
100
12 bit Accuracy
11 bit Accuracy
10 bit Accuracy
9 bit Accuracy
8 bit Accuracy
10
1
100m
10m
1
2 3 4 5 6 7 8 9
TEMPERATURE DRIFT (°C)
10
Figure 30. System Accuracy vs. TCVOS and Temperature Drift
COMMON MODE GENERATION
As the sensor's offset is bipolar, there is a need to supply a VCM to the sensor. This can be programmed as
1.15V or 2.59V (approximately mid rail of 3.3V or 5V supply). It is not recommended to use 2.59V VCM with 3.3V
supply
SPI INTERFACE
An SPI interface is available in order to program the device parameters like PGA gain of two stages, enabling
external filter, enabling power for PGAs, offset adjust and common mode (VCM) voltage.
Interface Pins
The Serial Interface consists of SDIO (Serial Data Input / Output), SCLK (Serial Interface Clock) and CSB (Chip
Select Bar). The serial interface is write-only by default. Read operations are supported after unlocking the
SDIO_MODE_PASSWD. This is discussed in detail later in the document.
CSB
Chip Select is a active-low signal. CSB needs to be asserted throughout a transaction. That is, CSB should not
pulse between the Instruction Byte and the Data Byte of a single transaction.
Note that CSB de-assertion always terminates an on-going transaction, if it is not already complete. Likewise,
CSB assertion will always bring the device into a state, ready for next transaction, regardless of the termination
status of a previous transaction.
CSB may be permanently tied low for a 2-wire SPI communication protocol.
SCLK
SCLK can idle High or Low for a write transaction. However, for a READ transaction, SCLK should idle high.
SCLK features a Schmitt-triggered input and although it has hysterisis, it is recommened to keep SCLK as clean
as possible to prevent glitches from inadvertently spoiling the SPI frame.
Communication Protocol
Communication on the SPI normally involves Write and Read transactions. Write transaction consists of single
Write Command Byte, followed by single Data byte. The following figure shows the SPI Interface Protocol for
write transaction.
14
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
LMP91050
www.ti.com
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
CSB
1
2
3
4
5
6
7
8
9
11
10
12
13
14
15
16
SCK
COMMAND FIELD
DATA FIELD
MSB
c7
Wb=0
c6
c5
c4
c3
Reserved to 0
c2
c1
c0
d7
LSB
d6
d5
Address (4 bits)
d4
d3
d2
d1
d0
Write Data (8-bits)
Figure 31. SPI Interface Protocol
For Read transactions, user first needs to write into a SDIO mode enable register for enabling the SPI read
mode. Once the device is enabled for Reading, the data is driven out on the SDIO pin during the Data field of the
Read Transaction. SDIO pin is designed as a bidirectional pin for this purpose. Figure 32 shows the Read
transaction. The sequence of commands that need to be issued by the SPI Master to enable SPI read mode is
illustrated in Figure 33.
Figure 32. Read Transaction
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
15
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
www.ti.com
Sequence of transactions for unlocking SDIO_MODE
CSB
SDI
Write cmd
(sdio_mod
e_en reg)
Write data Write cmd Write
(0xFE first (sdio_mode data
byte of
_en reg) (0xED)
sdio_mode
_en reg)
Read cmd (to
read contents of
any register
specified by the
address bits)
SDO
Read data
Bus turnaround time = half cycle
Note:
1. Once the SDIO_mode is unlocked. The user can read as many registers as long as nothing
else is written to sdio_mode_en register to disturb the state of SDIO_mode
2. The separate signals SDI and SDO are given in the figure for the sake of understanding.
However, only one signal SDIO exists in the design
Figure 33. Enable SDIO Mode for reading SPI registers
Registers Organization
Configuring the device is achieved using ‘Write’ of the designated registers in the device. All the registers are
organized into individually addressable byte-long registers that have a unique address. The format of the Write/
Read instruction is as shown below.
Table 3. Write / Read Instruction Format
Bit[7]
0 : Write Instruction
1 : Read Instruction
Bit[6:4]
Reserved to 0
Bit[3:0]
Address
REGISTERS
This section describes the programmable registers and the associated programming sequence, if any, for the
device. The following table shows the summary listing of all the registers that are available to the user and their
power-up values.
Title
Address (Hex)
Device Configuration
0x0
DAC Configuration
0x1
SDIO Mode Enable
0xF
Power-up/Reset
Value (Hex)
Type
Read-Write
(Read allowed in SDIO Mode)
Read-Write
(Read allowed in SDIO Mode)
Write-only
0x0
0x80
0x0
Device Configuration – Device Configuration Register (Address 0x0)
16
Bit
Bit Symbol
7
RESERVED
Description
Reserved to 0.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
LMP91050
www.ti.com
Bit
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
Bit Symbol
Description
00: PGA1 OFF PGA2 OFF (default)
[6:5]
EN
01: PGA1 OFF, PGA2 ON
10: PGA1 ON, PGA2 OFF
11: PGA1 ON, PGA2 ON
4
EXT_FILT
3
CMN_MODE
0: PGA1 to PGA2 direct (default)
1: PGA1 to PGA2 via external filter
0 : 1.15V (default)
1 : 2.59V
00: 4 (default)
[2:1]
GAIN2
01: 8
10: 16
11: 32
0
GAIN1
0: 250 (default)
1: 42
DAC Configuration – DAC Configuration Register (Address 0x1)
The output DC level will shift according to the formula Vout_shift = -33.8mV * (NDAC - 128).
Bit
Bit Symbol
[7:0]
NDAC
Description
128 (0x80): Vout_shift = -33.8mV * (128 - 128) = 0mV (default)
SDIO Mode – SDIO Mode Enable Register (Address 0xf)
Write-only
Bit
[7:0]
Bit Symbol
SDIO_MODE_EN
Description
To enter SDIO Mode, write the successive sequence 0xFE and 0xED.
Write anything other than this sequence to get out of mode.
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
17
LMP91050
SNAS517D – NOVEMBER 2011 – REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision C (March 2013) to Revision D
•
18
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 17
Submit Documentation Feedback
Copyright © 2011–2013, Texas Instruments Incorporated
Product Folder Links: LMP91050
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMP91050MM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
AN8A
LMP91050MME/NOPB
ACTIVE
VSSOP
DGS
10
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
AN8A
LMP91050MMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
AN8A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMP91050MM/NOPB
VSSOP
DGS
10
LMP91050MME/NOPB
VSSOP
DGS
LMP91050MMX/NOPB
VSSOP
DGS
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
10
250
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP91050MM/NOPB
VSSOP
DGS
10
1000
210.0
185.0
35.0
LMP91050MME/NOPB
VSSOP
DGS
10
250
210.0
185.0
35.0
LMP91050MMX/NOPB
VSSOP
DGS
10
3500
367.0
367.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated