Renesas HD74LS138P 3-line-to-8-line decoders / demultiplexer Datasheet

HD74LS138
3-Line-to-8-Line Decoders / Demultiplexers
REJ03D0434–0300
Rev.3.00
Jul.13.2005
The HD74LS138 decodes one-of-eight line dependent on the conditions at the three binaly select inputs and the three
enable inputs. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
Features
• Ordering Information
Part Name
Package Type
Package Code
(Previous Code)
Package
Abbreviation
Taping Abbreviation
(Quantity)
HD74LS138P
DILP-16 pin
PRDP0016AE-B
(DP-16FV)
P
-
HD74LS138FPEL
SOP-16 pin (JEITA)
PRSP0016DH-B
(FP-16DAV)
FP
EL (2,000 pcs/reel)
PRSP0016DG-A
RP
(FP-16DNV)
Note: Please consult the sales office for the above package availability.
HD74LS138RPEL
SOP-16 pin (JEDEC)
EL (2,500 pcs/reel)
Pin Arrangement
A
1
16
VCC
A
Select
Inputs
B
2
B
Y0
15
Y0
C
3
C
Y1
14
Y1
G2A
4
G2A
Y2
13
Y2
G2B
5
G2B
Y3
12
Y3
G1
6
G1
Y4
11
Y4
Outputs Y7
7
Y7
Y5
10
Y5
GND
8
9
Y6
Enable
Inputs
Y6
(Top view)
Rev.3.00, Jul.13.2005, page 1 of 7
Outputs
HD74LS138
Function Table
Inputs
Enable
G1
G2*
X
H
L
X
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
Select
B
X
X
L
L
H
H
L
L
H
H
C
X
X
L
L
L
L
H
H
H
H
Outputs
A
X
X
L
H
L
H
L
H
L
H
Y0
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
L
H
H
H
H
H
Y3
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
L
H ; high level, L ; low level, X ; irrelevant
* ; G2 = G2A + G2B
Block Diagram
Y0
Y1
Enable
Inputs
G1
Y2
G2A
G2B
Y3
Data
Outputs
Y4
Select
Inputs
A
Y5
B
Y6
C
Y7
Absolute Maximum Ratings
Symbol
Ratings
Unit
Supply voltage
Item
VCC
7
V
Input voltage
VIN
7
V
Power dissipation
PT
400
mW
Tstg
–65 to +150
°C
Storage temperature
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Supply voltage
Output current
Operating temperature
Rev.3.00, Jul.13.2005, page 2 of 7
Symbol
Min
Typ
Max
Unit
VCC
4.75
5.00
5.25
V
IOH
—
—
–400
µA
IOL
—
—
8
mA
Topr
–20
25
75
°C
HD74LS138
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
VIH
VIL
min.
2.0
—
typ.*
—
—
max.
—
0.8
Unit
V
V
VOH
2.7
—
—
V
—
—
—
—
—
—
—
—
—
—
0.4
0.5
20
–0.4
0.1
µA
mA
mA
VCC = 5.25 V, VI = 2.7 V
VCC = 5.25 V, VI = 0.4 V
VCC = 5.25 V, VI = 7 V
–20
—
–100
mA
VCC = 5.25 V
—
—
6.3
—
10
–1.5
mA
V
VCC = 5.25 V, Outputs enabled and open
VCC = 4.75 V, IIN = –18 mA
Output voltage
VOL
IIH
IIL
Input current
II
Short-circuit output
IOS
current
Supply current
ICC
Input clamp voltage
VIK
Note: * VCC = 5 V, Ta = 25°C
Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V,
IOH = –400 µA
IOL = 4 mA
VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
IOL = 8 mA
V
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Symbol
Propagation
delay time
tPLH
tPHL
tPLH
tPLH
tPLH
tPHL
tPLH
tPLH
Inputs
Binary
select
A, B, C
Enable
G2A, G2B
Enable
G1
Rev.3.00, Jul.13.2005, page 3 of 7
Output
Levels
of delay
2
Y
3
2
Y
3
min.
typ.
max.
Unit
—
—
—
—
—
—
13
27
18
26
12
21
20
41
27
39
18
32
ns
ns
ns
ns
ns
ns
—
—
17
25
26
38
ns
ns
Condition
CL = 15 pF,
RL = 2 kΩ
HD74LS138
Testing Method
Test Circuit
VCC
Output
4.5V
RL
Load circuit 1
Y0
CL
A
Input
See Testing Table
P.G.
Zout = 50Ω
Output
B
Y1
C
Same as Load Circuit 1.
Output
Y2
Same as Load Circuit 1.
Output
G1
G2A
Y3
Same as Load Circuit 1.
Output
G2B
Y4
Same as Load Circuit 1.
Output
Y5
Same as Load Circuit 1.
Output
Y6
Same as Load Circuit 1.
Output
Y7
Notes:
Same as Load Circuit 1.
1. CL includes probe and jig capacitance.
2. All diodes are 1S2074(H).
Waveform
tTHL
tTLH
90%
1.3 V
Input
3V
90%
1.3 V
10%
10%
0V
tPHL
tPLH
VOH
In phase Output
1.3 V
1.3 V
VOL
tPHL
tPLH
VOH
Out of phase Output
1.3 V
1.3 V
VOL
Note:
Input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50%
Rev.3.00, Jul.13.2005, page 4 of 7
HD74LS138
Relation Between Input and Output to Levels of Delay
Outputs
Inputs
A
B
C
G1
G2A, G2B
Y0
Y0
Y0
2 levels of delay
Y2
Y4
Y1
Y4
Y1
Y2
Rev.3.00, Jul.13.2005, page 5 of 7
Y0 to Y7
Y6
Y5
Y3
Y1
Y2
Y4
3 levels of delay
Y3
Y5
Y3
Y6
Y5
Y6
Y0 to Y7
Y7
Y7
Y7
HD74LS138
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
MASS[Typ.]
1.05g
Previous Code
DP-16FV
D
9
E
16
1
8
b3
0.89
Z
A1
A
Reference
Symbol
L
e
Nom
θ
c
e1
D
19.2
E
6.3
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
7.4
A1
0.51
b
p
0.40
b
3
0.48
0.56
1.30
c
0.19
θ
0°
e
2.29
0.25
0.31
2.54
2.79
15°
1.12
L
2.54
MASS[Typ.]
0.24g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
D
F
16
20.32
5.06
Z
( Ni/Pd/Au plating )
Max
7.62
1
A
bp
e
Dimension in Millimeters
Min
9
c
HE
*2
E
bp
Index mark
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
1
Z
*3
bp
Nom
D
10.06
E
5.50
Max
10.5
A2
8
e
Dimension in Millimeters
Min
x
A1
M
0.00
0.10
0.20
0.34
0.40
0.46
0.15
0.20
0.25
7.80
8.00
A
L1
2.20
bp
b1
c
A
c
A1
θ
y
L
Detail F
1
θ
0°
HE
7.50
e
1.27
x
0.12
y
0.15
0.80
Z
L
L
Rev.3.00, Jul.13.2005, page 6 of 7
8°
0.50
1
0.70
1.15
0.90
HD74LS138
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
*1
Previous Code
FP-16DNV
MASS[Typ.]
0.15g
D
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
16
9
c
*2
Index mark
HE
E
bp
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
Dimension in Millimeters
Min
Nom
Max
D
9.90
10.30
E
3.95
A2
8
1
Z
e
*3
bp
x
A1
0.10
0.14
0.25
0.34
0.40
0.46
0.15
0.20
0.25
6.10
6.20
1.75
A
M
L1
bp
b1
c
A
c
A1
θ
L
y
Detail F
1
θ
0°
HE
5.80
1.27
e
x
0.25
y
0.15
0.635
Z
0.40
L
L
Rev.3.00, Jul.13.2005, page 7 of 7
8°
1
0.60
1.08
1.27
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