CY28400-2 100-MHz Differential Buffer for PCI Express and SATA Features • SMBus Block/Byte/Word Read and Write support • 3.3V operation • CK409 and CK410 companion buffer • PLL Bypass-configurable • Four differential 0.7V clock output pairs • OE_INV input for inverting OE, PWRDWN, and SRC_STP active levels • Individual OE controls • Divide by 2 programmable outputs • 28-pin SSOP and TSSOP packages Functional Description • Low CTC jitter (< 50 ps) The CY28400-2 is a differential buffer and serves as a companion device to the CK409 or CK410 clock generator. The device is capable of distributing the Serial Reference Clock (SRC) in PCI Express and SATA implementations. • Programmable bandwidth • SRC_STP power management control Pin Configuration Block Diagram OE_INV DIFT1 Output Control DIFC1 DIFT2 SCLK SDATA SMBus Controller DIFC2 Output Buffer PLL/BYPASS# DIFT5 DIFC5 SRCT_IN SRCC_IN DIV HIGH_BW# VDD SRCT_IN SRCC_IN VSS VDD DIFT1 DIFC1 OE_1 DIFT2 DIFC2 VDD PLL/BYPASS# SCLK SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 CY28400-2 OE_1, OE_6 SRC_STP PWRDWN 25 24 23 22 21 20 19 18 17 16 15 VDD_A VSS_A IREF OE_INV VDD DIFT6 DIFC6 0E_6 DIFT5 DIFC5 VDD HIGH_BW# SRC_STP PWRDWN 28 SSOP/TSSOP DIFT6 DIFC6 PLL Cypress Semiconductor Corporation Document #: 38-07722 Rev *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 27, 2005 CY28400-2 Pin Description Pin 2,3 Name Type SRCT_IN, SRCC_IN 6,7;9,10;20,19; DIF[T/C][2:1] & [6:5] 23,22 I,DIF Description 0.7V Differential inputs O,DIF 0.7V Differential Clock Outputs 8,21 OE_1, OE_6 I,SE 3.3V LVTTL input for enabling differential outputs Active HIGH if OE_INV = 0 Active LOW if OE_INV = 1 17 HIGH_BW# I,SE 3.3V LVTTL input for selecting PLL bandwidth 0 = High BW, 1 = Low BW 15 PWRDWN I,SE 3.3V LVTTL input for Power Down Active LOW if OE_INV = 0 Active HIGH if OE_INV = 1 16 SRC_STP I,SE 3.3V LVTTL input for SRC_STP. Disables stoppable outputs. Active LOW if OE_INV = 0 Active HIGH if OE_INV = 1 I,SE SMBus Slave Clock Input 13 SCLK 14 SDATA 26 IREF I/O,OC Open collector SMBus data I A precision resistor is attached to this pin to set the differential output current I 3.3V LVTTL input for selecting fan-out or PLL operation 12 PLL/BYPASS# 28 VDD_A PWR 3.3V Power Supply for PLL 27 VSS_A GND Ground for PLL 4 VSS GND Ground for outputs 1,5,11,18,24 VDD PWR 3.3V power supply for outputs 25 OE_INV I, SE Input strap for setting polarity of OE_[7:0], SRC_STP, and PWRDWN Serial Data Interface Data Protocol To enhance the flexibility and function of the clock buffer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11011100 (DCh). Table 1. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 Description Start Slave address – 7 bits Document #: 38-07722 Rev *C Block Read Protocol Bit 1 2:8 Description Start Slave address – 7 bits Page 2 of 16 CY28400-2 Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 9 10 11:18 19 20:27 28 29:36 37 38:45 46 Block Read Protocol Description Bit Write = 0 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Description 9 Write = 0 10 Acknowledge from slave 11:18 19 Byte Count from master – 8 bits Acknowledge from slave 20 Acknowledge from slave Command Code – 8 bits '00000000' stands for block operation Repeat start 21:27 Slave address – 7 bits Data byte 0 from master – 8 bits 28 Read = 1 Acknowledge from slave 29 Acknowledge from slave Data byte 1 from master – 8 bits 30:37 Acknowledge from slave 38 .... Data bytes from master/Acknowledge .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop Byte count from slave – 8 bits Acknowledge from host 39:46 47 Data byte 0 from slave – 8 bits Acknowledge from host 48:55 Data byte 1 from slave – 8 bits 56 Acknowledge from host .... Data bytes from slave/Acknowledge .... Data byte N from slave – 8 bits .... Acknowledge from host .... Stop Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 Byte Read Protocol Description Bit Start 1 Slave address – 7 bits 2:8 Write = 0 Acknowledge from slave Command Code – 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits 28 Acknowledge from slave 29 Stop Description Start Slave address – 7 bits 9 Write = 0 10 Acknowledge from slave 11:18 19 20 21:27 Command Code – 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Acknowledge from master 39 Stop Byte 0: Control Register 0 Bit @pup Name 7 0 PWRDWN Drive Mode Power Down drive mode 0 = Driven when stopped, 1 = Tri-state 6 0 SRC_STP Drive Mode SRC Stop drive mode 0 = Driven when stopped, 1 = Tri-state Document #: 38-07722 Rev *C Description Page 3 of 16 CY28400-2 Byte 0: Control Register 0 (continued) Bit @pup Name Description 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 1 HIGH_BW# HIGH_BW# 0 = High Bandwidth, 1 = Low bandwidth 1 1 PLL/BYPASS# PLL/BYPASS# 0 = Fanout buffer, 1 = PLL mode 0 1 SRC_DIV2# SRC_DIV2# configures output frequency at half the input frequency 0 = Divided by 2 mode (output = input/2),1 = Normal (output = input) Byte 1: Control Register 1 Bit @pup 7 1 Reserved Name Reserved Description 6 1 OE_6 DIF[T/C]6 Output Enable 0 = Disabled (Tri-state) 1 = Enabled 5 1 OE_5 DIF[T/C]5 Output Enable 0 = Disabled (Tri-state) 1 = Enabled 4 1 Reserved Reserved 3 1 Reserved Reserved 2 1 OE_2 DIF[T/C]2 Output Enable 0 = Disabled (Tri-state) 1 = Enabled 1 1 OE_1 DIF[T/C]1 Output Enable 0 = Disabled (Tri-state) 1 = Enabled 0 1 Reserved Reserved Byte 2: Control Register 2 Bit @pup Name 7 0 Reserved Reserved 6 0 SRC_STP_DIF[T/C]6 Allow Control DIF[T/C]6 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 5 0 SRC_STP_DIF[T/C]5 Allow Control DIF[T/C]5 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 SRC_STP_DIF[T/C]2 Allow Control DIF[T/C]2 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 1 0 SRC_STP_DIF[T/C]1 Allow Control DIF[T/C]1 with assertion of SRC_STP 0 = Free-running 1 = Stopped with SRC_STP 0 0 Reserved Reserved Document #: 38-07722 Rev *C Description Page 4 of 16 CY28400-2 Byte 3: Control Register 3 Bit @pup Name Description 7 0 Reserved 6 0 Reserved 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 0 Reserved 1 0 Reserved 0 0 Reserved Byte 4: Vendor ID Register Bit @Pup Name Description 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 5 0 Revision Code Bit 1 4 0 Revision Code Bit 0 3 1 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Byte 5: Control Register 5 Bit @Pup 7 0 Name Reserved Description 6 0 Reserved 5 0 Reserved 4 0 Reserved 3 0 Reserved 2 0 Reserved 1 0 Reserved 0 0 Reserved OE_INV Clarification PWRDWN Clarification The OE_INV pin is an input strap sampled at power-on. The functionality of this input is to set the active level polarities for OE_1, OE_6, PWRDWN, and SRC_STP input pins. ‘Active HIGH’ indicates the functionality of the input is asserted when the input voltage level at the pin is high and deasserted when the voltage level at the input is low. ‘Active LOW’ indicates that the functionality of the input is asserted when the voltage level at the input is low and deasserted when the voltage level at the input pin is high. See VIH and VIL in the DC Electrical Specifications for input voltage high and low ranges. The PWRDWN pin is an asynchronous input used to shut off all clocks cleanly and instruct the device to evoke power savings mode. It may be active HIGH or active LOW depending on the strapped value of the OE_INV input. The PWRDWN pin should be asserted prior to shutting off the input clock or power to ensure all clocks shut down in a glitch-free manner. This signal is synchronized internal to the device prior to powering down the clock buffer. PWRDWN is an asynchronous input for powering up the system. When the PWRDWN pin is asserted, all clocks will be held high or tri-stated (depending on the state of the control register drive mode and OE bits) prior to turning off the VCO. All clocks will start and stop without any abnormal behavior and meet all AC and DC parameters. This means no glitches, frequency shifting or amplitude abnormalities among others. OE_INV PWRDWN SRC OE_1, OE_6 0 Active LOW Active LOW Active HIGH 1 Active HIGH Active HIGH Active LOW Document #: 38-07722 Rev *C Page 5 of 16 CY28400-2 OE_INV PWRDWN Mode 0 0 Power Down 0 1 Normal programmed to ‘0’, all clock outputs will be held with the DIFT pin driven high at 2 x Iref and DIFC tri-stated. However, if the control register PWRDWN Drive Mode bit is programmed to ‘1’, then both DIFT and the DIFC are tri-stated. 1 0 Normal PWRDWN—Deassertion 1 1 Power Down PWRDWN—Assertion When the power-down pin is sampled as being asserted by two consecutive rising edges of DIFC, all DIFT outputs will be held high or tri-stated (depending on the state of the control register drive mode and OE bits) on the next DIFC high to low transition. When the SMBus PWRDWN Drive Mode bit is The power-up latency is less than 1 ms. This is the time from the deassertion of the PWRDWN pin or the ramping of the power supply or the time from valid SRC_IN input clocks until the time that stable clocks are output from the buffer chip (PLL locked). IF the control register PWRDWN Drive Mode bit is programmed to ‘1’, all differential outputs must be driven high in less than 300 µs of the power down pin deassertion to a voltage greater than 200 mV. PWRDWN DIFT DIFC Figure 1. PWRDWN Assertion Diagram, OE_INV = 0 PWRDWN DIFT DIFC Figure 2. PWRDWN Assertion Diagram, OE_INV = 1 Tstable <1 ms PWRDWN DIFT DIFC Tdrive_Pwrdwn# <300 µs, >200 mV Figure 3. PWRDWN Deassertion Diagram, OE_INV = 0 Tstable <1 ms PWRDWN DIFT DIFC Tdrive_Pwrdwn# <300 µs, >200 mV Figure 4. PWRDWN Deassertion Diagram, OE_INV = 1 Document #: 38-07722 Rev *C Page 6 of 16 CY28400-2 Table 4. Buffer Power-up State Machine State Description 0 3.3V Buffer power off 1 After 3.3V supply is detected to rise above 1.8V - 2.0V, the buffer enters state 1 and initiates a 0.2-ms–0.3-ms delay 2[1] 3[2,3,4] Buffer waits for PWRDWN deassertion (and waits for a valid clock on the SRC_IN input in PLL mode) Once the PLL is locked to the SRC_IN input clock, the buffer enters state 3 and enables outputs for normal operation Figure 5. Buffer Power-up State Diagram SRC_STP Clarification SRC_STP Assertion The SRC_STP signal is an asynchronous input used for clean stopping and starting the DIFT/C outputs. This input can be Active HIGH or Active LOW based on the strapped value of the OE_INV input. The SRC_STP signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) In the case where the output is disabled via OE control, the output will always be tri-stated regardless of the SRC_STP Drive Mode register bit state. The impact of asserting the SRC_STP pin is that all DIF outputs that are set in the control registers to stoppable via assertion of SRC_STP are stopped after their next transition. When the control register SRC_STP tri-state bit is programmed to ‘0’, the final state of all stopped DIFT/C signals is DIFT clock = High and DIFC = Low. There will be no change to the output drive current values, DIFT will be driven high with a current value equal 6 x Iref, and DIFC will not be driven. When the control register SRC_STP three-state bit is programmed to ‘1’, the final state of all stopped DIF signals is low, both DIFT clock and DIFC clock outputs will not be driven. Table 5. SRC_STP Functionality[4] OE_INV SRC_STP DIFT DIFC 0 1 Normal Normal 0 0 Iref * 6 or Float Low 1 1 Iref * 6 or Float Low 1 0 Normal Normal Notes: 1. Disabling of the SRCT_IN input clock prior to assertion of PWRDWN is an undefined mode and not recommended. Operation in this mode may result in glitches excessive frequency shifting. 2. The total power up latency from power-on to all outputs active is less than 1 ms (assuming a valid clock is present on SRC_IN input). 3. In PLL Mode, if power is valid and PWRDWN is deasserted but no input clocks are present on the SRC_IN input, DIF clocks will remain disabled. Only after valid input clocks are detected, valid power, PWRDWN deasserted with the PLL locked and stable, are the DIF outputs enabled. 4. In the case where OE is asserted low, the output will always be three-stated regardless of SRC_STP drive mode register bit state. Document #: 38-07722 Rev *C Page 7 of 16 CY28400-2 SRC_STP Deassertion All differential outputs that were stopped will resume normal operation in a glitch-free manner. The maximum latency from the deassertion to active outputs is between 2–6 DIFT/C clock periods (2 clocks are shown) with all DIFT/C outputs resuming simultaneously. If the control register tri-state bit is programmed to ‘1’ (tri-state), then all stopped DIFT outputs will be driven high within 15 ns of SRC_STP deassertion to a voltage greater than 200 mV. 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 6. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 0 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 7. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV = 0 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 8. SRC_STP = Tri-state, PWRDWN = Tri-state, OE_INV = 0 Document #: 38-07722 Rev *C Page 8 of 16 CY28400-2 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 9. SRC_STP = Driven, PWRDWN = Driven, OE_INV = 1 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 10. SRC_STP = Tri-state, PWRDWN = Driven, OE_INV = 1 1 ms SRC_STP PWRDWN DIFT(Free Running DIFC(Free Running DIFT (Stoppable) DIFC (Stoppable) Figure 11. SRC_STP = Tri-state, PWRDWN = Tri-state, OE_INV = 1 Output Enable Clarification OE functionality allows for enabling and disabling individual outputs. OE_1 and OE_6 are Active HIGH or Active LOW inputs depending on the strapped value of the OE_INV input. Disabling the outputs may be implemented in two ways, via writing a ‘0’ to SMBus register bit corresponding to output of interest or by deasserting the OE input pin. In both methods, if SMBus registered bit has been written low or the OE pin is deasserted or both, the output of interest will be tri-stated. (The assertion and deassertion of this signal is absolutely asynchronous.) Document #: 38-07722 Rev *C Table 6. OE Functionality OE_INV OE (Pin) OE (SMBus Bit) DIF[T/C] 0 0 0 Tri-State 0 0 1 Tri-State 0 1 0 Tri-State 0 1 1 Enabled 1 0 0 Tri-State 1 0 1 Enabled 1 1 0 Tri-State 1 1 1 Tri-State Page 9 of 16 CY28400-2 OE Assertion SRC_DIV2# Deassertion All differential outputs that were tri-stated will resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2–6 DIF clock periods. In addition, DIFT clocks will be driven high within 15 ns of OE assertion to a voltage greater than 200 mV. The impact of deasserting the SRC_DIV2# is that all DIF outputs will transition cleanly in a glitch-free manner from divide by 2 mode to normal (output frequency is equal to the input frequency) operation within 2–6 DIF clock periods. OE Deassertion The impact of deasserting OE is that each corresponding output will transition from normal operation to tri-state in a glitch-free manner. The maximum latency from the deassertion to tri-stated outputs is between 2–6 DIF clock periods. SRC_DIV2# Clarification The SRC_DIV2# input is used to configure the DIF output mode to be equal to the SRC_IN input frequency or half the input frequency in a glitch-free manner. The SRC_DIV2# function may be implemented via writing a ‘0’ to SMBus register bit. SRC_DIV2# Assertion The impact of asserting the SRC_DIV2# is that all DIF outputs will transition cleanly in a glitch-free manner from normal operation (output frequency equal to input) to half the input frequency within 2–6 DIF clock periods. Document #: 38-07722 Rev *C PLL/BYPASS# Clarification The PLL/Bypass# input is used to select between bypass mode (no PLL) and PLL mode. In bypass mode, the input clock is passed directly to the output stage resulting in 50-ps additive jitter (50 ps + input jitter) on DIF outputs. In the case of PLL mode, the input clock is pass through a PLL to reduce high frequency jitter. The BYPASS# mode may be selected in two ways, via writing a ‘0’ to SMBus register bit or by asserting the PLL/BYPASS# pin low. In both methods, if the SMBus register bit has been written to ‘0’ or PLL/BYPASS# pin is low or both, the device will be configure for BYPASS operation. HIGH_BW# Clarification The HIGH_BW# input is used to set the PLL bandwidth. This mode is intended to minimize PLL peaking when two or more buffers are cascaded by staggering device bandwidths. The PLL high bandwidth mode may be selected in two ways, via writing a ‘0’ to SMBus register bit or by asserting the HIGH_BW# pin is low or both, the device will be configured for high-bandwidth operation. Page 10 of 16 CY28400-2 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDD_A Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Functional TJ Temperature, Junction Functional ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level 0 70 °C 150 °C 2000 V V–0 1 DC Electrical Specifications Parameter Description Condition Min. Max. Unit 3.135 3.465 V VDD_A, VDD 3.3V Operating Voltage 3.3 ± 5% VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VIL 3.3V Input Low Voltage VSS – 0.5 0.8 V VIH 3.3V Input High Voltage 2.0 VDD + 0.5 V VOL 3.3V Output Low Voltage IOL = 1 mA – 0.4 V VOH 3.3V Output High Voltage IOH = –1 mA 2.4 – V IIL Input Low Leakage Current except internal pull-up resistors, 0 < VIN < VDD –5 IIH Input High Leakage Current except internal pull-down resistors, 0 < VIN < VDD µA 5 µA CIN Input Pin Capacitance 1.5 5 pF COUT Output Pin Capacitance –- 6 pF LIN Pin Inductance IDD3.3V Dynamic Supply Current IPD3.3V Power-down Supply Current – 7 nH At max. load, Full Active Bypass Mode – 92 mA At max. load, Full Active PLL Mode – 115 mA OE1 and OE6 deasserted, Bypass – 60 mA SRC_STP asserted, Outputs Driven, Bypass – 80 mA SRC_STP asserted, Outputs Tri-state, Bypass – 2 mA SRC_STP asserted, Outputs Driven, PLL – 85 mA SRC_STP asserted, Outputs Tri-State, PLL – 2 mA PWRDWN asserted, Outputs driven – 40 mA PWRDWN asserted, Outputs Tri-stated – 4 mA AC Electrical Specifications (Measured in High Bandwidth Mode) Parameter Description Condition Min. Max. Unit Measured at crossing point VOX 9.9970 10.0533 ns TABSMIN-IN Absolute minimum clock periods Measured at crossing point VOX 9.8720 TR / TF DIFT and DIFC Rise and Fall Times Single ended measurement: VOL = 0.175 to VOH = 0.525V (Averaged) 4 V/ns VIH Differential Input High Voltage VIL Differential Input Low Voltage VOX Crossing Point Voltage at 0.7V Swing SRC_IN at 0.7V TPERIOD Average Period Document #: 38-07722 Rev *C 0.6 ns 150 Measured SE 250 mV –150 mV 550 mV Page 11 of 16 CY28400-2 AC Electrical Specifications (continued) (Measured in High Bandwidth Mode) Parameter Description Condition Min. Max. Unit 140 mV 100 mV ∆VOX Vcross Variation over all edges VRB Differential Ringback Voltage –100 TSTABLE Time before ringback allowed 500 VMAX Absolute maximum input voltage VMIN Absolute minimum input voltage TDC DIFT and DIFC Duty Cycle Measured at crossing point VOX 45 55 % TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 % FIN Input Frequency Bypass or PLL 1:1 90 210 MHz FERROR Input/Output Frequency Error Bypass or PLL 1:1 – 0 ppm TDC DIFT and DIFC Duty Cycle Measured at crossing point VOX 45 55 % TPERIOD Average Period Measured at crossing point VOX at 100 MHz 9.9970 10.0533 ns TR / TF DIFT and DIFC Rise and Fall Times Single ended measurement: VOL = 0.175 to VOH = 0.525V (Averaged) 175 700 ps TRFM Rise/Fall Matching Determined as a fraction of 2 * (TR – TF)/(TR + TF) – 20 % ∆TR/∆TF Rise and Fall Time Variation Variation Single ended measurement: VOL = 0.175 to VOH = 0.525V (Real Time) – 125 ps VHIGH Voltage High Measured SE 660 850 mv VLOW Voltage Low Measured SE –150 – mv VOX Crossing Point Voltage at 0.7V Swing Measured SE 250 550 mv ∆VOX Vcross Variation over all edges Measured SE – 140 mV VOVS Maximum Overshoot Voltage Measured SE – VHIGH + 0.3 V VUDS Minimum Undershoot Voltage Measured SE – –0.3 V VRB Ring Back Voltage Measured SE 0.2 N/A V TCCJ Cycle to Cycle Jitter PLL Mode – 50 ps Bypass Mode (Jitter is additive) – 50 ps TSKEW Any DIFT/C to DIFT/C Clock Skew Measured at crossing point VOX – 50 ps TPD Input to output skew in PLL mode Measured at crossing point VOX – ±250 ps Input to output skew in Non-PLL mode Measured at crossing point VOX 2.5 4.5 ns Measured SE ps 1.15 –0.3 V V DIF at 0.7V D IF T D IF C IR E F 475Ω 33Ω T PCB 4 9 .9 Ω 33Ω T PCB 4 9 .9 Ω M e a s u re m e n t P o in t 2 pF M e a s u re m e n t P o in t 2 pF T r a c e Im p e d a n c e M e a s u r e d D if f e r e n tia lly Figure 12. Differential Clock Termination Document #: 38-07722 Rev *C Page 12 of 16 CY28400-2 Switching Waveforms TRise (CLOCK) VOH = 0.525V CL OC K# K OC CL VCROSS VOL = 0.175V TFall (CLOCK) Figure 13. Single-Ended Measurement Points for TRise and TFall VOVS VRB VRB VLOW VUDS Figure 14. Single-ended Measurement Points for VOVS,VUDS and VRB Document #: 38-07722 Rev *C Page 13 of 16 CY28400-2 TPERIOD High Duty Cycle % Low Duty Cycle % Skew Management Point 0.000V Figure 15. Differential (Clock-Clock#) Measurement Points (Tperiod, Duty Cycle and Jitter) Ordering Information Ordering Code Package Type Operating Range Lead-free CY28400OXC-2 28-pin SSOP CY28400OXC-2T 28-pin SSOP—(Tape and Reel) Commercial, 0°C to 70°C CY28400ZXC-2 28-pin TSSOP Commercial, 0°C to 70°C CY28400ZXC-2T 28-pin TSSOP—(Tape and Reel) Commercial, 0°C to 70°C Document #: 38-07722 Rev *C Commercial, 0°C to 70°C Page 14 of 16 CY28400-2 Package Drawing and Dimensions 28-Lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C 28-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z28.173 DIMENSIONS IN MM[INCHES] MIN. MAX. PIN 1 ID 1 REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.16 gms 4.30[0.169] 4.50[0.177] 6.25[0.246] 6.50[0.256] PART # Z28.173 STANDARD PKG. ZZ28.173 LEAD FREE PKG. 28 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 9.60[0.378] 9.80[0.386] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85120-*A All product and company names mentioned in this document are trademarks of their respective owners. Document #: 38-07722 Rev *C Page 15 of 16 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28400-2 Document History Page Document Title: CY28400-2 100-MHz Differential Buffer for PCI Express and SATA Document Number: 38-07722 Rev. ECN No. Issue Date Orig. of Change ** 299694 See ECN RGL New data sheet *A 367458 See ECN RGL Added Lead-free devices, removed non lead-free to match the Devmaster *B 391558 See ECN RGL Added TSSOP lead-free device *C 404283 See ECN RGL IDD 3.3V Dynamic Supply Current: Description of Change At max. load, Full Active Bypass Mode – 92 mA At max. load, Full Active PLL Mode – 115 mA OE1 and OE6 deasserted, Bypass – 60 mA Document #: 38-07722 Rev *C Page 16 of 16