DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 DAC0800/DAC0802 8-Bit Digital-to-Analog Converters Check for Samples: DAC0800, DAC0802 FEATURES DESCRIPTION • • • • • • • The DAC0800 series are monolithic 8-bit high-speed current-output digital-to-analog converters (DAC) featuring typical settling times of 100 ns. When used as a multiplying DAC, monotonic performance over a 40 to 1 reference current range is possible. The DAC0800 series also features high compliance complementary current outputs to allow differential output voltages of 20 Vp-p with simple resistor loads. The reference-to-full-scale current matching of better than ±1 LSB eliminates the need for full-scale trims in most applications, while the nonlinearities of better than ±0.1% over temperature minimizes system error accumulations. 1 2 • • • • Fast Settling Output Current: 100 ns Full Scale Error: ±1 LSB Nonlinearity Over Temperature: ±0.1% Full Scale Current Drift: ±10 ppm/°C High Output Compliance: −10V to +18V Complementary Current Outputs Interface Directly with TTL, CMOS, PMOS and Others 2 Quadrant Wide Range Multiplying Capability Wide Power Supply Range: ±4.5V to ±18V Low Power Consumption: 33 mW at ±5V Low Cost The noise immune inputs will accept a variety of logic levels. The performance and characteristics of the device are essentially unchanged over the ±4.5V to ±18V power supply range and power consumption at only 33 mW with ±5V supplies is independent of logic input levels. The DAC0800, DAC0802, DAC0800C and DAC0802C are a direct replacement for the DAC-08, DAC-08A, DAC-08C, and DAC-08H, respectively. For single supply operation, refer to AN-1525. Typical Application Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 1. ±20 VP-P Output Digital-to-Analog Converter These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Absolute Maximum Ratings www.ti.com (1) Supply Voltage (V+ − V−) Power Dissipation ±18V or 36V (2) 500 mW Reference Input Differential Voltage V− to V+ (V14 to V15) Reference Input Common-Mode V− to V+ Range (V14, V15) Reference Input Current 5 mA − Logic Inputs − V to V plus 36V Analog Current Outputs (VS− = −15V) 4.25 mA (3) TBD V Storage Temperature −65°C to +150°C ESD Susceptibility Lead Temp. (Soldering, 10 seconds) PDIP Package (plastic) 260°C CDIP Package (ceramic) 300°C Surface Mount Package (1) Vapor Phase (60 seconds) 215°C Infrared (15 seconds) 220°C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. The maximum junction temperature of the DAC0800 and DAC0802 is 125°C. For operating at elevated temperatures, devices in the CDIP package must be derated based on a thermal resistance of 100°C/W, junction-to-ambient, 175°C/W for the molded PDIP package and 100°C/W for the SOIC package. Human body model, 100 pF discharged through a 1.5 kΩ resistor. (2) (3) Operating Conditions (1) Min Max Units Temperature (TA) −55 +125 °C DAC0800LC 0 +70 °C DAC0802LC 0 +70 °C DAC0800L − + − V (V ) + 10 (V ) + 30 V− −15 −5 V IREF (V− = −5V) 1 2 mA IREF (V− = −15V) 1 4 mA (1) 2 V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Electrical Characteristics The following specifications apply for VS = ±15V, IREF = 2 mA and TMIN ≤ TA ≤ TMAX unless otherwise specified. Output characteristics refer to both IOUT and IOUT. Parameter Typ Max Min Typ Max Resolution 8 8 8 8 8 8 Monotonicity 8 8 8 8 8 8 Bits ±0.19 %FS ±0.1 To ±½ LSB, All Bits Switched “ON” or “OFF”, TA=25°C ts Settling Time tPLH, Propagation Delay TCIFS 100 Bits 135 ns DAC0800L 100 135 ns DAC0800LC 100 150 ns TA=25°C Each Bit 35 60 35 60 ns All Bits Switched 35 60 35 60 ns ±10 ±50 ±10 ±50 ppm/°C 18 V 1.99 2.04 mA ±1 ±8.0 μA 0.2 2.0 μA 2.0 2.0 2.1 4.2 mA 0.8 V Full Scale Tempco VOC Output Voltage Compliance Full Scale Current Change <½ LSB, ROUT>20 MΩ, Typical IFS4 Full Scale Current VREF = 10.000V, R14 = R15 = 5.000 kΩ, TA=25°C IFSS Full Scale Symmetry IFS4−IFS2 IZS Zero Scale Current IFSR Units Min Nonlinearity tPHL DAC0800L/ DAC0800LC DAC0802LC Test Conditions Output Current Range V− = −5V V− = −8V to −18V Logic Input Levels VLC = 0V VIL Logic “0” VIH Logic “1” Logic Input Current −10 1.984 0 0 18 −10 1.992 2.00 1.94 ±0.5 ±4.0 0.1 1.0 2.0 2.0 2.1 4.2 0 0 0.8 2.0 2.0 V VLC = 0V IIL Logic “0” −10V ≤ VIN ≤ +0.8V −2.0 −10 −2.0 −10 μA IIH Logic “1” 2V ≤ VIN ≤ +18V 0.002 10 0.002 10 μA 18 V VIS Logic Input Swing V− = −15V −10 VTHR Logic Threshold Range VS = ±15V −10 I15 Reference Bias Current dl/dt Reference Input Slew Rate (Figure 26) PSSIFS+ Positive Power Supply Sensitivity 4.5V ≤ V+ ≤ 18V 0.0001 0.01 0.0001 0.01 %/% PSSIFS− Negative Power Supply Sensitivity −4.5V ≤ V− ≤ 18V, IREF = 1mA 0.0001 0.01 0.0001 0.01 %/% Power Supply Current VS = ±5V, IREF = 1 mA I+ I− I+ I− I+ I− PD Power Supply Current Power Supply Current Power Consumption −1.0 4.0 18 −10 13.5 −10 −3.0 8.0 −1.0 4.0 13.5 V −3.0 μA 8.0 mA/μs 2.3 3.8 2.3 3.8 mA −4.3 −5.8 −4.3 −5.8 mA 2.4 3.8 2.4 3.8 mA −6.4 −7.8 −6.4 −7.8 mA 2.5 3.8 2.5 3.8 mA −6.5 −7.8 −6.5 −7.8 mA ±5V, IREF = 1 mA 33 48 33 48 mW +5V, −15V, IREF = 2 mA 108 136 108 136 mW ±15V, IREF = 2 mA 135 174 135 174 mW VS = +5V, −15V, IREF = 2 mA VS = ±15V, IREF = 2 mA Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 Submit Documentation Feedback 3 DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com Connection Diagrams Figure 2. PDIP, CDIP Packages - Top View (See Package Number NFG0016E or NFE0016A) Figure 3. SOIC Package - Top View (See Package Number D0016A) Block Diagram Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 4. 4 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Typical Performance Characteristics Full Scale Current vs. Reference Current LSB Propagation Delay vs. IFS Figure 5. Figure 6. Reference Input Frequency Response Reference Amp Common-Mode Range Curve 1: CC=15 pF, VIN=2 Vp-p centered at 1V. Curve 2: CC=15 pF, VIN=50 mVp-p centered at 200 mV. Curve 3: CC=0 pF, VIN=100 mVp-p centered at 0V and applied through 50Ω connected to pin 14.2V applied to R14. Figure 7. Note. Positive common-mode range is always (V+) − 1.5V. Figure 8. Logic Input Current vs. Input Voltage VTH — VLC vs. Temperature Figure 9. Figure 10. Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 Submit Documentation Feedback 5 DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Output Current vs. Output Voltage (Output Voltage Compliance) Output Voltage Compliance vs. Temperature Figure 11. Figure 12. Bit Transfer Characteristics Power Supply Current vs. +V Note. B1–B8 have identical transfer characteristics. Bits are fully switched with less than ½ LSB error, at less than ±100 mV from actual threshold. These switching points are guaranteed to lie between 0.8 and 2V over the operating temperature range (VLC = 0V). Figure 13. 6 Figure 14. Power Supply Current vs. −V Power Supply Current vs. Temperature Figure 15. Figure 16. Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 EQUIVALENT CIRCUIT Figure 17. Equivalent Circuit Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 Submit Documentation Feedback 7 DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com TYPICAL APPLICATIONS Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. IO + IO = IFS for all logic states For fixed reference, TTL operation, typical values are: VREF = 10.000V RREF = 5.000k R15 ≈ RREF CC = 0.01 μF VLC = 0V (Ground) Figure 18. Basic Positive Reference Operation Figure 19. Recommended Full Scale Adjustment Circuit Figure 20. Basic Negative Reference Operation Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. 8 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 21. Basic Unipolar Negative Operation Table 1. Basic Unipolar Negative Operation B1 B2 B3 B4 B5 B6 B7 B8 IO mA IOmA EO EO Full Scale 1 1 1 1 1 1 1 1 1.992 0.000 −9.960 0.000 Full Scale−LSB 1 1 1 1 1 1 1 0 1.984 0.008 −9.920 −0.040 Half Scale+LSB 1 0 0 0 0 0 0 1 1.008 0.984 −5.040 −4.920 Half Scale 1 0 0 0 0 0 0 0 1.000 0.992 −5.000 −4.960 Half Scale−LSB 0 1 1 1 1 1 1 1 0.992 1.000 −4.960 −5.000 Zero Scale+LSB 0 0 0 0 0 0 0 1 0.008 1.984 −0.040 −9.920 Zero Scale 0 0 0 0 0 0 0 0 0.000 1.992 0.000 −9.960 Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 22. Basic Bipolar Output Operation Table 2. Basic Bipolar Output Operation B1 B2 B3 B4 B5 B6 B7 B8 EO EO Pos. Full Scale 1 1 1 1 1 1 1 1 −9.920 +10.000 Pos. Full Scale−LSB 1 1 1 1 1 1 1 0 −9.840 +9.920 Zero Scale+LSB 1 0 0 0 0 0 0 1 −0.080 +0.160 Zero Scale 1 0 0 0 0 0 0 0 0.000 +0.080 Zero Scale−LSB 0 1 1 1 1 1 1 1 +0.080 0.000 Neg. Full Scale+LSB 0 0 0 0 0 0 0 1 +9.920 −9.840 Neg. Full Scale 0 0 0 0 0 0 0 0 +10.000 −9.920 Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 Submit Documentation Feedback 9 DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com (1) Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. (2) If RL = RL within ±0.05%, output is symmetrical about ground. Figure 23. Symmetrical Offset Binary Operation Table 3. Symmetrical Offset Binary Operation B1 B2 B3 B4 B5 B6 B7 B8 EO Pos. Full Scale 1 1 1 1 1 1 1 1 +9.960 Pos. Full Scale−LSB 1 1 1 1 1 1 1 0 +9.880 (+)Zero Scale 1 0 0 0 0 0 0 0 +0.040 (−)Zero Scale 0 1 1 1 1 1 1 1 −0.040 Neg. Full Scale+LSB 0 0 0 0 0 0 0 1 −9.880 Neg. Full Scale 0 0 0 0 0 0 0 0 −9.960 (1) Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. (2) For complementary output (operation as negative logic DAC), connect inverting input of op amp to IO (pin 2), connect IO (pin 4) to ground. Figure 24. Positive Low Impedance Output Operation (1) Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. (2) For complementary output (operation as a negative logic DAC) connect non-inverting input of op am to IO (pin 2); connect IO (pin 4) to ground. Figure 25. Negative Low Impedance Output Operation 10 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 Typical values: RIN=5k,+VIN=10V Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 26. Pulsed Reference Operation VTH = VLC + 1.4V 15V CMOS, HTL, HNIL VTH = 7.6V Note. Do not exceed negative logic input range of DAC. Figure 27. Interfacing with Various Logic Families (a) IREF ≥ peak negative swing of IIN (b) +VREF must be above peak positive swing of VIN Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 28. Accommodating Bipolar References Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 Submit Documentation Feedback 11 DAC0800, DAC0802 SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 www.ti.com Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 29. Settling Time Measurement (1) For 1 μs conversion time with 8-bit resolution and 7-bit accuracy, an LM361 comparator replaces the LM319 and the reference current is doubled by reducing R1, R2 and R3 to 2.5 kΩ and R4 to 2 MΩ. (2) Pin numbers represent the PDIP package. The SOIC package pin numbers differ from that of the PDIP package. Figure 30. A Complete 2 μs Conversion Time, 8-Bit A/D Converter 12 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 DAC0800, DAC0802 www.ti.com SNAS538C – JUNE 1999 – REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision B (February 2013) to Revision C • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 12 Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: DAC0800 DAC0802 Submit Documentation Feedback 13 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) DAC-08EP Package Type Package Pins Package Drawing Qty NRND PDIP NFG 16 25 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking TBD Call TI Call TI 0 to 70 DAC0800LCN DAC-08EP (4/5) DAC0800LCM NRND SOIC D 16 48 TBD Call TI Call TI 0 to 70 DAC0800LCM DAC0800LCM/NOPB ACTIVE SOIC D 16 48 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 DAC0800LCM DAC0800LCMX NRND SOIC D 16 2500 TBD Call TI Call TI 0 to 70 DAC0800LCM DAC0800LCMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 DAC0800LCM DAC0800LCN NRND PDIP NFG 16 25 TBD Call TI Call TI 0 to 70 DAC0800LCN DAC-08EP DAC0800LCN/NOPB ACTIVE PDIP NFG 16 25 Pb-Free (RoHS) SN Level-1-NA-UNLIM 0 to 70 DAC0800LCN DAC-08EP DAC0802LCMX NRND SOIC D 16 2500 TBD Call TI Call TI 0 to 70 DAC0802LCM DAC0802LCMX/NOPB ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 DAC0802LCM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DAC0800LCMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DAC0800LCMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DAC0802LCMX SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 DAC0802LCMX/NOPB SOIC D 16 2500 330.0 16.4 6.5 10.3 2.3 8.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DAC0800LCMX SOIC D 16 2500 367.0 367.0 35.0 DAC0800LCMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 DAC0802LCMX SOIC D 16 2500 367.0 367.0 35.0 DAC0802LCMX/NOPB SOIC D 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NFG0016E N0016E N16E (Rev G) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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