NSC CD4030C Quad exclusive-or gate Datasheet

CD4030M/CD4030C Quad EXCLUSIVE-OR Gate
General Description
Applications
The EXCLUSIVE-OR gates are monolithic complementary
MOS (CMOS) integrated circuits constructed with N- and Pchannel enhancement mode transistors. All inputs are protected against static discharge with diodes to VDD and VSS.
Y
Y
Y
Y
Y
Features
Y
Y
Y
Y
Y
Wide supply voltage range
3.0V to 15V
Low power
100 nW (typ.)
Medium speed
tPHL e tPLH e 40 ns (typ.)
operation
at CL e 15 pF, 10V supply
High noise immunity
0.45 VCC (typ.)
Y
Automotive
Data terminals
Instrumentation
Medical electronics
Industrial controls
Remote metering
Computers
Schematic Diagram
TL/F/5961 – 1
Connection Diagram
Dual-In-Line Package
TL/F/5961 – 2
Order Number CD4030
C1995 National Semiconductor Corporation
TL/F/5961
RRD-B30M105/Printed in U. S. A.
CD4030M/CD4030C Quad EXCLUSIVE-OR Gate
February 1988
Absolute Maximum Ratings
Storage Temperature Range
Power Dissipation (PD)
Dual-In-Line
Small Outline
Operating VDD Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Voltage at Any Pin (Note 1)
Operating Temperature Range
CD4030M
CD4030C
VSS b0.3V to VSS a 15.5V
b 55§ C to a 125§ C
b 40§ C to a 85§ C
b 65§ C to a 150§ C
700 mW
500 mW
VSS a 3.0V to VSS a 15V
Lead Temperature
(Soldering, 10 seconds)
260§ C
DC Electrical Characteristics CD4030M
Limits
Symbol
Parameter
b 55§ C
Conditions
Min
Typ
a 25§ C
Max
Min
a 125§ C
Typ
Max
Min
Typ
Units
Max
IL
Quiescent Device
Current
VDD e 5.0V
VDD e 10V
0.5
1.0
0.005
0.01
0.5
1.0
30
60
mA
mA
PD
Quiescent Device
Dissipation Package
VDD e 5.0V
VDD e 10V
2.5
10
0.025
0.1
2.5
10
150
600
mW
mW
VOL
Output Voltage
Low Level
VDD e 5.0V
VDD e 10V
0.05
0.05
0
0
0.05
0.05
0.05
0.05
V
V
VOH
Output Voltage
High Level
VDD e 5.0V
VDD e 10V
4.95
9.95
4.95
9.95
5.0
10
4.95
9.95
V
V
VNL
Noise Immunity
(All Inputs)
VDD e 5.0V
VDD e 10V
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH
Noise Immunity
(All Inputs)
VDD e 5.0V
VDD e 10V
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
IDN
Output Drive Current
N-Channel (Note 2)
VDD e 5.0V
VDD e 10V
0.75
1.5
0.6
1.2
1.2
2.4
0.45
0.9
mA
mA
IDP
Output Drive Current
P-Channel (Note 2)
VDD e 5.0V
VDD e 10V
b 0.45
b 0.95
b 0.3
b 0.65
b 0.6
b 1.3
b 0.21
b 0.45
mA
mA
II
Input Current
VI e 0V or VI e VDD
10
pA
DC Electrical Characteristics CD4030C
Limits
Symbol
Parameter
b 40§ C
Conditions
Min
Typ
a 25§ C
Max
Min
a 85§ C
Typ
Max
Min
Typ
Units
Max
IL
Quiescent Device
Current
VDD e 5.0V
VDD e 10V
5.0
10
0.05
0.1
5.0
10
70
140
mA
mA
PD
Quiescent Device
Dissipation Package
VDD e 5.0V
VDD e 10V
25
100
0.25
1.0
25
100
350
1,400
mW
mW
VOL
Output Voltage
Low Level
VDD e 5.0V
VDD e 10V
0.05
0.05
0
0
0.05
0.05
0.05
0.05
V
V
VOH
Output Voltage
High Level
VDD e 5.0V
VDD e 10V
4.95
9.95
4.95
9.95
5.0
10
4.95
9.95
V
V
VNL
Noise Immunity
(All Inputs)
VDD e 5.0V
VDD e 10V
1.5
3.0
1.5
3.0
2.25
4.5
1.4
2.9
V
V
VNH
Noise Immunity
(All Inputs)
VDD e 5.0V
VDD e 10V
1.4
2.9
1.5
3.0
2.25
4.5
1.5
3.0
V
V
IDN
Output Drive Current
N-Channel (Note 2)
VDD e 5.0V
VDD e 10V
0.35
0.7
0.3
0.6
1.2
2.4
0.25
0.5
mA
mA
IDP
Output Drive Current
P-Channel (Note 2)
VDD e 5.0V
VDD e 10 V
b 0.21
b 0.45
b 0.15
b 0.32
b 0.6
b 1.3
b 0.12
b 0.25
mA
mA
II
Input Current
VI e 0V or VI e VDD
10
2
pA
AC Electrical Characteristics* CD4030M
Symbol
Parameter
Limits
Conditions
Min
Units
Typ
Max
tPHL
Propagation Delay Time
VDD e 5.0V
VDD e 10V
100
40
200
100
ns
ns
tPLH
Propagation Delay Time
VDD e 5.0V
VDD e 10V
100
40
200
100
ns
ns
tTHL
Transition Time
High to Low Level
VDD e 5.0V
VDD e 10V
70
25
150
75
ns
ns
tTLH
Transition Time
Low to High Level
VDD e 5.0V
VDD e 10V
80
30
150
75
ns
ns
CI
Input Capacitance
VI e 0V or VI e VDD
5.0
pF
*AC Parameters are guaranteed by DC correlated testing.
AC Electrical Characteristics* CD4030C
Symbol
Parameter
Limits
Conditions
Min
Units
Typ
Max
tPHL
Propagation Delay Time
VDD e 5.0V
VDD e 10V
100
40
300
150
ns
ns
tPLH
Propagation Delay Time
VDD e 5.0V
VDD e 10V
100
40
300
150
ns
ns
tTHL
Transition Time
High to Low Level
VDD e 5.0V
VDD e 10V
70
25
300
150
ns
ns
tTLH
Transition Time
Low to High Level
VDD e 5.0V
VDD e 10V
80
30
300
150
ns
ns
CI
Input Capacitance
VI e 0V or VI e VDD
5.0
*AC Parameters are guaranteed by DC correlated testing.
Note 1: This device should not be connected to circuits with power on because high transient voltages may cause permanent damage.
Note 2: IDN and IDP are tested one output at a time.
Truth Table (For One of Four Identical Gates)
A
B
J
0
0
0
1
0
1
0
1
1
1
1
0
Where: ‘‘1’’ e High Level
‘‘0’’ e Low Level
3
pF
CD4030M/CD4030C Quad EXCLUSIVE-OR Gate
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4030MJ or CD4030CJ
NS Package Number J14A
Molded Dual-In-Line Package (N)
Order Number CD4030MN or CD4030CN
NS Package Number N14A
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