Revised January 1999 CD4049UBC • CD4050BC Hex Inverting Buffer • Hex Non-Inverting Buffer General Description Features The CD4049UBC and CD4050BC hex buffers are monolithic complementary MOS (CMOS) integrated circuits constructed with N- and P-channel enhancement mode transistors. These devices feature logic level conversion using only one supply voltage (VDD ). The input signal high level (VIH) can exceed the VDD supply voltage when these devices are used for logic level conversions. These devices are intended for use as hex buffers, CMOS to DTL/ TTL converters, or as CMOS current drivers, and at VDD = 5.0V, they can drive directly two DTL/TTL loads over the full operating temperature range. ■ Wide supply voltage range: 3.0V to 15V ■ Direct drive to 2 TTL loads at 5.0V over full temperature range ■ High source and sink current capability ■ Special input protection permits input voltages greater than VDD Applications • CMOS hex inverter/buffer • CMOS to DTL/TTL hex converter • CMOS current “sink” or “source” driver • CMOS HIGH-to-LOW logic level converter Ordering Code: Order Number CD4049UBCM Package Number M16A Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4049UBCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide CD4050BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow CD4050BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagrams Pin Assignments for DIP CD4049UBC CD4050BC Top View Top View © 1999 Fairchild Semiconductor Corporation DS005971.prf www.fairchildsemi.com CD4049UBC • CD4050BC Hex Inverting Buffer • Hex Non-Inverting Buffer October 1987 CD4049UBC • CD4050BC Schematic Diagrams CD4049UBC 1 of 6 Identical Units CD4050BC 1 of 6 Identical Units www.fairchildsemi.com 2 Recommended Operating Conditions (Note 2) Supply Voltage (VDD) −0.5V to +18V Supply Voltage (VDD) 3V to 15V Input Voltage (VIN) −0.5V to +18V Input Voltage (VIN) 0V to 15V Voltage at Any Output Pin (VOUT) −0.5V to VDD + 0.5V Storage Temperature Range (TS) −65°C to +150°C Voltage at Any Output Pin (VOUT) 0 to VDD Operating Temperature Range (TA) Power Dissipation (PD) −40°C to +85°C CD4049UBC, CD4050BC Dual-In-Line 700 mW Small Outline 500 mW Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The table of “Recommended Operating Conditions” and “Electrical Characteristics” provides conditions for actual device operation. Lead Temperature (TL) (Soldering, 10 seconds) 260°C Note 2: VSS = 0V unless otherwise specified. DC Electrical Characteristics (Note 3) Symbol IDD VOL Parameter Quiescent Device Current LOW Level Output Voltage −40°C Conditions Min +25°C Max Min Typ +85°C Max Min Max Units VDD = 5V 4 0.03 4.0 30 µA VDD = 10V 8 0.05 8.0 60 µA VDD = 15V 16 0.07 16.0 120 µA VDD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V VIH = VDD, VIL = 0V, |IO| < 1 µA VOH HIGH Level Output Voltage VIH = VDD, VIL = 0V, |IO| < 1 µA VIL LOW Level Input Voltage (CD4050BC Only) VIL VIH IOL 5 4.95 V 9.95 10 9.95 V VDD = 15V 14.95 14.95 15 14.95 V |IO| < 1 µA VDD = 5V, VO = 0.5V 1.5 2.25 1.5 1.5 V VDD = 10V, VO = 1V 3.0 4.5 3.0 3.0 V VDD = 15V, VO = 1.5V 4.0 6.75 4.0 4.0 V (CD4049UBC Only) VDD = 5V, VO = 4.5V 1.0 1.5 1.0 1.0 V VDD = 10V, VO = 9V 2.0 2.5 2.0 2.0 V VDD = 15V, VO = 13.5V 3.0 3.5 3.0 3.0 V HIGH Level Input Voltage |IO| < 1 µA VDD = 5V, VO = 4.5V 3.5 3.5 2.75 3.5 V VDD = 10V, VO = 9V 7.0 7.0 5.5 7.0 V VDD = 15V, VO = 13.5V 11.0 11.0 8.25 11.0 V HIGH Level Input Voltage |IO| < 1 µA (CD4049UBC Only) VDD = 5V, VO = 0.5V 4.0 4.0 3.5 4.0 V VDD = 10V, VO = 1V 8.0 8.0 7.5 8.0 V VDD = 15V, VO = 1.5V 12.0 12.0 11.5 12.0 V LOW Level Output Current HIGH Level Output Current (Note 4) IIN 4.95 9.95 |IO| < 1 µA (Note 4) IOH 4.95 VDD = 10V LOW Level Input Voltage (CD4050BC Only) VIH VDD = 5V Input Current VIH = VDD, VIL = 0V VDD = 5V, VO = 0.4V 4.6 4.0 5 3.2 mA VDD = 10V, VO = 0.5V 9.8 8.5 12 6.8 mA VDD = 15V, VO = 1.5V 29 25 40 20 mA VIH = VDD, VIL = 0V VDD = 5V, VO = 4.6V −1.0 −0.9 −1.6 −0.72 mA VDD = 10V, VO = 9.5V −2.1 −1.9 −3.6 −1.5 mA −5 VDD = 15V, VO = 13.5V −7.1 −6.2 −12 VDD = 15V, VIN = 0V −0.3 −0.3 −10−5 −1.0 µA VDD = 15V, VIN = 15V 0.3 0.3 10−5 1.0 µA mA Note 3: VSS = 0V unless otherwise specified. 3 www.fairchildsemi.com CD4049UBC • CD4050BC Absolute Maximum Ratings(Note 1) (Note 2) CD4049UBC • CD4050BC DC Electrical Characteristics (Continued) Note 4: These are peak output current capabilities. Continuous output current is rated at 12 mA maximum. The output current should not be allowed to exceed this value for extended periods of time. IOL and IOH are tested one output at a time. AC Electrical Characteristics (Note 5) CD4049UBC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise specified Symbol tPHL tPLH tTHL tTLH CIN Typ Max Units Propagation Delay Time Parameter VDD = 5V 30 65 ns HIGH-to-LOW Level VDD = 10V 20 40 ns VDD = 15V 15 30 ns Propagation Delay Time VDD = 5V 45 85 ns LOW-to-HIGH Level VDD = 10V 25 45 ns VDD = 15V 20 35 ns Transition Time VDD = 5V 30 60 ns HIGH-to-LOW Level VDD = 10V 20 40 ns VDD = 15V 15 30 ns Transition Time VDD = 5V 60 120 ns LOW-to-HIGH Level VDD = 10V 30 55 ns VDD = 15V 25 45 ns Any Input 15 22.5 pF Input Capacitance Conditions Min Note 5: AC Parameters are guaranteed by DC correlated testing. AC Electrical Characteristics (Note 6) CD4050BC TA = 25°C, CL = 50 pF, RL = 200k, tr = tf = 20 ns, unless otherwise specified Symbol tPHL tPLH tTHL tTLH CIN Typ Max Propagation Delay Time Parameter VDD = 5V Conditions Min 60 110 Units ns HIGH-to-LOW Level VDD = 10V 25 55 ns VDD = 15V 20 30 ns Propagation Delay Time VDD = 5V 60 120 ns LOW-to-HIGH Level VDD = 10V 30 55 ns ns VDD = 15V 25 45 Transition Time VDD = 5V 30 60 ns HIGH-to-LOW Level VDD = 10V 20 40 ns ns VDD = 15V 15 30 Transition Time VDD = 5V 60 120 ns LOW-to-HIGH Level VDD = 10V 30 55 ns VDD = 15V 25 45 ns Any Input 5 7.5 pF Input Capacitance Note 6: AC Parameters are guaranteed by DC correlated testing. www.fairchildsemi.com 4 CD4049UBC • CD4050BC Switching Time Waveforms Typical Applications CMOS to TLL or CMOS at a Lower VDD VDD1 ≥ VDD2 In the case of the CD4049UBC the output drive capability increases with increasing input voltage. E.g., If VDD1 = 10V the CD4049UBC could drive 4 TTL loads. 5 www.fairchildsemi.com CD4049UBC • CD4050BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A www.fairchildsemi.com 6 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user. Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4049UBC • CD4050BC Hex Inverting Buffer • Hex Non-Inverting Buffer Physical Dimensions inches (millimeters) unless otherwise noted (Continued)