Rohm BH3866AS Dual-line serial control sound processor ic Datasheet

Video ICs
Dual-line serial control sound
processor IC
BH3866AS
The BH3866AS is a signal processing IC developed for the control of volume and tone quality in TV equipment.
Since dual-line serial control (I2C BUS) is used, the volume level and tone quality in TV equipment can be changed
using signals such as those from a microcomputer or similar device.
Applications
•DVDs,
personal computers, high-vision TVs, karaoke sets, digital broadcasts, CATVs, and other TV equipment
•1)Features
3-channel volume and sound quality control (for
stereo and center speakers).
2) Absorption of volume deviation between input
sources and improved S / N ratio, for better sound
quality, using an AGC circuit.
3) Control through I2C BUS serial control.
4) Internal pseudo-stereo circuit provides phase-shift
matrix surround effect.
•Absolute maximum ratings (Ta = 25°C)
Parameter
Power supply voltage
Symbol
Limits
Unit
VCC
10.0
V
mW
Pd
1250∗
Operating temperature
Topr
– 25 ~ + 75
°C
Storage temperature
Tstg
– 55 ~ + 125
°C
Power dissipation
∗ Reduced by 12.5mW for each increase in Ta of 1°C over 25°C.
•Recommended operating conditions (Ta = 25°C)
Parameter
Power supply voltage
Symbol
Min.
Typ.
Max.
Unit
VCC
7.0
—
9.5
V
1
Video ICs
BH3866AS
50k
COUT
SCV
DAC
24
23
22
21
20
19
18
17
BASS
OFF
SMON
10k
OFF
PHASE
Surr effect LFP
Volume
Tone
(bass / treble)
+
–
10k
OFF
+
ON
–
AMP
SHIFT
10k
SON
R-S
VCA
OFF
+
Tone
(bass / treble)
Volume
ON 10k
Increment
L-R
SSTE
–
Volume
L+S
10k
50k
Increment
10k
ON
L+R
–
–
VCA
A
G
C
+
10k
Volume
+
AGC
–
Tone
(bass / treble)
+
ON
–
50k
Volume
MIX ON
CSEL
L+R
OFF
–
Volume
CIN
+
50k
MIX OFF
+
–
+
25
10k
VCC
50k
LOUT
26
CB
27
CT
28
LB
BGAIN
29
LT
MSIN
30
STT
BIN
31
ADD
VCC
32
CIN
LIN
•Block diagram
–
+
I2C BUS
LOOP
ON
VCC
50k
–
interface
1
2 VCC
+
11
12
13
14
15
16
SLV
SCL
SDA
10
SRV
9
SDA
ROUT
8
SCL
RB
LS1
7
RT
AGCADJ
6
STB
GND
5
Vref
4
PS
3
SOUT
2
LS2
1
RIN
50k
•Pin descriptions
Pin No.
Pin name
1
RIN
2
Function
Pin No.
Pin name
Function
Rch input
17
DAC
Expansion DAC (L / H)
Ground
18
SCV
Vol Cch shock sound integration
AGC 0dB adjustment
19
COUT
Cch output
LS1
AGC level sensor 1
20
LOUT
Lch output
LS2
AGC level sensor 2
21
CB
Cch Bass fc setting
6
SOUT
Sch output pin and LPF
22
CT
Cch Treble fc setting
7
PS
Phase shift pin (internal resistance: 18kΩ)
23
LB
Lch Bass fc setting
8
Vref
1 / 2 VCC
24
LT
Lch Treble fc setting
9
STB
Bass shock sound integration
25
STT
2
GND
3
AGCADJ
4
5
Treble shock sound integration
10
RT
Rch Treble fc setting
26
BGAIN
11
RB
Rch Bass fc setting
27
MSIN
12
ROUT
Rch output
28
BIN
13
SRV
Vol Rch shock sound integration
29
ADD
14
SLV
Vol Lch shock sound integration
30
CIN
Cch input
15
SCL
I2C
31
VCC
Power supply, 9V
16
SDA
I2C communications data
32
LIN
Lch input
communications clock
Bass Mix Gain adjustment
Mono Sur input
Bass detection LPF operating amplifier input
L + R added output after AGC
Video ICs
BH3866AS
•Input / output circuits
Pin No. Pin name
Pin voltage
Zin
I/O
Equivalent circuit
Function
VCC
1
RIN
30
CIN
32
LIN
4.5V
50k
I
Input pins.
50k
GND
1
2 VCC
VCC
200
12
ROUT
19
COUT
4.5V
—
O
Output pins.
10k
20
LOUT
200
GND
VCC
3
AGCADJ
—
—
AGC 0dB adjustment pin.
This pin is connected to the
base of PNP.
The current output from this
pin is 1µA (Typ.) Max.
I
GND
VCC
200
4
LS1
—
—
—
430
2k
Time constant pin on the
side that suppresses the
AGC signal level.
GND
3
Video ICs
BH3866AS
Pin No. Pin name Pin voltage
Zin
I/O
Equivalent circuit
Function
VCC
200
5
LS2
—
—
20k
—
2k
Time constant pin on the side
that amplifies the AGC signal
level.
GND
VCC
200
10k
6
SOUT
4.5V
10k
Serves as both the output pin
for the surround and pseudostereo effects, and the LPF
pin.
O
GND
200
VCC
10k
10k
7
PS
—
—
18k
—
For the phase-shifter filter for
the surround and pseudostereo effects.
18k
GND
VCC
50k
8
Vref
4.5V
—
—
50k
GND
4
1 / 2 VCC.
This voltage serves as the
power supply for the signal
system.
Video ICs
BH3866AS
Pin No. Pin name Pin voltage
Zin
Equivalent circuit
I/O
Function
VCC
9
—
25
Integration pins that prevent
shock sound when switching
the bass and treble levels.
STB
30k
—
STT
30k
DAC
GND
VCC
10
RT
22
CT
24
LT
4.5V
30k
Treble filter pins for the left,
right, and center channels.
—
30k
GND
1
2 VCC
VCC
11
RB
21
CB
23
LB
4.5V
30k
Bass filter pins for the left,
right, and center channels.
—
30k
GND
1
2 VCC
VCC
13
SRV
14
SLV
18
SCV
—
30k
—
30k
Integration pins that prevent
shock sound when switching
the volume levels on the left,
right, and center channels.
DAC
GND
5
Video ICs
BH3866AS
Pin No. Pin name Pin voltage
Zin
Equivalent circuit
I/O
Function
VCC
15
SCL
—
—
SCL pin for the I2C BUS.
This is the clock pin.
I
GND
VCC
16
SDA
—
—
SDA pin for the I2C BUS.
The Acknowledge signal is
output from this pin.
This is the data pin.
I
GND
control
logic
VCC
200
17
DAC
0/5
—
O
0V and 5V output pin that
enables control with the
I2C BUS.
100k
74.6k
25.6k
GND
VCC
BIN
10k
26
BGAIN
4.5V
—
—
50k
GND
6
1
2 VCC
Gain adjustment pin used
to mix the bass on the left
and right channels.
Video ICs
BH3866AS
Pin No. Pin name Pin voltage
Zin
I/O
Equivalent circuit
Function
VCC
27
MSIN
4.5V
50k
Surround input section for
monaural signals in the
surround section.
I
50k
1
2 VCC
GND
VCC
BGAIN
28
BIN
4.5V
50k
Bass signal input to the left
and right channels.
I
50k
1
2 VCC
GND
VCC
200
29
ADD
4.5V
—
Incremented output from the
left and right channels following
AGC.
O
10k
10k
200
1
2 VCC
GND
31
VCC
9V
—
—
—
Power supply pin.
2
GND
0V
—
—
—
Ground pin.
7
Video ICs
BH3866AS
•Electrical characteristics (unless otherwise noted, Ta = 25°C, V
CC
Parameter
Symbol
Min.
Typ.
Max.
= 9V, f = 1kHz, Rg = 600Ω, RL = 10kΩ)
Conditions
Unit
Quiescent circuit current
IQ
—
35
65
mA
Max. output voltage, Rch
VOMR
2.1
2.5
—
Vrms
THD = 1%( C )
VIN = 0Vrms
Max. output voltage, Lch
VOML
2.1
2.5
—
Vrms
THD = 1%( C )
Max. output voltage, Cch
VOMC
2.1
2.5
—
Vrms
THD = 1%(C )
Voltage gain, Rch
GVR
– 1.5
0
1.5
dB
VIN = 1Vrms, GVR = 20log (B / VIN)
Voltage gain, Lch
GVL
– 1.5
0
1.5
dB
VIN = 1Vrms, GVL = 20log (B / VIN)
GVC
– 1.5
0
1.5
dB
VIN = 1Vrms, GVC = 20log ( B / VIN)
THDR
—
0.01
0.1
%
VIN = 1Vrms
Total harmonic distortion, Lch
THDL
—
0.01
0.1
%
VIN = 1Vrms
Total harmonic distortion, Cch
THDC
—
0.1
0.3
%
VIN = 1Vrms
Output noise voltage, Rch
VNOR
—
35
70
µVrms
Rg = 0Ω, DIN AUDIO
Output noise voltage, Lch
VNOL
—
35
70
µVrms
Rg = 0Ω, DIN AUDIO
Output noise voltage, Cch
VNOC
—
35
70
µVrms
Rg = 0Ω, DIN AUDIO
Residual noise voltage, Rch
VMNOR
—
3
10
µVrms
Rg = 0Ω, DIN AUDIO
Residual noise voltage, Lch
VMNOL
—
3
10
µVrms
Rg = 0Ω, DIN AUDIO
Residual noise voltage, Cch
VMNOC
—
3
10
µVrms
Rg = 0Ω, DIN AUDIO
Crosstalk, Rch→Lch
CTR-L
70
78
—
dB
VIN = 1Vrms, CTR-L = 20log ( B R / B L)
Crosstalk, Rch→Cch
CTR-C
70
78
—
dB
VIN = 1Vrms, CTR-C = 20log ( B R / B C)
Crosstalk, Lch→Rch
CTL-R
70
78
—
dB
VIN = 1Vrms, CTL-R = 20log ( B L / B R)
Crosstalk, Lch→Cch
CTL-C
66
71
—
dB
VIN = 1Vrms, CTL-C = 20log ( B L / B C)
Crosstalk, Cch→Rch
CTC-R
70
78
—
dB
VIN = 1Vrms, CTC-R = 20log ( B C / B R)
Crosstalk, Cch→Lch
CTC-L
70
78
—
dB
VIN = 1Vrms, CTC-L = 20log ( B C / B L)
Input impedance, Rch
RINR
35
50
65
kΩ
Input impedance, Lch
RINL
35
50
65
kΩ
Input impedance, Cch
RINC
35
50
65
kΩ
Output impedance, Rch
ROUTR
—
—
50
Ω
Output impedance, Lch
ROUTL
—
—
50
Ω
Output impedance, Cch
ROUTC
—
—
50
Ω
Ripple rejection, Rch
RRR
40
53
—
dB
fRR = 100Hz,
VRR
RRR = 20log
B
VRR = 100mVrms,
Ripple rejection, Lch
RRL
40
53
—
dB
fRR = 100Hz,
VRR
RRR = 20log
VRR = 100mVrms,
B
Ripple rejection, Cch
RRC
40
53
—
dB
fRR = 100Hz,
VRR
RRR = 20log
B
VRR = 100mVrms,
Muting level, Rch
VMUTER
80
90
—
dB
VIN = 1Vrms, VMUTER = 20log
VIN
B
Muting level, Lch
VMUTEL
80
90
—
dB
VIN = 1Vrms, VMUTEL = 20log
VIN
B
Muting level, Cch
VMUTEC
80
90
—
dB
VIN = 1Vrms, VMUTEC = 20log
VIN
B
Voltage gain, Cch
Total harmonic distortion, Rch
8
50k × A
(1 – A )
50k × A
fINL = 1kHz, VIN = 1Vrms, RINR =
(1 – A )
50k × A
fINC = 1kHz, VIN = 1Vrms, RINR =
(1 – A )
1k × D
fOUTR = 1kHz, ROUTR =
1– D
fINR = 1kHz, VIN = 1Vrms, RINR =
1k ×
1–
1k ×
fOUTC = 1kHz, ROUTC =
1–
fOUTL = 1kHz, ROUTL =
D
D
D
D
Video ICs
Parameter
BH3866AS
Symbol
Min.
Typ.
Max.
Unit
Volume attenuation, Rch
ATTMAXR
80
90
—
dB
VIN = 1Vrms, ATTMAXR = 20log
Volume attenuation, Lch
ATTMAXL
80
90
—
dB
VIN = 1Vrms, ATTMAXL = 20log
Volume attenuation, Cch
ATTMAXC
80
90
—
dB
VIN = 1Vrms, ATTMAXC = 20log
Conditions
VIN
B
VIN
B
VIN
B
BR
VIN = 1Vrms, CB1R-L = 20log
BL
BR
VIN = 1Vrms, CB1R-C = 20log
BC
Channel balance 1, Rch→Lch
CB1R-L
– 1.5
0
1.5
dB
Channel balance 1, Rch→Cch
CB1R-C
– 1.5
0
1.5
dB
Channel balance 1, Lch→Cch
CB1L-C
– 1.5
0
1.5
dB
VIN = 1Vrms, CB1L-C = 20log
BL
BC
Channel balance 2, Rch→Lch
CB2R-L
– 2.0
0
2.0
dB
VIN = 1Vrms, CB2R-L = 20log
BR
BL
Channel balance 2, Rch→Cch
CB2R-C
– 2.0
0
2.0
dB
VIN = 1Vrms, CB2R-C = 20log
BR
BC
Channel balance 2, Lch→Cch
CB2L-C
– 2.0
0
2.0
dB
VIN = 1Vrms, CB2L-C = 20log
BL
BC
Bass boost gain, Rch
VBMAXR
13
15.5
18
dB
Comparison with f = 100Hz,
VIN = 100mVrms, bass flat
Bass boost gain, Lch
VBMAXL
13
15.5
18
dB
Comparison with f = 100Hz,
VIN = 100mVrms, bass flat
Bass boost gain, Cch
VBMAXC
13
15.5
18
dB
Comparison with f = 100Hz,
VIN = 100mVrms, bass flat
Bass cut gain, Rch
VBMINR
– 18
– 15.5
– 13
dB
Comparison with f = 100Hz,
VIN = 100mVrms, bass flat
Bass cut gain, Lch
VBMINL
– 18
– 15.5
– 13
dB
Comparison with f = 100Hz,
VIN = 100mVrms, bass flat
Bass cut gain, Cch
VBMINC
– 18
– 15.5
– 13
dB
Comparison with f = 100Hz,
VIN = 100mVrms, bass flat
Treble boost gain, Rch
VTMAXR
9
12
15
dB
Comparison with f = 10kHz,
VIN = 100mVrms, treble flat
Treble boost gain, Lch
VTMAXL
9
12
15
dB
Comparison with f = 10kHz,
VIN = 100mVrms, treble flat
Treble boost gain, Cch
VTMAXC
9
12
15
dB
Comparison with f = 10kHz,
VIN = 100mVrms, treble flat
Treble cut gain, Rch
VTMINR
– 15
– 12
–9
dB
Comparison with f = 10kHz,
VIN = 100mVrms, treble flat
Treble cut gain, Lch
VTMINL
– 15
– 12
–9
dB
Comparison with f = 10kHz,
VIN = 100mVrms, treble flat
Treble cut gain, Cch
VTMINC
– 15
– 12
–9
dB
Comparison with f = 10kHz,
VIN = 100mVrms, treble flat
AGC input / output level 1, Rch
VAGC1R
0.7
1
1.4
AGC input / output level 1, Lch
VAGC1L
0.7
1
1.4
mVrms VIN = 1mVrms
AGC input / output level 2, Rch
VAGC2R
50
80
110
mVrms VIN = 50mVrms
AGC input / output level 2, Lch
VAGC2L
50
80
110
mVrms VIN = 50mVrms
AGC input / output level 3, Rch
VAGC3R
90
130
170
mVrms VIN = 110mVrms
AGC input / output level 3, Lch
VAGC3L
90
130
170
mVrms VIN = 110mVrms
AGC input / output level 4, Rch
VAGC4R
160
210
260
mVrms VIN = 1Vrms
mVrms VIN = 1mVrms
9
Video ICs
BH3866AS
Parameter
Symbol
Min.
Typ.
Max.
AGC input / output level 4, Lch
VAGC4L
Conditions
Unit
160
210
260
Total harmonic distortion at AGC ON, Rch THDAGCR
—
0.4
1
%
VIN = 200mVrms
Total harmonic distortion at AGC ON, Lch THDAGCL
—
0.4
1
%
VIN = 200mVrms
Max. surround gain, Rch
.
VSUMAXR
4
6
8
dB
VIN = 100mVrms,
VSUMAXR = 20log B / VIN
Max. surround gain, Lch
VSUMAXL
4
6
8
dB
VIN = 100mVrms,
VSUMAXL = 20log B / VIN
Min. surround gain, Rch
VSUMINR
0
1
3.5
dB
VIN = 100mVrms,
VSUMINR = 20log B / VIN
Min. surround gain, Lch
VSUMINL
0
1
3.5
dB
VIN = 100mVrms,
VSUMINL = 20log B / VIN
Surround gain at Loop ON, Rch
VLPSUR
1.5
4
6.5
dB
VIN = 100mVrms,
VLPSUR = 20log B / VIN
Surround gain at Loop ON, Lch
VLPSUL
1.5
4
6.5
dB
VIN = 100mVrms,
VLPSUL = 20log B / VIN
Bass Add ON gain, Rch
VBAONR
7.5
10
12.5
dB
f = 100Hz, VIN = 100mVrms,
VBAONR = 20log B / VIN
Bass Add ON gain, Lch
VBAONL
7.5
10
12.5
dB
f = 100Hz, VIN = 100mVrms,
VBAONL = 20log B / VIN
Pseudo-stereo gain, Rch
VMONR
– 6.5
–4
– 1.5
dB
VIN = 100mVrms,
VMONR = 20log B / VIN
Pseudo-stereo gain, Lch
VMONL
1.5
4
6.5
dB
VIN = 100mVrms,
VMONL = 20log B / VIN
DAC pin operating voltage 1
VDAC1
4.7
5
5.3
V
DAC pin operating voltage 2
VDAC2
—
0
0.3
V
Suction current at I2C BUS ACK
IACK
2
—
—
mA
SCL and SDA pin input high level
VIHI
3.5
—
5
V
SCL and SDA pin input low level
VILO
—
—
0.9
V
∗ The phases are the same between the input and output signal pins.
10
mVrms VIN = 1Vrms
Video ICs
BH3866AS
•Measurement circuit
∗
10k
47k
50
J
Rg: 50
V
∗
∗
∗
2
100µ
1 S1
VCC
A
2
1
0.33µ
∗
S8
∗
10k
20k
22µ
1µ
∗
470P
S5
∗
32
31
30
29
28
LIN
VCC
CIN
ADD
BIN
27
26
0.033µ 470P
∗
2k
1 S4
0.1µ
0.1µ
S7
0.33µ
∗
∗
VCC RR 100µ
1
2
2
∗
∗
0.039µ
I
2 1
1
0.022µ
0.022µ
50k
∗
0.033µ
∗
∗
5V
2
S11
2
S10
1
1
H
5k
∗
V
25
24
23
22
21
20
19
18
17
MSIN BGAIN STT
LT
LB
CT
CB
LOUT
COUT
SCV
DAC
BH3866AS
S2
50k 2
∗
A
RIN
V
Rg: 50
GND AGCADJ LS1
1
2
3
LS2
4
PS
Vref
STB
RT
RB
ROUT
SRV
SLV
SCL
SDA
6
7
8
9
10
11
12
13
14
15
16
5
∗
2
SOUT
S3
18k
4.7k
∗
10µ
15k
5V
2k
G
I2C BUS
serial input
A
∗
VCC
1
∗
4.7µ
∗
0.1µ
470P
100µ
∗
E
∗
F
V
0.033µ
V
0.0056µ
0.1µ
S6
100k
220k
1
2
S9
2
∗
1
1k
D
V
B
2.2µ
Rg: 50
qElements marked with an asterisk
• Carbon-sheathed resistors: ± 1%
• Film capacitors: ± 1%
• Ceramic capacitors: ± 1%
wUnless otherwise noted, the following
attachments should be used.
• Carbon-sheathed resistors: ± 5%
• Film capacitors: ± 20%
•Measurement circuit switch operation
C
THD
BW =
400Hz ~ 30kHz
10k
fOUT
䊊Recommended attachments
2.2µ V
∗
Fig.1
Precautions concerning wiring
qA bare ground should be used for GND.
wThe wiring pattern of the I2C BUS should be separate from that of the
analog unit, to avoid crosstalk.
eParallel positioning of the SCL and SDA lines of the I2C BUS should be
avoided wherever possible. If they are adjacent, they should be shielded.
Slave address
MSB
LSB
1
0
0
0
0
0
1
0
Symbol
I2C
BUS
SW NO.
Selected address / data
1 2 3 4 5 6 7 8 9 10 11 0 0 0 1 0 2 0 3 0 4 0 5 0 6
Measurement
point
Quiescent circuit current
IQ
1 — 1 1 1 1 1 1 — 1 — F F F F F F 2 0 2 0 0 0 0 C
I
Max. output voltage, Rch
VOMR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 0 0 0 C
B
Max. output voltage, Lch
VOML
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 0 0 0 C
B
Max. output voltage, Cch
VOMC
1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 2 0 2 0 0 0 0 C
B
Voltage gain, Rch
GVR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 0 0 0 C
B
Voltage gain, Lch
GVL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 0 0 0 C
B
Voltage gain, Cch
GVC
1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 2 0 2 0 0 0 0 C
B
Parameter
11
Video ICs
BH3866AS
Slave address
MSB
LSB
1
Parameter
0
0
0
0
0
1
0
I 2C
BUS
Measurement
SW
NO.
Symbol
Selected address / data
point
1 2 3 4 5 6 7 8 9 10 11 0 0 0 1 0 2 0 3 0 4 0 5 0 6
Total harmonic distortion, Rch
THDR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 0 0 0 C
C
Total harmonic distortion, Lch
THDL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 0 0 0 C
C
Total harmonic distortion, Cch
THDC
1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 2 0 2 0 0 0 0 C
C
Output noise voltage, Rch
VNOR
1 1 1 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 0 0 0 C
B
Output noise voltage, Lch
VNOL
1 1 1 1 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 0 0 0 C
B
Output noise voltage, Cch
VNOC
1 1 1 1 1 1 1 2 1 1 — 0 0 0 0 F F 2 0 2 0 0 0 0 C
B
Residual noise voltage, Rch
VMNOR
1 1 1 1 1 2 1 1 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
B
Residual noise voltage, Lch
VMNOL
1 1 1 1 1 1 2 1 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
C
Residual noise voltage, Cch
VMNOC
1 1 1 1 1 1 1 2 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
C
Crosstalk, Rch→Lch
CTR-L
1 1 2 1 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 C
B
Crosstalk, Rch→Cch
CTR-C
1 1 2 1 1 1 1 2 1 1 — 0 0 F F F F 2 0 2 0 0 0 0 C
B
Crosstalk, Lch→Rch
CTL-R
1 1 1 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 C
B
Crosstalk, Lch→Cch
CTL-C
1 1 1 2 1 1 1 2 1 1 — F F 0 0 F F 2 0 2 0 0 0 0 C
B
Crosstalk, Cch→Rch
CTC-R
1 1 1 1 2 2 1 1 1 1 — 0 0 F F F F 2 0 2 0 0 0 0 C
B
Crosstalk, Cch→Lch
CTC-L
1 1 1 1 2 1 2 1 1 1 — F F 0 0 F F 2 0 2 0 0 0 0 C
B
Input impedance, Rch
RINR
1 2 2 1 1 1 1 1 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
A
Input impedance, Lch
RINL
1 2 1 2 1 1 1 1 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
A
Input impedance, Cch
RINC
1 2 1 1 2 1 1 1 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
A
Output impedance, Rch
ROUTR
1 1 1 1 1 2 1 1 2 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
D
Output impedance, Lch
ROUTL
1 1 1 1 1 1 2 1 2 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
D
Output impedance, Cch
ROUTC
1 1 1 1 1 1 1 2 2 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
D
Ripple rejection, Rch
RRR
2 1 1 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 0 0 0 C
B
Ripple rejection, Lch
RRL
2 1 1 1 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 0 0 0 C
B
RRC
2 1 1 1 1 1 1 2 1 1 — 0 0 0 0 F F 2 0 2 0 0 0 0 C
B
Muting level, Rch
VMUTER
1 1 2 1 1 2 1 1 1 1 — F F F F F F 2 0 2 0 0 0 0 E
B
Muting level, Lch
VMUTEL
1 1 1 2 1 1 2 1 1 1 — F F F F F F 2 0 2 0 0 0 0 E
B
VMUTEC
Ripple rejection, Cch
1 1 1 1 2 1 1 2 1 1 — F F F F F F 2 0 2 0 0 0 0 E
B
Volume attenuation, Rch
ATTMAXR 1 1 2 1 1 2 1 1 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
B
Volume attenuation, Lch
ATTMAXL 1 1 1 2 1 1 2 1 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
B
Volume attenuation, Cch
ATTMAXC 1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 0 0 2 0 2 0 0 0 0 C
B
1 1 2 2 1 21/ 12/ 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 C
1 1 2 1 2 21/ 1 12/ 1 1 — 0 0 F F F F 2 0 2 0 0 0 0 C
B
Muting level, Cch
Channel balance 1, Rch→Lch
CB1R-L
Channel balance 1, Rch→Cch
CB1R-C
B
1 1 — F F 0 0 F F 2 0 2 0 0 0 0 C
B
1 1 — 3 3 3 3 0 0 2 0 2 0 0 0 0 C
B
1 1 — 0 0 3 3 3 3 2 0 2 0 0 0 0 C
B
1 1 — 3 3 0 0 3 3 2 0 2 0 0 0 0 C
B
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 7 F 2 0 0 0 0 C
B
Channel balance 1, Lch→Cch
CB1L-C
1 1 1 2
Channel balance 2, Rch→Lch
CB2R-L
1 1 2 2
Channel balance 2, Rch→Cch
CB2R-C
1 1 2 1
Channel balance 2, Lch→Cch
CB2L-C
1 1 1 2
Bass boost gain, Rch
VBMAXR
12
2 1 21/ 12/
1 21/ 12/ 1
2 22/ 1 12/
2 1 21/ 12/
Video ICs
BH3866AS
Slave address
MSB
LSB
1
Parameter
0
0
0
0
0
1
0
I 2C
BUS
Selected address / data
SW NO.
Symbol
1 2 3 4 5 6 7 8 9 10 11 0 0 0 1 0 2 0 3 0 4 0 5 0 6
Measurement
point
Bass boost gain, Lch
VBMAXL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 7 F 2 0 0 0 0 C
B
Bass boost gain, Cch
VBMAXC
1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 7 F 2 0 0 0 0 C
B
Bass cut gain, Rch
VBMINR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 0 0 2 0 0 0 0 C
B
Bass cut gain, Lch
VBMINL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 0 0 2 0 0 0 0 C
B
Bass cut gain, Cch
VBMINC
1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 0 0 2 0 0 0 0 C
B
Treble boost gain, Rch
VTMAXR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 7 F 0 0 0 C
B
Treble boost gain, Lch
VTMAXL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 7 F 0 0 0 C
B
Treble boost gain, Cch
VTMAXC
1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 2 0 7 F 0 0 0 C
B
Treble cut gain, Rch
VTMINR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 0 0 0 0 0 C
B
Treble cut gain, Lch
VTMINL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 0 0 0 0 0 C
B
Treble cut gain, Cch
VTMINC
1 1 1 1 2 1 1 2 1 1 — 0 0 0 0 F F 2 0 0 0 0 0 0 C
B
AGC input / output level 1, Rch
VAGC1R
1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
B
AGC input / output level 1, Lch
VAGC1L
1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
B
AGC input / output level 2, Rch
VAGC2R
1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
B
AGC input / output level 2, Lch
VAGC2L
1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
B
AGC input / output level 3, Rch
VAGC3R
1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
B
AGC input / output level 3, Lch
VAGC3L
1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
B
AGC input / output level 4, Rch
VAGC4R
1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
B
AGC input / output level 4, Lch
VAGC4L
1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
B
Total harmonic distortion at AGC ON, Rch THDAGCR 1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
C
Total harmonic distortion at AGC ON, Lch THDAGCL 1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 0 0 0 1
C
Max. surround gain, Rch
VSUMAXR 1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 C F 0 0
B
Max. surround gain, Lch
VSUMAXL 1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 C F 0 0
B
Min. surround gain, Rch
VSUMINR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 C 0 0 0
B
Min. surround gain, Lch
VSUMINL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 C 0 0 0
B
Surround gain at Loop ON, Rch
VLPSUR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 D 6 0 0
B
Surround gain at Loop ON, Lch
VLPSUL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 D 6 0 0
B
Bass Add ON gain, Rch
VBAONR
1 1 2 1 1 2 1 1 1 1 — 0 0 F F 0 0 2 0 2 0 0 0 1 0
B
Bass Add ON gain, Lch
VBAONL
1 1 1 2 1 1 2 1 1 1 — F F 0 0 0 0 2 0 2 0 0 0 1 0
B
Pseudo-stereo gain, Rch
VMONR
1 1 2 2 1 2 1 1 1 1 — F F F F 0 0 2 0 2 0 A F 0 0
B
Pseudo-stereo gain, Lch
VMONL
1 1 2 2 1 1 2 1 1 1 — F F F F 0 0 2 0 2 0 A F 0 0
B
DAC pin operating voltage 1
VDAC1
1 1 1 1 1 1 1 1 1 2 1 0 0 0 0 0 0 2 0 2 0 0 0 2 0
H
DAC pin operating voltage 2
VDAC2
1 1 1 1 1 1 1 1 1 2 2 0 0 0 0 0 0 2 0 2 0 0 0 0 0
H
Suction current at I2C BUS ACK
IACK
1 1 1 1 1 1 1 1 1 1 —
G
SCL and SDA pin input high level
VIHI
1 1 1 1 1 1 1 1 1 1 —
E F
SCL and SDA pin input low level
VILO
1 1 1 1 1 1 1 1 1 1 —
E F
13
Video ICs
BH3866AS
setting methods
•(1)Data
I C BUS timing
2
Parameter
Symbol
Min.
Typ.
Max.
Unit
Clock frequency range
FSCL
0
—
100
kHz
The HIGH period of the clock
tHIGH
4
—
—
µs
THe LOW period of the clock
tLOW
4.7
—
—
µs
SCL rise time
tr
—
—
1
µs
SCL fall time
tf
—
—
0.3
µs
Set-up time for start condition
tsu; STA
4.7
—
—
µs
Hold time for start condition
tHD; STA
4
—
—
µs
Set-up time for stop condition
tsu; STO
4.7
—
—
µs
tBUF
4.7
—
—
µs
tsu; DAT
250
—
—
ns
Time bus must be free before a
new transmission can start
Set-up time DATA
t
t
r
f
SCL
t
t
LOW
HIG
SDA start condition
t
t
SU; ST
HD; ST
SDA stop condition
t
t
SU; ST
BUF
SDA
t
t
SU; DA
HD; DA
t
SU; STA = start code set-up time.
HD; STA = start code hold time.
t
SU; STO = stop code set-up time.
t
t
BUF = bus free time.
SU; DAT = data set-up time.
t
HD; DAT = data hold time.
t
Fig.2 Timing requirements for I2C BUS
The above characteristics are logical values in the IC design, and are not guaranteed
based on the shipping inspection. Any problems that may arise will be handled through
mutual discussion in good faith.
14
Video ICs
BH3866AS
(2) I2C BUS format
MSB
LSB
MSB
LSB
MSB LSB
S
Slave Address
A
Selected Address
A
Data
A
P
1bit
8bit
1bit
8bit
1bit
8bit
1bit
1bit
• S = Start condition (recognition of start bit)
• Slave Address = Recognition of IC. First 7 bits may consist of any data. The last bit must be LOW for writing purposes.
• A = Acknowledge bit (recognition of recognition response)
• Selected Address = Selection of volume, bass, treble, or matrix surround.
• Data = Various items of volume and sound quality data.
• P = Stop condition (recognition of stop bit)
(3) Interface protocol
1) Basic format
S
Slave Address
MSB
A
LSB
Selected Address
MSB
A
LSB
Data
A
P
MSB LSB
2) Auto increment (the selected address is incremented ( + 1) by the number of data)
S
Slave Address
MSB
A
LSB
Selected Address
MSB
A
LSB
Data 1, Data 2, ..., Data N
MSB
A
P
LSB
(Examples) q Data 1 is set as the data of the address specified by the "Selected Address" parameter.
w Data 2 is set as the data of the address specified by the "Selected Address" parameter + 1.
e Data 3 is set as the data of the address specified by the "Selected Address" parameter + N.
3) Configuration which cannot be transmitted (in this case, only selected address 1 is set)
S
Slave Address
MSB
LSB
A
Selected Address 1
MSB
LSB
A
Data
MSB LSB
A
Selected Address 2
MSB
LSB
A
Data
A
P
MSB LSB
CAUTION: If Selected Address 2 was sent as data following the data parameter,
the contents will be recognized as data, and not as Selected Address 2.
15
Video ICs
BH3866AS
(4) BH3866AS slave address
MSB
LSB
A6
A5
A4
A3
A2
A1
A0
R/W
1
0
0
0
0
0
1
0
The above slave address has been registered with Philips Corporation.
(5) Selected addresses
MSB
Set item
Selected address
LSB
A7
A6
A5
A4
A3
A2
A1
A0
0
Lch volume
0
0
0
0
0
0
0
0
1
Rch volume
0
0
0
0
0
0
0
1
2
Cch volume
0
0
0
0
0
0
1
0
3
Tone (bass)
0
0
0
0
0
0
1
1
4
Tone (treble)
0
0
0
0
0
1
0
0
5
Surround
0
0
0
0
0
1
0
1
6
AGC
0
0
0
0
0
1
1
0
When sending continuous data, the auto increment function moves through the selected addresses in the following
sequence.
0
16
1
2
3
4
5
6
Video ICs
BH3866AS
(6) Data
Selected address
MSB
Set item
A7
Data
A6
A5
LSB
A3
A4
00H
Lch volume
Lch Vol
01H
Rch volume
Rch Vol
02H
Cch volume
Cch Vol
03H
Tone (bass)
04H
Tone (treble)
05H
Surround
06H
AGC
∗
∗
A2
A1
A0
MUTE
AGC
L / R / C Bass
L / R / C Treble
SON
SSTE
SMON
LOOP
∗
∗
DAC
BASS
Selected
address
Surround effect
CSEL
CON
Contents
Volume:
00H
all H: ATT 0dB
02H
all L: – ∞ (95dB)
1.0dB step level
03H
Bass / Tre:
all H: Max. (FULL BOOST)
04H
all L: Min. (FULL CUT)
Surr effect: (Broad gain adjustment)
all H: Max. (15dB)
all L: Min. (0dB) 1dB step
05H
06H
· LOOP
H: on / L: off
Switch that varies the stage of the phase shift
· SSTE
H: on / L: off
ON / OFF switch for (L – R) signal (stereo surround)
· SMON
H: on / L: off
ON / OFF switch for (L + R) signal (pseudo-stereo)
· SON
H: on / L: off
ON / OFF switch for surround effect
· Mute
H: on / L: off
Muting switch
· AGC
H: on / L: off
AGC ON / OFF switch
· BASS
H: mix on / L: mix off
Low-pitch range mixing switch
· CSEL
H: C on / L: C off
Selector switch for CIN input of COUT output or (L + R) signal
· CON
H: H out / L: L off
Switch that selects whether or not COUT is output
· DAC
H: H out / L: L out
0V or 5V output switch
17
Video ICs
BH3866AS
(7) Volume and amount of attenuation (reference examples)
ATT
(dB)
DATA
(HEX)
ATT
(dB)
DATA
(HEX)
ATT
(dB)
DATA
(HEX)
0
FF
– 19
4A
– 56
16
–1
C4
– 20
48
– 58
15
–2
AD
– 22
43
– 60
14
–3
9F
– 24
3E
– 62
13
–4
93
– 26
3A
– 63
12
–5
8A
– 28
36
– 67
10
–6
82
– 30
33
– 68
0F
–7
7B
– 32
30
– 70
0E
–8
75
– 34
2D
– 73
0D
–9
6F
– 36
2A
– 76
0C
– 10
6A
– 38
27
– 78
0B
– 11
66
– 40
25
– 84
09
– 12
61
– 42
23
–∞
00
– 13
5D
– 44
21
– 14
5A
– 46
1F
– 15
56
– 48
1D
– 16
53
– 50
1B
– 17
50
– 52
19
– 18
4D
– 54
18
CAUTION: The settings in the above table are reference values. When using them,
make sure values are confirmed carefully before being set.
18
Video ICs
BH3866AS
(8) Bass and treble gain settings (reference examples)
Step
I2 C
DATA
(HEX)
Bass
Gain
(dB)
Treble
Gain
(dB)
Step
I2C
DATA
(HEX)
Bass
Gain
(dB)
Treble
Gain
(dB)
15
7F
15.9
12.0
–1
18
– 1.5
– 0.8
14
36
15.2
11.2
–2
17
– 2.4
– 1.3
13
34
14.3
10.4
–3
16
– 3.4
– 2.0
12
32
13.0
9.2
–4
15
– 4.6
– 2.8
11
31
12.2
8.5
–5
14
– 5.8
– 3.7
10
30
11.3
7.6
–6
13
– 7.1
– 4.7
9
2F
10.4
6.8
–7
12
– 8.3
– 5.7
8
2E
9.3
5.8
–8
11
– 9.5
– 6.6
7
2D
8.0
4.8
–9
10
– 10.6
– 7.5
6
2C
6.7
3.8
– 10
0F
– 11.5
– 8.3
5
2B
5.3
2.9
– 11
0E
– 12.3
– 9.0
4
2A
4.0
2.0
– 12
0D
– 13.0
– 9.6
3
29
2.9
1.4
– 13
0B
– 14.2
– 10.6
2
28
1.8
0.8
– 14
09
– 15.0
– 11.3
1
27
1.1
0.4
– 15
00
– 15.6
– 11.8
0
20
0.0
0.0
Table 5: Tone microcomputer data (the gain value is given as a guide).
CAUTION:
(1) The gain values given in the table above for treble and bass data are the data
when the filter constant is specified such that the peak and bottom values on the
frequency characteristic diagram will be at the maximum and minimum gain levels.
(2) The settings in the above table are reference values. When using them, make
sure values are confirmed carefully before being set.
19
Video ICs
BH3866AS
•Application example
0.022µ
100k
10µ
–
+
100k
VCC
100k
0.012µ
10µ
10µ
10µ
10µ
0.039µ
10k
47k
4.7µ
0.022µ
470P
0.033µ
470P
10µ
0.033µ
10µ
4.7µ
2k
10k
100µ
10µ
26
50k
MIX ON
CSEL
L+R
OFF
SMON
AGC
L+S
10k
OFF
Surr effect LFP
PHASE
ON 10k
Tone
(bass / treble)
17
DAC
+
–
Tone
(bass / treble)
+
–
10k
OFF
ON
–
AMP
SHIFT
10k
SON
R-S
VCA
–
18
SCV
+
L-R
SSTE
50k
19
COUT
10k
ON
L+R
20
LOUT
10k
VCA
A
G
C
21
CB
–
10k
–
22
CT
Volume
+
OFF
+
–
50k
+
ON
50k
23
LB
MIX OFF
BASS
–
+
CIN
–
50k
24
LT
OFF
+
Volume
+
25
MSIN BGAIN 10k STT
Volume
27
BIN
Volume
ADD
CIN
Volume
VCC
28
Increment
VCC
29
Volume
LIN
30
Increment
31
32
Tone
(bass / treble)
–
+
LOOP
ON
VCC
I2C BUS interface
1
2 VCC
–
50k
+
50k
RIN
GND AGCADJ
1
2
3
LS1
LS2
4
PS
SOUT
5
6
SCL
Vref
7
STB
8
RT
9
RB
10
ROUT
11
SRV
12
SLV
13
SCL
14
SDA
SDA
15
16
0.0056µ
VCC
10µ
18k
15k
10µ
4.7µ
0.1µ
100k
100µ
4.7µ
470P
0.033µ
10µ
4.7µ
I2C BUS
serial
control
4.7µ
220k 4.7k
Units Resistance: Ω
Capacitance: F
Fig.3
notes
•(1)Operation
Operating power supply voltage range
Within the operating power supply voltage range, operation of the basic circuit functions is guaranteed for the
ambient operating temperature, but when using the
product, be sure that settings for constants and elements, voltage settings, and temperature settings are
carefully confirmed.
(2) Operating temperature
Within the recommended operating voltage range,
operation of the circuit functions is guaranteed for the
operating temperature range. Be aware that power dissipation conditions are related to the temperature. Also,
except for conditions determined by electrical characteristics within this range, the rated values for electrical
characteristics cannot be guaranteed, but the essential
functions are maintained.
20
(3) Application example
We guarantee the application circuit design, but recommend that you thoroughly check its characteristics in
actual use. If you change any of the external component values, check both the static and transient characteristics of the circuit, and allow sufficient margin in
your selections to take into account variations in the
components and ICs.
Note that Rohm has not fully investigated patent rights
regarding this product.
Video ICs
BH3866AS
(4) Bass filter for tone control
VCC
· Determining cutoff frequencies
RB, LB, and CB pins
1
1
=
2πC1 × 30k
2πC1R1
At a frequency of fC1, the LPF will be –3dB.
+
fC1 =
–
R1
30k
C1
25k
5k
1
2 VCC
1
2 VCC
GND
Fig.4
(5) Treble filter for tone control
VCC
HPF configuration
+
RT, LT, and CT pins
+
+
–
–
LPF
R2
30k
C2
1
2 VCC
fC2 =
GND
1
1
=
2πC2 × 30k
2πC2R2
Fig.5
(6) Setting the AGC level
The AGC level is set by the voltage divider between
voltage VCC and GND. A gain of 0dB voltage should be
used in the range of 100mVrms to 400mVrms.
10
VCC = 9V
LR same-phase input
500
1
Gain 0dB voltage (Vrms)
OUTPUT VOLTAGE (Vrms)
Gain 0dB voltage
600
VCC = 9V
AGCADJ voltage = 4.1V
LR common-mode input
AGC off
0.1
AGC on
0.01
400
300
200
100
0.001
0.001
0
0.01
0.1
1
10
2
2.5
3
3.5
4
4.5
5
INPUT VOLTAGE (Vrms)
AGCADJ VOLTAGE (V) [3pin]
Fig. 6 (Reference data)
AGC characteristic
Fig. 7 (Reference data) Relation
between AGCADJ voltage
and gain 0dB voltage
21
Video ICs
BH3866AS
(7) Determining the external LS1 (pin 4) and LS2 (pin 5)
for the AGC
(8) Attachment of external SOUT (pin 6) of surround
section L.P.F.
+
SOUT
10k
+
6
–
–
R1
0.0056µ
C
R01
430
R2
4.7k
4
LS1
Amplifier which determines
level of surround effect
C1
Fig.10
RL1
10µ
100k
Fig.8 Suppressing phase detecting circuit
• Attack time: R01 × C1
• Recovery time: RL1 × C1
f1 =
1
2πCR2
1
2πC (R1 + R2)
R2
A1 =
R1 + R2
f2 =
A2 = 1
R02
20k
A2
Gain
(dB)
5
A1
LS2
C2
4.7µ
RL2
f2
f1
Frequency (Hz)
220k
Fig.11
Fig.9 Amplifying phase detection circuit
• Attack time: R02 × C2
• Recovery time: RL2 × C2
(9) External PS (pin 7) of the phase shifter
18k
R2 18k
The attack and recovery times should be determined
based on the internal resistors in the IC and on the
external capacitor and resistor. The internal resistors
are R01 = 430Ω and R02 = 20kΩ (Typ.). Reducing the
constant of the C2 capacitor of LS2 shifts the point
where amplification begins in the direction of a lower
input voltage. The distortion ratio changes as well, in the
direction of worse distortion. Reducing the constant of
the C 1 capacitor of LS1 causes worse distortion.
Increasing the resistance value of RL 1 causes the
amount of suppression to decrease.
22
R3
–
+
R1 18k
7
C1
0.1µ
Fig.12
The resistance in the IC is 18kΩ (Typ.).
φ = –2tan-1 (2πfR1C1)
Video ICs
BH3866AS
(10) Surround and pseudo-stereo effects
1) Surround
∆t: Time of delay caused by phase shifter
P: Amount attenuated at phase shifter stage
E: Amount of surround effect
Lch
+
32
+
20
LOUT = L + ∆t (L – R) EP
12
ROUT = R + ∆t (R – L) EP
+
L–R
∆t × P
×E
Phase shifter
Effect adjustment
LPF
–
Rch
1
+
+
Fig.13
2) Pseudo-stereo effect
Lch
+
32
L+R
BPF
∆t × P
×E
Phase shifter
Effect adjustment
+
+
20
LOUT = L + ∆t (L + R) EP
12
ROUT = R – ∆t (L + R) EP
LPF
Configured externally
–
Rch
1
+
+
Fig.14
The internal blocks in the IC for the surround and pseudo-stereo effects are configured as shown above. The
feeling of the surround location and the stereo feeling of
the pseudo-stereo effect can be changed by varying the
amount of the effect. Also, the loop switch can be turned
on to create a pseudo-increase in the number of phase
shifter stages. Raising the gain of the effect level with
the loop switch on causes instability, however, so the
level of the effects should be kept at around 6dB or
below. In order to prevent a popping sound when switching between the surround and pseudo-stereo effects, the
switch on the stereo surround side of the SSTE should
be left in the ON position.
(12) Pin 17 (DAC) output
Setting the DAC command for the I2C BUS to HIGH
enables 5V output, and setting it to LOW enables 0V
output.
(13) BASS command
Creating an external LPF with the signals (L + R) output
from ADD (pin 29) and inputting those signals to BIN
(pin 28) enables configuration of a low-pitch amplification circuit. This switch serves as the I2C BUS bass command. The gain for the amplifier can be set through the
external resistance, using BGAIN (pin 26).
BIN
+
28
–
(11) The level of the surround effect
The level of the surround effect can be varied between 0
and 15dB, using I2C BUS data. Please be aware, however, that this gain is not the total gain between input
and output. In precise terms, it specifies the effect level
control range of the surround signal for the SOUT pin.
(With single-side input and the stereo / surround effects:
VCC = 9V, f = 1kHz, VIN = 100mVrms, Ta = 25°C.)
BASS SW
50k
10k
1
2 VCC
26
R1
10µ
Fig.15
Gain = 20log 10k + R1
R1
23
Video ICs
BH3866AS
(14) The necessity for Cch and the application
If there are only a left and right speaker, moving slightly
to the left or right of the television set causes a difference in the sound paths, and a characteristic trough
from 500Hz to 2kHz is created by the ensuing interference, producing a muffled or contained sound. Also, listeners positioned to the left or right hear the sounds from
the closest speaker causing the positions of the image
and sound to not match. Due to their setup, low-pitched
sounds are produced more easily from the left and right
speakers. However, in front of the speakers, because
the placement of the speakers directs the sound in a
cone-shaped direction, traveling along the sides of the
television, a "port" effect results and the sound becomes
muffled. To solve this problem, a center speaker is provided, and assuming this speaker is attached directly to
the center grille, the orientation and clarity are improved
significantly. Also, as a center channel application, this
can be used to adjust the microphone mixing level,
enabling use of the set as a karaoke set.
(15) Noise when the step is switched
In the application circuit example, using the SRV, SLV,
SCV, STB, and STT pins as an example, constants are
provided for each. These constants change depending
on the signal level setting, the mounting wiring pattern,
and other factors. Careful consideration should be given
to the constants before they are determined. An internal
equivalent circuit is shown below. (A primary integration
circuit is set, so that changes are implemented slowly.)
R
Each pin
+
–
C
(External)
Fig.16
R value (kΩ)
SRV, SLV, SCV, STB, STT
30
(16) Level settings for volume and tone
In this databook, values are noted for the control serial
data in relation to the amount of attenuation or gain, as
reference values. Since the internal D / A converter is
configured on the R-2R system, data exists in locations
where there are no continuous changes between one
item of data and the next. This can be used where
detailed settings are required. However, the volume
must be set within eight bits (256 steps), and the tone
24
within seven bits (64 + 1 step).
(17) I2C BUS control
High-frequency digital signals are input to the SCL and
SDA pins, so the wiring and wiring patterns must be
arranged in such a way that they do not interfere with
the analog signal system line.
(18) Power On Reset
When the power supply is turned on, an internal circuit
carries out an initialization within the IC. When the power
supply is turned on, the volume levels of the left, right,
and center channels are set to – ∞, and the DAC output
(pin 17) is set to 0V. Once it has been turned on, if the
power supply is turned off and then immediately turned
on again, if there is any residual load on the capacitor,
there may be cases when the status described above
does not occur. If this happens, operation should be carried out with the muting function on, until an I2C BUS
command is transmitted.
(19) Vref (pin 8) capacitor
A capacitance of 100µF is recommended for the power
supply filter attached to VREF. If this capacitance is set
too low, the minimum attenuation level of the volume
deteriorates. Crosstalk also tends to deteriorate. The IC
contains internal pre-charge and discharge circuits for
the capacitor attached to Vref.
(20) Excessive input
Steps have been taken with this product to avoid a situation in which, if a signal is input which exceeds the maximum input voltage for the LIN, RIN, and CIN pins, a
rebound waveform is produced even if hard clipping of
the output signal is implemented. Consequently, there is
no need to worry that the listener will hear distorted
sound because of a rebound waveform.
(21) Request concerning the fundamental design
Due to its pin layout, it is difficult to remove crosstalk
from the left channel to the center channel in this IC.
This is because the output signal at LOUT (pin 20) overlaps the capacitance coupling of CB (pin 21) and CT (pin
22). This should be given adequate consideration in the
fundamental design of the set, when the pattern is laid
out. The following illustration shows an example of countermeasures.
LOUT
CB
CT
19
20
21
C
10µ
Lch output
+
C
0.033µ
C
470p
Video ICs
BH3866AS
(22) Relation with the BH3865S
The BH3866AS and BH3865S are pin compatible, and
share some of the same selected address and data
parameters for the I2C BUS. Therefore, the same substrates and software can be shared at the product planning stage.
•Electrical characteristic curves
45
40
35
30
25
20
15
10
5
1
0.5
0.1
0.05
0.01
0
5
6
7
8
9
VCC = 9V
f = 1kHz
100m
1
INPUT VOLTAGE: VIN (Vrms)
POWER SUPPLY VOLTAGE: VCC (V)
Fig. 18 Total harmonic distortion
vs. input voltage
Fig. 17 Quiescent current vs.
power supply voltage
VCC = 9V
VIN = 100mVrms
–4
–8
During boost
– 12
– 16
– 20
– 24
– 28
During cut
– 32
– 36
10m
10
+0
OUTPUT VOLTAGE: VOUT (dBV)
TOTAL HARMONIC DISTORTION: THD (%)
QUIESCENT CURRENT: IQ (mA)
50
– 40
10
100
1k
10k
100k
FREQUENCY: f (Hz)
Fig. 19 Output gain vs. frequency
•External dimensions (Units: mm)
28.0 ± 0.3
17
8.4 ± 0.3
32
16
0.51Min.
3.2 ± 0.2 4.7 ± 0.3
1
10.16
0.3 ± 0.1
0.5 ± 0.1 0° ~ 15°
1.778
SDIP32
25
Similar pages