MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM PRELIMINARY Some of contents are described for general products and are subject to change w ithout notice. DESCRIPTION M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M 2V64S20DTP, M 2V64S30DTP and M 2V64S40DTP achieve very high speed data rate up to 133MHz for -6, and are suitable for main memory or graphic memory in computer systems. FEATURES M2V64S20/30/40DTP ITEM -6 -7 -8 tCLK Clock Cycle T ime (Min.) 7.5ns 10ns tRAS (Min.) (Min.) 45ns 50ns 10ns 50ns tRCD Active to Precharge Command Period Row to Column Delay 20ns 20ns 20ns tAC Access Time from CLK (Max.) (CL=3) Ref /Active Command Period (Min.) 6ns 70ns 6ns tRC 5.4ns 67.5ns 70ns Icc1 Icc6 Operation Current Self Refresh Current (Max.) (Single Bank) V64S20D 75mA 70mA 70mA V64S30D 75mA 70mA 70mA V64S40D 85mA 80mA 80mA 1mA 1mA 1mA (Max.) - Single 3.3v±0.3V power supply - Max. Clock frequency -6:133MHz<3-3-3>, -7:100MHz<2-2-2>, -8:100MHz<3-2-2> - Fully Synchronous operation referenced to clock rising edge - 4 bank operation controlled by BA0 & BA1 (Bank Address) - /CAS latency- 2 and 3 (programmable) - Burst length- 1, 2, 4, 8 and full page (programmable) - Burst type- sequential and interleave (programmable) - Byte Control- DQM L and DQMU for M2V64S40DTP - Random column access - Auto p recharge and All bank precharge controlled by A10 - Auto refresh and Self refresh - 4096 refresh cycles every 64ms - LVTTL Interface - 400-mil, 54-pin Thin Small Outline Package (TSOP II) with 0.8mm lead pitch MITSUBISHI ELECTRIC 1 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM PIN CONFIGURATION (TOP VIEW) M2V64S20DTP M2V64S30DTP M2V64S40DTP PIN CONFIGURATION (TOP VIEW) Vdd NC VddQ NC DQ0 VssQ NC NC VddQ NC DQ1 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ NC DQ1 VssQ NC DQ2 VddQ NC DQ3 VssQ NC Vdd NC /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd Vdd DQ0 VddQ DQ1 DQ2 VssQ DQ3 DQ4 VddQ DQ5 DQ6 VssQ DQ7 Vdd DQML /WE /CAS /RAS /CS BA0(A13) BA1(A12) A10(AP) A0 A1 A2 A3 Vdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 Vss DQ15 VssQ DQ14 DQ13 VddQ DQ12 DQ11 VssQ DQ10 DQ9 VddQ DQ8 Vss NC DQMU CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss DQ7 VssQ NC DQ6 VddQ NC DQ5 VssQ NC DQ4 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss Vss NC VssQ NC DQ3 VddQ NC NC VssQ NC DQ2 VddQ NC Vss NC DQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 Vss CLK : Master Clock DQM : Output Disable/ Write Mask CKE : Clock Enable A0-11 : Address Input /CS : Chip Select /RAS : Row Address Strobe BA0,1 : Bank Address /CAS : Column Address Strobe Vdd : Power Supply /WE : Write Enable VddQ : Power Supply for Output DQ0-15 : Data I/O Vss : Ground VssQ : Ground for Output MITSUBISHI ELECTRIC 2 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM BLOCK DIAGRAM DQ0-7 I/O Buffer Memory Array Memory Array Memory Array Memory Array 4096 x512 x8 Cell Array 4096 x512 x8 Cell Array 4096 x512 x8 Cell Array 4096 x512 x8 Cell Array Bank #0 Bank #1 Bank #2 Bank #3 Mode Register Control Circuitry Address Buffer Control Signal Buffer Clock Buffer A0-11 CLK BA0,1 /CS CKE /RAS /CAS /WE DQM Note : This figure shows the M2V64S30DTP. The M2V64S20DTP configration is 4096x1024x4 of cell array and DQ 0-3. The M2V64S40DTP configration is 4096x256x16 of cell array and DQ 0-15. Type Designation Code These rules are only applied to the Synchronous DRAM family. M2 V 64 S 3 0 D TP -8 Access Item -6 : 7.5ns (PC133 3-3-3), -7 : 10ns (PC100 2-2-2), -8 : 10ns (PC100 3-2-2) P ackage T ype T P : T S O P (II) P rocess Generation D : 5th gen. Function R eserved for Future Use Organization 2 : x4, 3 : x8, 4 : x16 Synchronous DRAM Density 64 : 64Mbit Interface V : LVT T L Mitsubishi DRAM MITSUBISHI ELECTRIC 3 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM PIN FUNCTION Input Master Clock: All other inputs are referenced to the rising edge of CLK. CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / selfrefresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. /CS Input Chip Select: When /CS is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. Input A0-11 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-11. The Column Address is specified by A0-9 (x4) / A0-8 (x8) / A0-7 (x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. Input Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. CLK A0-11 BA0,1 DQ0-3(x4), DQ0-7(x8), DQ0-15(x16) Data In and Data out are referenced to the rising edge of CLK. Input / Output Din Mask and Output Disable: When DQM(U, L) is high in burst write, Din for the current cycle is masked. When DQM(U, L) is high in burst read, Dout is disabled at the next but one cycle. DQM(x4,x8), DQM(U, L)(x16) Input Vdd, Vss Power Supply Power Supply for the memory array and peripheral circuitry. VddQ, VssQ Power Supply VddQ and VssQ are supplied to the Output Buffers only. MITSUBISHI ELECTRIC 4 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM BASIC FUNCTIONS The M 2V64S20, 30 and 40DTP provides basic functions, bank (row) activate, burst read and write, bank (row) precharge, and auto and self refresh. Each command is defined by control signals of /RAS, /CAS and /WE at CLK rising edge. In addition to 3 signals, /CS ,CKE and A10 are used as chip select, refresh option, and precharge option, respectively. To know the detailed definition of commands, please see the command truth table. CLK /CS Chip Select : L=select, H=deselect /RAS Command /CAS Command /WE Command CKE Ref resh Option @ref resh command A10 Precharge Option @precharge or read/write command def ine basic commands Activate (ACT) [/RAS =L, /CAS =/WE =H] ACT command activates a row in an idle bank indicated by BA. Read (READ) [/RAS =H, /CAS =L, /WE =H] READ command starts burst read from the active bank indicated by BA. First output data appears after /CAS latency. When A10 =H at this command, the bank is deactivated after the burst read (autoprecharge,READA) Write (WRITE) [/RAS =H, /CAS =/WE =L] WRITE command starts burst write to the active bank indicated by BA. Total data length to be written is set by burst length. When A10 =H at this command, the bank is deactivated after the burst write (auto-p recharge, WRITEA). Precharge (PRE) [/RAS =L, /CAS =H, /WE =L] PRE command deactivates the active bank indicated by BA. This command also terminates burst read /write operation. When A10 =H at this command, all banks are deactivated (precharge all, PREA). Auto-Refresh (REFA) [/RAS =/CAS =L, /WE =CKE =H] REFA command starts auto-refresh cycle. Refresh address are generated internally. After this command, the banks are precharged automatically. MITSUBISHI ELECTRIC 5 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM COMMAND TRUTH TABLE CKE CKE n-1 n COMMAND MNEMONIC Deselect DESEL H X H X X X X X X X No Operation NOP H X L H H H X X X X Row Address Entry & Bank Activate ACT H X L L H H V V V V Single Bank Precharge PRE H X L L H L V X L X Precharge All Banks PREA H X L L H L X X H X WRITE H X L H L L V V L V WRITEA H X L H L L V V H V Column Address Entry & Read READ H X L H L H V V L V Column Address Entry & Read with Auto-Precharge READA H X L H L H V V H V Auto-Refresh REFA H H L L L H X X X X Self-Refresh Entry REFS H L L L L H X X X X L H H X X X X X X X L H L H H H X X X X Column Address Entry & Write Column Address Entry & Write with Auto-Precharge Self-Refresh Exit /CS /RAS /CAS /WE BA0,1 A11 A10 A0-9 REFSX Burst Terminate TBST H X L H H L X X X X Mode Register Set MRS H X L L L L L L L V*1 H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number NOTE: 1. A7-A9 =0, A0-A6 =Mode Address MITSUBISHI ELECTRIC 6 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM FUNCTION TRUTH TABLE Current State /CS IDLE H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ & WRITE ILLEGAL*2 L L H H BA, RA ACT L L H L BA, A10 PRE & PREA L L L H X REFA Auto-Refresh*5 L L L L Op-Code, Mode-Add MRS Mode Register Set*5 H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST NOP L H L H BA, CA, A10 L H L L L L H L L L L ROW ACT IVE /RAS /CAS /WE Address Command Action Bank Active, Latch RA NOP*4 READ & READA WRITE & BA, CA, A10 WRITEA Begin Read, Latch CA, Determine Auto-Precharge H BA, RA ACT Bank Active / ILLEGAL*2 H L BA, A10 PRE & PREA Precharge / Precharge All L L H X REFA ILLEGAL L L L Op-Code, Mode-Add MRS ILLEGAL Begin Write, Latch CA, Determine Auto-Precharge MITSUBISHI ELECTRIC 7 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM FUNCTION TRUTH TABLE (continued) Current State /CS READ H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST L H L H BA, CA, A10 READ /READA L H L L BA, CA, A10 WRITE & Terminate Burst, Latch CA, Begin WRITEA Write, Determine Auto-Precharge*3 L L H H BA, RA ACT L L H L BA, A10 PRE & PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE & PREA Terminate Burst, Precharge L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE /RAS /CAS /WE Address Command Action READ & READA WRITE & WRITEA Terminate Burst Terminate Burst, Latch CA, Begin New Read, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 Terminate Burst Terminate Burst, Latch CA, Begin Read, Determine Auto-Precharge*3 Terminate Burst, Latch CA,Begin Write, Determine Auto-Precharge*3 Bank Active / ILLEGAL*2 MITSUBISHI ELECTRIC 8 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM FUNCTION TRUTH TABLE (continued) Current State /CS READ with AUTO PRECHARGE H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST ILLEGAL L H L H BA, CA, A10 READ & READA ILLEGAL L H L L BA, CA, A10 WRITE & WRITEA ILLEGAL L L H H BA, RA ACT L L H L BA, A10 PRE & PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Continue Burst to END) L H H H X NOP NOP (Continue Burst to END) L H H L X TBST L H L H BA, CA, A10 L H L L BA, CA, A10 L L H H BA, RA ACT L L H L BA, A10 PRE & PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL WRITE with AUTO PRECHARGE /RAS /CAS /WE Address Command Action READ & READA WRITE & WRITEA Bank Active / ILLEGAL*2 ILLEGAL ILLEGAL ILLEGAL Bank Active / ILLEGAL*2 MITSUBISHI ELECTRIC 9 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM FUNCTION TRUTH TABLE (continued) Current State /CS PRE CHARGING H X X X X DESEL NOP (Idle after tRP) L H H H X NOP NOP (Idle after tRP) L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ & WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE & PREA NOP*4 (Idle after tRP) L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Row Active after tRCD) L H H H X NOP NOP (Row Active after tRCD) L H H L X TBST L H L X BA, CA, A10 READ & ILLEGAL*2 WRITE L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE & PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ROW ACTIVATING /RAS /CAS /WE Address Command Action ILLEGAL*2 MITSUBISHI ELECTRIC 10 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM FUNCTION TRUTH TABLE (continued) Current State /CS WRITE RECOVERING H X X X X DESEL NOP L H H H X NOP NOP L H H L X TBST ILLEGAL*2 L H L X BA, CA, A10 READ & WRITE ILLEGAL*2 L L H H BA, RA ACT ILLEGAL*2 L L H L BA, A10 PRE & PREA ILLEGAL*2 L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL H X X X X DESEL NOP (Idle after tRC) L H H H X NOP NOP (Idle after tRC) L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ & WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE & PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL REFRESHING /RAS /CAS /WE Address Command Action MITSUBISHI ELECTRIC 11 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM FUNCTION TRUTH TABLE (continued) Current State /CS /RAS /CAS /WE Address Command Action MODE REGISTER SETTING H X X X X DESEL NOP (Idle after tRSC) L H H H X NOP NOP (Idle after tRSC) L H H L X TBST ILLEGAL L H L X BA, CA, A10 READ & WRITE ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE & PREA ILLEGAL L L L H X REFA ILLEGAL L L L L Op-Code, Mode-Add MRS ILLEGAL ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care BA=Bank Address, RA=Row Address, CA=Column Address, NOP=No OPeration NOTES: 1. All entries assume that CKE was High during the preceding clock cycle and the current clock cycle. 2. ILLEGAL to bank in specified state; function may be legal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA. 5. ILLEGAL if any bank is not idle. ILLEGAL = Device operation and/or data-integrity are not guaranteed. MITSUBISHI ELECTRIC 12 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM FUNCTION TRUTH TABLE for CKE Current State SELFREFRESH*1 POWER DOWN ALL BANKS IDLE*2 ANY STATE other than listed above CKE n-1 CKE n /CS H X X X X X X INVALID L H H X X X X Exit Self-Refresh (Idle after tRC) L H L H H H X Exit Self-Refresh (Idle after tRC) L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self-Refresh) H X X X X X X INVALID L H X X X X X Exit Power Down to Idle L L X X X X X NOP (Maintain Power Down) H H X X X X X Refer to Function Truth Table H L L L L H X Enter Self-Refresh H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L X X X ILLEGAL L X X X X X X Refer to Current State =Power Down H H X X X X X Refer to Function Truth Table H L X X X X X Begin CLK Suspend at Next Cycle*3 L H X X X X X Exit CLK Suspend at Next Cycle*3 L L X X X X X Maintain CLK Suspend /RAS /CAS /WE Add Action ABBREVIATIONS: H=High Level, L=Low Level, X=Don't Care NOTES: 1. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum setup time must be satisfied before any command other than EXIT. 2. Power-Down and Self-Refresh can be entered only from the All Banks Idle State. 3. Must be legal command. MITSUBISHI ELECTRIC 13 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM SIMPLIFIED STATE DIAGRAM SELF REFRESH REFS REFSX MODE REGISTER SET MRS REFA IDLE AUTO REFRESH CKEL CLK SUSPEND CKEH ACT POWER DOWN CKEL CKEH ROW ACTIVE TERM TERM WRITE WRITE SUSPEND READ WRITEA CKEL READA READ WRITE WRITE CKEH CKEL READ CKEH READA WRITEA WRITEA WRITEA SUSPEND POWER APPLIED READ SUSPEND READA CKEL CKEL WRITEA PRE CKEH CKEH POWER ON READA PRE PRE READA SUSPEND PRE PRE CHARGE Automatic Sequence Command Sequence MITSUBISHI ELECTRIC 14 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM POWER ON SEQUENCE Before starting normal operation, the following power on sequence is necessary to prevent a SDRAM from damaged or malfunctioning. 1. Apply power and start clock. Attempt to maintain CKE high, DQM high and NOP condition at the inputs. 2. M aintain stable power, stable clock, and NOP input conditions for a minimum of 200µs. 3. Issue precharge commands for all banks. (PRE or PREA) 4. After all banks become idle state (after tRP), issue 8 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. After these sequence, the SDRAM is idle state and ready for normal operation. MODE REGISTER CLK Burst Length, Burst Type, /CAS Latency and Write M ode can be programmed by setting the mode register (MRS). The mode register stores these data until the next MRS command, which may be issued when both banks are in idle state. After tRSC from a MRS command, the SDRAM is ready for new command. /CS /RAS /CAS /WE BA0,1 A11-A0 BA0 BA1 A11 A10 A9 0 0 0 0 Write Mode LATENCY MODE CL 000 001 010 011 100 101 110 111 WM 0 1 A8 A7 0 0 A6 A5 A4 LTMODE A3 A2 BT A1 A0 BL Burst Write Single Write /CAS LATENCY R R 2 3 R R R R BL BURST LENGTH BURST TYPE V 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 BT=0 1 2 4 8 R R R Full Page BT=1 1 2 4 8 R R R R SEQUENTIAL INTERLEAVED R: Reserved for Future Use MITSUBISHI ELECTRIC 15 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM CLK Command Read Write Y Y Address Q0 DQ Q1 Q2 Q3 D0 D1 D2 D3 /CAS Latency CL= 3 BL= 4 Burst Length Burst Length Burst Type Initial Address BL Column Addressing A2 A1 A0 Sequential Interleaved 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 8 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 4 - 1 0 2 3 0 1 2 3 0 1 - 1 1 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 1 0 1 0 - - 1 2 MITSUBISHI ELECTRIC 16 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM OPERATIONAL DESCRIPTION BANK ACTIVATE One of four banks is activated by an ACT command. An bank is selected by BA0-1. A row is selected by A0-11. M ultiple banks can be active state concurrently by issuing multiple ACT commands. M inimum activation interval between one bank and another bank is tRRD. PRECHARGE An open bank is deactivated by a PRE command. A bank to be deactivated is designated by BA0-1. When multiple banks are active, a precharge all command (PREA, PRE + A10=H) deactivates all of open banks at the same time. BA0-1 are "Don't Care" in this case. M inimum delay of an ACT command after a PRE command to the same bank is tRP. Bank Activation and Precharge All (BL=4, CL=2) CLK Command ACT ACT tRRD READ tRCD ACT tRP A0-9,11 Xa Xb Yb A10 Xa Xb 0 BA0-1 00 01 01 DQ PRE Xa Xa 1 00 Qb0 Qb1 Qb2 Qb3 Precharge All READ A READ command can be issued to any active bank. The start address is specified by A0-9(x4), A0-8 (x8), A0-7 (x16). 1st output data is available after the /CAS Latency from the READ. The consecutive data length is defined by the Burst Length. The address sequence of the burst data is defined by the Burst Type. M inimum delay of a READ command after an ACT command to the same bank is tRCD. When A10 is high at a READ command, auto-precharge (READA) is performed. Any command (READ, WRITE, PRE, ACT,TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at the BL after READA. The next ACT command can be issued after (BL + tRP) from the previous READA. In any case, tRCD+BL > tRASmin must be met. = MITSUBISHI ELECTRIC 17 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Multi Bank Interleaving Read (CL=2, BL=4) CLK Command ACT READ ACT tRCD READ PRE ACT tRCD tRP A0-9,11 Xa Ya Xb Yb A10 Xa 0 Xb 0 0 Xa BA0-1 00 00 01 01 00 00 Qa2 Qa3 DQ Qa0 Qa1 Xa Qb0 Qb1 Qb2 Qb3 Read with Auto-Precharge (CL=2, BL=4) CLK Command ACT READ tRCD ACT BL tRP A0-9,11 Xa Ya Xa A10 Xa 1 Xa BA0-1 00 00 00 DQ Qa0 Qa1 Qa2 Qa3 internal precharge starts Auto-Precharge Timing (READ, BL=4) CLK Command ACT READ tRCD DQ CL=2 DQ CL=3 ACT BL Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 internal precharge starts MITSUBISHI ELECTRIC 18 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM WRITE A WRITE command can be issued to any active bank.The start address is specified by A0-9(x4), A0-8 (x8), A0-7 (x16). 1st input data is set at the same cycle as the WRITE. The consecutive data length to be written is defined by the Burst Length. The address sequence of burst data is defined by the Burst Type. M inimum delay of a WRITE command after an ACT command to the same bank is tRCD. From the last input data to the PRE command, the write recovery time (tWR) is required. When A10 is high at a WRITE command, auto-precharge (WRITEA) is performed. Any command (READ, WRITE, PRE, ACT, TBST) to the same bank is inhibited till the internal precharge is complete. The internal precharge starts at tWR after the last input data cycle. The next ACT command can be issued after (BL + tWR -1 +tRP) from the p revious WRITEA. In any case, tRCD + BL + tWR -1 > tRASmin must be met. = Write (BL=4) CLK Command ACT Write PRE BL tRCD ACT tRP A0-9,11 Xa Ya A10 Xa 0 0 Xa BA0-1 00 00 00 00 Xa tWR DQ Da0 Da1 Da2 Da3 Write with Auto-Precharge (BL=4) CLK Command ACT Write ACT tRCD BL tRP A0-9,11 Xa Ya Xa A10 Xa 1 Xa BA0-1 00 00 00 tWR DQ Da0 Da1 Da2 Da3 internal precharge starts MITSUBISHI ELECTRIC 19 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM BURST INTERRUPTION [ Read Interrupted by Read ] Burst read op eration can be interrupted by new read of any active bank. Random column access is allowed. READ to READ interval is minimum 1 CLK. Read interrupted by Read (CL=2, BL=4) CLK READ Command A0-9,11 A10 BA0-1 READ READ Ya Yb Yc 0 0 0 00 00 10 Qa1 Qa2 Qa0 DQ Qb0 Qc0 Qc1 Qc2 Qc3 [ Read Interrupted by Write ] Burst read op eration can be interrupted by write of any active bank. Random column access is allowed. In this case, the DQ should be controlled adequately by using the DQM to prevent the bus contention. The output is disabled automatically 1 cycle after WRITE assertion. Read interrupted by Write (CL=2, BL=4) CLK Command ACT READ Write A0-9,11 Xa Ya Ya A10 Xa 0 0 BA0-1 00 00 00 DQM DQ Qa0 Da0 Da1 Output disable by DQM Da2 Da3 by WRITE MITSUBISHI ELECTRIC 20 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM [ Read Interrupted by Precharge ] A burst read operation can be interrupted by a precharge of the same bank . READ to PRE interval is minimum 1 CLK. A PRE command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Precharge (BL=4) CLK Command READ Q0 DQ Command PRE READ Q1 Q2 PRE CL=2 DQ Command Q0 READ PRE DQ Command Q0 READ PRE DQ Command Q1 READ Q0 Q1 Q0 Q1 Q2 PRE CL=3 DQ Command DQ READ PRE Q0 MITSUBISHI ELECTRIC 21 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM [ Read Interrupted by Burst Terminate ] Similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. The terminated bank remains active. READ to TBST interval is minimum 1 CLK. A TBST command to output disable latency is equivalent to the /CAS Latency. Read interrupted by Terminate (BL=4) CLK Command READ Q0 DQ Command TBST READ Q1 Q2 TBST CL=2 DQ Command Q0 READ TBST DQ Command Q0 READ TBST DQ Command Q1 READ Q0 Q1 Q0 Q1 Q2 TBST CL=3 DQ Command DQ READ TBST Q0 MITSUBISHI ELECTRIC 22 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM [ Write Interrupted by Write ] Burst write operation can be interrupted by new write of any active bank. Random column access is allowed. WRITE to WRITE interval is minimum 1 CLK. Write interrupted by Write (BL=4) CLK Command Write Write Write A0-9,11 Ya Yb Yc 0 0 0 BA0-1 00 00 10 DQ Da0 Db0 Dc0 A10 Da1 Da2 Dc1 Dc2 Dc3 [ Write Interrupted by Read ] Burst write operation can be interrupted by read of any active bank. Random column access is allowed. WRITE to READ interval is minimum 1 CLK. The input data on DQ at the interrupting READ cycle is "Don't Care". Write interrupted by Read (CL=2, BL=4) CLK Command ACT Write A0-9,11 Xa Ya Yb A10 Xa 0 0 BA0-1 00 00 00 DQ Da0 READ Da1 Qb0 Qb1 Qb2 Qb3 don't care MITSUBISHI ELECTRIC 23 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM [ Write Interrupted by Precharge ] Burst write operation can be interrupted by precharge of the same bank. Write recovery time (tWR) is required from the last data to PRE command. During write recovery, data inputs must be masked by DQM . Write interrupted by Precharge (BL=4) CLK Command ACT Write PRE ACT tRP A0-9,11 A10 BA0-1 Xa Ya Xa 0 0 0 0 00 00 00 00 DQM tWR Da0 DQ Da1 [ Write Interrupted by Burst Terminate ] Burst terminate command can terminate burst write operation. In this case, the write recovery time is not required and the bank remains active. WRITE to TBST interval is minimum 1 CLK. Write interrupted by Terminate (BL=4) CLK Command ACT Write A0-9,11 Xa Ya Yb 0 0 0 00 00 00 A10 BA0-1 DQ Da0 TBST Write Da1 Db0 Db1 Db2 Db3 MITSUBISHI ELECTRIC 24 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM [ Write with Auto-Precharge Interrupted by Write or Read to another Bank ] Burst write with auto-precharge can be interrupted by write or read to another bank. Next ACT comand can be issued after (BL+tWR-1+tRP) from the WRITEA. Auto-precharge interruption by a command to the same bank is inhibited. WRITEA interrupted by WRITE to another bank (BL=4) CLK Command Write ACT Write BL A0-9,11 Ya tRP Xa Yb tWR 1 0 Xa BA0-1 00 10 00 DQ Da0 A10 Da1 Db0 Db1 Db2 Db3 auto-precharge interrupted activate WRITEA interrupted by READ to another bank (CL=2, BL=4) CLK Command Write ACT Read BL A0-9,11 Ya tRP Xa Yb tWR 1 0 Xa BA0-1 00 10 00 DQ Da0 A10 Da1 Qb0 Qb1 Qb2 auto-precharge interrupted Qb3 activate MITSUBISHI ELECTRIC 25 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM [ Read with Auto-Precharge Interrupted by Read to another Bank ] Burst read with auto-precharge can be interrupted by read to another bank. Next ACT comand can be issued after (BL+tRP) from the READA. Auto-precharge interruption by a command to the same bank is inhibited. READA interrupted by READ to another bank (CL=2, BL=4) CLK Command Read Read ACT BL A0-9,11-12 A10 BA0-1 DQ tRP Ya Yb Xa 1 0 Xa 00 10 00 Qa0 Qa1 auto-precharge interrupted Qb0 Qb1 Qb2 Qb3 activate Full Page Burst Full page burst length is available for only the sequential burst type. Full page burst read or write is repeated untill a Precharge or a Burst Terminate command is issued. In case of the full page burst, a read or write with auto-precharge command is illegal. Single Write When sigle write mode is set, burst length for write is always one, independently of Burst Length defined by (A2-0). MITSUBISHI ELECTRIC 26 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM AUTO REFRESH Single cycle of auto-refresh is initiated with a REFA (/CS= /RAS= /CAS= L, /WE= /CKE= H) command. The refresh address is generated internally. 4096 REFA cycles within 64ms refresh 64M bit memory cells. The auto-refresh is performed on 4 banks concurrently. Before performing an autorefresh, all banks must be in idle state. Auto-refresh to auto-refresh interval is minimum tRFC. Any command must not be issued before tRFC from the REFA command. Auto-Refresh CLK /CS NOP or DESELECT /RAS /CAS /WE CKE minimum tRFC A0-11 BA0-1 Auto Refresh on All Banks Auto Refresh on All Banks MITSUBISHI ELECTRIC 27 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM SELF REFRESH Self-refresh mode is entered by issuing a REFS command (/CS= /RAS= /CAS= L, /WE= H, CKE= L). Once the self-refresh is initiated, it is maintained as long as CKE is kept low. During the self-refresh mode, CKE is asynchronous and the only enabled input. All other inputs including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved. To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then asserting CKE=H. After tRFC from the 1st CLK edge following CKE=H, all banks are in idle state and a new command can be issued, but DESEL or NOP commands must be asserted till then. Self-Refresh CLK Stable CLK NOP /CS /RAS /CAS /WE CKE new command A0-11 X BA0-1 00 Self Refresh Entry Self Refresh Exit minimum tRFC for recovery MITSUBISHI ELECTRIC 28 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM CLK SUSPEND and POWER DOWN CKE controls the internal CLK at the following cycle. Figure below shows how CKE works. By negating CKE, the next internal CLK is suspended. The purpose of CLK suspend is power down, output suspend or input suspend. CKE is a synchronous input except during the self-refresh mode. CLK suspend can be performed either when the banks are active or idle. A command at the suspended cycle is ignored. ext.CLK tIH tIS tIH tIS CKE int.CLK Power Down by CKE CLK Standby Power Down CKE Command PRE NOP NOP NOP Activ e Power Down CKE Command ACT NOP NOP NOP DQ Suspend by CKE CLK CKE Command DQ Write D0 Read D1 D2 D3 Q0 Q1 Q2 Q3 MITSUBISHI ELECTRIC 29 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM DQM CONTROL DQM (U, L) is a dual functional signal defined as the data mask for writes and the output disable for reads. During writes, DQM (U, L) masks input data word by word. DQM (U, L) to Data In latency is 0. During reads, DQM (U, L) forces output to Hi-Z word by word. DQM (U, L) to output Hi-Z latency is 2. DQM Function CLK Command Write Read DQM(U, L) DQ D0 D2 D3 masked by DQM(U, L)=H Q0 Q1 Q3 disabled by DQM(U, L)=H MITSUBISHI ELECTRIC 30 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM ABSOLUTE MAXIMUM RATINGS Symbol Parameter Conditions Ratings Unit Vdd Supply Voltage with respect to Vss -0.5 ~ 4.6 V -0.5 ~ 4.6 V VddQ Supply Voltage for Output with respect to VssQ VI Input Voltage with respect to Vss -0.5 ~ Vdd+0.5 V VO Output Voltage with respect to VssQ -0.5 ~ VddQ+0.5 V IO Output Current 50 mA Pd Power Dissipation 1000 mW Ta = 25'C Topr Operating Temperature 0 ~ 70 'C Tstg Storage Temperature -65 ~ 150 'C RECOM M ENDED OPERATING CONDITIONS (Ta=0 ~ 70'C, unless otherwise noted) Limits Symbol Parameter Vdd Unit Min. Typ. Max. Supply Voltage 3.0 3.3 3.6 V Vss Supply Voltage 0 0 0 V VddQ Supply Voltage for Output 3.0 3.3 3.6 V VssQ Supply Voltage for Output 0 0 0 V VIH *1 High-Level Input Voltage all inputs 2.0 Vdd+0.3 V VIL *2 Low-Level Input Voltage all inputs -0.3 0.8 V NOTES) 1. VIH(max)=5.5V AC f or pulse width less than 10ns. 2. VIL(min)=-1.0V AC f or pulse width less than 10ns. CAPACITANCE (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) Limits Symbol CI(A) Parameter Test Condition Input Capacitance, address pin CI(C) Input Capacitance, control pin CI(K) Input Capacitance, CLK pin CI/O Input Capacitance, I/O pin VI=1.4v f=1MHz VI=200mVrms Unit Min. Max. 2.5 3.8 pF 2.5 3.8 pF 2.5 3.5 pF 4.0 6.5 pF MITSUBISHI ELECTRIC 31 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM AVERAGE SUPPLY CURRENT from Vdd (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, Output Open, unless otherwise noted) ITEM Symbol Organization Icc1 -7 -8 x4 75 70 70 x8 75 70 70 x16 85 80 80 Icc2N x4/x8/x16 20 20 20 mA Icc2NS x4/x8/x16 15 15 15 mA tCLK = 15ns CKE = L Icc2P x4/x8/x16 2 2 2 mA CLK = L CKE = L Icc2PS x4/x8/x16 1 1 1 mA CKE = H, tCLK=15ns Icc3N x4/x8/x16 30 30 30 CKE = H, CLK=L Icc3NS x4/x8/x16 25 25 25 x4 90 70 70 x8 90 70 70 x16 100 80 80 x4/x8/x16 130 110 110 mA 1 1 1 mA 0.5 0.5 0.5 mA single bank operation precharge standby current in Non Power down mode /CS > Vcc -0.2V tCLK = 15ns CKE = H VIH > Vcc - 0.2V VIL < 0.2V CLK = L & CKE = H VIH > Vcc - 0.2V VIL < 0.2V all input signals are fixed. precharge standby current in Power down mode /CS > Vcc -0.2V active standby current burst current Unit -6 operating current tRC=min, tCLK =min, BL=1 , CL=3 Limits (max.) mA mA All Bank Active tCLK = min BL=4, CL=3 Icc4 auto-refresh current tRC=min, tCLK=min Icc5 self-refresh current CKE < 0.2V Icc6 x4 6,7,8 /x8 /x16 6L,7L,8L mA NOTE) 1. Icc(max) is specif ied at the output open condition. 2. Input signals are changed one time during 30ns. AC OPERATING CONDITIONS AND CHARACTERISTICS (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) Symbol Parameter Limits Test Conditions Min. VOH(DC) High-Level Output Voltage (DC) IOH=-2mA VOL(DC) Low-Level Output Voltage (DC) IOL= 2mA IOZ Off-state Output Current Q floating Vo=0 ~ VddQ II Input Current VIH=0 ~ VddQ+0.3V Unit Max. 2.4 V 0.4 V -5 5 µA -5 5 µA MITSUBISHI ELECTRIC 32 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM AC TIM ING REQUIREMENTS (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) Input Pulse Levels: 0.8V to 2.0V Input Timing Measurement Level: 1.4V Limits -6 Parameter Symbol Min. tCLK CLK cycle time -7 Max. Min. Unit -8 Max. Min. Max. CL=2 10 10 13 ns CL=3 7.5 10 10 ns tCH CLK High pulse width 2.5 3 3 ns tCL CLK Low pulse width 2.5 3 3 ns Transition time of CLK 1 tT 10 10 1 1 10 ns tIS Input Setup time (all inputs) 1.5 2 2 ns tIH Input Hold time (all inputs) 0.8 1 1 ns tRC Row Cycle time 67.5 70 70 ns tRFC Refresh Cycle time 75 80 80 ns tRCD Row to Column Delay 20 20 20 ns tRAS Row Active time 45 tRP Row Precharge time 20 20 20 ns tWR Write Recovery time 12 12 12 ns tRRD Act to Act delay 15 20 20 ns tRSC Mode Register Set Cycle time 10 10 10 ns tREF Refresh Interval time CLK Signal 100K 100K 50 64 64 50 100K 64 ns ms 1.4V 1.4V AC timing is referenced to the input signal crossing through 1.4V. MITSUBISHI ELECTRIC 33 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM SWITCHING CHARACTERISTICS (Ta=0 ~ 70'C, Vdd = VddQ = 3.3 ± 0.3V, Vss = VssQ = 0V, unless otherwise noted) SWITCHING CHARACTERISTICS (Ta=0 – 70'C, Vdd= VddQ= 3.3 ± 0.3V, Vss= VssQ= 0V, unless otherwise noted ) Limits Symbol Parameter -6 Min. tAC tOH Access time f rom CLK Output Hold time f rom CLK -8 -7 Max. Max. Min. Min. Unit Note Max. CL=2 6 6 7 ns CL=3 5.4 6 6 ns CL=2 CL=3 3 3 3 ns 2.7 3 3 ns 0 0 ns tOLZ Delay , output lowimpedance f rom CLK 0 tOHZ Delay , output highimpedance f rom CLK 2.7 5.4 3 6 3 6 *1 ns NOTE) 1. If clock rising time is longer than 1ns, (tr /2–0.5ns) should be added to the parameter. Output Load Condition CLK VOUT 1.4V 50pF 1.4V DQ Output Timing Measurement Reference Point CLK 1.4V tOLZ DQ 1.4V tAC tOH tOHZ MITSUBISHI ELECTRIC 34 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Burst Write (Single Bank) [BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC /CS tRAS tRP /RAS tRCD tRCD /CAS tWR tWR /WE CKE DQM A0-8 X A10 X X A9,11 X X BA0,1 0 DQ Y 0 D0 ACT#0 X 0 D0 WRITE#0 D0 0 D0 Y 0 D0 PRE#0 ACT #0 0 D0 WRITE#0 D0 D0 PRE#0 Italic paramater shows minimum case MITSUBISHI ELECTRIC 35 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Burst Write (Multi Bank) [BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC tRC /CS tRAS tRP tRRD /RAS tRCD tRCD tRCD /CAS tWR tWR /WE CKE DQM A0-8 X A10 X X X X A9,11 X X X X BA0,1 0 DQ Y X 0 1 D0 D0 Y D0 ACT#0 WRITE#0 ACT#1 D0 X 1 0 D1 D1 PRE#0 D1 Y 0 0 D1 D0 ACT #0 WRITEA#1 (Auto-Precharge) X 1 D0 D0 0 D0 WRITE#0 PRE#0 ACT#1 Italic paramater shows minimum case MITSUBISHI ELECTRIC 36 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Burst Read (Single Bank) [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC /CS tRAS tRP tRAS /RAS tRCD tRCD /CAS /WE CKE DQM A0-8 X A10 X X A9,11 X X BA0,1 0 Y X 0 DQ 0 Q0 ACT#0 READ#0 Q0 Q0 PRE#0 Y 0 0 Q0 0 Q0 ACT #0 READ#0 Q0 Q0 Q0 PRE#0 Italic paramater shows minimum case MITSUBISHI ELECTRIC 37 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Burst Read (Multi Bank) [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC tRC /CS tRRD tRAS /RAS tRCD tRCD tRCD /CAS /WE CKE DQM A0-8 X A10 X X X X A9,11 X X X X BA0,1 0 Y X 0 Y 1 DQ X 1 Q0 Q0 Q0 0 Q0 ACT#0 READA#0 ACT#1 Y X 0 Q1 Q1 ACT #0 Q1 1 Q1 Q0 READ#0 0 Q0 Q0 Q0 PRE#0 ACT #1 READA#1 Italic paramater shows minimum case MITSUBISHI ELECTRIC 38 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Write Interrupted by Write [BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS tRRD /RAS tRCD /CAS tWR /WE CKE DQM A0-8 X A10 X X X A9,11 X X X BA0,1 0 DQ Y X 0 1 D0 D0 ACT#0 WRITE#0 ACT#1 Y Y 0 D0 D0 Y 1 D0 D1 X 0 D1 WRITE#0 WRITEA#1 interrupt interrupt same other bank bank D1 D0 0 D0 WRITE#0 interrupt other bank D0 1 D0 PRE#0 ACT #1 Italic paramater shows minimum case MITSUBISHI ELECTRIC 39 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Read Interrupted by Read [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS tRRD /RAS tRCD tRCD /CAS /WE CKE DQM A0-8 X A10 X X X A9,11 X X X BA0,1 0 Y 0 X Y 1 DQ 1 Q0 ACT#0 READ#0 ACT#1 Y Q0 READ#1 interrupt other bank Y 1 Q0 Q1 X 0 Q1 Q1 Q1 READA#1 READ#0 interrupt interrupt same bank other bank 1 Q1 Q0 Q0 Q0 Q0 ACT #1 Italic paramater shows minimum case MITSUBISHI ELECTRIC 40 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Write Interrupted by Read, Read Interrupted by Write [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS tRRD /RAS tRCD tRCD /CAS tWR /WE CKE DQM A0-8 X X A10 X X A9,11 X X BA0,1 0 1 DQ Y Y Y 0 1 1 D0 ACT#0 D0 WRITE#0 READ#1 Q1 Q1 D1 1 D1 WRITE#1 D1 D1 PRE#1 ACT#1 Italic paramater shows minimum case MITSUBISHI ELECTRIC 41 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Write / Read Terminated by Precharge [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRC /CS tRP tRAS tRP /RAS tRCD tRCD /CAS tWR /WE CKE DQM A0-8 X A10 X X X A9,11 X X X BA0,1 0 DQ Y 0 D0 ACT#0 X 0 Y 0 0 D0 WRITE#0 X 0 Q0 PRE#0 ACT#0 Terminate READ#0 0 Q0 PRE#0 ACT#0 Terminate Italic paramater shows minimum case MITSUBISHI ELECTRIC 42 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Write / Read Terminated by Burst Terminate [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS tRCD /CAS tWR /WE CKE DQM A0-8 X A10 X A9,11 X BA0,1 0 DQ Y Y Y 0 0 0 D0 ACT#0 D0 Q0 Q0 WRITE#0 TERM READ#0 TERM D0 0 D0 WRITE#0 D0 D0 PRE#0 Italic paramater shows minimum case MITSUBISHI ELECTRIC 43 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Single Write Burst Read [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0,1 0 DQ Y Y 0 0 D0 Q0 Q0 Q0 Q0 ACT#0 WRITE#0 READ#0 Italic paramater shows minimum case MITSUBISHI ELECTRIC 44 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Power-Up Sequence and Intialize CLK 200µs /CS tRP tRFC tRFC tRSC /RAS /CAS /WE CKE DQM A0-8 MA X A10 0 X A9,11 0 X BA0,1 0 0 DQ NOP Power On PRE ALL REFA REFA REFA MRS ACT #0 Minimum 8 REFA cycles Italic paramater shows minimum case MITSUBISHI ELECTRIC 45 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Auto Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRFC /CS tRP /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0,1 0 DQ Y 0 D0 PRE ALL REFA ACT#0 D0 D0 D0 WRITE#0 All banks must be idle before REFA is issued. Italic paramater shows minimum case MITSUBISHI ELECTRIC 46 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Self Refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK tRFC /CS tRP /RAS /CAS /WE CKE DQM A0-8, X A10 X A9,11 X BA0,1 0 DQ PRE ALL Self Refresh Entry Self Refresh Exit ACT#0 All banks must be idle before REFS is issued. Italic paramater shows minimum case MITSUBISHI ELECTRIC 47 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM CLK Suspension [CL=2, BL=4] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS tRCD /CAS /WE CKE DQM A0-8 X A10 X A9,11 X BA0,1 0 DQ Y Y 0 0 D0 D0 D0 ACT#0 WRITE#0 internal CLK suspended D0 Q0 READ#0 Q0 Q0 Q0 internal CLK suspended Italic paramater shows minimum case MITSUBISHI ELECTRIC 48 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Power Down 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 CLK /CS /RAS /CAS /WE Standby Power Down Active Power Down CKE DQM A0-8 X A10 X A9,11 X BA0,1 0 DQ PRE ALL ACT #0 Italic paramater shows minimum case MITSUBISHI ELECTRIC 49 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Revison History Description Rev. Date 1.0 Jun '99 -1st edition 2.0 July '99 -single write mode is added -Icc5 for -6 is changed form 110mA to 130mA -tRFC is added -tRSC is changed 3.0 Oct. '99 -tSRX and tPDE are removed 3.1 Oct. '99 -tWR is changed to 12ns MITSUBISHI ELECTRIC 50 MITSUBISHI LSIs SDRAM (Rev.3.2) Feb.'00 M2V64S20DTP-6,-6L,-7,-7L,-8,-8L M2V64S30DTP-6,-6L,-7,-7L,-8,-8L M2V64S40DTP-6,-6L,-7,-7L,-8,-8L (4-BANK x 4,194,304-WORD x 4-BIT) (4-BANK x 2,097,152-WORD x 8-BIT) (4-BANK x 1,048,576-WORD x 16-BIT) 64M Synchronous DRAM Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum ef f ort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury , f ire or property damage. Remember to giv e due consideration to saf ety when making y our circuit designs, with appropriate measures such as (i) placement of substitutiv e, auxiliary circuits, (ii) use of non-f lammable material or (iii) prev ention against any m alf unction or mishap. Notes regarding these materials 1.These materials are intended as a ref erence to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not conv ey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party . 2.Mitsubishi Electric Corporation assumes no responsibility f or any damage, or inf ringement of any thirdparty 's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3.All inf ormation contained in these materials, including product data, diagrams, charts, programs and algorithms represents inf ormation on products at the time of publication of t hese materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improv ements or other reasons. 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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein f or any specif ic purposes, such as apparatus or systems for transportation, v ehicular, medical, aerospace, nuclear, or undersea repeater use. 6.The prior written approv al of Mitsubishi Electric Corporation is necessary t o reprint or reproduce in whole or in part these materials. 7.If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license f rom the Japanese gov ernment and cannot be imported into a country other than the approv ed destination. Any div ersion or reexport contrary t o the export control laws and regulations of Japan and/or the country of destination is prohibited. 8.Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor f or f urther details on these materials or the products contained therein. MITSUBISHI ELECTRIC 51