EL7457 ® Data Sheet January 3, 2005 40MHz Non-Inverting Quad CMOS Driver Features The EL7457 is a high speed, non-inverting, quad CMOS driver. It is capable of running at clock rates up to 40MHz and features 2A peak drive capability and a nominal onresistance of just 3Ω. The EL7457 is ideal for driving highly capacitive loads, such as storage and vertical clocks in CCD applications. It is also well suited to ATE pin driving, levelshifting, and clock-driving applications. • Clocking speeds up to 40MHz The EL7457 is capable of running from single or dual power supplies while using ground referenced inputs. Each output can be switched to either the high (VH) or low (VL) supply pins, depending on the related input pin. The inputs are compatible with both 3V and 5V CMOS and TTL logic. The output enable (OE) pin can be used to put the outputs into a high-impedance state. This is especially useful in CCD applications, where the driver should be disabled during power down. • Low quiescent current - <1mA The EL7457 also features very fast rise and fall times which are matched to within 1ns. The propagation delay is also matched between rising and falling edges to within 2ns. The EL7457 is available in 16-pin QSOP, 16-pin SO (0.150"), and 16-pin QFN packages. All are specified for operation over the full -40°C to +85°C temperature range. Pinouts FN7288.3 • 4 channels • 12ns tR/tF at 1000pF CLOAD • 1ns rise and fall time match • 1.5ns prop delay match • Fast output enable function - 12ns • Wide output voltage range • 8V ≥ VL ≥ -5V • -2V ≤ VH ≤ 16.5V • 2A peak drive • 3Ω on resistance • Input level shifters • TTL/CMOS input-compatible • Pb-free available (RoHS compliant) Applications • CCD drivers • Digital cameras OUTB 14 VL 2 4 VL NC 13 VL 3 5 GND VH 12 GND 4 6 NC OUTC 11 7 INC OUTD 10 8 IND VS- 9 • Clock/line drivers • Ultrasound transducer drivers 13 OUTA 3 INB • Pin drivers • Ultrasonic and RF generators 12 OUTB • Level shifting 11 VH THERMAL PAD* 10 VH 9 OUTC OUTD 8 INB 1 VS- 7 OUTA 15 IND 6 2 OE 14 VS+ 16 OE VS+ 16 INC 5 1 INA 15 INA EL7457 [16-PIN QFN (4x4mm)] TOP VIEW EL7457 [16-PIN SO (0.150”), QSOP (0.150”)] TOP VIEW * THERMAL PAD CONNECTED TO PIN 7 (VS-) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002-2005. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL7457 Ordering Information PART NUMBER PACKAGE TAPE & REEL PKG. DWG. # PART NUMBER PACKAGE TAPE & REEL PKG. DWG. # EL7457CU 16-Pin QSOP (0.150”) - MDP0040 EL7457CSZ (See Note) 16-Pin SO (0.150”) (Pb-Free) - MDP0027 EL7457CU-T7 16-Pin QSOP (0.150”) 7” MDP0040 EL7457CSZ-T7 (See Note) 16-Pin SO (0.150”) (Pb-Free) 7” MDP0027 EL7457CU-T13 16-Pin QSOP (0.150”) 13” MDP0040 EL7457CSZ-T13 (See Note) 16-Pin SO (0.150”) (Pb-Free) 13” MDP0027 EL7457CUZ (See Note) 16-Pin QSOP (0.150”) (Pb-Free) - MDP0040 EL7457CL 16-Pin QFN (4x4mm) - MDP0046 EL7457CUZ-T7 (See Note) 16-Pin QSOP (0.150”) (Pb-Free) 7” MDP0040 EL7457CL-T7 16-Pin QFN (4x4mm) 7” MDP0046 EL7457CUZ-T13 (See Note) 16-Pin QSOP (0.150”) (Pb-Free) 13” MDP0040 EL7457CL-T13 16-Pin QFN (4x4mm) 13” MDP0046 EL7457CS 16-Pin SO (0.150”) - MDP0027 EL7457CLZ (See Note) 16-Pin QFN (4x4mm) (Pb-Free) - MDP0046 EL7457CS-T7 16-Pin SO (0.150”) 7” MDP0027 EL7457CLZ-T7 (See Note) 16-Pin QFN (4x4mm) (Pb-Free) 7” MDP0046 EL7457CS-T13 16-Pin SO (0.150”) 13” MDP0027 EL7457CLZ-T13 (See Note) 16-Pin QFN (4x4mm) (Pb-Free) 13” MDP0046 NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020C. 2 FN7288.3 January 3, 2005 EL7457 Absolute Maximum Ratings (TA = 25°C) Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . .+18V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.3V, VS+ +0.3V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Maximum Die Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . +125°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = -5V, VH = +5V, VL = -5V, TA = 25°C, unless otherwise specified. DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT VIH Logic “1” Input Voltage IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current CIN Input Capacitance 3.5 pF RIN Input Resistance 50 MΩ 2.0 VIH = 5V VIL = 0V V 0.1 0.1 10 µA 0.8 V 10 µA OUTPUT ROH ON Resistance VH to OUTx IOUT = -100mA 4.5 6 Ω ROL ON Resistance VL to OUTx IOUT = +100mA 4 6 Ω ILEAK Output Leakage Current VH = VS+, VL = VS- 0.1 10 µA IPK Peak Output Current Source 2.0 A Sink 2.0 A Inputs = VS+ 0.5 POWER SUPPLY IS Power Supply Current 1.5 mA SWITCHING CHARACTERISTICS tR Rise Time CL = 1000pF 13.5 ns tF Fall Time CL = 1000pF 13 ns tRF∆ tR, tF Mismatch CL = 1000pF 0.5 ns tD+ Turn-Off Delay Time CL = 1000pF 12.5 ns tD- Turn-On Delay Time CL = 1000pF 14.5 ns tDD tD-1 - tD-2 Mismatch CL = 1000pF 2 ns tENABLE Enable Delay Time 12 ns tDISABLE Disable Delay Time 12 ns 3 FN7288.3 January 3, 2005 EL7457 Electrical Specifications PARAMETER VS+ = +15V, VS- = 0V, VH = +15V, VL = 0V, TA = 25°C, unless otherwise specified DESCRIPTION CONDITION MIN TYP MAX UNIT INPUT VIH Logic “1” Input Voltage IIH Logic “1” Input Current VIL Logic “0” Input Voltage IIL Logic “0” Input Current CIN Input Capacitance 3.5 pF RIN Input Resistance 50 MΩ 2.4 VIH = 5V VIL = 0V V 0.1 0.1 10 µA 0.8 V 10 µA OUTPUT ROH ON Resistance VH to OUT IOUT = -100mA 3.5 5 Ω ROL ON Resistance VL to OUT IOUT = +100mA 3 5 Ω ILEAK Output Leakage Current VH = VS+, VL = VS- 0.1 10 µA IPK Peak Output Current Source 2.0 A Sink 2.0 A Inputs = VS+ 0.8 POWER SUPPLY IS Power Supply Current 2 mA SWITCHING CHARACTERISTICS tR Rise Time CL = 1000pF 11 ns tF Fall Time CL = 1000pF 12 ns tRF∆ tR, tF Mismatch CL = 1000pF 1 ns tD+ Turn-Off Delay Time CL = 1000pF 11.5 ns tD- Turn-On Delay Time CL = 1000pF 13 ns tDD tD-1 - tD-2 Mismatch CL = 1000pF 1.5 ns tENABLE Enable Delay Time 12 ns tDISABLE Disable Delay Time 12 ns 4 FN7288.3 January 3, 2005 EL7457 Typical Performance Curves T=25°C 2 HIGH LIMIT=2.4V 1.6 HYSTERESIS 1.4 1.2 1 SUPPLY CURRENT (V) INPUT VOLTAGE (V) 1.8 LOW LIMIT=0.8V 5 7 10 12 ALL INPUTS=0 1.6 1.2 0.8 0.4 0 15 T=25°C ALL INPUTS=VS+ 5 7 FIGURE 1. SWITCH THRESHOLD vs SUPPLY VOLTAGE 25 RISE/FALL TIME (ns) “ON” RESISTANCE (Ω) IOUT=100mA 8 T=25°C 7 6 VH TO OUT 5 VL TO OUT tR 20 tF 15 10 3 5 7 10 12 5 15 CL=1000pF T=25°C 5 7 SUPPLY VOLTAGE (V) DELAY TIME (ns) RISE/FALL TIME (ns) 25 14 tF 10 tR 8 6 -50 -25 0 25 50 75 100 125 TEMPERATURE (°C) FIGURE 5. RISE/FALL TIME vs TEMPERATURE 5 12 15 FIGURE 4. RISE/FALL TIME vs SUPPLY VOLTAGE CL=1000pF VS+=15V 12 10 SUPPLY VOLTAGE (V) FIGURE 3. “ON” RESISTANCE vs SUPPLY VOLTAGE 16 15 FIGURE 2. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE 9 2 12 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) 4 10 CL=1000pF 20 tD2 15 tD1 10 5 5 7 10 12 15 SUPPLY VOLTAGE (V) FIGURE 6. PROPAGATION DELAY vs SUPPLY VOLTAGE FN7288.3 January 3, 2005 EL7457 Typical Performance Curves 18 140 CL=1000pF VS+=15V VS+=15V 120 14 RISE/FALL TIME (ns) 16 DELAY TIME (ns) (Continued) tD2 12 tD1 10 8 100 80 60 tF 40 tR 20 6 -50 0 -25 50 25 100 75 0 100 125 TEMPERATURE (°C) VS+=VH=10V VS-=VL=0V 10 f=100kHz POWER DISSIPATION (W) SUPPLY CURRENT (mA) 1.2 8 6 4 2 1K 10K LOAD CAPACITANCE (pF) 10K JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 909mW 0.8 SO16 (0.150”) θJA=110°C/W 667mW 0.6 633mW QFN16 θJA=150°C/W 0.4 QSOP16 (0.150”) θJA=158°C/W 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 9. SUPPLY CURRENT PER CHANNEL vs CAPACITIVE LOAD POWER DISSIPATION (W) 4.7K FIGURE 8. RISE/FALL TIME vs LOAD 12 3 2.2K LOAD CAPACITANCE (pF) FIGURE 7. PROPAGATION DELAY vs TEMPERATURE 0 100 1K 470 FIGURE 10. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 2.500W 2.5 QFN16 θJA=40°C/W 2 SO16 (0.150”) θJA=80°C/W 1.5 1.250W 1 893mW 0.5 0 QSOP16 (0.150”) θJA=112°C/W 0 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (°C) FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 6 FN7288.3 January 3, 2005 EL7457 Timing Diagram TABLE 1. NOMINAL OPERATING VOLTAGE RANGE PIN MIN MAX VS+ to VS- 5V 16.5V VS- to GND -5V 0V VH VS- + 2.5V VS+ VL VS- VS+ VH to VL 0V 16.5V VL to VS- 0V 8V 5V INPUT 2.5V 0 OUTPUT 90% 10% t D+ tDtR tF Standard Test Configuration (CS/CU) VS+ 0.1µF 4.7µF VS+ 10kΩ 1 INA 16 OUTA 1000pF EN INB 2 15 3 14 OUTB 1000pF VL 4.7µF 4 13 0.1µF 0.1µF 5 12 6 11 VH 4.7µF OUTC 1000pF INC 7 10 IND 8 9 OUTD 1000pF VS0.1µF 7 4.7µF FN7288.3 January 3, 2005 EL7457 Pin Descriptions 16-PIN QSOP (0.150”), SO (0.150”) 16-PIN QFN (4x4mm) NAME 1 15 INA FUNCTION EQUIVALENT CIRCUIT Input channel A VS+ VS+ INPUT VS- VS- CIRCUIT 1 2 16 OE Output Enable (Reference Circuit 1) 3 1 INB Input channel B (Reference Circuit 1) 4 2, 3 VL Low voltage input pin 5 4 GND 6, 13 Input logic ground NC No connection 7 5 INC Input channel C (Reference Circuit 1) 8 6 IND Input channel D (Reference Circuit 1) 9 7 VS- Negative supply voltage 10 8 OUTD Output channel D VH VS+ OUTPUT VSVSVL CIRCUIT 2 11 9 OUTC 12 10, 11 VH 14 12 OUTB Output channel B (Reference Circuit 2) 15 13 OUTA Output channel A (Reference Circuit 2) 16 14 VS+ 8 Output channel C (Reference Circuit 2) High voltage input pin Positive supply voltage FN7288.3 January 3, 2005 EL7457 Block Diagram OE VH VS+ INPUT GND LEVEL SHIFTER 3-STATE CONTROL OUTPUT VSVL Applications Information Product Description The EL7457 is a high performance 40MHz high speed quad driver. Each channel of the EL7457 consists of a single Pchannel high side driver and a single N-channel low side driver. These 3Ω devices will pull the output (OUTX) to either the high or low voltage, on VH and VL respectively, depending on the input logic signal (INX). It should be noted that there is only one set of high and low voltage pins. A common output enable (OE) pin is available on the EL7457. This pin, when pulled low will put all outputs in to the high impedance state. The EL7457 is available in 16-pin SO (0.150"), 16-pin QSOP, and ultra-small 16-pin QFN packages. The relevant package should be chosen depending on the calculated power dissipation. Supply Voltage Range and Input Compatibility The EL7457 is designed for operation on supplies from 5V to 15V with 10% tolerance (i.e. 4.5V to 18V). The table on page 6 shows the specifications for the relationship between the VS+, VS-, VH, VL, and GND pins. The EL7457 does not contain a true analog switch and therefore VL should always be less than VH. All input pins are compatible with both 3V and 5V CMOS signals With a positive supply (VS+) of 5V, the EL7457 is also compatible with TTL inputs. Power Supply Bypassing When using the EL7457, it is very important to use adequate power supply bypassing. The high switching currents developed by the EL7457 necessitate the use of a bypass capacitor on both the positive and negative supplies. It is recommended that a 4.7µF tantalum capacitor be used in parallel with a 0.1µF low-inductance ceramic MLC capacitor. These should be placed as close to the supply pins as possible. It is also recommended that the VH and VL pins have some level of bypassing, especially if the EL7457 is driving highly capacitive loads. 9 Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL7457 drive capability is limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125°C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated: 4 PD = ( V S × I S ) + 2 2 × f) ∑ ( CINT × VS × f ) + ( CL × VOUT 1 where: VS is the total power supply to the EL7457 (from VS+ to VS-) VOUT is the swing on the output (VH - VL) CL is the load capacitance CINT is the internal load capacitance (80pF max) IS is the quiescent supply current (3mA max) f is frequency Having obtained the application’s power dissipation, the maximum junction temperature can be calculated: T JMAX = T MAX + Θ JA × PD where: TJMAX is the maximum junction temperature (125°C) TMAX is the maximum ambient operating temperature PD is the power dissipation calculated above θJA is the thermal resistance, junction to ambient, of the application (package + PCB combination). Refer to the Package Power Dissipation curves on page 6. FN7288.3 January 3, 2005 EL7457 QSOP Package Outline Drawing 10 FN7288.3 January 3, 2005 EL7457 SO Package Outline Drawing 11 FN7288.3 January 3, 2005 EL7457 QFN Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at <http://www.intersil.com/design/packages/index.asp> All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN7288.3 January 3, 2005