ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS FEATURES • 12/10/8-Bit Monotonic Quad DACs in 16 lead QSOP Package • Wide Output Voltage Swing • 150 µA per DAC at 5V Supply • 100 µA per DAC at 3V Supply • On Board Reference • Three-wire SPI Interface • Serial Data Out for Daisy-Chaining • 8µs Full-Scale Settling Time APPLICATIONS Battery-Powered Applications Industrial Process Control Digital Gain and Offset Adjustment respectively, with guaranteed monotonic behavior. They include a 1.25V reference for ease of use and flexibility. The reference output is available on a separate pin and can be used to drive the reference input of each DAC. Alternately, each DAC can be driven by an external reference. There is a wide operating supply range of 2.7V to 5.5V. The input interface is an easy to use three-wire SPI/QSPI compatible interface. Each DAC can be individually controlled and has a double buffered digital input. There is a serial data output to allow for daisy-chaining applications. OVERVIEW The ICM7363, ICM7343 and ICM7323 are Quad 12-Bit, 10-Bit and 8-Bit wide output voltage swing DACs BLOCK DIAGRAM REFD REFOUT SDI REFC REFB VDD REFA ICM 7363/7343/7323 Reference Input and DAC Latch 12/10/8 -Bit DAC A x2 VOUT A Input and DAC Latch 12/10/8 -Bit DAC B x2 VOUT B Input and DAC Latch 12/10/8 -Bit DAC C x2 VOUT C Input and DAC Latch 12/10/8 -Bit DAC D x2 VOUT D Input Control Logic, Registers and Latches SDO Power-OnReset SCK Rev. A8 CS CLR GND ICmic reserves the right to change the specifications without prior notice. 1 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS PACKAGE 16-Pin QSOP VDD 1 16 GND VOUTA 2 15 VOUTD REFA 3 14 REFD VOUTB 4 13 VOUTC REFB 5 12 REFC REFOUT 6 11 CS 7 10 SDO SDI 8 9 SCK CLR PIN DESCRIPTION Pin No Symbol Description 1 VDD Supply Voltage 2 VOUT A DAC A Output 3 REF A DAC A Reference Input 4 VOUT B DAC B Output 5 REF B DAC B Reference Input 6 REFOUT Reference Output (1.25V) 7 CLR Clear Input (TTL or CMOS) 8 SDI Serial Data Input (TTL or CMOS) 9 SCK Serial Clock Input (TTL or CMOS) 10 SDO Serial Data Output 11 CS Chip Select (TTL or CMOS) 12 REF C DAC C Reference Input 13 VOUT C DAC C Output 14 REF D DAC D Reference Input 15 VOUT D DAC D Output 16 GND Ground ABSOLUTE MAXIMUM RATING Symbol VDD Parameter Value Unit Supply Voltage -0.3 to 7.0 V IIN Input Current +/- 25.0 mA VIN_ Digital Input Voltage (SCK, SDI, CS, CLR) -0.3 to 7.0 V Reference Input Voltage -0.3 to 7.0 V -65 to +150 o VIN_REF TSTG Rev. A8 Storage Temperature C ICmic reserves the right to change the specifications without prior notice. 2 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS TSOL o 300 Soldering Temperature C Note: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ORDERING INFORMATION Part ICM7363 ICM7343 ICM7323 Temperature Range Package -40 oC to 85 oC -40 oC to 85 oC -40 oC to 85 oC 16-Pin QSOP 16-Pin QSOP 16-Pin QSOP DC ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 5.5V, VREF IN = 1.25V ; VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted) Symbol Parameter DC PERFORMANCE ICM7363 N Resolution DNL Differential Nonlinearity INL Integral Nonlinearity ICM7343 N Resolution DNL Differential Nonlinearity INL Integral Nonlinearity ICM7323 N Resolution DNL Differential Nonlinearity INL Integral Nonlinearity GE Gain Error OE Offset Error POWER REQUIREMENTS VDD Supply Voltage IDD Supply Current Symbol Parameter OUTPUT CHARACTERISTICS Output Voltage Range VOSC Short Circuit Current ROUT Amp Output Impedance Output Line Regulation LOGIC INPUTS VIH Digital Input High VIL Digital Input Low Digital Input Leakage REFERENCE RIN Reference Input Resistance Reference Input Range VREFOUT Reference Output Reference Output Line Regulation Rev. A8 Test Conditions Min Typ Max 12 (Notes 1 & 3) (Notes 1 & 3) 0.4 4.0 +1.0 +12.0 Bits LSB LSB 0.1 1.0 +1.0 +3.0 Bits LSB LSB 0.05 0.25 +1.0 +0.75 Bits LSB LSB +0.5 +25 % of FS mV 5.5 2.5 V mA 10 (Notes 1 & 3) (Notes 1 & 3) 8 (Notes 1 & 3) (Notes 1 & 3) 2.7 (Note 4) Test Conditions (Note 3) 1.2 Min 60 1.0 100 0.4 At Mid-scale At Zero-scale Vdd=2.7 to 5.5 V (Note 2) (Note 2) (Note 2) Vdd=2.7 to 5.5 V Typ 0 Max 41 1.25 0.8 Unit VDD 150 5.0 200 3.0 V mA Ω Ω mV/V 0.8 5 V V µΑ 65 VDD -1.5 1.3 4.0 kΩ V V mV/V 2.4 25 0.5 1.2 Unit ICmic reserves the right to change the specifications without prior notice. 3 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS AC ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 5.5V, VREF IN = 1.25V ; VOUT unloaded; all specifications TMIN to TMAX unless otherwise noted) Symbol SR Parameter Test Conditions Min Typ Slew Rate Settling Time Full-scale settling Mid-scale Transition Glitch Energy Note 1: Note 2: Note 3: Note 4: Max Unit 2 V/µs 8 µs 40 nV-S Linearity is defined from code 64 to 4095 (ICM7363) Linearity is defined from code 16 to 1023 (ICM7343) Linearity is defined from code 4 to 255 (ICM7323) Guaranteed by design; not tested in production See Applications Information All digital inputs are either at GND or Vdd TIMING CHARACTERISTICS (VDD = 2.7V to 5.5V; all specifications TMIN to TMAX unless otherwise noted) Symbol Parameter Test Conditions Min Typ Max Unit t1 t2 t3 SCK Cycle Time Data Setup Time Data Hold Time (Note 2) (Note 2) (Note 2) 30 10 10 ns ns ns t4 SCK Falling edge to CS Rising Edge (Note 2) 0 ns t5 CS Falling Edge to SCK Rising Edge 15 ns t6 CS Pulse Width 20 ns (Note 2) (Note 2) (Note 2) t7 t8 Rev. A8 CLR Pulse Width SDO Delay 20 (Note 2) ICmic reserves the right to change the specifications without prior notice. 100 ns ns 4 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS t1 SCK t3 t2 SDI C3 C2 LSB t5 Input Word for DAC N t4 CS t6 t8 SDO C3 C2 Input Word for DAC N Figure 1: Serial Interface Timing Diagram CONTENTS OF INPUT SHIFT REGISTER ICM7363 (12-Bit DAC) MSB C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB D0 D0 X LSB X X X LSB X Figure 2: Contents of ICM7363 Input Shift Register ICM7343 (10-Bit DAC) MSB C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 Figure 3: Contents of ICM7343 Input Shift Register ICM7323 (8-Bit DAC) MSB C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 X Figure 4: Contents of ICM7323 Input Shift Register Rev. A8 ICmic reserves the right to change the specifications without prior notice. 5 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS C3 C2 C1 C0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 DATA Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data X DAC FUNCTION A A A B B B C C C D D D A-D A-D A-D X Load Input Latch Update DAC Load Input Latch and Update DAC Load Input Latch Update DAC Load Input Latch and Update DAC Load Input Latch Update DAC Load Input Latch and Update DAC Load Input Latch Update DAC Load Input Latch and Update DAC Load Input Latch Update DAC Load Input Latch and Update DAC No Operation Table 1: Serial Interface Control Command Rev. A8 ICmic reserves the right to change the specifications without prior notice. 6 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS DETAILED DESCRIPTION The ICM7363 is a 12-bit quad voltage output DAC. The ICM7343 is the 10-bit version of this family and the ICM7323 is the 8-bit version. This family of DACs employs a resistor string architecture guaranteeing monotonic behavior. There is a 1.25V onboard reference and a wide operating supply range of 2.7V to 5.5V. Reference Input and Output Each DAC has its own reference input pin which can be driven from ground to VDD -1.5V. The input resistance on each of these pins is typically 41 kΩ. There is a gain of two in the output amplifiers which means they swing from ground at code 0 to 2 x VREF IN at full-scale : Vout = 2 x (VREF IN xD)/2n Where D=digital input (decimal) and n= number of bits, i.e. 12 for ICM7363, 10 for ICM7343 and 8 for ICM7323. be low before the CS pin is pulled back low. As the CS pin is pulled high the shift register contents are transferred to a bank of 16 latches. The 4 bit control word (C3~C0) is then decoded and the appropriate DAC is updated or loaded depending on the control word (see Table 1). Each DAC has a double-buffered input with an input latch and a DAC latch. The DAC output will swing to its new value when data is loaded into the DAC latch. For each DAC, the user has three options: loading only the input latch, updating the DAC with data previously loaded into the input latch or loading the input latch and updating the DAC at the same time with a new code. The user also has the ability to perform this operation simultaneously for all DACs as shown in Table 1. Power-On Reset There is a power-on reset on board that will clear the contents of all the latches to all 0s on power-up and the DAC voltage outputs will go to ground. The CLR pin will also perform this same operation asynchronously when it is pulled low. There is also an onboard band-gap reference on all these parts. This reference output is nominally 1.25V and is brought out to a separate pin, REFOUT and can be used to drive the reference input of the DACs. The outputs will nominally swing from 0 to 2.5V when using this reference. Output Amplifier Each DAC has its own output amplifier with a wide output voltage swing. The actual swing of the output amplifier will be limited by offset error and gain error. See the Applications Information Section for a more detailed discussion. The amplifiers are configured in a gain of 2 with internal gain resistors of about 50 kΩ. The output swing will be from 0V to 2 x VREF IN at full-scale. The output amplifier can drive a load of 2.0 kΩ to VDD or GND in parallel with a 500 pF load capacitance. The output amplifier has a full-scale typical settling time of 8 µs and it dissipates about 150 µA with a 5V supply voltage. Serial Interface and Input Logic This quad DAC family uses a standard 3-wire connection compatible with SPI/QSPI interfaces. There is also a serial data output pin that allows daisy-chaining. Data is loaded in 16-bit words which consist of 4 address and control bits (MSBs) followed by 12 bits of data (see table 1). The ICM7343 has the last two LSBs as don’t cares and the ICM7323 has the last 4 LSBs as don’t cares. Each DAC is double buffered with an input latch and a DAC latch. All the digital inputs are CMOS/TTL compatible. The current dissipation of the device however, will be higher when the inputs are driven at TTL levels. The output of the 16-bit input shift register is available at the SDO pin. Data is clocked in on the rising edge of SCK which has a Schmitt trigger internally to allow for noise immunity on the SCK pin. This specially eases the use for opto-coupled interfaces. The CS pin must be low when data is being clocked into the part. After the 16th clock pulse the CS pin must be pulled high (level-triggered) for the data to be transferred to an input bank of latches. The CS pin also disables the SCK pin internally when pulled high and the SCK pin must Rev. A8 ICmic reserves the right to change the specifications without prior notice. 7 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS ground. This is why the linearity is specified for a starting code greater than zero. APPLICATIONS INFORMATION Power Supply Bypassing and Layout Considerations As in any precision circuit, careful consideration has to be given to layout of the supply and ground. The return path from the GND to the supply ground should be short with low impedance. Using a ground plane would be ideal. The supply should have some bypassing on it. A 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic with a low ESR can be used. Ideally these would be placed as close as possible to the device. Avoid crossing digital and analog signals, specially the reference, or running them close to each other. Output Swing Limitations The ideal rail-to-rail DAC would swing from GND to VDD however, offset and gain error limit this ability. Figure 5 illustrates how a negative offset error will affect the output. The output will limit close to ground since this is single supply part, resulting in a deadband area. As a larger input is loaded into the DAC the output will eventually rise above Figure 6 illustrates how a gain error or positive offset error will affect the output when it is close to VDD. A positive gain error or positive offset will cause the output to be limited to the positive supply voltage resulting in a deadband of codes close to full-scale. This can be avoided by using a reference voltage slightly less then 0.5 x VDD ensuring that the full-scale of the DAC is always less than VDD. DEADBAND NEGATIVE OFFSET Figure 5: Effect of Negative Offset OFFSET AND GAIN ERROR VDD DEADBAND POSITIVE OFFSET Figure 6: Effect of Gain Error and Positive Offset Rev. A8 ICmic reserves the right to change the specifications without prior notice. 8 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS PACKAGE INFORMATION Rev. A8 ICmic reserves the right to change the specifications without prior notice. 9 ICM7363/7343/7323 ICmic QUAD 12/10/8-BIT VOLTAGE-OUTPUT DACS IC MICROSYSTEMS ORDERING INFORMATION ICM73X3 P G Device 6 - ICM7363 4 - ICM7343 2 - ICM7323 Rev. A8 G = RoHS Compliant Lead-Free package. Blank = Standard package. Non lead-free. Package Q = 16-Lead QSOP ICmic reserves the right to change the specifications without prior notice. 10