M28W320CT M28W320CB 32 Mbit (2Mb x16, Boot Block) Low Voltage Flash Memory PRELIMINARY DATA ■ SUPPLY VOLTAGE – VDD = 2.7V to 3.6V: for Program, Erase and Read – VDDQ = 1.65V or 2.7V: Input/Output option – VPP = 12V: optional Supply Voltage for fast Program ■ µBGA ACCESS TIME – 2.7V to 3.6V: 90ns – 2.7V to 3.6V: 100ns ■ PROGRAMMING TIME: TSOP48 (N) 12 x 20mm µBGA47 (GB) 8 x 6 solder balls – 10µs typical – Double Word Programming Option ■ PROGRAM/ERASE CONTROLLER (P/E.C.) ■ COMMON FLASH INTERFACE ■ MEMORY BLOCKS Figure 1. Logic Diagram – Parameter Blocks (Top or Bottom location) – Main Blocks ■ BLOCK PROTECTION UNPROTECTION VDD VDDQ VPP – All Blocks protected at Power Up – Any combination of blocks can be protected – WP for block locking ■ SECURITY 21 A0-A20 – 64-bit user Programmable OTP cells W – 64-bit unique device identifier E – One Parameter Block Permanently Lockable G ■ AUTOMATIC STAND-BY MODE ■ PROGRAM and ERASE SUSPEND RP ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK WP ■ 20 YEARS of DATA RETENTION – Defectivity below 1ppm/year ■ ELECTRONIC SIGNATURE 16 DQ0-DQ15 M28W320CT M28W320CB VSS AI03521 – Manufacturer Code: 20h – Top Device Code, M28W320CT: 88BAh – Bottom Device Code, M28W320CB: 88BBh May 2000 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/42 M28W320CT, M28W320CB Figure 2. µBGA Connections (Top view through package) 1 2 3 A A13 A11 A8 B A14 A10 W C A15 A12 A9 D A16 DQ14 DQ5 E VDDQ DQ15 F VSS DQ7 4 5 6 7 8 V PP WP A19 A7 A4 RP A18 A17 A5 A2 A20 A6 A3 A1 DQ11 DQ2 DQ8 E A0 DQ6 DQ12 DQ3 DQ9 DQ0 VSS DQ13 DQ4 VDD DQ10 DQ1 G AI02686 Figure 3. TSOP Connections A15 A14 A13 A12 A11 A10 A9 A8 NC A20 W RP VPP WP A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 Table 1. Signal Names 48 12 M28W320CT 37 13 M28W320CB 36 24 25 AI03522 2/42 A16 VDDQ VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 A0-A20 Address Inputs DQ0-DQ7 Data Input/Output, Command Inputs DQ8-DQ15 Data Input/Output E Chip Enable G Output Enable W Write Enable RP Reset WP Write Protect VDD Supply Voltage VDDQ Power Supply for Input/Output Buffers VPP Optional Supply Voltage for Fast Program & Erase VSS Ground NC Not Connected Internally M28W320CT, M28W320CB Table 2. Absolute Maximum Ratings (1) Symbol Value Unit Ambient Operating Temperature (2) –40 to 85 °C TBIAS Temperature Under Bias –40 to 125 °C TSTG Storage Temperature –55 to 155 °C –0.6 to VDDQ+0.6 V Supply Voltage –0.6 to 4.1 V Program Voltage –0.6 to 13 V TA V IO VDD, VDDQ V PP Parameter Input or Output Voltage Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. Depends on range. DESCRIPTION The M28W320C is a 32 Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a Word-byWord basis. The device is offered in the TSOP48 (10 x 20mm) and the µBGA47, 0.75mm ball pitch packages. When shipped, all bits of the M28W320C are in the 1 state. The array matrix organisation allows each block to be erased and reprogrammed without affecting other blocks. All blocks are protected against programming and erase at Power UP. Blocks can be unprotected to make changes in the application and then reprotected. A parameter block ”Security Block” can be permanently protected against programming and erase in order to increase the data security. Each block can be programmed and erased over 100,000 cycles. VDDQ allows to drive the I/O pin down to 1.65V. An optional 12V VPP power supply is provided to speed up the program phase at customer production line environment. An internal Command Interface (C.I.) decodes the instructions to access/modify the memory content. The Program/Erase Controller (P/E.C.) automatically executes the algorithms taking care of the timings necessary for program and erase operations. Verification is performed too, unburdening the microcontroller, while the Status Register tracks the status of the operation. The following instructions are executed by the M28W320C: Read Array, Read Electronic Signature, Read Status Register, Clear Status Register, Program, Double Word Program, Block Erase, Program/Erase Suspend, Program/Erase Resume, CFI Query, Block Protect, Block Lock, Block Unprotect, Protection Program. Organisation The M28W320C is organised as 2 Mbit by 16 bits. A0-A20 are the address lines; DQ0-DQ15 are the Data Input/Output. Memory control is provided by Chip Enable E, Output Enable G and Write Enable W inputs. The Program and Erase operations are managed automatically by the P/E.C. Block protection against Program or Erase provides additional data security. Memory Blocks The device features an asymmetrical blocked architecture. The M28W320C has an array of 71 blocks: 8 Parameter Blocks of 4 KWord and 63 Main Blocks of 32 KWord. M28W320CT has the Parameter Blocks at the top of the memory address space while the M28W320CB locates the Parameter Blocks starting from the bottom. The memory maps are shown in Tables 3 and 4. All Blocks are protected at power up. Instruction are provided to protect, unprotect any block in the application. A second register locks the protection status while WP is low (see Block Protection Description). Each block can be erased separately. Erase can be suspended in order to perform either read or program in any other block and then resumed. Program can be suspended to read data in any other block and then resumed. The architecture includes a 128 bits Protection register that are divided into Two 64-bits segment. In the first one, starting from address 81h to 84h, is written a unique device number, while the second one, starting from 85h to 88h, is programmable by the user. The user programmable segment can be permanently protected programming the bit.1 of the Protection Lock Register (see protection register and Security Block). The parameter block (# 0) is a security block. It can be permanently protected by the user programming the bit.2 of the Protection Lock Register (see protection register and Security Block). 3/42 M28W320CT, M28W320CB Table 3. Top Boot Block Addresses, M28W320CT 36 32 120000-127FFF 35 32 118000-11FFFF # Size (KWord) Address Range 34 32 110000-117FFF 70 4 1FF000-1FFFFF 33 32 108000-10FFFF 32 100000-107FFF 69 4 1FE000-1FEFFF 32 68 4 1FD000-1FDFFF 31 32 0F8000-0FFFFF 32 0F00000-F7FFF 67 4 1FC000-1FCFFF 30 66 4 1FB000-1FBFFF 29 32 0E8000-0EFFFF 32 0E0000-0E7FFF 65 4 1FA000-1FAFFF 28 64 4 1F9000-1F9FFF 27 32 0D8000-0DFFFF 1F8000-1F8FFF 26 32 0D0000-0D7FFF 25 32 0C8000-0CFFFF 24 32 0C0000-0C7FFF 32 0B8000-0BFFFF 63 4 62 32 1F0000-1F7FFF 61 32 1E8000-1EFFFF 60 32 1E0000-1E7FFF 23 59 32 1D8000-1DFFFF 22 32 0B0000-0B7FFF 32 0A8000-0AFFFF 58 32 1D0000-1D7FFF 21 57 32 1C8000-1CFFFF 20 32 0A0000-0A7FFF 1C0000-1C7FFF 19 32 098000-09FFFF 18 32 090000-097FFF 17 32 088000-08FFFF 32 080000-087FFF 56 32 55 32 1B8000-1BFFFF 54 32 1B0000-1B7FFF 53 32 1A8000-1AFFFF 16 52 32 1A0000-1A7FFF 15 32 078000-07FFFF 14 32 070000-077FFF 51 32 198000-19FFFF 50 32 190000-197FFF 13 32 068000-06FFFF 32 060000-067FFF 058000-05FFFF 49 32 188000-18FFFF 12 48 32 180000-187FFF 11 32 178000-17FFFF 10 32 050000-057FFF 32 048000-04FFFF 47 32 46 32 170000-177FFF 9 45 32 168000-16FFFF 8 32 040000-047FFF 7 32 038000-03FFFF 44 32 160000-167FFF 43 32 158000-15FFFF 6 32 030000-037FFF 5 32 028000-02FFFF 4 32 020000-027FFF 32 018000-01FFFF 42 32 150000-157FFF 41 32 148000-14FFFF 40 32 140000-147FFF 3 39 32 138000-13FFFF 2 32 010000-017FFF 130000-137FFF 1 32 008000-00FFFF 128000-12FFFF 0 32 000000-007FFF 38 37 4/42 32 32 M28W320CT, M28W320CB Table 4. Bottom Boot Block Addresses, M28W320CB # Size (KWord) Address Range 70 32 1F8000-1FFFFF 69 32 1F0000-1F7FFF 68 32 1E8000-1EFFFF 67 32 1E0000-1E7FFF 66 32 1D8000-1DFFFF 65 32 1D0000-1D7FFF 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 1B8000-1BFFFF 61 32 1B0000-1B7FFF 60 32 1A8000-1AFFFF 59 32 1A0000-1A7FFF 58 32 198000-19FFFF 57 32 190000-197FFF 56 32 188000-18FFFF 55 32 180000-187FFF 54 32 178000-17FFFF 53 32 170000-177FFF 52 32 168000-16FFFF 51 32 160000-167FFF 50 32 158000-15FFFF 49 32 150000-157FFF 48 32 148000-14FFFF 47 32 140000-147FFF 46 32 138000-13FFFF 45 32 130000-137FFF 44 32 128000-12FFFF 43 32 120000-127FFF 42 32 118000-11FFFF 41 32 110000-117FFF 40 32 108000-10FFFF 39 32 100000-107FFF 38 37 32 32 0F8000-0FFFFF 0F0000-0F7FFF 36 32 35 32 0E8000-0EFFFF 0E0000-0E7FFF 34 32 0D8000-0DFFFF 33 32 0D0000-0D7FFF 32 32 0C8000-0CFFFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF 22 32 078000-07FFFF 21 32 070000-077FFF 20 32 068000-06FFFF 19 32 060000-067FFF 18 32 058000-05FFFF 17 32 050000-057FFF 16 32 048000-04FFFF 15 32 040000-047FFF 14 32 038000-03FFFF 13 32 030000-037FFF 12 32 028000-02FFFF 11 32 020000-027FFF 10 32 018000-01FFFF 9 32 010000-017FFF 8 32 008000-00FFFF 7 4 007000-007FFF 6 4 006000-006FFF 5 4 005000-005FFF 4 4 004000-004FFF 3 4 003000-003FFF 2 4 002000-002FFF 1 4 001000-001FFF 0 4 000000-000FFF 5/42 M28W320CT, M28W320CB SIGNAL DESCRIPTIONS See Figure 1 and Table 1. Address Inputs (A0-A20). The address signals are inputs driven with CMOS voltage levels. They are latched during a write operation. Data Input/Output (DQ0-DQ15). The data inputs, a word to be programmed or a command to the C.I., are latched on the Chip Enable E or Write Enable W rising edge, whichever occurs first. The data output from the memory Array, the Electronic Signature, the block protection status or Status Register is valid when Chip Enable E and Output Enable G are active. The output is high impedance when the chip is deselected, the outputs are disabled or RP is tied to VIL. Commands are issued on DQ0-DQ7. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. E at VIH deselects the memory and reduces the power consumption to the stand-by level. E can also be used to control writing to the command register and to the memory array, while W remains at VIL. Output Enable (G). The Output Enable controls the data Input/Output buffers. Write Enable (W). This input controls writing to the Command Register, Input Address and Data latches. Write Protect (WP). This input gives an additional hardware protection level against program or erase when pulled at VIL, as described in the Block Protection description. Reset Input (RP). The RP input provides hardware reset of the memory. When RP is at VIL, the 6/42 memory is in reset mode: the outputs are put to High-Z and the current consumption is minimised. When RP is at VIH, the device is in normal operation. Exiting reset mode the device enters read array mode. VDD Supply Voltage (2.7V to 3.6V). VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). It ranges from 2.7V to 3.6V. VDDQ Supply Voltage (1.65V to VDD). VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from V DD. VDDQ can be tied to VDD or it can use a separate supply. It can be powered either from 1.65V to VDD. VPP Program Supply Voltage (12V). VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to 3.6V) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions. VPP value is only sampled at the beginning of a program or erase; a change in its value after the operation has been started does not have any effect and program or erase are carried on regularly. If VPP is used in the range 11.4V to 12.6V acts as a power supply pin. In this condition VPP value must be stable until P/E algorithm is completed (see Table 24 and 25). VSS Ground. VSS is the reference for all the voltage measurements. M28W320CT, M28W320CB DEVICE OPERATIONS Four control pins rule the hardware access to the Flash memory: E, G, W, RP. The following operations can be performed using the appropriate bus cycles: Read, Write the Command of an Instruction, Output Disable, Stand-by, Reset (see Table 5). Read. Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the CFI. Both Chip Enable (E) and Output Enable (G) must be at VIL in order to perform the read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output independently of the device selection. The data read depend on the previous command written to the memory (see instructions RD, RSIG, RSR, RCFI). Read Array is the default state of the device when exiting reset or after power-up. Write. Write operations are used to give Commands to the memory or to latch Input Data to be programmed. A write operation is initiated when Chip Enable E and Write Enable W are at VIL with Output Enable G at VIH. Commands, Input Data and Addresses are latched on the rising edge of W or E, whichever occur first. Output Disable. The data outputs are high impedance when the Output Enable G is at VIH. Stand-by. Stand-by disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable E is at VIH and the device is in read mode. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable G or Write Enable W inputs. If E switches to VIH during program or erase operation, the device enters in stand-by when finished. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high impedance. The memory is in Reset mode when RP is at VIL. The power consumption is reduced to the stand-by level, independently from the Chip Enable E, Out-put Enable G or Write Enable W inputs. If RP is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid as it has been compromised by the aborted operation. (1) Table 5. User Bus Operations E G W RP WP VPP DQ0-DQ15 Read VIL VIL VIH VIH X Don’t Care Data Output Write VIL VIH V IL VIH X VDD or VPPH Data Input Output Disable VIL VIH VIH VIH X Don’t Care Hi-Z Stand-by VIH X X VIH X Don’t Care Hi-Z X X X VIL X Don’t Care Hi-Z Operation Reset Note: 1. X = VIL or VIH, VPPH = 12V ± 5%. Table 6. Read Electronic Signature (RSIG Instruction) Code Device E G W A0 A1 A2-A7 A8-A11 A12-A20 DQ0-DQ7 DQ8-DQ15 VIL VIL VIH VIL VIL 0 Don’t Care Don’t Care 20h 00h M28W320CT VIL VIL VIH VIH VIL 0 Don’t Care Don’t Care BAh 88h M28W320CB VIL VIL VIH VIH VIL 0 Don’t Care Don’t Care BBh 88h Manufact. Code Device Code 7/42 M28W320CT, M28W320CB Table 7. Read Block Signature (RSIG Instruction) Block Status E G W A0 A1 A2-A7 Protected Block VIL V IL VIH VIL VIH 0 Unprotected Block VIL V IL VIH VIL VIH Locked Block VIL V IL VIH VIL VIH A8-A11 A12-A20 DQ0 DQ1 DQ2-DQ15 Don’t Care Block Address 1 0 00h 0 Don’t Care Block Address 0 0 00h 0 Don’t Care Block Address X (1) 1 00h Note: 1. A Locked Block can be protected ”DQ0 = 1” or unprotected ”DQ0 = 0”; see Block protection section. Table 8. Read Protection Register and Protection Register Lock (RSIG Instruction) Word E G W A0-A7 A8-A20 DQ0 DQ1 DQ2 Lock VIL V IL VIH 80h Don’t Care 0 OTP Prot. data Security prot. data 00h 00h Unique Id 0 VIL V IL VIH 81h Don’t Care ID data ID data ID data ID data ID data Unique Id 1 VIL V IL VIH 82h Don’t Care ID data ID data ID data ID data ID data Unique Id 2 VIL V IL VIH 83h Don’t Care ID data ID data ID data ID data ID data Unique Id 3 VIL V IL VIH 84h Don’t Care ID data ID data ID data ID data ID data OTP 0 VIL V IL VIH 85h Don’t Care OTP data OTP data OTP data OTP data OTP data OTP 1 VIL V IL VIH 86h Don’t Care OTP data OTP data OTP data OTP data OTP data OTP 2 VIL V IL VIH 87h Don’t Care OTP data OTP data OTP data OTP data OTP data OTP 3 VIL V IL VIH 88h Don’t Care OTP data OTP data OTP data OTP data OTP data 8/42 DQ3-DQ7 DQ8-DQ15 M28W320CT, M28W320CB INSTRUCTIONS AND COMMANDS Sixteen instructions are available (see Tables 9 and 10) to perform Read Memory Array, Read Status Register, Read Electronic Signature, CFI Query, Erase, Program, Double Word Program, Clear Status Register, Program/Erase Suspend, Program/Erase Resume, Block Protect, Block Unprotect, Block Lock and Protection Register Program. Status Register output may be read at any time, during programming or erase, to monitor the progress of the operation. An internal Command Interface (C.I.) decodes the instructions while an internal Program/Erase Controller (P/E.C.) handles all timing and verifies the correct execution of the Program and Erase instructions. P/E.C. provides a Status Register whose bits indicate operation and exit status of the internal algorithms. The Command Interface is reset to Read Array when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequence must be followed exactly. Any invalid combination of commands will reset the device to Read Array. Read (RD) The Read instruction consists of one write cycle (refer to Device Operations section) giving the command FFh. Next read operations will read the addressed location and output the data. When a device reset occurs, the memory is in Read Array as default. Read Status Register (RSR) The Status Register indicates when a program or erase operation is complete and the success or failure of operation itself. Issue a Read Status Register Instruction (70h) to read the Status Register content. The Read Status Register instruction may be issued at any time, also when a Program/ Erase operation is ongoing. The following Read operations output the content of the Status Register. The Status Register is latched on the falling edge of E or G signals, and can be read until E or G returns to VIH. Either E or G must be toggled to update the latched data. Additionally, any read attempt during program or erase operation will automatically output the content of the Status Register. Read Electronic Signature (RSIG) The Read Electronic Signature instruction consists of one write cycle (refer to Device Operations section) giving the command 90h. A subsequent read will output the Manufacturer Code, the Device Code, the Block protection Status, or the Protection Register. See Tables 6, 7 and 8 for the valid address. The Electronic Signature can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of M28W320C. CFI Query (RCFI) The Common Flash Interface Query mode is entered by writing 98h. Next read operations will read the CFI data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at this address 81h. This area can be accessed only in read mode and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode (refer to the Common Flash Interface section). Table 9. Commands Hex Code Command 00h Invalid/Reserved 10h Alternative Program Set-up 20h Erase Set-up 30h Double Word Program Set-up 40h Program Set-up 50h Clear Status Register 70h Read Status Register 90h or 98h Read Electronic Signature, or CFI Query B0h Program/Erase Suspend D0h Program/Erase Resume, Erase Confirm or Unprotect Confirm FFh Read Array 01h Protect Confirm 2Fh Lock Confirm C0h Protection Program 60h Protection Set-up 9/42 M28W320CT, M28W320CB Table 10. Instructions Mnemonic RD RSR Instruction Read Memory Array Read Status Register Cycles 1st Cycle Operat. Addr. (1) 2nd Cycle Data Addr. Data Data Status Register 1+ Write X FFh Read (2) Read Address 1+ Write X 70h Read (2) X RSIG Read Electronic Signature 1+ Write X RCFI Read CFI 1+ Write 55h EE Erase 2 Write X 20h Write PG Program 2 Write X 40h or 10h Write Address 3 Write X 30h Write Address 1 1 Write X 50h 1 Write X B0h 1 Write X D0h Double Word Program Clear Status CLRS (5) Register Program/ PES Erase Suspend Program/ PER Erase Resume DPG (4) 3nd Cycle Operat. Signature 90h or Read (2) 98h Address (3) 98h or Read (2) 90h BP Block Protect 2 Write X 60h Write BU Block Unprotect 2 Write X 60h Write BL Block Lock 2 Write X 60h Write PRP Protection Register Program 2 Write X C0h Write CFI Address Block Address Operat. Addr. Data Write Address 2 Data Input Data Query D0h Data Input Data Input Block Address Block Address Block Address D0h Address Data Input 01h 2Fh Note: 1. X = Don’t Care. 2. The first cycle of the RD, RSR, RSIG or RCFI instruction is followed by read operations in the memory array or special register. Any number of read cycle can occur after one command cycle. 3. The signature address recognized are listed in the Tables 6, 7 and 8. 4. Address 1 and Address 2 must be consecutive address differing only for address bit A0. 5. A read cycle after a CLSR instruction will output the memory array. Erase (EE) Block erasure sets all the bits within the selected block to ’1’. One block at a time can be erased. It is not necessary to program the block with 00h as the P/E.C. will do it automatically before erasing. This instruction uses two write cycles. The first command written is the Erase Set up command 20h. The second command is the Erase Confirm command D0h. An address within the block to be erased is given and latched into the memory during the input of the second command. If the second command given is not an erase confirm, the status register bits b4 and b5 are set and the instruction aborts. Read operations output the status register after erasure has started. 10/42 Status Register bit b7 returns ’0’ while the erasure is in progress and ’1’ when it has completed. After completion the Status Register bit b5 returns ’1’ if there has been an Erase Failure. Status register bit b1 returns ’1’ if the user is attempting to program a protected block. Status Register bit b3 returns a ’1’ if VPP is below VPPLK. Erase aborts if RP turns to VIL. As data integrity cannot be guaranteed when the erase operation is aborted, the erase must be repeated. A Clear Status Register instruction must be issued to reset b1, b3, b4 and b5 of the Status Register. During the execution of the erase by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. M28W320CT, M28W320CB Table 11. Protection States (1) Current State (2) Next State After Event (3) (WP, DQ1, DQ0) Program/Erase Allowed Protect Unprotect Lock WP transition 100 yes 101 100 111 000 101 no 101 100 111 001 110 yes 111 110 111 011 111 no 111 110 111 011 000 yes 001 000 011 100 001 no 001 000 011 101 011 no 011 011 011 111 or 110 (4) Note: 1. All blocks are protected at power-up, so the default configuration is 001 or 101 according to WP status. 2. Current state and Next state gives the protection status of a block. The protection status is defined by the write protect pin and by DQ1 (= 1 for a locked block) and DQ0 (= 1 for a protected block) as read in the Read Electronic Signature instruction with A1 = VIH and A0 = VIL. 3. Next state is the protection status of a block after a Protect or Unprotect or Lock command has been issued or after WP has changed its logic value. 4. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. Table 12. Status Register Bits Mnemonic P/ECS ESS ES PS VPPS PSS BPS Bit 7 6 5 4 3 2 1 Name Logic Level ’1’ Ready ’0’ Busy ’1’ Suspended ’0’ In progress or Completed ’1’ Erase Error ’0’ Erase Success ’1’ Program Error ’0’ Program Success ’1’ VPP Invalid, Abort ’0’ VPP OK Program Suspend Status ’1’ Suspended ’0’ In Progress or Completed Block Protection Status ’1’ P/E.C. Status Erase Suspend Status Erase Status Program Status V PP Status ’0’ 0 Definition Note Indicates the P/E.C. status, check during Program or Erase, and on completion before checking bits b4 or b5 for Program or Erase Success. On an Erase Suspend instruction P/ECS and ESS bits are set to ’1’. ESS bit remains ’1’ until an Erase Resume instruction is given. ES bit is set to ’1’ if P/E.C. has applied the maximum number of erase pulses to the block without achieving an erase verify. PS bit set to ’1’ if the P/E.C. has failed to program a word. VPPS bit is set if the VPP voltage is below VPPLK when a Program or Erase instruction is executed. VPP is sampled only at the beginning of the erase/program operation. On a Program Suspend instruction P/ECS and PSS bits are set to ’1’. PSS remains ’1’ until a Program Resume Instruction is given. Program/Erase on protected Block, BPS bit is set to ’1’ if a Program or Erase Abort operation has been attempted on a protected block. No operation to protected blocks Reserved Note: Logic level ’1’ is High, ’0’ is Low. 11/42 M28W320CT, M28W320CB Program (PG) The memory array can be programmed word-byword. This instruction uses two write cycles. The first command written is the Program Set-up command 40h (or 10h). A second write operation latches the Address and the Data to be written and starts the P/E.C. Read operations output the Status Register content after the programming has started. The Status Register bit b7 returns ’0’ while the programming is in progress and ’1’ when it has completed. After completion the Status register bit b4 returns ’1’ if there has been a Program Failure. Status register bit b1 returns ’1’ if the user is attempting to program a protected block. Status Register bit b3 returns a ’1’ if VPP is below VPPLK. Programming aborts if RP goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruction must be issued to reset b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. Double Word Program (DPG) This feature is offered to improve the programming throughput, writing a page of two adjacent words in parallel.The two words must differ only for the address A0. Programming should not be attempted when VPP is not at VPPH. The operation can also be executed if V PP is below VPPH but result could be uncertain. This instruction uses three write cycles. The first command written is the Double Word Program Set-Up command 30h. A second write operation latches the Address and the Data of the first word to be written, the third write operation latches the Address and the Data of the second word to be written and starts the P/E.C. Read operations output the Status Register content after the programming has started. The Status Register bit b7 returns ’0’ while the programming is in progress and ’1’ when it has completed. After completion the Status register bit b4 returns ’1’ if there has been a Program Failure. Status register bit b1 returns ’1’ if the user is attempting to program a protected block. Status Register bit b3 returns a ’1’ if VPP is below VPPLK. Programming aborts if RP goes to V IL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be erased and reprogrammed. A Clear Status Register instruc- 12/42 tion must be issued to reset b4, b3 and b1 of the Status Register. During the execution of the program by the P/E.C., the memory accepts only the RSR (Read Status Register) and PES (Program/Erase Suspend) instructions. Clear Status Register (CLRS) The Clear Status Register uses a single write operation which clears bits b1, b3, b4 and b5 to 0. Its use is necessary before any new operation when an error has been detected. The Clear Status Register is executed writing the command 50h. Program/Erase Suspend (PES) Program/Erase suspend is accepted only during the Program Erase instruction execution. When a Program/Erase Suspend command is written to the C.I., the P/E.C. freezes the Program/Erase operation. Program/Erase Resume (PER) continues the Program/Erase operation. Program/Erase Suspend consists of writing the command B0h without any specific address. The Status Register bit b2 is set to ’1’ (within 5µs) when the program has been suspended. b2 is set to ’0’ in case the program is completed or in progress. The Status Register bit b6 is set to ’1’ (within 30µs) when the erase has been suspended. b6 is set to ’0’ in case the erase is completed or in progress. The valid commands while erase is suspended are: Program/Erase Resume, Program, Read Array, Read Status Register, Read Identifier, CFI Query, Block Protect, Block Unprotect, Block Lock and Protection Program. The user can protect the Block being erased issuing the Block Protect, Block Lock or Protection Program commands. In this case the protection status bit will change immediately, but when the erase is resumed, the operation will complete The valid commands while program is suspended are: Program/ Erase Resume, Read Array, Read Status Register, Read Identifier, CFI Query. During program/erase suspend mode, the chip can be placed in a pseudo-stand-by mode by taking E to VIH This reduces active current consumption. Program/Erase is aborted if RP turns to VIL. Program/Erase Resume (PER) If a Program/Erase Suspend instruction was previously executed, the program/erase operation may be resumed by issuing the command D0h. The status register bit b2/b6 is cleared when program/ erase resumes. Read operations output the status register after the program/erase is resumed. M28W320CT, M28W320CB The suggested flow charts for programs that use the programming, erasure and program/erase suspend/resume features of the memories are shown from Figures 11, 12, 13, 14 and 15. Protection Register Program (PRP) The Protection Register Program uses two write cycles. The first command written is the protection program command C0h. The second write operation latches the Address and the Data to be written to the Protection Register (see Protection Register and Security Block) and start the PE/C. Read operations output the Status Register content after the programming has started. The 64 bits user programmable Segment (85h to 88h) are programmed 16 bits at a time, it can be protected by the user programming bit 1 of the Protection Lock register. The bit 1 of the Protection Lock register protect the bit 2 of the Protection Lock Register. Writing the bit 2 of the Protection Lock Register will result in a permanent protection of the Security Block. Attempting to program a previously protected protection Register will result in a status register error (bit 1 and bit 4 of the status register will be set to ’1’). The protection of the Protection Register and/or the Security Block is not reversible. The Protection Register Program cannot be suspended. Block Protect (BP) The BP instruction use two write cycles. The first command written is the protection setup 60h. The second command is block Protect command 01h. The address within the block being protected must be given in order to write the protection state. If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. To read the status register write the RSR command. Block Unprotect (BU) The instruction use two write cycles. The first command written is the protection setup 60h. The second command is block Unprotect command d0h. The address within the block being unprotected must be given in order to write the unprotection state. If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. To read the status register write the RSR command. Block Lock (BL) The instruction use two write cycles. The first command written is the protection setup 60h. The second command is block Lock command 2Fh. The address within the block being Locked must be given in order to write the Locking state. If the second command is not recognized by the C.I the bit 4 and bit 5 of the status register will be set to indicate a wrong sequence of commands. To read the status register write the RSR command. Table 13. Program, Erase Times and Program/Erase Endurance Cycles (TA = 0 to 70°C or –40 to 85°C; VDD = 2.7V to 3.6V) M28W320C Parameter Test Condition s Word Program Double Word Program Main Block Program Unit Typ (1) Max VPP = VDD 10 200 µs VPP = 12V ±5% 10 200 µs VPP = 12V ±5% 0.16 5 sec VPP = VDD 0.32 5 sec VPP = 12V ±5% 0.02 4 sec VPP = VDD 0.04 4 sec VPP = 12V ±5% 1 10 sec VPP = VDD 1 10 sec VPP = 12V ±5% 0.8 10 sec VPP = VDD 0.8 10 sec Min Parameter Block Program Main Block Erase Parameter Block Erase Program/Erase Cycles (per Block) 100,000 cycles Note: TA = 25 °C. 13/42 M28W320CT, M28W320CB BLOCK PROTECTION The M28W320C provide a flexible protection of all the memory providing the protection unprotection and locking of any blocks. All blocks are protected at power-up. Each block of the array has two levels of protection against program or erase operation. The first level is set by the Block Protect instruction; a protected block cannot be programmed or erased until a Block Unprotect instruction is given for that block. A second level of protection is set by the Block Lock instruction, and requires the use of the WP pin, according to the following scheme: – when WP is at VIH, the Lock status is overridden and all blocks can be protected or unprotected; – when WP is at VIL, Lock status is enabled; the locked blocks are protected, regardless of their previous protect state, and protection status cannot be changed. Blocks that are not locked can still change their protection status; – the lock status is cleared for all blocks at power up. The protection and lock status can be monitored for each block using the Read Electronic Signature (RSIG) instruction. Protected blocks will output a ’1’ on DQ0 and locked blocks will output a ’1’ in DQ1. PROTECTION REGISTER and SECURITY BLOCK The M28W320C features a 128-bit protection register and a security Block in order to increase the protection of a system design. The Protection Register is divided in two 64-bit segment. The first segment (81h to 84h) is a unique device number, while the second one (85h to 88h) can be programmed by the user. When shipped the user programmable segment is read at ’1’. It can be only programmed at ’0’; The user programmable segment can be protected writing the bit 1 of the Protection Lock register (80h). The bit 1 protect also the bit 2 of the Protection Lock Register. The M28W320C feature a security Block. The security Block is located at 1FF000-1FFFFF (M28W320CT) or at 000000000FFF (M28W320CB) of the device. This block can be permanently protected by the user programming the bit 2 of the Protection Lock Register. The protection Register and the Protection Lock Register can be read using the RSIG command. A subsequent read in the address starting from 80h to 88h, the user will retrieve respectively the Protection Lock register, the unique device number segment and the OTP user programmable register segment (see Table 8). Figure 4. Security Block Memory Map 88h User Programmable OTP 85h 84h Parameter Block # 0 Unique device number 81h 80h Protection Register Lock 2 1 0 AI03523 14/42 M28W320CT, M28W320CB POWER CONSUMPTION The M28W320C puts itself in one of four different modes depending on the status of the control signals: Active Power, Automatic Stand-by, Stand-by and Reset define decreasing levels of current consumption. These allow the memory power to be minimised, in turn decreasing the overall system power consumption. As different recovery time are linked to the different modes, please refer to the AC timing Table to design your system. Active Power When E is at VIL and RP is at VIH, the device is in active mode. Refer to DC Characteristics to get the values of the current supply consumption. Automatic Stand-by Automatic Stand-by provides a low power consumption state during read mode. Following a read operation, after a delay close to the memory access time, the device enters Automatic Standby: the Supply Current is reduced to ICC1 values. The device keeps the last output data stable, till a new location is accessed. Stand-by or Reset Refer to the Device Operations section. Power Up The Supply voltage VDD and the Program Supply voltage VPP can be applied in any order. The memory Command Interface is reset on power up to Read Memory Array, but a negative transition of Chip Enable E or a change of the addresses is required to ensure valid data outputs. Care must be taken to avoid writes to the memory when VDD is above VLKO. Writes can be inhibited by driving either E or W to VIH. The memory is disabled if RP is at VIL. Supply Rails Normal precautions must be taken for supply voltage decoupling, each device in a system should have the VDD and V PP rails decoupled with a 0.1µF capacitor close to the VDD and VPP pins.The PCB trace widths should be sufficient to carry the required V PP program and erase currents. 15/42 M28W320CT, M28W320CB COMMON FLASH INTERFACE (CFI) The Common Flash Interface (CFI) specification is a JEDEC approved, standardised data structure that can be read from the Flash memory device. CFI allows a system software to query the flash device to determine various electrical and timing parameters, density information and functions supported by the device. CFI allows the system to easily interface to the Flash memory, to learn about its features and parameters, enabling the software to configure itself when necessary. Tables 14, 15, 16, 17, 18 and 19 show the address used to retrieve each data. The CFI data structure gives information on the device, such as the sectorization, the command set and some electrical specifications. Tables 14, 15, 16 and 17 show the addresses used to retrieve each data. The CFI data structure contains also a security area; in this section, a 64 bit unique security number is written, starting at address 81h. This area can be accessed only in read mode and there are no ways of changing the code after it has been written by ST. Write a read instruction to return to Read mode. Refer to the CFI Query instruction to understand how the M28W320C enters the CFI Query mode. Table 14. Query Structure Overview Offset Sub-section Name Description 00h Reserved Reserved for algorithm-specific information 10h CFI Query Identification String Command set ID and algorithm data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout P Primary Algorithm-specific Extended Query table Additional information specific to the Primary Algorithm (optional) A Alternate Algorithm-specific Extended Query table Additional information specific to the Alternate Algorithm (optional) Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 15, 16, 17, 18 and 19. Query data are always presented on the lowest order data outputs. Table 15. CFI Query Identification String Offset Data Description 00h 0020h 01h 88BAh - top 88BBh - bottom 02h-0Fh reserved 10h 0051h Query Unique ASCII String ”QRY” 11h 0052h Query Unique ASCII String ”QRY” 12h 0059h Query Unique ASCII String ”QRY” 13h 0003h 14h 0000h Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm 15h offset = P = 0035h 16h 0000h 17h 0000h 18h 0000h 19h value = A = 0000h 1Ah 0000h Manufacturer Code Device Code Reserved Address for Primary Algorithm extended Query table Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported (note: 0000h means none exists) Address for Alternate Algorithm extended Query table note: 0000h means none exists Note: Query data are always presented on the lowest - order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. 16/42 M28W320CT, M28W320CB Table 16. CFI Query System Interface Information Offset Data 1Bh 0027h VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV 1Ch 0036h VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 mV 00B4h VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Note: This value must be 0000h if no VPP pin is present 1Eh 00C6h VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Note: This value must be 0000h if no VPP pin is present 1Fh 0004h Typical timeout per single byte/word program (multi-byte program count = 1), 2n µs (if supported; 0000h = not supported) 20h 0000h Typical timeout for maximum-size multi-byte program or page write, 2n µs (if supported; 0000h = not supported) 21h 000Ah Typical timeout per individual block erase, 2n ms (if supported; 0000h = not supported) 22h 0000h Typical timeout for full chip erase, 2n ms (if supported; 0000h = not supported) 23h 0004h Maximum timeout for byte/word program, 2n times typical (offset 1Fh) (0000h = not supported) 24h 0000h Maximum timeout for multi-byte program or page write, 2n times typical (offset 20h) (0000h = not supported) 25h 0003h Maximum timeout per individual block erase, 2n times typical (offset 21h) (0000h = not supported) 26h 0000h Maximum timeout for chip erase, 2n times typical (offset 22h) (0000h = not supported) 1Dh Description 17/42 M28W320CT, M28W320CB Table 17. Device Geometry Definition Offset Word Mode Data 27h 0016h 28h 0001h 29h 0000h 2Ah 0000h 2Bh 0000h 2Ch 0002h Description Device Size = 2n in number of bytes Flash Device Interface Code description: Asynchronous x16 Maximum number of bytes in multi-byte program or page = 2n Number of Erase Block Regions within device bit 7 to 0 = x = number of Erase Block Regions Note:1. x = 0 means no erase blocking, i.e. the device erases at once in ”bulk.” 2. x specifies the number of regions within the device containing one or more contiguous Erase Blocks of the same size. For example, a 128KB device (1Mb) having blocking of 16KB, 8KB, four 2KB, two 16KB, and one 64KB is considered to have 5 Erase Block Regions. Even though two regions both contain 16KB blocks, the fact that they are not contiguous means they are separate Erase Block Regions. 3. By definition, symmetrically block devices have only one blocking region. M28W320CT M28W320CT Erase Block Region Information 2Dh 001Eh 2Eh 0000h 2Fh 0000h 30h 0001h 31h 0007h 32h 0000h 33h 0020h 34h 0000h M28W320CB M28W320CB 2Dh 0007h 2Eh 0000h 2Fh 0020h 30h 0000h 31h 001Eh 32h 0000h 33h 0000h 34h 0001h 18/42 bit 31 to 16 = z, where the Erase Block(s) within this Region are (z) times 256 bytes in size. The value z = 0 is used for 128 byte block size. e.g. for 64KB block size, z = 0100h = 256 => 256 * 256 = 64K bit 15 to 0 = y, where y+1 = Number of Erase Blocks of identical size within the Erase Block Region: e.g. y = D15-D0 = FFFFh => y+1 = 64K blocks [maximum number] y = 0 means no blocking (# blocks = y+1 = ”1 block”) Note: y = 0 value must be used with number of block regions of one as indicated by (x) = 0 M28W320CT, M28W320CB Table 18. Primary Algorithm-Specific Extended Query Table Offset Data (P)h = 35h 0050h 0052h Description Primary Algorithm extended Query table unique ASCII string “PRI” 0049h (P+3)h = 38h 0031h Major version number, ASCII (P+4)h = 39h 0030h Minor version number, ASCII (P+5)h = 3Ah 0006h Extended Query table contents for Primary Algorithm 0000h (P+7)h 0000h (P+8)h 0000h (P+9)h = 3Eh 0001h bit 0 bit 1 bit 2 bit 3 bit 4 bit 31 to 5 Supported Functions after Suspend Read Array, Read Status Register and CFI Query are always supported during Erase or Program operation bit 0 bit 7 to 1 (P+A)h = 3Fh 0000h (P+B)h 0000h Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend (1 = Yes, 0 = No) Lock/Unlock supported (1 = Yes, 0 = No) Quequed Erase supported (1 = Yes, 0 = No) Reserved; undefined bits are ‘0’ Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are ‘0’ Block Lock Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block Lock Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are ‘0’ (P+C)h = 41h 0027h VDD Logic Supply Optimum Program/Erase voltage (highest performance) bit 7 to 4 bit 3 to 0 (P+D)h = 42h 00C0h VPP Supply Optimum Program/Erase voltage bit 7 to 4 bit 3 to 0 (P+E)h 0000h HEX value in volts BCD value in 100 mV HEX value in volts BCD value in 100 mV Reserved Table 19. Security Code Area Offset Data 80h 00XX 81h XXXX 82h XXXX 83h XXXX 84h XXXX 85h XXXX 86h XXXX 87h XXXX 88h XXXX Description Protection Register Lock 64 bits: unique device number 64 bits: User Programmable OTP 19/42 M28W320CT, M28W320CB Table 20. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VDD = VDDQ = 2.7V to 3.6V) Symbol Parameter Typ Max Unit ±1 µA Output Leakage Current 0V≤ VOUT ≤V DDQ ±10 µA ICC Supply Current (Read) ICC1 Supply Current (Stand-by or Automatic Stand-by) ICC2 Supply Current (Reset) ICC4 Min Input Leakage Current ILO ICC3 Test Conditio n 0V≤ V IN ≤ VDDQ ILI Supply Current (Program) Supply Current (Erase) E = VSS, G = VIH, f = 5MHz 10 20 mA E = VDDQ ± 0.2V, RP = VDDQ ± 0.2V 15 50 µA RP = VSS ± 0.2V 15 50 µA Program in progress VPP = 12V ± 5% 10 20 mA Program in progress VPP = VDD 10 20 mA Erase in progress VPP = 12V ± 5% 5 20 mA Erase in progress VPP = VDD 5 20 mA E = VDDQ ± 0.2V, Erase suspended 50 µA ICC5 Supply Current (Program/Erase Suspend) IPP Program Current (Read or Stand-by) VPP > VDD 400 µA IPP1 Program Current (Read or Stand-by) VPP ≤ VDD 5 µA IPP2 Program Current (Reset) RP = VSS ± 0.2V 5 µA Program in progress VPP = 12V ± 5% 10 mA Program in progress VPP = VDD 5 µA Erase in progress VPP = 12V ± 5% 10 mA Erase in progress VPP = VDD 5 µA 0.4 V IPP3 IPP4 VIL VIH Program Current (Program) Program Current (Erase) Input Low Voltage Input High Voltage –0.5 V DDQ ≥ 2.7V V DDQ ≥ 2.7V –0.5 0.8 V V DDQ –0.4 VDDQ +0.4 V 0.7 VDDQ VDDQ +0.4 V 0.1 V VOL Output Low Voltage IOL = 100µA, VDD = VDD min, VDDQ = VDDQ min VOH Output High Voltage IOH = –100µA, VDD = VDD min, VDDQ = VDDQ min V PP1 Program Voltage (Program or Erase operations) 1.65 3.6 V VPPH Program Voltage (Program or Erase operations) 11.4 12.6 V VPPLK Program Voltage (Program and Erase lock-out) 1 V V LKO VDD Supply Voltage (Program and Erase lock-out) 2 V 20/42 VDDQ –0.1 V M28W320CT, M28W320CB Table 21. AC Measurement Conditions Input Rise and Fall Times Figure 6. AC Testing Load Circuit ≤ 10ns VDDQ/2 0 to VDDQ Input Pulse Voltages Input and Output Timing Ref. Voltages VDDQ/2 1N914 3.3kΩ Figure 5. AC Testing Input Output Waveform DEVICE UNDER TEST VDDQ OUT CL = 50pF VDDQ/2 0V CL includes JIG capacitance AI00610 AI00609B Table 22. Capacitance (1) (TA = 25 °C, f = 1 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF Note: 1. Sampled only, not 100% tested. 21/42 M28W320CT, M28W320CB Table 23. Read AC Characteristics (1) (TA = 0 to 70°C or –40 to 85°C) M28W320C Symbol Alt Parameter 90 100 VDD = 2.7V to 3.6V VDDQ = 2.7V min V DD = 2.7V to 3.6V VDDQ = 1.65V min Min Max Min Unit Max tAVAV tRC Address Valid to Next Address Valid tAVQV tACC Address Valid to Output Valid tAXQX (2) tOH Address Transition to Output Transition 0 0 ns tEHQX (2) tOH Chip Enable High to Output Transition 0 0 ns tEHQZ (2) tHZ Chip Enable High to Output Hi-Z 25 30 ns tELQV (3) tCE Chip Enable Low to Output Valid 90 100 ns tELQX (2) tLZ Chip Enable Low to Output Transition 0 0 ns tGHQX (2) tOH Output Enable High to Output Transition 0 0 ns tGHQZ (2) tDF Output Enable High to Output Hi-Z 25 30 ns tGLQV (3) tOE Output Enable Low to Output Valid 30 35 ns tGLQX (2) tOLZ Output Enable Low to Output Transition tPHQV tPWH Reset High to Output Valid tPLPH (2,4) tRP Note: 1. 2. 3. 4. 22/42 Reset Pulse Width 90 100 90 0 ns 100 0 150 100 See AC Testing Measurement conditions for timing measurements. Sampled only, not 100% tested. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. The device Reset is possible but not guaranteed if tPLPH < 100ns. ns 150 100 ns ns ns POWER-UP AND STANDBY Note: Write Enable (W) = High. RP DQ0-DQ15 G E A0-A20 ADDRESS VALID AND CHIP ENABLE tPHQV tGLQX OUTPUTS ENABLED tGLQV tELQV tELQX tAVQV VALID tAVAV DATA VALID VALID STANDBY tGHQZ tGHQX tEHQZ tEHQX AI02688 tAXQX M28W320CT, M28W320CB Figure 7. Read AC Waveforms 23/42 M28W320CT, M28W320CB Table 24. Write AC Characteristics, Write Enable Controlled (1) (TA = 0 to 70°C or –40 to 85°C) M28W320C Symbol Alt Parameter 90 100 VDD = 2.7V to 3.6V VDDQ = 2.7V min VDD = 2.7V to 3.6V VDDQ = 1.65V min Min Max Min Unit Max tAVAV tWC Write Cycle Time 90 100 ns tAVWH tAS Address Valid to Write Enable High 50 50 ns tDVWH tDS Data Valid to Write Enable High 50 50 ns tELWL tCS Chip Enable Low to Write Enable Low 0 0 ns tPHWL tPS Reset High to Write Enable Low 90 100 ns tPLPH (2, 3) tRP Reset Pulse Width 100 100 ns µs tPLRH (2, 4) Reset Low to Program/Erase Abort tQVVPL (2, 5) Output Valid to VPP Low 0 0 ns Data Valid to Write Protect Low 0 0 ns 200 200 ns tQVWPL 30 30 t VPHWH (2) tVPS VPP High to Write Enable High tWHAX tAH Write Enable High to Address Transition 0 0 ns tWHDX tDH Write Enable High to Data Transition 0 0 ns tWHEH tCH Write Enable High to Chip Enable High 0 0 ns Write Enable High to Output Enable Low 30 30 ns tWHGL tWHWL tWPH Write Enable High to Write Enable Low 30 30 ns tWLWH tWP Write Enable Low to Write Enable High 50 50 ns Write Protect High to Write Enable High 50 50 ns tWPHWH tAVAV tWC Write Cycle Time 90 100 ns tAVWH tAS Address Valid to Write Enable High 50 50 ns Note: 1. 2. 3. 4. 5. 24/42 See AC Testing Measurement conditions for timing measurements. Sampled only, not 100% tested. The device Reset is possible but not guaranteed if tPLPH < 100ns. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode. Applicable if VPP is seen as a logic input (VPP < 3.6V). VPP WP RP DQ0-DQ15 W G E A0-A20 tPHWL tWLWH COMMAND POWER-UP AND SET-UP COMMAND tDVWH tELWL tWHDX tWHWL tWHEH CMD or DATA CONFIRM COMMAND OR DATA INPUT tVPHWH tWPHWH tAVWH VALID tAVAV tWHQV tWHGL tWHAX PROGRAM OR ERASE STATUS REGISTER READ 1st POLLING tQVVPL AI03574 tQVWPL STATUS REGISTER M28W320CT, M28W320CB Figure 8. Write AC Waveforms, W Controlled 25/42 M28W320CT, M28W320CB Table 25. Write AC Characteristics, Chip Enable Controlled (1) (TA = 0 to 70°C or –40 to 85°C) M28W320C 90 Symbol Alt Parameter 100 V DD = 2.7V to 3.6V VDD = 2.7V to 3.6V V DDQ = 2.7V min VDDQ = 1.65V min Min Max Min Unit Max tAVAV tWC Write Cycle Time 90 100 ns tAVEH tAS Address Valid to Chip Enable High 50 50 ns tDVEH tDS Data Valid to Chip Enable High 50 50 ns t EHAX tAH Chip Enable High to Address Transition 0 0 ns tEHDX tDH Chip Enable High to Data Transition 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low 30 30 ns Chip Enable High to Output Enable Low 30 30 ns t EHGL tEHWH tWH Chip Enable High to Write Enable High 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High 50 50 ns tPHEL tPS Reset High to Chip Enable Low 90 100 ns tPLPH (2, 3) tRP Reset Pulse Width 100 100 ns tPLRH (2, 4) Reset Low to Program/Erase Abort t QVVPL (2, 5) tQVWPL 30 30 µs Output Valid to VPP Low 0 0 ns Data Valid to Write Protect Low 0 0 ns 200 200 ns tVPHEH (2) tVPS VPP High to Chip Enable High t WLEL tCS Write Enable Low to Chip Enable Low 0 0 ns Write Protect High to Chip Enable High 50 50 ns tWPHEH tAVAV tWC Write Cycle Time 90 100 ns tAVEH tAS Address Valid to Chip Enable High 50 50 ns Note: 1. 2. 3. 4. 5. 26/42 See AC Testing Measurement conditions for timing measurements. Sampled only, not 100% tested. The device Reset is possible but not guaranteed if tPLPH < 100ns. The reset will complete within 100ns if RP is asserted while not in Program nor in Erase mode. Applicable if VPP is seen as a logic input (VPP < 3.6V). VPP WP RP DQ0-DQ15 E G W A0-A20 tPHEL tELEH COMMAND POWER-UP AND SET-UP COMMAND tDVEH tWLEL tEHDX tEHEL tEHWH CMD or DATA CONFIRM COMMAND OR DATA INPUT tVPHEH tWPHEH tAVEH VALID tAVAV tEHQV tEHGL tEHAX PROGRAM OR ERASE STATUS REGISTER READ 1st POLLING tQVVPL AI03575 tQVWPL STATUS REGISTER M28W320CT, M28W320CB Figure 9. Write AC Waveforms, E Controlled 27/42 M28W320CT, M28W320CB Figure 10. Reset AC Waveform Reset during Read Mode tPLPH RP tPHQV Reset during Program with tPLPH ≤ tPLRH Abort Complete tPLRH tPHWL tPHEL tPLPH RP Reset during Program/Erase with tPLPH > tPLRH Abort Complete Reset tPLRH tPHWL tPHEL tPLPH RP AI03537 28/42 M28W320CT, M28W320CB Figure 11. Program Flowchart and Pseudo Code Start Write 40h or 10h Command Program instruction: – write 40h or 10h command – write Address & Data (memory enters read status state after the Program instruction) Write Address & Data do: – read status register (E or G must be toggled) if PES instruction given execute suspend program loop NO Read Status Register Suspend b7 = 1 NO YES Suspend Loop while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: – error handler NO Program Error (1, 2) If b4 = 1, Program error: – error handler NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 If b1 = 1, Program to protected block error: – error handler YES End AI03538 Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 29/42 M28W320CT, M28W320CB Figure 12. Double Word Program Flowchart and Pseudo Code Start Write 30h Command DPG instruction: – write 30h command – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) (memory enters read status state after the Program instruction) Write Address 1 & Data 1 (3) Write Address 2 & Data 2 (3) NO Read Status Register Suspend b7 = 1 NO YES Suspend Loop while b7 = 1 YES b3 = 0 do: – read status register (E or G must be toggled) if PES instruction given execute DPG suspend loop NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: – error handler NO Program Error (1, 2) If b4 = 1, Program error: – error handler NO Program to Protected Block Error (1, 2) YES b4 = 0 YES b1 = 0 If b1 = 1, Program to protected block error: – error handler YES End AI03539 Note: 1. Status check of b1 (Protected Block), b3 (VPP Invalid) and b4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for address bit A0. 30/42 M28W320CT, M28W320CB Figure 13. Program Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command PES instruction: – write B0h command do: – read status register (E or G must be toggled) Write 70h Command Read Status Register b7 = 1 NO while b7 = 1 YES b2 = 1 NO Program Complete If b2 = 0 Program completed YES Write a read Command Read data from another address Write D0h Command Write FFh Command Program Continues Read Data PER instruction: – write D0h command to resume the program – if the program operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued). AI03540 31/42 M28W320CT, M28W320CB Figure 14. Erase Flowchart and Pseudo Code Start Write 20h Command EE instruction: – write 20h command – write Block Address (A12-A20) & command D0h (memory enters read status state after the EE instruction) Write Block Address & D0h Command Read Status Register Suspend b7 = 1 do: – read status register (E or G must be toggled) if PES instruction given execute suspend erase loop NO NO YES Suspend Loop while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1) NO Command Sequence Error (1) If b3 = 1, VPP invalid error: – error handler YES b4, b5 = 0 If b4, b5 = 1, Command sequence error: – error handler YES b5 = 0 NO Erase Error (1) If b5 = 1, Erase error: – error handler YES b1 = 0 NO Erase to Protected Block Error (1) If b1 = 1, Erase to protected block error: – error handler YES End AI03541 Note: 1. If an error is found, the Status Register must be cleared (CLRS instruction) before further P/E.C. operations. 32/42 M28W320CT, M28W320CB Figure 15. Erase Suspend & Resume Flowchart and Pseudo Code Start Write B0h Command PES instruction: – write B0h command do: – read status register (E or G must be toggled) Write 70h Command Read Status Register b7 = 1 NO while b7 = 1 YES b6 = 1 NO Erase Complete If b6 = 0, Erase completed YES Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock Write D0h Command Write FFh Command Erase Continues Read Data PER instruction: – write D0h command to resume erasure – if the erase operation completed then this is not necessary. The device returns to Read Array as normal (as if the Program/Erase suspend was not issued). AI03542 33/42 M28W320CT, M28W320CB Figure 16. Command Interface and Program Erase Controller Flowchart (a) WAIT FOR COMMAND WRITE (1) NO 90h YES READ SIGNATURE NO 98h YES CFI QUERY NO 70h YES READ STATUS 50h NO YES CLEAR STATUS NO 60h YES BP/BU/BL SET-UP D C0h NO YES READ STATUS PRP SET-UP 40h or 10h READ ARRAY NO YES YES READY (2) PROGRAM SET-UP PRP 30h NO YES C NO B DPG SET-UP YES C NO D0h NO YES 2Fh NO BP/BU/BL COMMAND ERROR ERASE SET-UP BLOCK UNPROTECT NO FFh YES YES D0h BLOCK PROTECT NO YES B 01h 20h BLOCK LOCK NO YES A ERASE COMMAND ERROR AI03543 Note: 1. If no command is written, the Command Interface remains in its previous valid state. Upon power-up, on exit from power-down or if VDD falls below V LKO, the Command Interface defaults to Read Array mode. 2. P/E.C. status (Ready or Busy) is read on Status Register bit 7. 34/42 M28W320CT, M28W320CB Figure 17. Command Interface and Program Erase Controller Flowchart (b) A B ERASE YES (READ STATUS) READY (2) NO B0h ERASE NO SUSPENDED NO YES READ STATUS YES ERASE SUSPEND READ STATUS YES 70h YES NO READ SIGNATURE YES NO 90h NO CFI QUERY YES READY (2) READ STATUS 98h NO PROGRAM SET-UP YES c 40h or 10h NO DPG SET-UP YES c 30h NO C0h YES PRP SET-UP NO BP/BU/BL SET-UP YES D PRP READY (2) NO YES B 60h NO READ ARRAY NO D0h YES ERASE RESUME (READ STATUS) AI03544 Note: 2. P/E. C. status (Ready or Busy) is read on Status Register bit 7. 35/42 M28W320CT, M28W320CB Figure 18. Command Interface and Program Erase Controller Flowchart (c) C B PROGRAM YES (READ STATUS) READY (2) NO B0h NO YES READ STATUS PROGRAM SUSPEND NO PROGRAM SUSPENDED YES YES READY (2) NO READ STATUS YES READ STATUS 70h NO READ SIGNATURE YES 90h NO CFI QUERY YES 98h NO READ ARRAY NO D0h YES PROGRAM RESUME (READ STATUS) AI03545 Note: 2. P/E. C. status (Ready or Busy) is read on Status Register bit 7. 36/42 M28W320CT, M28W320CB Table 26. Ordering Information Scheme Example: M28W320CT 90 N 6 T Device Type M28 Operating Voltage W = VDD = 2.7V to 3.6V; V DDQ = 1.65V or 2.7V Device Function 320C = 32 Mbit (2 Mb x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Random Speed 90 = 90 ns 100 = 100 ns Package N = TSOP48: 12 x 20 mm GB = µBGA47: 0.75 mm pitch Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Optio n T = Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. Table 27. Daisy Chain Ordering Scheme Example: M28W320C -GB T Device Type M28W320C Daisy Chain -GB = µBGA47: 0.75 mm pitch Optio n T = Tape & Reel Packing For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you. 37/42 M28W320CT, M28W320CB Table 28. Revision History Date Revision Details February 2000 First Issue 04/19/00 Daisy Chain part numbering defined µBGA Package Outline diagram change (Figure 20) µBGA Chain diagrams, Package and PCB Connection re-designed (Figure 21, 22) 05/17/00 µBGA Package Outline diagram and Package Mechanical Data change (Figure 20, Table 30) 38/42 M28W320CT, M28W320CB Table 29. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data mm inches Symbol Typ Min Max A Typ Min 1.20 Max 0.0472 A1 0.05 0.15 0.0020 0.0059 A2 0.95 1.05 0.0374 0.0413 B 0.17 0.27 0.0067 0.0106 C 0.10 0.21 0.0039 0.0083 D 19.80 20.20 0.7795 0.7953 D1 18.30 18.50 0.7205 0.7283 E 11.90 12.10 0.4685 0.4764 – – – – L 0.50 0.70 0.0197 0.0276 α 0° 5° 0° 5° N 48 e 0.50 0.0197 48 CP 0.10 0.0039 Figure 19. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline A2 1 N e E B N/2 A D1 CP D DIE C TSOP-a A1 α L Drawing is not to scale. 39/42 M28W320CT, M28W320CB Table 30. µBGA47 - 8 x 6 balls, 0.75 mm pitch, Package Mechanical Data mm inch Symbol Typ Min Max A Typ Min 1.000 A1 0.0394 0.180 0.0071 A2 0.700 – – 0.0276 – – b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 10.500 10.450 10.550 0.4134 0.4114 0.4154 D1 3.750 – – 0.1476 – – ddd 0.080 0.0031 e 0.750 – – 0.0295 – – E 6.390 6.340 6.440 0.2516 0.2496 0.2535 E1 5.250 – – 0.2067 – – FD 3.375 – – 0.1329 – – FE 0.570 – – 0.0224 – – Figure 20. µBGA47 - 8 x 6 balls, 0.75 mm pitch, Bottom View Package Outline E E1 SE FE FD SD D D1 e BALL ”A1” ddd e b A2 A A1 BGA-G06 Drawing is not to scale. 40/42 Max M28W320CT, M28W320CB Figure 21. µBGA47 Daisy Chain - Package Connections (Top view through package) 1 2 3 4 5 6 7 8 A B C D E F AI03295 Figure 22. µBGA47 Daisy Chain - PCB Connections (Top view through package) 1 2 3 4 5 6 7 8 START POINT A B C D E END POINT F AI3296 41/42 M28W320CT, M28W320CB Information furnished is believed to be accurate and reliable. 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