Fairchild FAN6793NY Highly integrated, dual-pwm combination controller Datasheet

FAN6791 / FAN6793
Highly Integrated, Dual-PWM Combination Controller
Features
Description
ƒ High-Voltage Startup
ƒ Low Operating Current
ƒ Interleaved Stand-by PWM / Forward PWM Switching
ƒ Green Mode Stand-by PWM / Forward PWM
ƒ Linearly Decreasing Stand-by PWM Frequency to
The highly integrated FAN6791/3 dual PWM
combination controller provides several features to
enhance the performance of converters.
20kHz
ƒ Remote On / Off
ƒ AC Brownout Protection
ƒ Forward PWM with Soft-Start
ƒ Frequency Hopping to Reduce EMI Emissions
ƒ Cycle-by-Cycle Current Limiting for Stand-by PWM /
Forward PWM
ƒ Leading-Edge Blanking for Stand-by PWM / Forward
PWM
ƒ Synchronized Slope Compensation for Stand-by
PWM / Forward PWM
ƒ GATE Output Maximum Voltage Clamp
ƒ VDD Over-Voltage Protection (OVP)
ƒ VDD Under-Voltage Lockout (UVLO)
ƒ Internal Open-Loop Protection for Stand-by PWM /
Forward PWM
ƒ Constant Power Limit for Stand-by PWM / Forward
PWM
To minimize standby power consumption, a proprietary
green-mode function provides off-time modulation to
linearly decrease the switching frequency at light-load
conditions. To avoid acoustic-noise problems, the
minimum PWM frequency is set above 20KHz. This
green-mode function enables the power supply to meet
international power conservation requirements. With the
internal high-voltage startup circuitry, the power loss
due to bleeding resistors is also eliminated. To further
reduce
power
consumption,
FAN6791/3
is
manufactured using the CMOS process, which allows
an operating current of only 6mA.
FAN6791/3 integrates a frequency-jittering function
internally to reduce EMI emissions of a power supply
with minimum line filters. The built-in synchronized slope
compensation achieves stable peak-current-mode
control. The proprietary internal line compensation
ensures constant output power limit.
FAN6791/3 provides many protection functions,
including brownout protection, cycle-by-cycle current
limiting, and an internal open-loop protection circuit to
ensure safety should an open-loop or output shortcircuit failure occur. PWM output is disabled until VDD
drops below the UVLO lower limit when the controller
restarts. As long as VDD exceeds ~24.5V, the internal
OVP circuit is triggered.
Applications
General-purpose switch-mode power supplies and
flyback power converters, including:
ƒ PC-ATX Power Supplies
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
April 2009
Part
Number
OPWM
Operating
Maximum Duty Temperature Range
Eco Status
Package
Packing
Method
FAN6791NY
48%
-40°C to +105°C
Green
16-pin Dual In-Line
Package (DIP)
Tube
FAN6793NY
65%
-40°C to +105°C
Green
16-pin Dual In-Line
Package (DIP))
Tube
FAN6791MY
48%
-40°C to +105°C
Green
16-pin Small Out-Line
Package (SOP)
Tape & Reel
FAN6793MY
65%
-40°C to +105°C
Green
16-pin Small Out-Line
Package (SOP)
Tape & Reel
For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html.
Application Diagram
FAN6791 / FAN6793 —Highly Integrated, Dual-PWM Combination Controller
Ordering Information
Figure 1. Typical Application
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
2
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Block Diagram
Pattern
Generator
Figure 2. Function Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
3
F – Fairchild Logo
Z – Plant Code
X – 1-Digit Year Code
Y – 1-Digit Week Code
TT – 2-Digit Die Run Code
T – Package Type (N:DIP, M:SOP)
P – Y: Green Package
M – Manufacture Flow Code
Figure 3. Top Mark
Pin Configuration
Figure 4. Pin Configuration (Top View)
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
4
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Marking Information
Pin #
Name
Description
1
HV
For startup, this pin is pulled HIGH to the line input or bulk capacitor via resistors.
2
NC
No connection.
3
GND
Ground.
4
RI
Oscillator Setting. One resistor connected between RI and ground pins determines the switching
frequency (resistance between 12 ~ 47kΩ is recommended). The switching frequency is equal to
[1560 / RI]kHz, where RI is in kΩ. For example, if RI is equal to 24kΩ, then the switching frequency
is 65kHz.
5
FBFYB
Voltage Feedback for Flyback PWM Stage. It is internally pulled HIGH through a 6.5kΩ resistor.
An external opto-coupler from secondary feedback circuit is usually connected to this pin.
6
IFYB
7
FBPWM
Voltage Feedback for Forward PWM Stage. It is internally pulled HIGH through a 6.5kΩ resistor.
An external opto-coupler from secondary feedback circuit is usually connected to this pin.
8
IPWM
PWM Current Sense for Forward PWM Stage. Via a current sense resistor, this pin provides the
control input for peak-current-mode control and cycle-by-cycle current limiting.
9
VREF
Reference voltage. This pin can provide a reference voltage 5V.
10
SS
PWM Soft-Start. During startup, the SS pin charges an external capacitor with a 20µA constant
current source. The voltage on FBPWM is clamped by SS during startup. In the event of a
protection condition occurring and/or forward PWM being disabled, the SS pin quickly discharges.
11
ON/OFF
PWM Remote ON/OFF. Active HIGH. The forward PWM is disabled whenever the voltage at this
pin is lower than 0.8V or the pin is open.
12
PGND
Ground. The power ground.
13
OPWM
Forward PWM Gate Drive. The totem-pole output drive for the forward PWM MOSFET. This pin is
internally clamped under 16V to protect the MOSFET.
14
VDD
15
OFYB
Flyback PWM Gate Drive. The totem-pole output drive for the forward PWM MOSFET. This pin is
internally clamped under 16V to protect the MOSFET.
16
VRMS
Line-Voltage Detection. The pin is used for line compensation, for forward, and brownout
protection.
PWM Current Sense for Flyback PWM Stage. The sensed voltage is used for peak-currentmode control and cycle-by-cycle current limiting.
Power Supply. The internal protection circuit disables PWM output as long as VDD exceeds the
OVP trigger point.
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
5
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Pin Definitions
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. All voltage values, except differential voltage, are given with
respect to GND pin. Stresses beyond those listed under “absolute maximum ratings “may cause permanent damage
to the device.
Symbol
Parameter
Min.
Max.
Unit
VDD
DC Supply Voltage
27
V
VHV
Input Voltage to HV Pin
500
V
VHIGH
OPWM, OFYB, ON/OFF
-0.3
27.0
V
VLOW
Others
-0.3
7.0
V
800
°C/W
PD
Power Dissipation (TA < 50°C)
TJ
Operating Junction Temperature
-40
+125
°C
TSTG
Storage Temperature Range
-55
+150
°C
RΘ j-a
Thermal Resistance (Junction-to-Case)
82.5
°C/W
Lead Temperature (Wave Soldering, 10 Seconds)
+260
°C
TL
ESD
Human Body Model , JEDEC:JESD22-A114
(All Pins Except HV Pin)
3.5
Charged Device Model , JEDEC:JESD22-C101
(All Pins Except HV Pin)
1.5
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
Min.
Max.
Unit
-40
+105
°C
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6
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Absolute Maximum Ratings
VDD=18V; RI=24kΩ;TA =25°C, unless noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
22
V
VDD Section
VDD-OP
Continuously Operating Voltage
IDD ST
Startup Current
VDD – 0.16V
10
50
μA
IDD-OP1
Operating Current 1
VDD=15V, GATE Open
6
10
mA
IDD-OP2
Operating Current 2
VDD=15V, GATE Open,
IREF=10mA
16
20
VTH-ON
Start Threshold Voltage
15
16
17
V
VTH-OFF
Minimum Operating Voltage
9
10
11
V
VTH-OLP
IDD-OLP Off Voltage
6.5
7.5
8.0
V
70
80
100
μA
23.4
24.5
25.5
80
100
120
1.5
2.5
3.5
mA
10
50
μA
1.176
1.200
1.224
V
62
65
68
±3.7
±4.2
±4.7
18
20
22
kHz
12
24
47
kΩ
ITH-OLP
Internal Sink Current
VDD-OVP
VDD Over-voltage Protection
(Turn Off PWM with Delay)
tOVP
VDD Over-Voltage Protection
Debounce
VTH-OLP +0.1V
VDD-OVP=26V
mA
V
μs
HV
ID
Maximum Input Current
VAC=90V(VDC=120V),
VDD=10µF
IHV-CS
Internal Current Source
HV=500V,VDD=15V
Oscillator and Green-Mode Operation
VRI
RI Voltage
fOSC
Normal PWM Frequency
Center Frequency,
RI=24kΩ
Jitter Range
fOSC-G-MIN
RI
Minimum Frequency in Green
Mode
RI=24kΩ
RI Range
RIOPEN
RI Pin Open Protection
If RI > RIOPEN, PWM
Turned Off
RISHORT
RI Pin Short Protection
If RI > RISHORT, PWM
Turned Off
1
kHz
MΩ
6
kΩ
0.85
V
VRMS-UVP-1
+0.21
V
VRMS for AC Brownout Protection
VRMS-OFF
Off Threshold Voltage for AC
Brownout Protection
VRMS-ON
Start Threshold Voltage for AC
Brownout Protection
0.75
0.80
VRMS-UVP-1 VRMS-UVP-1
+0.17
+0.19
AC Brownout Protection
Debounce Time
RI=24kΩ
150
195
240
ms
Reference Voltage
IREF=1mA, CREF=0.1µF
4.75
5.00
5.25
V
△VREF1
Load Regulation of Reference
Voltage
CREF=0.1µF,
IREF=1mA to 10mA
80
mV
△VREF2
Line Regulation of Reference
Voltage
CREF=0.1µF,
VDD=12V to 22V
25
mV
IREF_MAX
Maximum Current
10
15
mA
Output Short Circuit
15
25
mA
tRMS
VREF
VREF
IOS
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
20
www.fairchildsemi.com
7
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Electrical Characteristics
VDD=18V; RI=24kΩ;TA =25°C, unless noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
100
kΩ
ON/OFF
RON/OFF
Impedance ON/OFF Pin
50
VON
High Threshold Level of
Synchronizing Signal
2.4
3.0
3.6
V
VOFF
Low Threshold Level of
Synchronizing Signal
0.8
1.0
1.2
V
130
140
+150
°C
100
110
+120
°C
1/3.75
1/3.20
1/2.75
V/V
4
5
7
kΩ
5.0
5.2
4.2
4.5
Over Temperature Protection (OTP)
TOff
TRestart
Protection Junction
(1)
Temperature
Restart Junction Temperature
(2)
Flyback PWM Stage
FBFYB Feedback Input
AV-FLY
ZFB
VHGH
VFB-OLP
FB Input to Current Comparator
Attenuation
Input Impedance
Output High Voltage
FB Pin Open
FB Open-Loop Trigger Level
V
4.8
V
tOLP
FB Open-Loop Protection Delay
53
56
59
ms
VN
Green Mode Entry FB Voltage
2.4
2.5
2.6
V
SG
Slope of Green-Mode Modulation
60
75
90
Hz/mV
VG
Green Mode Ending FB Voltage
1.8
1.9
2.0
V
VFBPWM for Zero Duty Cycle
(Forward Turn On)
1.2
1.3
1.4
V
VOZ-OFYB
IFYB Current Sense
ZCS
Input Impedance
12
VLIMIT1
Peak Current Limit Threshold
Voltage 1
VRMS=1V
VLIMIT2
Peak Current Limit Threshold
Voltage 2
VRMS=1.5V
Propagation Delay to GATE
Output
VDD=15V, OFYB Drops
to 9V
tPD
tBNK
ΔVSLOPE
0.75
Leading-Edge Blanking Time
Slope Compensation
VS-SCP
Threshold Voltage for SENSE
Short-Circuit Protection
tD-SSCP
Delay Time for SENSE ShortCircuit Protection
Duty=DCYMAX
VSENSE<0.15V,
RI=24KΩ
0.80
kΩ
0.85
VLIMIT1 -0.1
60
V
V
120
ns
200
270
350
ns
0.34
0.37
0.41
V
0.1
0.15
0.2
V
100
180
240
µs
16
18
V
1.5
V
OFYB-GATE Driver
Flyback PWM Gate Output
Clamping Voltage
VDD=22V
VOL-OFYB
Output Voltage Low
VDD=15V; IO=20mA
VOH-OFYB
Output Voltage High
VDD=12V; IO=20mA
8
tR-OFYB
Rising Time
VDD=15V; Gate=1nF;
Gate=2~9V
30
60
120
ns
tF-OFYB
Falling Time
VDD=15V; Gate=1nF;
Gate=9~2V
30
50
90
ns
60
65
70
%
VOFYB-CLAMP
DCYMAX-OFYB Maximum Duty Cycle
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
V
www.fairchildsemi.com
8
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Electrical Characteristics
VDD=18V; RI=24kΩ;TA =25°C, unless noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
1/3.2
1/2.7
1/2.2
V/V
4
5
7
kΩ
5.0
5.2
4.2
4.5
4.8
V
Forward PWM Stage
FBPWM-Feedback Input
AV
FB to Current Comparator
Attenuation
ZFB
Input Impedance
VHGH
VOPEN-PWM
Output High Voltage
FB Pin Open
PWM Open-Loop Protection
Voltage
V
Interval of PWM Open-Loop
Protection Reset
RI=24kΩ
500
600
700
ms
tOPEN-PWM
PWM Open-Loop Protection
Delay Time
RI=24kΩ
80
95
120
ms
VOZ-OPWM
VFBPWM for Zero Duty Cycle
1.2
1.3
1.4
V
120
ns
0.85
V
tOPEN-PWMHICCUP
IPWM-Current Sense
tPD
Propagation Delay to Output –
VLIMIT Loop
VDD=15V, OPWM
Drops to 9V
VLIMIT1
Peak Current Limit Threshold
Voltage 1
VRMS=1V
VLIMIT2
Peak Current Limit Threshold
Voltage 2
VRMS=1.5V
60
0.75
0.80
VLIMIT1-0.1
V
tBNK
Leading-Edge Blanking Time
270
350
450
ns
ΔVSLOPE
Slope Compensation
ΔVs=ΔVSLOPE x (ton/t)
ΔVs: Compensation Voltage
Added to Current Sense
0.40
0.45
0.55
V
16
18
V
1.5
V
OPWM-GATE Driver
Output Voltage Maximum
(Clamp)
VDD=22V
VOL
Output Voltage Low
VDD=15V; IO=100mA
VOH
Output Voltage High
VDD=13V; IO=100mA
8
tR
Rising Time
VDD=15V; CL=5nF;
O/P=2V to 9V
30
60
120
ns
tF
Falling Time
VDD=15V; CL=5nF;
O/P=9V to 2V
30
50
110
ns
47
48
49
60
65
70
17
20
23
µA
470
564
Ω
VOPWM-CLAMP
DCYMAX-OPWM
FAN6791 Maximum Duty Cycle
FAN6793 Maximum Duty Cycle
RI=24kΩ
V
%
Soft Start
ISS
Constant Current Output for
Soft-Start
RD
Discharge Resistance
RI=24kΩ
Notes:
1. When activated, the output is disabled and the latch is turned off.
2. This is the threshold temperature for enabling the output again and resetting the latch after over-temperature
protection has been activated.
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
9
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Electrical Characteristics
10.0
9.0
9.0
8.0
8.0
7.0
7.0
IDDOP1(uA)
IDDST(uA)
10.0
6.0
5.0
4.0
6.0
5.0
4.0
3.0
3.0
2.0
2.0
1.0
1.0
0.0
0.0
-40℃ -25℃ -10℃
5℃
20℃ 35℃ 50℃ 65℃ 80℃
-40℃ -25℃ -10℃
95℃ 110℃ 125℃
Figure 5. Startup Current IDD-ST vs. Temperature
5℃
20℃
35℃ 50℃
65℃
80℃
95℃ 110℃ 125℃
Figure 6. IDD-OP1 vs. Temperature
2.5
20.0
19.0
2.0
18.0
IDMAX(uA)
IDDOP2(uA)
17.0
16.0
15.0
14.0
1.5
1.0
13.0
0.5
12.0
11.0
10.0
0.0
-40℃ -25℃ -10℃
5℃
20℃
35℃
50℃
65℃
80℃
-40℃ -25℃ -10℃
95℃ 110℃ 125℃
Figure 7. IDD-OP2 vs. Temperature
5℃
20℃
35℃
50℃
65℃
80℃
95℃ 110℃ 125℃
Figure 8. ID-MAX vs. Temperature
16.2
10.2
10.1
16.1
10.0
9.9
VDDOFF(V)
VDDON(V)
16.0
15.9
15.8
9.8
9.7
9.6
9.5
15.7
9.4
15.6
9.3
15.5
9.2
-40℃ -25℃ -10℃
5℃
20℃
35℃ 50℃
65℃
80℃
95℃ 110℃ 125℃
-40℃ -25℃ -10℃
Figure 9. VDD-ON vs. Temperature
35℃ 50℃
65℃
80℃
95℃ 110℃ 125℃
64.4
64.3
47.45
64.2
47.40
OFYB Max Duty(%)
OPWM Max Duty(%)
20℃
Figure 10. VDD-OFF vs. Temperature
47.50
47.35
47.30
47.25
47.20
64.1
64.0
63.9
63.8
63.7
63.6
63.5
47.15
63.4
47.10
-40℃ -25℃ -10℃
5℃
63.3
5℃
20℃
35℃
-40℃ -25℃ -10℃
50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 11. OPWM Maximum Duty Cycle
vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
5℃
20℃
35℃ 50℃
65℃
80℃
95℃ 110℃ 125℃
Figure 12. OFYB Maximum Duty Cycle
vs. Temperature
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FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Typical Characteristics
57.5
32.05
57.0
32.00
56.5
TF OPWM(ns)
TR OPWM(ns)
32.10
31.95
31.90
31.85
54.5
54.0
53.5
5℃
20℃ 35℃ 50℃ 65℃
80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃
Figure 13. Rising Time tR-OPWM vs. Temperature
5℃
20℃
35℃ 50℃
65℃
80℃
95℃ 110℃ 125℃
Figure 14. Falling Time tF-OPWM vs. Temperature
27.4
39
27.2
38
37
TF OFYB(ns)
27.0
TR OFYB(ns)
55.0
31.75
-40℃ -25℃ -10℃
26.8
26.6
26.4
26.2
36
35
34
33
32
26.0
31
25.8
30
-40℃ -25℃ -10℃
5℃
20℃
35℃ 50℃
65℃
80℃
95℃ 110℃ 125℃
-40℃ -25℃ -10℃
Figure 15. Rising Time tR-OFYB vs. Temperature
0.802
0.667
0.800
0.666
0.798
0.796
0.794
0.792
0.790
35℃
50℃
65℃
80℃
95℃ 110℃ 125℃
0.665
0.664
0.663
0.662
0.661
0.659
5℃
20℃ 35℃
50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃
Figure 17. IPWM-VLIMIT (VRMS=1V) vs. Temperature
5℃
20℃ 35℃ 50℃ 65℃ 80℃ 95℃ 110℃ 125℃
Figure 18. IPWM-VLIMIT (VRMS=1.5V) vs. Temperature
0.815
0.653
0.652
IFYB Vlimit(V) Vrms=1.5V
0.810
0.805
0.800
0.795
0.790
0.785
0.651
0.650
0.649
0.648
0.647
0.646
0.645
0.644
0.780
-40℃ -25℃ -10℃
20℃
0.660
0.788
-40℃ -25℃ -10℃
5℃
Figure 16. Falling Time tF-OFYB vs. Temperature
IPWM Vlimit(V) Vrms=1.5V
IPWM Vlimit(V) Vrms=1V
55.5
31.80
31.70
IFYB Vlimit(V) Vrms=1V
56.0
0.643
5℃
20℃
35℃
50℃ 65℃ 80℃ 95℃ 110℃ 125℃
-40℃ -25℃ -10℃
Figure 19. IFYB-VLIMIT (VRMS=1V) vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
5℃
20℃
35℃ 50℃ 65℃
80℃
95℃ 110℃ 125℃
Figure 20. IFYB-VLIMIT (VRMS=1.5V)vs. Temperature
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11
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Typical Characteristics
66.3
66.0
66.2
OFYB Frequncy(Hz
OPWM Freqency(Hz)
66.1
65.9
65.8
65.7
65.6
66.0
65.9
65.8
65.7
65.5
-40℃ -25℃ -10℃
66.1
65.6
5℃
20℃
35℃
50℃
65℃
80℃
-40℃ -25℃ -10℃
95℃ 110℃ 125℃
Figure 21. OPWM Frequency vs. Temperature
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
5℃
20℃ 35℃
50℃ 65℃
80℃
95℃ 110℃ 125℃
Figure 22. OFYB Frequency vs. Temperature
www.fairchildsemi.com
12
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Typical Characteristics
The highly integrated FAN6791 / FAN6793 dual-PWM
combination controller provides several features to
enhance the performance of converters.
Proprietary interleave switching synchronizes the
flyback and forward PWM stages. This reduces
switching noise.
The proprietary frequency jittering function for the
flyback and forward PWM stages helps reduce
switching EMI emissions.
Figure 23. Oscillation Frequency in Green Mode
For the flyback and forward PWM, the synchronized
slope compensation ensures the stability of the current
loop under continuous-mode operation. In addition,
FAN6791/3 provides complete protection functions,
such as brownout protection and RI open/short.
Line Voltage Detection (VRMS)
Figure 24 shows a resistive divider with low-pass
filtering for line-voltage detection on VRMS pin. The
VRMS voltage is used for the PFC multiplier and
brownout protection. For brownout protection, when the
VRMS voltage drops below 0.8V, OPFC turns off.
Startup Current
For startup, the HV pin is connected to the line input or
bulk capacitor through external resistor RHV,
recommended as 100KΩ. Typical startup current drawn
from pin HV is 2mA and it charges the hold-up capacitor
through the resistor RHV. When the VDD capacitor level
reaches VDD-ON, the startup current switches off. At this
moment, the VDD capacitor only supplies the FAN6791/3
to maintain the VDD before the auxiliary winding of the
main transformer provides the operating current.
Oscillator Operation
A resistor connected from the RI pin to the GND pin
generates a constant current source for the FAN6791/3
controller. This current is used to determine the center
PWM frequency. Increasing the resistance reduces
PWM frequency. Using a 24KΩ resistor results in a
corresponding 65kHz PWM frequency. The switching
frequency is programmed by the resistor RI connected
between RI pin and GND. The relationship is:
fPWM =
1560
(kHz )
R I (kΩ)
Figure 24. Line-Voltage Detection on VRMS Pin
Remote On/Off
Figure 25 shows the remote on / off function. When the
supervisor FPO pin pulls down and enables the system
by connecting an opto-coupler, VREF applies to the
ON/OFF pin to enable forward PWM stage.
(1)
The range of the PWM oscillation frequency is designed
as 33KHz ~ 130KHz. FAN6791/3 integrates frequency
hopping function internally. The frequency variation
ranges from around 61KHz to 69KHz for a center
frequency 65KHz. The frequency hopping function helps
reduce EMI emission of a power supply with minimum
line filters.
For power saving, flyback PWM stage has a green
mode function. Frequency linearly decreases when VFB
is within VG and VN. Once VFB is lower than VG,
switching frequency disables, and it enters burst mode.
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
Figure 25. Remote On/Off
www.fairchildsemi.com
13
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Functional Description
Constant Power Control
The FAN6791/3 uses interleaved switching to
synchronize the stand-by PWM / forward PWM stages.
This reduces switching noise and spreads the EMI
emissions. Figure 26 shows that an off-time tOFF is
inserted in between the turn-off of the stand-by gate
drives and the turn-on of the forward PWM.
To limit the output power of the converter constantly, a
power-limit function is included. Sensing the converter
input voltage through the VRMS pin, the power limit
function generates a relative peak-current-limit threshold
voltage for constant power control, as shown in Figure 28.
Figure 26. Interleaved Switching
Slope Compensation
The stand-by PWM and forward PWM stage are
designed for flyback and forward power converters.
Peak-current-mode control is used to optimize system
performance. Slope compensation is added to stabilize
the current loop. The FAN6791/3 inserts a
synchronized, positively sloped ramp at each switching
cycle. The positively sloped ramp is represented by the
voltage signal Vs-comp in Figure 27.
Figure 28. Constant Power Control
Protections
The FAN6791/3 provides full protection functions to
prevent the power supply and the load from being
damaged. The protection features include:
VDD Over-Voltage Protection. The stand-by PWM and
forward PWM stages will be disabled whenever the
VDD voltage exceeds the over-voltage threshold.
AC Under-Voltage Protection. The VRMS pin is used to
detect the AC input voltage. When voltage is lower than
the brownout threshold, voltage disables both forward
and stand-by PWM.
RI Pin Open / Short Protection. The RI pin is used to set
the switching frequency and internal current reference.
The stand-by PWM and forward PWM stages are
disabled whenever the RI pin is short or open.
Open-Loop Protection. The stand-by PWM and forward
PWM stages of FAN6791/3 is disabled whenever the
FBFYB / FBPWM pin is open.
Figure 27. Slope Compensation
Gate Drivers
FAN6791/3 output stages are fast totem-pole gate
drivers. The output driver is clamped by an internal 18V
Zener diode to protect the power MOSFET.
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
14
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Interleave Switching
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Reference Circuit
Figure 29. Reference Circuit
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
15
Reference
Component
Reference
Component
C1
C/0.47µF/X2
R18
R/100 1/8W
C2
C/0.47µF/X2
R20
R/1/1W
C3
C/471P/50V
R21
R/1 1/8W
C4
C/471P/50V
R22
R/402 1/8W
C5
C/102P/50V
R23
R/47K 3W
C6
C/102P/50V
R24
R/10K 1/8W
C7
C/102P/50V
R26
R/2K 1/8W
C8
C/472/400V
R29
R/470 1/8W
C9
C/472/400V
R31
R/0.1/2W
C10
C/102P/50V
R35
R/N.A 1/4W
C11
C/10µF/50V
R37
R/20K 1% 1/8W
C12
C/104P/50V
R38
R/20K 1% 1/8W
C20
C/102P/1KV
Q1
2N/60
C21
C/470µF/200V
Q2
9N90
C22
C/470µF/200V
Z3
7D271
C23
C/103P/1KV
Z2
7D271
C24
C/1000µF/10V
Z1
7D561
C25
C/330µF/10V
D1
D/1N4007
C28
C/103P/50V
D2
D/UF107
R1
R/680K 1/4W NC
D3
D/SB540
R2
R/680K 1/4W
D4
D/UF1007
R3
R/51.1K 1/4W
BD1
D/6A/600V
R4
R/51.1K 1/4W
U1
SG6791/3
R5
R/2.4M 1/4W
U2
PC-817
R6
R/2.4M 1/4W
U3
TL431
R7
R/24K 1/8W
U6
PC-817
R8
R/1K 1/8W
R9
R/19.1K 1/8W
R10
R/1K 1/8W
R13
R/100K 1/2W
R14
R/10 1/8W
R15
R/10 1/8W
R17
R/100 1/8W
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
16
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
BOM List
19.68
18.66
16
A
9
6.60
6.09
1
8
(0.40)
TOP VIEW
0.38 MIN
5.33 MAX
8.13
7.62
3.42
3.17
3.81
2.92
2.54
0.35
0.20
0.58 A
0.35
1.78
1.14
15
0
8.69
17.78
SIDE VIEW
NOTES: UNLESS OTHERWISE SPECIFIED
A THIS PACKAGE CONFORMS TO
JEDEC MS-001 VARIATION BB
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH, AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-1994
E) DRAWING FILE NAME: N16EREV1
Figure 30. 16-pin Dual In-Line Package (DIP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
17
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Physical Dimension
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
Physical Dimensions (Continued)
Figure 31. 16-Pin Small Outline Package (SOIC)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
18
FAN6791 / FAN6793 — Highly Integrated, Dual-PWM Combination Controller
© 2008 Fairchild Semiconductor Corporation
FAN6791 / FAN6793 • Rev. 1.0.2
www.fairchildsemi.com
19