LINER LT3751IUFD Capacitor charger controller with regulation Datasheet

LT3751
High Voltage Capacitor
Charger Controller with Regulation
Description
Features
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Charges Any Size Capacitor
Low Noise Output in Voltage Regulation Mode
Stable Operation Under a No-Load Condition
Integrated 2A MOSFET Gate Driver with Rail-to-Rail
Operation for VCC ≤ 8V
Selectable 5.6V or 10.5V Internal Gate Drive
Voltage Clamp
User-Selectable Over/Undervoltage Detect
Easily Adjustable Output Voltage
Primary or Secondary Side Output Voltage Sense
Wide Input VCC Voltage Range (5V to 24V)
Available in 20-Pin QFN 4mm × 5mm and 20-Lead
TSSOP Packages
Applications
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The LT®3751 is a high input voltage capable flyback controller designed to rapidly charge a large capacitor to a
user-adjustable high target voltage set by the transformer
turns ratio and three external resistors. Optionally, a feedback pin can be used to provide a low noise high voltage
regulated output.
The LT3751 has an integrated rail-to-rail MOSFET gate
driver that allows for efficient operation down to 4.75V.
A low 106mV differential current sense threshold voltage
accurately limits the peak switch current. Added protection is provided via user-selectable overvoltage and
undervoltage lockouts for both VCC and VTRANS. A typical
application can charge a 1000µF capacitor to 500V in less
than one second.
The CHARGE pin is used to initiate a new charge cycle and
provides ON/OFF control. The DONE pin indicates when
the capacitor has reached its programmed value and the
part has stopped charging. The FAULT pin indicates when
the LT3751 has shut down due to either VCC or VTRANS
voltage exceeding the user-programmed supply tolerances.
High Voltage Regulated Supply
High Voltage Capacitor Charger
Professional Photoflash Systems
Emergency Strobe
Security/Inventory Control Systems
Detonators
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents including 6518733 and 6636021.
Typical Application
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
+
T1
1:10
330µF
×2
10µF
RVTRANS
RDCM
CHARGE
CLAMP
RVOUT
VCC LT3751
TO
DONE
MICRO
FAULT
374k
UVLO1
VTRANS
475k
OVLO1
374k
UVLO2
VCC
475k
OVLO2
GND
HVGATE
LVGATE
CSP
18.2k
•
•
500V
0 TO 150mA
+
100µF
0.47µF
40.2k
VCC
6mΩ
CSN
715k
500
90
498
84
496
78
494
72
492
66
OUTPUT VOLTAGE
EFFICIENCY
FB
RBG
1.74k
10nF
732Ω
3751 TA01a
490
EFFICIENCY (%)
OFF ON
VCC
24V
10µF
×2
40.2k
Load Regulation and Efficiency
D1
OUTPUT VOLTAGE (V)
VTRANS
24V
0
50
100
LOAD CURRENT (mA)
60
150
3751 TA01b
3751fc
1
LT3751
Absolute Maximum Ratings
(Note 1)
VCC, CHARGE, CLAMP...............................................24V
DONE, FAULT.............................................................24V
LVGATE (Note 8)........................................................24V
VCC – LVGATE..............................................................8V
HVGATE.................................................................Note 9
RBG, CSP, CSN............................................................2V
FB ...............................................................................5V
Current into DONE Pin............................................ ±1mA
Current into FAULT Pin............................................ ±1mA
Current into RV TRANS Pin....................................... ±1mA
Current into RVOUT Pin......................................... ±10mA
Current into RDCM Pin......................................... ±10mA
Current into UVLO1 Pin........................................... ±1mA
Current into UVLO2 Pin.......................................... ±1mA
Current into OVLO1 Pin........................................... ±1mA
Current into OVLO2 Pin........................................... ±1mA
Maximum Junction Temperature........................... 125°C
Operating Temperature Range (Note 2).. –40°C to 125°C
Storage Temperature Range................... –65°C to 125°C
Pin Configuration
RDCM
UVLO1
RVTRANS
TOP VIEW
TOP VIEW
1
20 RDCM
UVLO1
2
19 NC
OVLO1
3
18 RVOUT
OVLO1 1
16 RVOUT
UVLO2
4
17 NC
UVLO2 2
15 NC
OVLO2
5
16 RBG
OVLO2 3
FAULT
6
15 HVGATE
FAULT 4
DONE
7
14 LVGATE
DONE 5
CHARGE
8
13 VCC
CLAMP
9
12 CSP
FB 10
11 CSN
20 19 18 17
14 RBG
21
13 HVGATE
12 LVGATE
FE PACKAGE
20-LEAD PLASTIC TSSOP
TJMAX = 125°C, θJA = 38°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB
11 VCC
9 10
CSP
8
CSN
7
FB
CHARGE 6
CLAMP
21
NC
RVTRANS
UFD PACKAGE
20-PIN (4mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE TIED TO PCB
Order Information
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3751EFE#PBF
LT3751EFE#TRPBF
LT3751FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3751IFE#PBF
LT3751IFE#TRPBF
LT3751FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3751EUFD#PBF
LT3751EUFD#TRPBF
3751
20-Pin (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3751IUFD#PBF
LT3751IUFD#TRPBF
3751
20-Pin (4mm × 5mm) Plastic QFN
–40°C to 125°C
LEAD BASED FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3751EFE
LT3751EFE#TR
LT3751FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3751IFE
LT3751IFE#TR
LT3751FE
20-Lead Plastic TSSOP
–40°C to 125°C
LT3751EUFD
LT3751EUFD#TR
3751
20-Pin (4mm × 5mm) Plastic QFN
–40°C to 125°C
LT3751IUFD
LT3751IUFD#TR
3751
20-Pin (4mm × 5mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
2
3751fc
LT3751
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
VCC Voltage
MIN
MAX
UNITS
l
4.75
24
V
l
4.75
65
V
5.5
0
8
1
mA
µA
35
40
0
45
1
µA
µA
42
47
0
52
1
µA
µA
RVTRANS Voltage
(Note 3)
VCC Quiescent Current
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
RVTRANS, RDCM Quiescent Current
(Note 4)
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
l
(Note 4)
Not Switching, CHARGE = 5V
Not Switching, CHARGE = 0.3V
l
RVOUT Quiescent Current
TYP
UVLO1, UVLO2, OVLO1, OVLO2 Clamp Voltage
Measured at 1mA into Pin, CHARGE = 0V
55
V
RVTRANS, RVOUT, RDCM Clamp Voltage
Measured at 1mA into Pin, CHARGE = 0V
60
V
CHARGE Pin Current
CHARGE = 24V
CHARGE = 5V
CHARGE = 0V
425
60
µA
µA
µA
CHARGE Minimum Enable Voltage
CHARGE Maximum Disable Voltage
l
IVCC ≤ 1µA
V
0.3
l
Minimum CHARGE Pin Low Time
20
One-Shot Clock Period
VOUT Comparator Trip Voltage
Measured at RBG Pin
VOUT Comparator Overdrive
2µs Pulse Width,
RVTRANS, RVOUT = 25kΩ
RBG = 0.83kΩ
DCM Comparator Trip Voltage
Measured as VDRAIN – VTRANS, RDCM = 25kΩ, VCC = 4.75V
(Note 5)
Current Limit Comparator Trip Voltage
FB Pin = 0V
FB Pin = 1.3V
FB Pin Bias Current
Current Sourced from FB Pin, Measured at FB Pin Voltage
FB Pin Voltage
(Note 6)
V
μs
l
32
38
44
l
0.955
0.98
1.005
20
40
mV
350
600
900
mV
100
7
106
11
112
15
mV
mV
64
300
nA
1.19
1.22
1.25
V
1.12
1.16
1.2
V
l
l
l
FB Pin Charge Mode Threshold
FB Pin Charge Mode Hysteresis
1
1.5
(Note 7)
55
FB Pin Overvoltage Mode Threshold
1.29
FB Pin Overvoltage Hysteresis
1.34
μs
V
mV
1.38
V
60
mV
100kΩ to 5V
5
V
DONE Output Signal Low
100kΩ to 5V
40
200
mV
DONE Leakage Current
DONE = 5V
5
200
nA
DONE Output Signal High
FAULT Output Signal High
100kΩ to 5V
5
FAULT Output Signal Low
100kΩ to 5V
40
200
mV
V
FAULT Leakage Current
FAULT = 5V
5
200
nA
UVLO1 Pin Current
UVLO2 Pin Current
UVLO1 Pin Voltage = 1.24V
l
48.5
50
51.5
μA
UVLO2 Pin Voltage = 1.24V
l
48.5
50
51.5
μA
OVLO1 Pin Current
OVLO1 Pin Voltage = 1.24V
l
48.5
50
51.5
μA
OVLO2 Pin Current
OVLO2 Pin Voltage = 1.24V
l
48.5
50
51.5
μA
3751fc
3
LT3751
Electrical Characteristics
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
UVLO1 Threshold
Measured from Pin to GND
UVLO2 Threshold
Measured from Pin to GND
l
1.195
1.225
1.255
V
l
1.195
1.225
1.255
V
OVLO1 Threshold
Measured from Pin to GND
l
1.195
1.225
1.255
V
Measured from Pin to GND
l
OVLO2 Threshold
1.195
1.225
1.255
Gate Minimum High Time
V
0.7
μs
Gate Peak Pull-Up Current
VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
2.0
1.5
A
A
Gate Peak Pull-Down Current
VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
1.2
1.5
A
A
Gate Rise Time
10% → 90%, CGATE = 3.3nF (Note 8)
VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
40
55
ns
ns
Gate Fall Time
90% → 10%, CGATE = 3.3nF (Note 8)
VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
30
30
ns
ns
Gate High Voltage
(Note 8):
VCC = 5V, LVGATE Active
VCC = 12V, LVGATE Inactive
VCC = 12V, LVGATE Inactive, CLAMP Pin = 5V
VCC = 24V, LVGATE Inactive
5
10.5
5.6
10.5
11.5
6.5
11.5
V
V
V
V
180
ns
Gate Voltage Overshoot
500
mV
CLAMP Pin Threshold
1.6
V
Gate Turn-Off Propagation Delay
CGATE = 3.3nF
25mV Overdrive Applied to CSP Pin
4.98
10
5
10
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3751E is guaranteed to meet performance specifications
from 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design
characterization and correlation with statistical process controls. The
LT3751I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: A 60V internal clamp is connected to RVTRANS, RDCM, RVOUT,
UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that
the pin currents do not exceed the Absolute Maximum Ratings.
Note 4: Currents will increase as pin voltages are taken higher than the
internal clamp voltage.
Note 5: Refer to Block Diagram for VTRANS and VDRAIN definitions.
Note 6: Low noise regulation of the output voltage requires a resistive
voltage divider from output voltage to FB pin. FB pin should not be
grounded in this configuration. Refer to the Typical Application diagram for
proper FB pin configuration.
Note 7: The feedback pin has built-in hysteresis that defines the boundary
between charge-only mode and low noise regulation mode.
Note 8: LVGATE should be used in parallel with HVGATE when VCC is less
than or equal to 8V (LVGATE active). When not in use, LVGATE should be
tied to VCC (LVGATE inactive).
Note 9: Do not apply a positive or negative voltage or current source to
HVGATE, otherwise permanent damage may occur.
3751fc
4
LT3751
Typical Performance Characteristics
VCC Pin Current
150
IVTRANS CURRENT (µA)
PIN CURRENT (mA)
CHARGE Pin Current
5
4
3
2
–40°C
25°C
125°C
1
0
4
12
8
16
PIN VOLTAGE (V)
130
125
120
110
10
30
20
40
PIN VOLTAGE (V)
50
1.1
1.1
1.0
0.9
0.8
VCC = 5V
VCC = 12V
VCC = 24V
20 40 60 80
TEMPERATURE (°C)
0.9
0.8
0.7
0
20 40 60 80
TEMPERATURE (°C)
0
20 40 60 80
TEMPERATURE (°C)
250
200
150
100
3751 G07
100µA SINK
10µA SINK
0
20 40 60 80
TEMPERATURE (°C)
100 120
3751 G06
UVLO1 Trip Current
50.5
50.4
UVLO1 PIN CURRENT (µA)
VDRAIN – VTRANS VOLTAGE (V)
100 120
1.232
1.230
1.228
VCC = 5V
VCC = 12V
VCC = 24V
1.226
1.224
–40 –20
24
1mA SINK
0
–40 –20
1.234
100 120
20
300
3751 G05
UVLO1 PIN VOLTAGE (V)
28.4
–40 –20
350
UVLO1 Trip Voltage
VTRANS = 48V
VTRANS = 72V
12
8
16
PIN VOLTAGE (V)
50
0.5
–40 –20
RVTRANS, RVOUT = 25.5k (RTOL = 1%)
RBG = 833Ω
VTRANS = 5V
VTRANS = 12V
VTRANS = 24V
4
400
1.236
29.2
0
DONE, FAULT Pin Voltage Low
1.0
VOUT Comparator Trip Voltage
29.6
–40°C
25°C
125°C
3751 G03
0.6
100 120
30.0
28.8
0
60
VCC = 5V
VCC = 12V
VCC = 24V
3751 G04
30.4
150
50
PIN LOW VOLTAGE (mV)
1.2
CHARGE PIN VOLTAGE (V)
CHARGE PIN VOLTAGE (V)
1.2
0
200
CHARGE Pin Maximum
Disable Voltage
1.3
0.6
–40 –20
250
100
–40°C
25°C
125°C
0
300
3751 G02
CHARGE Pin Minimum
Enable Voltage
0.7
350
135
115
24
20
400
140
3751 G01
30.8
450
RVTRANS, RVOUT, RDCM = 25k
145 VCC, CHARGE = 5V
IVTRANS = IRVTRANS + IRVOUT + IRDCM
6
0
VTRANS Supply Current
CURRENT (µA)
7
0
20 40 60 80
TEMPERATURE (°C)
100 120
3751 G08
50.3
50.2
50.1
50.0
49.9
VCC = 5V
VCC = 12V
VCC = 24V
49.8
49.7
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
100 120
3751 G09
3751fc
5
LT3751
Typical Performance Characteristics
Current Comparator Trip Voltage
(Charge Mode)
VTH = VCSP – VCSN
VTH = VCSP – VCSN
12.8 FB = 1.3V
12.6
VTH VOLTAGE (mV)
VTH VOLTAGE (mV)
108.5
108.0
107.5
107.0
–40 –20
20 40 60 80
TEMPERATURE (°C)
12.2
12.0
11.8
11.6
VCC = 5V
VCC = 12V
VCC = 24V
11.2
11.0
–40 –20
100 120
0
20 40 60 80
TEMPERATURE (°C)
SOURCED PIN CURRENT (nA)
1.219
–40 –20
60
1.168
60
1.160
1.156
40
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
1.152
–40 –20
100 120
0
3751 G13
1.350
1.348
0
20 40 60 80
TEMPERATURE (°C)
100 120
3751 G16
20 40 60 80
TEMPERATURE (°C)
1.9
60.6
1.8
60.2
59.8
59.0
–40 –20
VCC = 5V
VCC = 12V
VCC = 24V
0
20 40 60 80
TEMPERATURE (°C)
100 120
CLAMP Pin Threshold
61.0
59.4
1.346
0
3751 G15
CLAMP PIN VOLTAGE (V)
HYSTERESIS (mV)
1.352
1.344
–40 –20
50
–40 –20
100 120
FB Pin Overvoltage
Mode Hysteresis
VCC = 5V
VCC = 12V
VCC = 24V
1.354
54
3751 G14
FB Pin Overvoltage Mode
Threshold Voltage
1.356
20 40 60 80
TEMPERATURE (°C)
56
52
VCC = 5V
VCC = 12V
VCC = 24V
50
100 120
VCC = 5V
VCC = 12V
VCC = 24V
58
HYSTERESIS (mV)
FB PIN VOLTAGE (V)
70
20 40 60 80
TEMPERATURE (°C)
FB Pin Regulation
Mode Hysteresis
1.164
80
0
3751 G12
FB Pin Regulation
Mode Threshold
MEASURED AT FB PIN VOLTAGE
VCC = 12V
90
100 120
VCC = 5V
VCC = 12V
VCC = 24V
3751 G11
FB Pin Bias Current
100
1.221
1.220
11.4
VCC = 5V
VCC = 12V
VCC = 24V
0
1.222
12.4
3751 G10
FB PIN VOLTAGE (V)
FB Pin Voltage
1.223
13.0
FB PIN VOLTAGE (V)
109.0
Current Comparator Minimum
Trip Voltage (Regulation Mode)
100 120
3751 G17
VCC = 12V
VCC = 24V
1.7
1.6
1.5
1.4
–40
0
40
80
TEMPERATURE (°C)
120
3751 G18
3751fc
6
LT3751
typical performance characteristics
10.8
10.7
10.6
0.64
VCC = 12V
CLAMP = 12V
0.62
5.65
DCM TRIP VOLTAGE (V)
HVGATE PIN VOLTAGE (V)
10.9
5.70
VCC = 24V
CLAMP = 0V
HVGATE PIN VOLTAGE (V)
11.0
DCM Trip Voltage (VDRAIN – VTRANS),
RVTRANS = RDCM = 25kΩ
HVGATE Pin Clamp Voltage
HVGATE Pin Clamp Voltage
5.60
5.55
0
20 40 60 80
TEMPERATURE (°C)
100 120
5.50
–40 –20
0
20 40 60 80
TEMPERATURE (°C)
3751 G19
Pin Functions
0.60
0.58
0.56
10.5
10.4
–40 –20
VTRANS = 5V
VTRANS = 12V
VTRANS = 24V
VTRANS = 48V
100 120
3751 G20
0.54
–40
0
40
80
TEMPERATURE (°C)
120
3751 G21
(TSSOP/QFN)
RVTRANS (Pin 1/Pin 19): Transformer Supply Sense Pin.
Connect a resistor between the RVTRANS pin and the
VTRANS supply. Refer to Table 2 for proper sizing of the
RVTRANS resistor. The minimum operation voltage for
VTRANS is 4.75V.
UVLO1 (Pin 2/Pin 20): VTRANS Undervoltage Lockout Pin.
Senses when VTRANS drops below:
VUVLO1 = 1.225 + 50µA •RUVLO1
and trips the FAULT latch low, disabling switching. After
VTRANS rises above VUVLO1, toggling the CHARGE pin
reactivates switching.
OVLO1 (Pin 3/Pin 1): VTRANS Overvoltage Lockout Pin.
Senses when VTRANS rises above:
VOVLO1 = 1.225 + 50µA •ROVLO1
and trips the FAULT latch low, disabling switching. After
VTRANS drops below VOVLO1, toggling the CHARGE pin
reactivates switching.
UVLO2 (Pin 4/Pin 2): VCC Undervoltage Lockout Pin.
Senses when VCC drops below:
VUVLO2 = 1.225 + 50µA •RUVLO2
and trips the FAULT latch low, disabling switching. After
VCC rises above VUVLO2, toggling the CHARGE pin reactivates switching.
OVLO2 (Pin 5/Pin 3): VCC Overvoltage Lockout Pin. Senses
when VCC rises above:
VOVLO2 = 1.225 + 50µA •ROVLO2
and trips the FAULT latch low, disabling switching. After
VCC drops below VOVLO2, toggling the CHARGE pin reactivates switching.
FAULT (Pin 6/Pin 4): Open Collector Indication Pin. When
either VTRANS or VCC exceeds the user-selected voltage
range, or an internal UVLO condition occurs, a transistor
turns on. The part will stop switching. This pin needs a
proper pull-up resistor or current source.
3751fc
7
LT3751
Pin Functions
DONE (Pin 7/ Pin 5): Open Collector Indication Pin. When
the target output voltage (charge mode) is reached or the
FAULT pin goes low, a transistor turns on. This pin needs
a proper pull-up resistor or current source.
CHARGE (Pin 8/Pin 6): Charge Pin. Initiates a new charge
cycle (charge mode) or enables the part (regulation mode)
when driven higher than 1.5V. Bring this pin below 0.3V
to discontinue charging and put the part into shutdown.
Turn-on ramp rates should be between 10ns to 10ms.
CHARGE pin should not be directly ramped with VCC or
LT3751 may not properly initialize.
CLAMP (Pin 9/Pin 7): Internal Clamp Voltage Selection
Pin. Tie this pin to VCC to activate the internal 5.6V gate
driver clamp. Tie this pin to ground to activate the internal
10.5V gate driver clamp.
FB (Pin 10/Pin 8): Feedback Regulation Pin. Use this pin
to achieve low noise voltage regulation. FB is internally
regulated to 1.22V when a resistive divider is tied from
this pin to the output. FB pin should not float. Tie FB pin
to either a resistor divider or ground.
CSN (Pin 11/Pin 9): Negative Current Sense Pin. Senses
external NMOS source current. Connect to local RSENSE
ground connection for proper Kelvin sensing. The current
limit is set by 106mV/RSENSE.
CSP (Pin 12/Pin 10): Positive Current Sense Pin. Senses
NMOS source current. Connect the NMOS source terminal
and the current sense resistor to this pin. The current
limit is fixed at 106mV/RSENSE in charge mode. The current limit can be reduced to a minimum 11mV/RSENSE in
regulation mode.
VCC (Pin 13/Pin 11): Input Supply Pin. Must be locally bypassed with high grade (X5R or better) ceramic capacitor.
The minimum operating voltage for VCC is 4.75V.
below 8V. The internal gate driver will drive the voltage to
the VCC rail. When operating VCC higher than 8V, tie this
pin directly to VCC.
HVGATE (Pin 15/Pin 13): High Voltage Gate Pin. Connect
NMOS gate terminal to this pin for all VCC operating voltages. Internal gate driver will drive the voltage to within
VCC – 2V during each switch cycle.
RBG (Pin 16/Pin 14): Bias Generation Pin. Generates a bias
current set by 0.98V/RBG. Select RBG to achieve desired
resistance for RDCM, RVOUT, and RVTRANS.
NC (Pins 17, 19/Pins 15, 18): No Connection.
RVOUT (Pin 18/Pin 16): Output Voltage Sense Pin. Develops a current proportional to the output capacitor voltage. Connect a resistor between this pin and the drain of
NMOS such that:
 RV 
VOUT = 0.98 • N •  OUT  − VDIODE
 RBG 
when RVOUT is set equal to RVTRANS, otherwise:

 RVOUT

RV
VOUT = N • 0.98 • OUT + VTRANS 
− 1 
RBG
 RVTRANS  

− VDIODE
where VDIODE = forward voltage drop of diode D1 (refer
to the Block Diagram).
RDCM (Pin 20/Pin 17): Discontinuous Mode Sense Pin.
Senses when the external NMOS drain is equal to 20µA •
RDCM + VTRANS and initiates the next switch cycle. Place
a resistor equal to 0.45 times the resistor on the RVTRANS
pin between this pin and VDRAIN.
GND (Pin 21/Pin 21): Ground. Tie directly to local ground
plane.
LVGATE (Pin 14/Pin 12): Low Voltage Gate Pin. Connect
the NMOS gate terminal to this pin when operating VCC
3751fc
8
LT3751
Block Diagram
DONE
ENABLE
GATE
DRIVER
–
100k
DCM
COMPARATOR
DCM
ONE-SHOT
S R FAULT
Q Q LATCH
VTRANS
RUVLO1
191k
DIFF. AMP
COMPARATOR
WITH
INTERNAL
60V CLAMPS
3.8V
+
VCC
–
UVLO1
LVGATE
162mV
– +–
+
26kHz
ONE-SHOT
CLOCK
MAIN
106mV
– +–
–
TO CHARGE
ONE-SHOT
+
26kHz
ONE-SHOT
CLOCK
ERROR
AMP
+
–
TO VOUT
COMPARATOR
GND
RBG
1.33k
DIE
TEMP
RSENSE
12mΩ
160ºC
+
1.22V
REFERENCE
A1
–
+
–
55V
CSN
TIMING AND PEAK
CURRENT CONTROL 11mV TO 106mV
MODULATION
55V
1.22V
REFERENCE
CSP
+
UVLO/OVLO
COMPARATORS
OVLO2
VCC
+
–
ROVLO2
240k
SECONDARY
CLAMP
RESET
AUXILIARY
CLK
COUNT
55V
UVLO2
VDRAIN
M1
COUNTER
RUVLO2
191k
RDCM
18.2k
HVGATE
GATE DRIVE
CIRCUITRY
+
VCC
COUT
VCC
–
OVLO1
RDCM
SWITCH
LATCH
55V
ROVLO1
240k
+
RVOUT
40.2k
VCC
S Q
R Q
VOUT
450V
60V
26kHz ONE-SHOT
CLOCK
INTERNAL
UVLO
•
D1
60V
1.22V
REFERENCE
+
FAULT
•
60V
RVOUT
MASTER
LATCH
S R
Q Q
10µF
RVTRANS
0.98V
REFERENCE
+
100k
–
10µF
RVTRANS
40.2k
START-UP
ONE-SHOT
OTLO
VCC
VCC
12V
47µF
×2
VOUT
COMPARATOR
CHARGE
OFF ON
T1
1:10
+
PRIMARY
VTRANS
12V
MODE
CONTROL
RFBH
3.65M
FB
10nF
RBG
RFBL
10k
3751 BD
3751fc
9
LT3751
Operation
The LT3751 can be used as either a fast, efficient high
voltage capacitor charger controller or as a high voltage,
low noise voltage regulator. The FB pin voltage determines
one of the three primary modes: charge mode, low noise
regulation, or no-load operation (see Figure 1).
FB PIN
VOLTAGE
ILPRI
IPK
VTRANS – VDS(ON)
LPRI
ILSEC
NO-LOAD
OPERATION
VOUT + VDIODE
LSEC
IPK
N
1.34V
REGULATION
1.16V
CHARGE
MODE
VPRI
VTRANS – VDS(ON)
0.0V
3751 F01
Figure 1. FB Pin Modes
Charge Mode
When the FB pin voltage is below 1.16V, the LT3751 acts
as a rapid capacitor charger. The charging operation has
four basic states for charge mode steady-state operation
(see Figure 2).
–(VOUT + VDIODE)
N
VSEC
VOUT + VDIODE
1. Start-Up
The first switching cycle is initiated approximately 2µs
after the CHARGE pin is raised high. During this phase,
the start-up one-shot enables the master latch turning
on the external NMOS and beginning the first switching
cycle. After start-up, the master latch will remain in the
switching-enable state until the target output voltage is
reached or a fault condition occurs.
The LT3751 utilizes circuitry to protect against transformer
primary current entering a runaway condition and remains
in start-up mode until the DCM comparator has enough
headroom. Refer to the Start-Up Protection section for
more detail.
–N (VTRANS – VDS(ON))
V
+ VDIODE
VTRANS + OUT
N
VDRAIN
VTRANS
VDS(ON)
VDS(ON)
3751 F02
1.
PRIMARY-SIDE
CHARGING
2.
3.
SECONDARY
DISCONTINUOUS
ENERGY TRANSFER
MODE
AND OUTPUT
DETECTION
DETECTION
2. Primary-Side Charging
When the NMOS switch latch is set, and depending on the
use of LVGATE, the gate driver rapidly charges the gate
pin to VCC – 2V in high voltage applications or directly to
VCC in low voltage applications (refer to the Application
Figure 2. Idealized Charging Waveforms
3751fc
10
LT3751
operation
Information section for proper use of LVGATE). With the
gate driver output high, the external NMOS turns on,
forcing VTRANS – VDS(ON) across the primary winding.
Consequently, current in the primary coil rises linearly at
a rate (VTRANS – VDS(ON))/LPRI. The input voltage is mirrored on the secondary winding –N • (VTRANS – VDS(ON))
which reverse-biases the diode and prevents current flow
in the secondary winding. Thus, energy is stored in the
core of the transformer.
3. Secondary Energy Transfer
When current limit is reached, the current limit comparator
resets the NMOS switch latch and the device enters the
third phase of operation, secondary energy transfer. The
energy stored in the transformer core forward-biases the
diode and current flows into the output capacitor. During
this time, the output voltage (neglecting the diode drop)
is reflected back to the primary coil. If the target output
voltage is reached, the VOUT comparator resets the master
latch and the DONE pin goes low. Otherwise, the device
enters the next phase of operation.
4. Discontinuous Mode Detection
During secondary energy transfer to the output capacitor, (VOUT + VDIODE)/N will appear across the primary
winding. A transformer with no energy cannot support a
DC voltage, so the voltage across the primary will decay
to zero. In other words, the drain of the NMOS will ring
down from VTRANS + (VOUT + VDIODE)/N to VTRANS. When
the drain voltage falls to VTRANS + 20µA • RDCM, the DCM
comparator sets the NMOS switch latch and a new switch
cycle begins. Steps 2-4 continue until the target output
voltage is reached.
Start-Up Protection
The LT3751 at start-up, when the output voltage is very
low (or shorted), usually does not have enough VDRAIN
node voltage to trip the DCM comparator. The part in startup mode uses the internal 26kHz clock and an auxiliary
current comparator. Figure 3 shows a simplified block
diagram of the start-up circuitry.
FROM AUXILIARY
CURRENT
COMPARATOR
INCREMENT
COUNTER 1
FROM DCM
COMPARATOR
–
RESET
+
INCREMENT
FROM CLK
SWITCH
LATCH
COUNTER 2
FROM GATE
DRIVER ON
RESET
3751 F03
Figure 3. Start-Up Protection Circuitry
Toggling the CHARGE pin always generates a start-up
one-shot to turn on the external switch, initiating the charging process. After the start-up one-shot, the LT3751 waits
for either the DCM comparator to generate a one-shot or
the output of the start-up protection circuitry going high,
which ever comes first. If the switch drain node, VDRAIN,
is below the DCM comparator threshold (see Entering
Normal Boundary Mode), the DCM comparator will never
fire and the start-up circuitry is dominant.
V
VTH1
VTH2
VDRAIN
VOUT
DCM
1-SHOT
START-UP
(DCM THRESHOLD = VTH1)
BOUNDARY-MODE
(DCM THRESHOLD = VTH2)
BELOW VTH2
(WAIT FOR TIME-OUT)
t
3751 F04
Figure 4. DCM Comparator Thresholds
3751fc
11
LT3751
Operation
At very low output voltages, the boundary-mode switching
cycle period increases significantly such that the energy
stored in the transformer core is not depleted before the
next clock cycle. In this situation, the clock may initiate
another switching cycle before the secondary winding
current reaches zero and cause the LT3751 to enter
continuous-mode conduction. Normally, this is not a
problem; however, if the secondary energy transfer time
is much longer than the CLK period, significant primary
current overshoot can occur. This is due to the non-zero
starting point of the primary current when the switch turns
on and the finite speed of the current comparator.
The LT3751 startup circuitry adds an auxiliary current
comparator with a trip level 50% higher than the nominal
trip level. Every time the auxiliary current comparator
trips, the required clock count between switching cycles is
incremented by one. This allows more time for secondary
energy transfer.
Counter 1 in Figure 3 is set to its maximum count when
the first DCM comparator one-shot is generated. If no
DCM one-shot is initiated in normal boundary-mode
operation during a maximum count of approximately
500µs, the LT3751 re-enters start-up mode and the count
is returned to zero.
Note that Counter 1 is initialized to zero at start-up. Thus,
the output of the startup circuitry will go high after one clock
cycle. Counter 2 is reset when the gate driver goes high.
This repeats until either the auxiliary current comparator
increments the required clock count or until VDRAIN is high
enough to sustain normal operation described in steps 2
through 4 in the previous section.
Entering Normal Boundary Mode
The LT3751 has two DCM comparator thresholds that
are dependent on what mode the part is in, either startup mode or normal boundary-mode, and the state of the
mode latch. For boundary-mode switching, the LT3751
requires the DCM sense voltage (VDRAIN) to exceed VTRANS
by the ΔDCM comparator threshold, ΔVDRAIN:
ΔVDRAIN = (40µA + IOFFSET) • RDCM – 40µA • RVTRANS
where IOFFSET is mode dependent. The DCM one-shot
signal is negative edge triggered by the switch node,
VDRAIN, and indicates that the energy in the secondary
winding has depleted. For this to happen, VDRAIN must
exceed VTRANS + ΔVDRAIN prior to its negative edge; otherwise, the DCM comparator will not generate a one-shot
to initiate the next switching cycle. The part would remain
stuck in this state indefinitely; however, the LT3751 uses
the start-up protection circuitry to jumpstart switching if
the DCM comparator does not generate a one-shot after
a maximum time-out of 500µs.
Figure 4 shows a typical VDRAIN node waveform with
a test circuit voltage clamp applied to the output. VTH1
is the start-up threshold and is set internally by forcing
IOFFSET to 40μA. Once the first DCM one-shot is initiated,
the mode latch is set to boundary-mode. The mode latch
then sets the clock count to maximum (500µs) and lowers
the DCM comparator threshold to VTH2 (IOFFSET = 20μA).
This provides needed hysteresis between start-up mode
and boundary-mode operation.
Low Noise Regulation
Low noise voltage regulation can be achieved by adding
a resistive divider from the output node to the LT3751 FB
pin. At start-up (FB pin below 1.16V), the LT3751 enters
the charge mode to rapidly charge the output capacitor.
Once the FB pin is within the threshold range of 1.16V
to 1.34V, the part enters into low noise regulation. The
switching methodology in regulation mimics that used
in the capacitor charging mode, but with the addition of
peak current and duty cycle control techniques. Figure 5
shows the steady state operation for both regulation
techniques. Figure 6 shows how both techniques are
combined to provide stable, low noise operation over a
wide load and supply range.
During heavy load conditions, the LT3751 sets the peak
primary current to its maximum value, 106mV/RSENSE and
sets the maximum duty cycle to approximately 95%. This
allows for maximum power delivery. At very light loads,
the opposite occurs, and the LT3751 reduces the peak
primary current to approximately one tenth its maximum
value while modulating the duty cycle below 10%. The
LT3751 controls moderate loads with a combination of
peak current mode control and duty cycle control.
3751fc
12
LT3751
operation
CHARGE MODE
LIGHT LOAD OPERATION
26kHz
ONE-SHOT
CLK
SWITCH
ENABLE
26kHz
ONE-SHOT
CLK
...
...
...
MAXIMUM
PEAK CURRENT
NO BLANKING
SWITCH
ENABLE
IPRI
IPRI
...
DUTY CYCLE
CONTROL
...
t
tPER ≈ 38µs
NO-LOAD OPERATION
HEAVY LOAD OPERATION
26kHz
ONE-SHOT
CLK
26kHz
ONE-SHOT
CLK
...
FORCED
BLANKING
...
FORCED
BLANKING
t
SWITCH
ENABLE
DUTY CYCLE
CONTROL
110%
VOUT, NOM
VOUT
...
PEAK CURRENT
CONTROL
...
...
105%
VOUT, NOM
...
IPRI
1/10TH IPK
IPRI
...
t
t
tPER ≈ 38µs
3751 F05
Figure 5. Modes of Operation (Steady State)
ILIM(
IMAX
) DUTY CYCLE (
)
95%
NO-LOAD
OPERATION
1/10
IMAX
10%
0
LIGHT LOAD
MODERATE
LOAD
HEAVY LOAD
CHARGE
MODE
LOAD
CURRENT
3751 F06
Figure 6. Regulation Technique
3751fc
13
LT3751
Operation
Periodic Refresh
Light Load Operation
When the LT3751 enters regulation, the internal circuitry
deactivates switching when the internal one-shot clock
is high. The clock operates at a 1/20th duty cycle with a
minimum blank time of 1.5µs. This reset pulse is timed to
drastically reduce switching frequency content within the
audio spectrum and is active during all loading conditions.
Each reset pulse guarantees at least one energy cycle. A
minimum load is required to prevent the LT3751 from
entering no-load operation.
The LT3751 uses duty cycle control to drastically reduce
audible noise in both the transformer (mechanical) and
the ceramic capacitors (piezoelectric effects). Internal
control circuitry forces a one-shot condition at a periodic
rate greater than 20kHz and out of the audio spectrum.
The regulation loop then determines the number of pulses
that are required to maintain the correct output voltage.
Figure 5 shows the use of duty-cycle control.
Heavy Load Operation
The LT3751 enters peak current mode control at higher
output load conditions. The control loop maximizes the
number of switch cycles between each reset pulse. Since
the control scheme operates in boundary mode, the resonant boundary-mode period changes with varying peak
primary current:
 1
N 
Period =IPK • LPRI • 
+

 VTRANS VOUT 
and the power output is proportional to the peak primary
current:
POUT =
1/ 2 •IPK
 1
N 
+


 VTRANS VOUT 
No-Load Operation
The LT3751 can remain in low noise regulation at very low
loading conditions. Below a certain load current threshold
(Light Load Operation), the output voltage would continue
to increase and a runaway condition could occur. This is
due to the periodic one-shot forced by the periodic refresh
circuitry. By design, the LT3751 has built-in overvoltage
protection associated with the FB pin.
When the FB pin voltage exceeds 1.34V (±20mV), the
LT3751 enters no-load operation. No-load operation does
not reset with the one-shot clock. Instead, the pulse train
is completely load-dependent. These bursts are asynchronous and can contain long periods of inactivity. This allows
regulation at a no-load condition but with the increase of
audible noise and voltage ripple. Note that when operating
with no-load, the output voltage will increase 10% above
the nominal output voltage.
Noise becomes an issue at very low load currents. The
LT3751 remedies this problem by setting the lower peak
current limit to one tenth the maximum level and begins
to employ duty-cycle control.
3751fc
14
LT3751
Applications Information
The LT3751 charger controller can be optimized for either
capacitor charging only or low noise regulation applications. Several equations are provided to aid in the design
process.
Large capacitors charged to high voltage can deliver a lethal
amount of energy if handled improperly. It is particularly
important to observe appropriate safety measures when
designing the LT3751 into applications. First, create a
discharge circuit that allows the designer to safely discharge the output capacitor. Second, adequately space
high voltage nodes from adjacent traces to satisfy printed
circuit board voltage breakdown requirements.
Selecting Operating Mode
Tie the FB pin to GND to operate the LT3751 as a capacitor
charger. In this mode, the LT3751 charges the output at
peak primary current in boundary mode operation. This
constitutes maximum power delivery and yields the fastest charge times. Power delivery is halted once the output
reaches the desired output voltage set by the RVOUT and
RBG pins.
Tie a resistor divider from the FB pin to VOUT and GND
to operate the LT3751 as a low noise voltage regulator
(refer to Low Noise regulation section for proper design
procedures). The LT3751 operates as a voltage regulator
using both peak current and duty cycle modulation to
vary output current during different loading conditions.
Selecting Component Parameters
Most designs start with the initial selection of VTRANS,
VOUT, COUT, and either charge time, tCHARGE, (capacitor
charger) or POUT,MAX (regulator). These design inputs
are then used to select the transformer ratio, N, the peak
primary current, IPK, and the primary inductance, LPRI.
Figure 7 can be used as a rough guide for maximum power
output for a given VTRANS and IPK.
P = 20 WATTS
P = 50 WATTS
P = 100 WATTS
90
80
70
VTRANS (V)
Safety Warning
100
60
50
40
30
20
10
0
1
10
PEAK PRIMARY CURRENT (A)
100
3751 F07
Figure 7. Maximum Power Output
Selecting Transformer Turns Ratio
The transformer ratio, N, should be selected based on
the input and output voltages. Smaller N values equate
to faster charge times and larger available output power.
Note that drastically reducing N below the VOUT/VTRANS
ratio will increase the flyback voltage on the drain of the
NMOS and increase the current through the output diode.
The ratio, N, should not be drastically increased either, due
to the increased capacitance, N2 • CSEC, reflected to the
primary. A good choice is to select N equal to VOUT/VTRANS.
V
N ≤ OUT
VTRANS
Choosing Capacitor Charger IPK
When operating the LT3751 as capacitor charger, choose
IPK based on the required capacitor charge time, tCHARGE,
and the initial design inputs.
IPK =
(2 • N • VTRANS + VOUT ) • COUT • VOUT
Efficiency • VTRANS • ( tCHARGE − t d )
The converter efficiency varies over the output voltage
range. The IPK equation is based on the average efficiency over the entire charging period. Several factors can
cause the charge time to increase. Efficiency is the most
dominant factor and is mainly affected by the transformer
winding resistance, core losses, leakage inductance, and
transistor RDS. Most applications have overall efficiencies
above 70%.
3751fc
15
LT3751
Applications Information
The total propagation delay, td, is the second most dominant
factor that affects efficiency and is the summation of gate
driver on-off propagation delays and the discharge time
associated with the secondary winding capacitance. There
are two effective methods to reduce the total propagation
delay. First, reduce the total capacitance on the secondary
winding, most notably the diode capacitance. Second,
reduce the total required NMOS gate charge. Figure 8
shows the effect of large secondary capacitance.
The energy stored in the secondary winding capacitance
is ½ • CSEC • VOUT 2. This energy is reflected to the primary
when the diode stops forward conduction. If the reflected
capacitance is greater than the total NMOS drain capacitance, the drain of the NMOS power switch goes negative
and its intrinsic body diode conducts. It takes some time
for this energy to be dissipated and thus adds to the total
propagation delay.
VDRAIN
Transformer Design
The transformer’s primary inductance, LPRI, is determined
by the desired VOUT and previously calculated N and IPK
parameters. Use the following equation to select LPRI:
LPRI =
The previous equation guarantees that the VOUT comparator
has enough time to sense the flyback waveform and trip
the DONE pin latch. Operating VOUT significantly higher
than that used to calculate LPRI could result in a runaway
condition and overcharge the output capacitor.
The LPRI equation is adequate for most regulator applications. Note that if both IPK and N are increased significantly
for a given VTRANS and VOUT, the maximum IPK will not be
reached within the refresh clock period. This will result in
a lower than expected maximum output power. To prevent
this from occurring, maintain the condition in the following equation.
LPRI <
ISEC
NO SEC.
CAPACITANCE
IPRI
SEC. DISCHARGE
t
3751 F08
Figure 8. Effect of Secondary Winding Capacitance
Choosing Regulator Maximum IPK
The IPK parameter in regulation mode is calculated based
on the desired maximum output power instead of charge
time like that in a capacitor charger application.
IPK = 2 •
POUT(AVG)  1
•
Efficiency  V
TRANS
+
N 
VOUT 
3µs • VOUT
IPK •N
38µs
 1
N 
IPK • 
+

 VTRANS VOUT 
The upper constraint on LPRI can be reduced by increasing VTRANS and starting the design process over. The best
regulation occurs when operating the boundary-mode
frequency above 100kHz (refer to Operation section for
boundary-mode definition).
Figure 9 defines the maximum boundary-mode switching
frequency when operating at a desired output power level
and is normalized to LPRI/POUT (μH/Watt). The relationship of output power, boundary-mode frequency, IPK, and
primary inductance can be used as a guide throughout
the design process.
Note that the LT3751 regulation scheme varies the peak
current based on the output load current. The maximum
IPK is only reached during charge mode or during heavy
load conditions where output power is maximized.
3751fc
16
LT3751
applications information
Table 1. Recommended Transformers
MANUFACTURER
PART NUMBER
SIZE L × W × H (mm)
MAXIMUM IPRI (A)
LPRI (µH)
TURNS RATIO (PRI:SEC)
Coilcraft
www.coilcraft.com
DA2033-AL
DA2034-AL
GA3459-BL
GA3460-BL
HA4060-AL
HA3994-AL
17.4 × 24.1 × 10.2
20.6 × 30 × 11.3
32.65 × 26.75 × 14
32.65 × 26.75 × 14
34.29 × 26.75 × 14
34.29 × 28.75 × 14
5
10
20
50
2
5
10
10
5
2.5
300
7.5
1:10
1:10
1:10
1:10
1:3
2:1:3:3*
Würth Elektronik/Midcom
www.we-online.com
750032051
750032052
750310349
750310355
28.7 × 22 × 11.4
28.7 × 22 × 11.4
36.5 × 42 × 23
36.5 × 42 × 23
5
10
20
50
10
10
5
2.5
1:10
1:10
1:10
1:10
Sumida
www.sumida.com
C8117
C8119
PS07-299
PS07-300
23 × 18.6 × 10.8
32.2 × 27 × 14
32.5 × 26.5 × 13.5
32.5 × 26.5 × 13.5
5
10
20
50
10
10
5
2.5
1:10
1:10
1:10
1:10
TDK
www.tdk.com
DCT15EFD-U44S003
DCT20EFD-U32S003
DCT25EFD-U27S005
22.5 × 16.5 × 8.5
30 × 22 × 12
27.5 × 33 × 15.5
5
10
20
10
10
5
1:10
1:10
1:10
*Transformer has three secondaries where the ratio is designated as PRI:SEC1:SEC2:SEC3
LPRI/WATT (µH/WATT)
10.000
fMAX = 50kHz
fMAX = 100kHz
fMAX = 200kHz
1.000
0.100
0.010
0.001
1
10
PEAK PRIMARY CURRENT (A)
100
3751 F09
Figure 9. Maximum Switching Frequency
RVTRANS, RVOUT and RDCM Selection
RVTRANS sets the common-mode reference voltage for
both the DCM comparator and VOUT comparator. Select
RVTRANS from Table 2 based on the transformer supply
voltage range, VTRANS, and the maximum trip voltage,
∆VDRAIN (VDRAIN-VTRANS).
The RVTRANS pin is connected to an internal 40µA current
source. Pin current increases as the pin voltage is taken
higher than the internal 60V Zener clamp. The LT3751 can
operate from VTRANS greater than the 60V internal Zener
clamps by limiting the RVTRANS pin current to 250µA.
Operating VTRANS above 200V requires the use of resistor dividers. Two applications are presented that operate
Table 2. Suggested RVTRANS, RVOUT, and RDCM Values
VTRANS Range
(V)
∆VDRAIN RANGE
(V)
RVTRANS
(kΩ)
RVOUT
(kΩ)
RDCM
(kΩ)
4.75 to 55
0 to 5
5.11
5.11
2.32
2.5 to 50
25.5
25.5
11.5
5 to 80
40.2
40.2
18.2
8 to 80
8 to 160
80.6
80.6
36.5
80 to 200
2mA • RVOUT
VTRANS − 55V
0.25
VTRANS − 55V
0.25
0.86 • RVTRANS
>200
Resistor Divider Dependent
Use Resistor Divider
Use Resistor Divider
Use Resistor Divider
4.75 to 60
3751fc
17
LT3751
Applications Information
with VTRANS between 100V and 400V (refer to Typical
Applications section). Consult applications engineering
for applications with VTRANS operating above 400V.
RVOUT is required for capacitor charger applications but
may be removed for regulator applications. Note that the
VOUT comparator can be used as secondary protection
for regulator applications. If the VOUT comparator is used
for protection, design VOUT,TRIP 15% to 20% higher than
the regulation voltage. Tie the RVOUT pin to ground when
RVOUT resistor is removed.
RDCM needs to be properly sized in relation to RVTRANS.
Improper selection of RDCM can lead to undesired switching
operation at low output voltages. Use Table 2 to size RDCM.
Parasitic capacitance on RVTRANS , RVOUT, and RDCM should
be minimized. Capacitances on these nodes slow down
the response times of the VOUT and DCM comparators.
Keep the distance between the resistor and pin short. It
is recommended to remove all ground and power planes
underneath these pins and their respective components
(refer to the recommended board layout at the end of
this section).
RBG Selection
RBG sets the trip current (0.98/RBG) and is directly related
to the selection of RVOUT. The best accuracy is achieved
with a trip current between 100µA and 2mA. Choosing
RVOUT from Table 2 meets this criterion. Use the following
equation to size RBG (VTRANS ≤ 80V):


RVOUT
RBG = 0.98 •N • 

 VOUT,TRIP + VDIODE 
Tie RBG pin to ground when not using the VOUT comparator. Consult applications engineering for calculating RBG
when operating VTRANS above 80V.
NMOS Switch Selection
Choose an external NMOS power switch with minimal gate
charge and on-resistance that satisfies current limit and
voltage break-down requirements. The gate is nominally
driven to VCC – 2V during each charge cycle. Ensure that
this does not exceed the maximum gate to source voltage
rating of the NMOS but enhances the channel enough to
minimize the on-resistance.
Similarly, the maximum drain-source voltage rating of the
NMOS must exceed VTRANS + VOUT/N or the magnitude of
the leakage inductance spike, whichever is greater. The
maximum instantaneous drain current rating must exceed
selected current limit. Because the switching period decreases with output voltage, the average current though
the NMOS is greatest when the output is nearly charged
and is given by:
IPK • VOUT(PK)
IAVG,M =
2(VOUT(PK) + N • VTRANS )
See Table 3 for recommended external NMOS transistors.
Table 3. Recommended NMOS Transistors
MANUFACTURER
PART NUMBER
ID (A)
VDS(MAX) (V)
RDS(ON) (mΩ)
QG(TOT) (nC)
PACKAGE
Fairchild Semiconductor
www.fairchildsemi.com
FDS2582
FQB19N20L
FQP34N20L
FQD12N20L
FQB4N80
4.1
21
31
12
3.9
150
200
200
200
800
66
140
75
280
3600
11
27
55
16
19
SO-8
D2PAK
TO-220
DPAK
D2PAK
On Semiconductor
www.onsemi.com
MTD6N15T4G
NTD12N10T4G
NTB30N20T4G
NTB52N10T4G
6
12
30
52
150
100
200
100
300
165
81
30
15
14
75
72
DPAK
DPAK
D2PAK
D2PAK
Vishay
www.vishay.com
Si7820DN
Si7818DN
SUP33N20-60P
2.6
3.4
33
200
150
200
240
135
60
12.1
20
53
1212-8
1212-8
TO-220
3751fc
18
LT3751
applications information
Table 4. Recommended Output Diodes
MANUFACTURER
PART NUMBER
IF(AV) (A)
VRRM (V)
TRR (ns)
PACKAGE
Central Semiconductor
www.centralsemi.com
CMR1U-10M
CMSH2-60M
CMSH5-40
1
2
5
1000
60
40
100
SMA
SMA
SMC
Fairchild Semiconductor
www.fairchildsemi.com
ES3J
ES1G
ES1J
3
1
1
600
400
600
35
35
35
SMC
SMA
SMA
On Semiconductor
www.onsemi.com
MURS360
MURA260
MURA160
3
2
1
600
600
600
75
75
75
SMC
SMA
SMA
Vishay
www.vishay.com
USB260
US1G
US1M
GURB5H60
2
1
1
5
600
400
1000
600
30
50
75
30
SMB
SMA
SMA
D2PAK
Gate Driver Operation
The LT3751 gate driver has an internal, selectable 10.5V
or 5.6V clamp with up to 2A current capability (using
LVGATE). For 10.5V operation, tie CLAMP pin to ground,
and for 5.6V operation, tie the CLAMP pin to the VCC pin.
Choose a clamp voltage that does not exceed the NMOS
manufacturer’s maximum VGS ratings. The 5.6V clamp
can also be used to reduce LT3751 power dissipation
and increase efficiency when using logic-level FETs. The
typical gate driver overshoot voltage is 0.5V above the
clamp voltage.
The LT3751’s gate driver also incorporates a PMOS pullup device via the LVGATE pin. The PMOS pull-up driver
should only be used for VCC applications of 8V or below.
Operating LVGATE with VCC above 8V will cause permanent damage to the part. LVGATE is active when tied to
HVGATE and allows rail-to-rail gate driver operation. This
is especially useful for low VCC applications, allowing better NMOS drive capability. It also provides the fastest rise
times, given the larger 2A current capability verses 1.5A
when using only HVGATE.
Output Diode Selection
The output diode(s) are selected based on the maximum
repetitive reverse voltage (VRRM) and the average forward
current (IF(AV)). The output diode’s VRRM should exceed
VOUT + N • VTRANS. The output diode’s IF(AV) should exceed
IPK /2N, the average short-circuit current. The average diode
current is also a function of the output voltage.
IAVG =
IPK • VTRANS
2 • (VOUT + N • VTRANS )
The highest average diode current occurs at low output
voltages and decreases as the output voltage increases.
Reverse recovery time, reverse bias leakage and junction
capacitance should also be considered. All affect the overall charging efficiency. Excessive diode reverse recovery
times can cause appreciable discharging of the output
capacitor, thereby increasing charge time. Choose a diode
with a reverse recovery time of less than 100ns. Diode
leakage current under high reverse bias bleeds the output
capacitor of charge and increases charge time. Choose a
diode that has minimal reverse bias leakage current. Diode
junction capacitance is reflected back to the primary, and
energy is lost during the NMOS intrinsic diode conduction.
Choose a diode with minimal junction capacitance. Table 4
recommends several output diodes for various output
voltages that have adequate reverse recovery times.
Setting Current Limit
Placing a sense resistor from the positive sense pin, CSP,
to the negative sense pin, CSN, sets the maximum peak
switch current. The maximum current limit is nominally
106mV/RSENSE. The power rating of the current sense
resistor must exceed:


VOUT(PK)
I2 • R
PRSENSE ≥ PK SENSE 

3
 VOUT(PK) + N • VTRANS 
Additionally, there is approximately a 180ns propagation delay from the time that peak current limit is
3751fc
19
LT3751
Applications Information
detected to when the gate transitions to the low state.
This delay increases the peak current limit by (VTRANS)
(180ns)/LPRI.
of resistor values. When under/overvoltage lockout comparators are tripped, the master latch is disabled, power
delivery is halted, and the FAULT pin goes low.
Sense resistor inductance (LRSENSE) is another source of
current limit error. LRSENSE creates an input offset voltage
(VOS) to the current comparator and causes the current
comparator to trip early. VOS can be calculated as:
Adequate supply bulk capacitors should be used to reduce
power supply voltage ripple that could cause false tripping
during normal switching operation. Additional filtering
may be required due to the high input impedance of the
under/overvoltage lockout pins to prevent false tripping.
Individual capacitors ranging from 100pF to 1nF may be
placed between each of the UVLO1, UVLO2, OVLO1 and
OVLO2 pins and ground. Disable the undervoltage lockouts
by directly connecting the UVLO1 and UVLO2 pins to VCC.
Disable the overvoltage lockouts by directly connecting
the OVLO1 and OVLO2 pins to ground.
 L

VOS = VTRANS •  RSENSE 
 LPRIMARY 
The change in current limit becomes VOS /RSENSE. The error
is more significant for applications using large di/dt ratios
in the transformer primary. It is recommended to use very
low inductance (< 2nH) sense resistors. Several resistors
can be placed in parallel to help reduce the inductance.
Care should also be taken in placement of the sense lines.
The negative return line, CSN, must be a dedicated trace
to the low side resistor terminal. Haphazardly routing the
CSN connection to the ground plane can cause inaccurate
current limit and can also cause an undesirable discontinuous charging profile.
DONE and FAULT Pin Design
Both the DONE and FAULT pins require proper pull-up
resistors or current sources. Limit pin current to 1mA
into either of these pins. 100kΩ pull-up resistors are
recommended for most applications. Both the DONE and
FAULT pins are latched in the low output state. Resetting
either latch requires the CHARGE pin to be toggled. A fault
condition will also cause the DONE pin to go low. A third,
non-latching condition occurs during startup when the
CHARGE pin is driven high. During this start-up condition,
both the DONE and FAULT pins will go low for several micro
seconds. This indicates the internal rails are still ramping
to their proper levels. External RC filters may be added to
both indication pins to remove start-up indication. Time
constants for the RC filter should be between 5µs to 20µs.
Under/Overvoltage Lockout
The LT3751 provides user-programmable under and
overvoltage lockouts for both VCC and VTRANS. Use the
equations in the Pin Functions section for proper selection
The LT3751 provides internal Zener clamping diodes to
protect itself in shutdown when VTRANS is operated above
55V. Supply voltages should only be applied to UVLO1,
UVLO2, OVLO1 and OVLO2 with series resistance such
that the Absolute Maximum pin currents are not exceeded.
Pin current can be calculated using:
IPIN =
VAPPLIED − 55V
RSERIES
Note that in shutdown, RVTRANS, RVOUT, RDCM, UVLO1,
UVLO2, OVLO1 and OVLO2 currents increase significantly
when operating VTRANS above the Zener clamp voltages
and are inversely proportional to the external series pin
resistances.
NMOS Snubber Design
The transformer leakage inductance causes a parasitic
voltage spike on the drain of the power NMOS switch during the turn-off transition. Transformer leakage inductance
effects become more apparent at high peak primary currents. The worst-case magnitude of the voltage spike is
determined by the energy stored in the leakage inductance
and the total capacitance on the VDRAIN node.
VD,LEAK =
LLEAK •I2PK
C VDRAIN
Two problems can arise from large VD,LEAK. First, the
magnitude of the spike may require an NMOS with an
3751fc
20
LT3751
applications information
unnecessarily high V(BR)DSS which equates to a larger
RDS(ON). Secondly, the VDRAIN node will ring—possibly
below ground—causing false tripping of the DCM comparator or damage to the NMOS switch (see Figure 11).
Both issues can be remedied using a snubber. If leakage
inductance causes issues, it is recommended to use a RC
snubber in parallel with the primary winding, as shown
in Figure 10. Size CSNUB and RSNUB based on the desired
leakage spike voltage, known leakage inductance, and an
RC time constant less than 1µs. Otherwise, the leakage
voltage spike can cause false tripping of the VOUT comparator and stop charging prematurely.
Figure 11 shows the effect of the RC snubber resulting in
a lower voltage spike and faster settling time.
RSNUB LPRI
LOW NOISE REGULATION
The LT3751 has the option to provide a low noise regulated output voltage when using a resistive voltage divider
from the output node to the FB pin. Refer to the Selecting
Component Parameters section to design the transformer,
NMOS power switch, output diode, and sense resistor.
Use the following equations to select the feedback resistor values based on the power dissipation and desired
output voltage:
RFBH
2
VOUT − 1.22)
(
=
PD
; Top Feedback Resistor

1.22 
RFBL = 
• RFBH ; Bottom Feedback Resistor
 VOUT − 1.22 
RFBH, depending on output voltage and type used, may
require several smaller values placed in series. This will
reduce the risk of arcing and damage to the feedback resistors. Consult the manufacturer’s rated voltage specification
for safe operation of the feedback resistors.
•
•
CSNUB
LLEAK
The LT3751 has a minimum periodic refresh frequency
limit of 23kHz. This drastically reduces switching frequency
components in the audio spectrum. The LT3751 can operate with no-load, but the regulation scheme switches to
no-load operation and audible noise and output voltage
ripple increase. This can be avoided by operating with a
minimum load current.
CVDRAIN
3751 F11
Figure 10. RC Snubber Circuit
Minimum Load Current
Periodic refresh circuitry requires an average minimum
load current to avoid entering no-load operation. Usually,
the feedback resistors should be adequate to provide this
minimum load current.
VDRAIN
(WITHOUT
SNUBBER)
0V
VDRAIN
(WITH
SNUBBER)
NMOS DIODE
CONDUCTS
ILOAD(MIN) ≥
0V
IPRI
3751 F12
Figure 11. Effects of RC Snubber
LPRI •I 2PK • 23kHz
100 • VOUT
IPK is the peak primary current at maximum power delivery.
The LT3751 will enter no-load operation if the minimum
load current is not met. No-load operation will prevent the
application from entering a runaway condition; however,
the output voltage will increase 10% over the nominal
regulated voltage.
3751fc
21
LT3751
Applications Information
Large Signal Stability
Small Signal Stability
Large signal stability can be an issue when audible noise
is a concern. Figure 12 shows that the problem originates
from the one-shot clock and the output voltage ripple. The
load must be constrained such that the output voltage
ripple does not exceed the regulation range of the error
amplifier within one clock period (approximately 6mV
referred to the FB pin).
The LT3751’s error amplifier is internally compensated to
increase its operating range but requires the converter’s
output node to be the dominant pole. Small signal stability
constraints become more prevalent during heavy loading conditions where the dominant output pole moves
to higher frequency and closer to the internal feedback
poles and zeros. The feedback loop requires the output
pole frequency to remain below 200Hz to guarantee small
signal stability. This allows smaller RLOAD values than the
large signal constraint. Thus, small signal issues should
not arise if the large signal constraint is met.
The output capacitance should be increased if oscillations
occur or audible noise is present. Use Figure 13 to determine the maximum load for a given output capacitance to
maintain low audible noise operation. A small capacitor
can also be added from the FB pin to ground to lower the
ripple injected into FB pin.
LOAD
DROOP
VOUT
The high voltage operation of the LT3751 demands careful attention to the board layout, observing the following
points:
1. Minimize the area of the high voltage end of the secondary winding.
IPRI
2. Provide sufficient spacing for all high voltage nodes
(NMOS drain, VOUT and secondary winding of the
transformer) in order to meet the breakdown voltage
requirements.
26kHz
ONE-SHOT
CLK
3751 F13
Figure 12. Voltage Ripple Stability Constraint
30
VOUT = 150V
VOUT = 300V
VOUT = 600V
25
COUT, MIN (µF)
Board Layout
4. Reduce the total node capacitance on the RVOUT and
RDCM pins by removing any ground or power planes
underneath the RDCM and RVOUT pads and traces.
Parasitic capacitance can cause unwanted behavior
on these pins.
20
15
10
5
0
0
150
50
100
OUTPUT POWER (W)
3. Keep the electrical path formed by CVTRANS, the primary
of T1, and the drain of the NMOS as short as possible.
Increasing the length of this path effectively increases
the leakage inductance of T1, potentially resulting in an
overvoltage condition on the drain of the NMOS.
200
3751 F14
Figure 13. COUT(MIN) vs Output Power
5. Thermal vias should be added underneath the Exposed
Pad, Pin 21, to enhance the LT3751’s thermal performance. These vias should go directly to a large area of
ground plane.
6. Isolated applications require galvanic separation of the
output-side ground and primary-side ground. Adequate
spacing between both ground planes is needed to meet
voltage safety requirements.
3751fc
22
ANALOG
GND
CHARGE
VCC
RDONE
RFAULT
ROVLO2
RUVLO2
+
VTRANS
ROVLO1
RUVLO1
18
16
6
5
4
9
RFBH3
RFBL
CFB
11
12
SINGLE
POINT
GND
ANALOG
GND
VCC
RBG
RVOUT
RDCM
CVTRANS4
POWER
GND RETURN
CVCC
CVTRANS3
M1
RSENSE
ANALOG
GND
RFBH2
REMOVE COPPER
FROM ALL SUB-LAYERS
(SEE ITEM 4)
T1
1:N
•
RFBH1
•
POWER
GND RETURN
SECONDARY
Figure 14. QFN Package Recommended Board Layout (Not to Scale)
8
ANALOG
GND VIAS
13
14
10
17
3
LT3751
19
15
7
20
RVTRANS
2
1
CVTRANS2
PRIMARY
CVTRANS1
DVOUT
CVOUT1
+
+
POWER
GND
3751 F15
CVOUT2
VOUT
POWER
GND
LT3751
applications information
3751fc
23
24
CHARGE
VCC
RDONE
RFAULT
ROVLO2
RUVLO2
ROVLO1
RUVLO1
RVTRANS
17
16
4
5
13
12
11
8
9
10
POWER
GND RETURN
ANALOG
GND
VCC
RSENSE
CVCC
RBG
RVOUT
RDCM
REMOVE COPPER
FROM ALL SUB-LAYERS
(SEE ITEM 4)
CVTRANS2
+
CVTRANS4
M1
ANALOG
GND
POWER
GND RETURN
CVTRANS3
•
T1
1:N
Figure 15. TSSOP Package Recommended Board Layout (Not to Scale)
RFBL
14
7
CFB
18
3
15
19
2
6
20
1
LT3751
ANALOG
GND
POWER
GND
CVTRANS1
+
PRIMARY
VTRANS
•
CVOUT1
DVOUT
CVOUT2
+
3751 F16
RFBH2
RFBH1
VOUT
LT3751
applications information
3751fc
SECONDARY
LT3751
Typical Applications
42A Capacitor Charger
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
VTRANS
12V TO 24V
T1**
1:10
+
OFF ON
VCC
12V TO 24V
C1
10µF
R1, 191k
R2, 475k
R3, 191k
VCC
R7, 18.2k
VCC
R8, 40.2k
LT3751
R4, 475k
DONE
RVOUT
HVGATE
LVGATE
CSP
FAULT
UVLO1
OVLO1
CSN
UVLO2
FB
VCC
D2***
•
RVTRANS
CHARGE
CLAMP
RDCM
R10, 100k
R11, 100k
VTRANS
C2
10µF
×3
R6
40.2k
C3
1000µF
D1
+
•
VOUT
500V
* M1, M2 REQUIRES PROPER
HEATSINK/THERMAL DISSIPATION
TO MEET MANUFACTURER’S SPECIFICATIONS
C4
1200µF
** THERMAL DISSIPATION OF T1 WILL LIMIT
THE CHARGE/DISCHARGE DUTY CYCLE OF C4
*** D2 MAY BE OMITTED FOR OUTPUT
VOLTAGE OPERATION BELOW 300V
4.7nF
Y-RATED
M1, M2*
R5
2.5mΩ
OVLO2
GND RBG
C1: 25V X5R OR X7R CERAMIC CAPACITOR
C2: 25V X5R OR X7R CERAMIC CAPACITOR
C3: 25V ELECTROLYTIC
C4: HITACHI FX22L122Y 1200µF, 550V ELECTROLYTIC
OR: CORNELL DUBILIER DCMC192T550CE2B 1900µF, 550V ELECTROLYTIC
D1, D2: VISHAY GURB5H60 600V, 5A ULTRAFAST RECTIFIER
M1, M2: 2 PARALLEL VISHAY SUP33N20-60P 200V, 33A NMOS
R1 THRU R4, R6 THRU R11: USE 1% 0805 RESISTORS
R5: USE 2 PARALLEL 5mΩ IRC LR SERIES 2512 RESISTORS
T1: COILCRAFT GA3460-BL 50A SURACE MOUNT TRANSFORMER
3751 TA02
R9
787Ω
FOR ANY VOUT VOLTAGE BETWEEN
50V AND 500V SELECT R9 ACCORDING TO:
 40.2kΩ 
R9 = 0.98 • N • 
 VOUT + VDIODE 
Efficiency
Output Capacitor Charge Times
1200
85
CHARGE TIME (ms)
EFFICIENCY (%)
80
75
800
Charging Waveform
VOUT = 500V, VTRANS = 24V
VOUT = 500V, VTRANS = 12V
VOUT = 300V, VTRANS = 24V
VOUT = 300V, VTRANS = 12V
VOUT = 100V,
VTRANS = 24V
VOUT = 100V,
VTRANS = 12V
VOUT = 500V
VTRANS = 24V
C4 = 1200µF
VOUT
100V/DIV
400
70
65
VTRANS = 12V
VTRANS = 24V
50
150
250
350
OUTPUT VOLTAGE (V)
450
3751 TA02b
0
200
AVERAGE
INPUT
CURRENT
5A/DIV
1000
400
600
800
OUTPUT CAPACITANCE (µF)
1200
100ms/DIV
3751 TA02d
3751 TA02c
3751fc
25
LT3751
typical applications
High Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
VTRANS
5V TO 24V
+
T1*
1:10
C3
680µF
C1
10µF
DONE
TO
MICRO
R1, 69.8k
VTRANS
R2, 475k
R3, 69.8k
VCC
R6
40.2k
RVTRANS
CHARGE
RDCM
CLAMP
LT3751
VCC
RVOUT
OFF ON
VCC
5V TO 24V
C2
5× 2.2µF
R4, 475k
UVLO1
•
R7, 18.2k
UVLO2
* M1 AND T1 REQUIRE PROPER
HEATSINK/THERMAL DISSIPATION
TO MEET MANUFACTURER’S SPECIFICATIONS
*** C4 MUST BE SIZED TO MEET LARGE SIGNAL
STABILITY CRITERIA DESCRIBED IN THE
APPLICATIONS INFORMATION SECTION
M1*
VCC
R5
6mΩ
R10**
FB
OVLO2
C4***
100µF
C5
0.47µF
** DEPENDING ON DESIRED OUTPUT VOLTAGES,
R10 MUST BE SPLIT INTO MULTIPLE RESISTORS,
TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION.
CSN
OVLO1
+
VOUT
100V TO 500V
R8, 40.2k
HVGATE
LVGATE
CSP
FAULT
•
D1
C6
10nF
GND RBG
R11
3751 TA04
R9
C1: 25V X5R OR X7R CERAMIC
C2: 25V X5R OR X7R CERAMIC
C3: 25V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
D1: VISHAY US1M 1000V
M1: FAIRCHILD FQP34N20L
R1 THRU R4, R6 THRU R9, R11: USE 1% 0805
R5: IRC LR SERIES 2512 RESISTORS
R10: USE 200V 1206 RESISTOR(S)
T1: COILCRAFT GA3459-AL
Suggested Component Values
VOUT
(V)
IOUT(MAX) (mA)
IOUT(MAX) (mA)
AT VTRANS = 5V,
AT VTRANS = 24V,
5% VOUT DEFLECTION 5% VOUT DEFLECTION
Steady-State Operation with
1.1mA Load Current
R9
(kΩ)
R11
(kΩ)
R10
(kΩ)
100
180
270
3.32
0.383
30.9
200
110
315
1.65
0.768
124
300
75
245
1.10
1.13
274
400
55
200
0.825
1.54
499
500†
40
170
Tie to GND
1.74
715
VOUT
AC COUPLED
2V/DIV
VDRAIN
50V/DIV
IPRI
10A/DIV
10µs/DIV
† Transformer primary inductance limits V
OUT comparator operation to VOUT = 400VMAX. RVOUT
and RBG should be tied to ground when operating VOUT above 400V.
Efficiency (VOUT = 500V)
90
515
VTRANS = 12V
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
85
80
75
VTRANS = 5V
70
Steady-State Operation with
100mA Load Current
Load Regulation (VOUT = 500V)
VTRANS = 24V
3751 TA03b
VOUT
COUPLED
2V/DIV
510
VDRAIN
50V/DIV
VTRANS = 24V
IPRI
10A/DIV
505
VTRANS = 12V
10µs/DIV
500
3751 TA03e
65
60
0
26
50
100
ILOAD (mA)
150
200
3751 TA03c
495
VTRANS = 5V
0
50
100
ILOAD (mA)
150
200
3751 TA03d
3751fc
LT3751
typical applications
1.6A High Input Voltage, Isolated Capacitor Charger
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
VTRANS
100V TO
400VDC
T1*
1:3
F1, 1A
+
R6
625k
C3
47µF
R7, 96.2k
OFF ON
VCC
10V TO 24V
C1
10µF
TO
MICRO
R1, 1.5M
VTRANS
R2, 9M
R3, 154k
VCC
R4, 475k
R9
67.3k
HVGATE
LVGATE
FB
OVLO1
•
VCC
4.7nF
Y-RATED
R13
68mΩ
3751 TA04a
R12
Output Trip Voltage
and Charge Time
(VOUT = 500V, COUT = 220µF)
Efficiency
530
1000
VOUT,TRIP (V)
700
CHARGE TIME
550
500
300
200
INPUT VOLTAGE (V)
400
400
CHARGE TIME (ms)
VOUT,TRIP
510
EFFICIENCY (%)
850
520
Charging Waveform
100
95
490
100
FOR ANY OUTPUT VOLTAGE BETWEEN 50V
TO 500V, SET R12 GIVEN BY:
0.98
R12 =
VOUT,TRIP
+ 40µA • 2
3 • R10
C1: 25V X5R OR X7R CERAMIC
C2: 630V X5R OR X7R CERAMIC
C3: 450V ILLINOIS CAP 476CKE450MQW
C4: 50V TO 500V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
D1, D2: VISHAY US1M 1000V
F1: BUSSMANN PCB-1-R
M1: FAIRCHILD FQB4N80
R1, R2: 2 X 1206 RESISTORS IN SERIES, 1%
R3 THRU R5, R9, R12: 0805 RESISTORS, 1%
R6, R10: 3 X 1206 RESISTORS IN SERIES, 0.1%
R7, R11: 0805 RESISTORS, 0.1%
R8: 3 X 1206 RESISTORS IN SERIES, 1%
R13: IRC LR SERIES 1206 RESISTOR, 1%
T1: COILCRAFT HA4060-AL
M1**
CSN
OVLO2
GND RBG
VOUT
50V TO 500V * T1 REQUIRES PROPER THERMAL MANAGEMENT
TO ACHIEVE DESIRED OUTPUT POWER LEVELS
C4
** M1 REQUIRES PROPER HEAT SINK/THERMAL
220µF
DISSIPATION TO MEET MANUFACTURER’S
SPECIFICATIONS
C5
0.47µF
CSP
UVLO2
+
R10
208k
R11
32.1k R5
20Ω
FAULT
D2
•
R8
417k
RVTRANS
RDCM
CHARGE
CLAMP
LT3751
VCC
RVOUT
DONE
UVLO1
C2
2.2µF
×5
D1
VOUT = 500V
VTRANS = 300V
VOUT = 12V
VIN = 100V
90
VIN = 250V
85
VOUT
100V/DIV
VIN = 400V
80
70
AVERAGE
INPUT
CURRENT
200mA/DIV
65
CHARGE
10V/DIV
75
50
150
250
350
450
OUTPUT VOLTAGE (V)
3751 TA04b
100ms/DIV
3751 TA04d
3751 TA04c
3751fc
27
LT3751
typical applications
High Input Voltage, High Output Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
VTRANS
100V TO
400VDC
T1*
1:3
F1, 1A
+
C3
47µF
C1
10µF
DONE
TO
MICRO
R1, 1.5M
VTRANS
R2, 9M
R3, 154k
VCC
R7, 97.6k
RVTRANS
CHARGE
RDCM
CLAMP
LT3751
VCC
RVOUT
OFF ON
VCC
10V TO
24V
R6, 625k
R4, 475k
FAULT
UVLO1
OVLO1
UVLO2
OVLO2
HVGATE
LVGATE
CSP
C2
2.2µF
×5
R8, 417k
R5, 20Ω
GND RBG
** M1 REQUIRES PROPER HEAT SINK/THERMAL
DISSIPATION TO MEET MANUFACTURER’S
SPECIFICATIONS
100µF
•
C5
0.47µF
R9
67.3k
VCC
* T1 REQUIRES PROPER THERMAL MANAGEMENT
TO ACHIEVE DESIRED OUTPUT POWER LEVELS
+
C4
•
*** DEPENDING ON DESIRED OUTPUT VOLTAGE,
R10 MUST BE SPLIT INTO MULTIPLE RESISTORS
TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION
M1**
R12
68mΩ
CSN
FB
VOUT
100V TO 500V
D1 D2
R10***
C6
10nF
R11
3751 TA05a
C1: 25V X5R OR X7R CERAMIC
C2: 630V X5R OR X7R CERAMIC
C3: 450V ILLINOIS CAP 476CKE450MQW
C4: 50V TO 500V ELECTROLYTIC
C5: TDK CKG57NX7R2J474M
C6: 6.3V X5R OR X7R CERAMIC
D1, D2: VISHAY US1M 1000V
F1: BUSSMANN PCB-1-R
M1: FAIRCHILD FQB4N80
R1, R2: 2 X 1206 RESISTORS IN SERIES, 1%
R3 THRU R5, R7, R9, R11: 0805 RESISTORS, 1%
R6, R8: 3 X 1206 RESISTORS IN SERIES, 1%
R10: 1206 RESISTOR(S), 1%
R12: IRC LR SERIES 1206 RESISTOR, 1%
T1: COILCRAFT HA4060-AL
Suggested Component Values
IOUT(MAX) (mA)
IOUT(MAX) (mA)
AT VTRANS = 100V,
AT VTRANS = 400V,
1% VOUT DEFLECTION 1% VOUT DEFLECTION
55
130
VOUT
(V)
100
R10
(kΩ)
R11
(kΩ)
30.9
0.383
200
110
150
124
0.768
300
95
175
274
1.13
400
80
130
499
1.54
500
65
140
715
1.74
Efficiency
Steady-State Operation with
50mA Load Current
Line Regulation
398
90
VIN = 200V
VOUT = 400V
VIN = 100V
VIN = 250V
OUTPUT VOLTAGE (V)
EFFICIENCY (%)
80
70
VIN = 400V
60
IOUT = 10mA
VDRAIN
100V/DIV
397
IOUT = 25mA
396
IOUT = 50mA
IPRI
2A/DIV
50
40
0
50
25
OUTPUT CURRENT (mA)
75
3751 TA05b
395
100
300
200
INPUT VOLTAGE (V)
400
10µs/DIV
3751 TA05d
3751 TA05c
3751fc
28
LT3751
typical applications
Isolated 282V Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
D2
R2, 10Ω
ISOLATION BOUNDARY
•
T1
Npb
VTRANS
100V TO
200VDC
F1, 2A
VTRANS
R1
49.9k
D5
+
M1
C3
22µF
×2
OFF ON
C1
100pF
RVTRANS
RDCM
CHARGE
CLAMP
LT3751 RV
V
CC
Load Regulation
R4
105k
R5
210k
•
Np
D3
R16
249k
•
C5
0.01µF
VCC
Nsb
R15
5.11Ω D6
R6
40mΩ
100
95
D7
U1
R20
274Ω
EFFICIENCY (%)
50
100
150
IOUT (mA)
200
250
3751 TA06b
R18
1k
OPTO
Steady-State Operation with
7.1mA Load Current
63W OUTPUT
48W OUTPUT
25W OUTPUT
VDRAIN
100V/DIV
85
IPRIMARY
2A/DIV
80
3751 TA06d
20µs/DIV
75
0
R17
221k
4.7nF
Y RATED
90
70
100
FB
C8
22nF
R19
3.16k
OC
–0.25
–0.50
COMP
LT4430
GND
0.25
0
VIN
C9
3.3µF
Efficiency
0.50
U2
C10
0.47µF
VCC
VOUT
282V
225mA
C7
400µF
D4
M2
R7
475Ω
+
C6
0.1µF
Ns
•
OUT
C1, C8: 16V COG CERAMIC
C2
D1
DONE
HVGATE
TO
C2: 16V X5R OR X74 CERAMIC
1µF
MICRO
C3: 350V ELECTROLYTIC
FAULT
LVGATE
C4: 250V X5R OR X7R CERAMIC
R9, 2.7M
C5, C6, C11, C12: 630V X5R OR X7R CERAMIC
CSP
UVLO1
C7: 350V ELECTROLYTIC
VTRANS
R10, 4.3M
C9, C10: 25V X5R OR X7R CERAMIC
OVLO1
F1: 250V, 2A FUSE
R11, 84.5k
R1: 2010 RESISTOR, 1%
UVLO2
CSN
R2, R3, R6, R16, R17: 1206 RESISTORS, 1%
VCC
R12, 442k
R4, R5: TWO 1206 RESISTORS IN SERIES, 1%
OVLO2
FB
R7 THRU R12, R15 THRU R20: 0805 RESISTORS, 1%
D1: 12V ZENER
GND RBG
D2: VISHAY MURS140
3751 TA06a
D3: VISHAY P6KE200A
R8
D4: VISHAY MURS160
2.49k
D5: STMICROELECTRONICS STTH112A
D6: VISHAY BAT54
T1: TDK SRW24LQ
D7: NXP SEMICONDUCTORS BAS516
(Np:Ns:Npb:Nsb = 1:2:0.08:0.08)
M1: VISHAY IRF830
U1: NEC PS2801-1
M2: STMICROELECTRONICS STB11NM60FD U2: LINEAR TECHNOLOGY LT4430
OUTPUT VOLTAGE ERROR (V)
C4
1µF
×2
R3
210k
120
140
180
160
INPUT VOLTAGE (V)
Steady-State Operation with
225mA Load Current
200
3751 TA06c
VDRAIN
100V/DIV
IPRIMARY
2A/DIV
20µs/DIV
3751 TA06e
3751fc
29
LT3751
typical applications
Wide Input Voltage Range, 15 Watt, Triple Output Voltage Regulator
T1
2:1:3:3
(P1:S1:S2:S3) D1
VIN
5V TO 24V
+
C2
1000µF
×2
R5
25.5k
RVTRANS
CHARGE
CLAMP
OFF ON
C1
10µF
R1, 100k
R2, 100k
R3, 66.5k
C1, C3: 25V X5R OR X7R CERAMIC
C2: 25V SANYO 25ME1000AX
C4, C5: 35V SANYO 35ME470AX
C6: 10V KEMET T520D107M010ASE055
C7, C8: 16V CERAMIC, TDK C4532X7R1E106M
C9: 6.3V CERAMIC, TDK C4532X5R0J107M
D1, D2: CENTRAL SEMI CMSH2-60M
D3: CENTRAL SEM1 CMSH5-40
M1: FAIRCHILD FQD12N20L
R1 THRU R10, R12, R13: 0805 RESISTOR, 1%
R11: 1206 RESISTOR, 1%
T1: COILCRAFT HA3994-AL, 2:1:3:3 (P1:S1:S2:S3)
C3
10µF
R4, 464k
RDCM
VCC
LT3751
RVOUT
DONE
•
S3
P1
R7
25.5k
R12
4.99k
C5
470µF
R13
4.99k
+
D3
•
VCC
CSN
UVLO2
C4
470µF
C9
100µF
S1
+
VOUT2
–15V
VOUT1
+5V
C6
100µF
×2
R11
25mΩ
R9
309Ω
FB
OVLO2
GND RBG
VOUT3
+15V
•
M1
OVLO1
C8
10µF
S2
•
FAULT
UVLO1
+
D2
R6
11.5k
HVGATE
LVGATE
CSP
C7
10µF
R10
100Ω
R8
2.21k
3751 TA07a
Maximum Output Conditions
IOUT(MAX)* (mA)
VCC
(V)
POUT(MAX)
(W)
VOUT1
VOUT2
VOUT3
5
6.5
750
300
300
12
10
1750
300
300
24
13
2500
300
300
*All other output currents set to 0mA
Cross Regulation
(IVOUT1 = 100mA)
Cross Regulation
(IVOUT1 = 500mA)
VIN = 24V
VIN = 5V
VIN = 12V
16
26
90
24
85
VIN = 5V
22
EFFICIENCY (%)
18
–VOUT2, VOUT3 (V)
–VOUT2, VOUT3 (V)
20
Efficiency
(IVOUT1 = 500mA)
VIN = 24V
20
VIN = 12V
18
VIN = 24V
VIN = 12V
80
75
70
VIN = 5V
65
16
14
1
10
100
–IVOUT2, IVOUT3** (mA)
1000
3751 TA07b
14
1
10
100
–IVOUT2, IVOUT3** (mA)
1000
3751 TA07c
60
0
400
600
200
–IVOUT2 + IVOUT3 (mA)
800
3751 TA07d
**SOURCE/SINK IDENTICAL CURRENTS FROM BOTH VOUT2 AND VOUT3, RESPECTIVELY
3751fc
30
LT3751
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev I)
Exposed Pad Variation CB
6.40 – 6.60*
(.252 – .260)
3.86
(.152)
3.86
(.152)
20 1918 17 16 15 14 13 12 11
6.60 ±0.10
2.74
(.108)
4.50 ±0.10
6.40
2.74 (.252)
(.108) BSC
SEE NOTE 4
0.45 ±0.05
1.05 ±0.10
0.65 BSC
1 2 3 4 5 6 7 8 9 10
RECOMMENDED SOLDER PAD LAYOUT
4.30 – 4.50*
(.169 – .177)
0.09 – 0.20
(.0035 – .0079)
0.25
REF
0.50 – 0.75
(.020 – .030)
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS
MILLIMETERS
2. DIMENSIONS ARE IN
(INCHES)
3. DRAWING NOT TO SCALE
1.20
(.047)
MAX
0° – 8°
0.65
(.0256)
BSC
0.195 – 0.30
(.0077 – .0118)
TYP
0.05 – 0.15
(.002 – .006)
FE20 (CB) TSSOP REV I 0211
4. RECOMMENDED MINIMUM PCB METAL SIZE
FOR EXPOSED PAD ATTACHMENT
*DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.150mm (.006") PER SIDE
3751fc
31
LT3751
Package Description
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UFD Package
20-Pin Plastic QFN (4mm × 5mm)
(Reference LTC DWG # 05-08-1711 Rev B)
0.70 ±0.05
4.50 ± 0.05
1.50 REF
3.10 ± 0.05
2.65 ± 0.05
3.65 ± 0.05
PACKAGE OUTLINE
0.25 ±0.05
0.50 BSC
2.50 REF
4.10 ± 0.05
5.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 ± 0.10
(2 SIDES)
0.75 ± 0.05
PIN 1 NOTCH
R = 0.20 OR
C = 0.35
1.50 REF
R = 0.05 TYP
19
20
0.40 ± 0.10
PIN 1
TOP MARK
(NOTE 6)
1
2
5.00 ± 0.10
(2 SIDES)
2.50 REF
3.65 ± 0.10
2.65 ± 0.10
(UFD20) QFN 0506 REV B
0.200 REF
0.00 – 0.05
R = 0.115
TYP
0.25 ± 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3751fc
32
LT3751
Revision History
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
B
5/10
Updated FAULT (Pin 6/Pin 4) description in Pin Functions
7
Updated DONE (Pin 7/Pin 5) description in Pin Functions
8
Updated Block Diagram
9
C
6/12
PAGE NUMBER
Revised Applications Information section
17, 18
Revised Typical Applications illustration
30
Revised Applications Information section
20
Corrected Schematic R8 value from 3.40k to 2.21k
30
Updated FE package drawing
31
3751fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LT3751
Typical Application
300V Regulated Power Supply
VTRANS
24V
T1
1:10
+
C3
680µF
OFF ON
R6
40.2k
RVTRANS
CHARGE
CLAMP
VCC
24V
C1
10µF
C2
2.2µF
×5
RDCM
R7
18.2k
•
D1
+
•
RVOUT
VCC
TO
MICRO
R1
432k
VTRANS
R2
475k
R3
432k
VCC
R4
475k
C4
20µF
VOUT
300V
0mA TO 270mA
HVGATE
LVGATE
CSP
DONE
FAULT
R5
6mΩ
UVLO1
LT3751
OVLO1
CSN
UVLO2
FB
R9
1.13k
OVLO2
GND
R8*
274k
M1
VCC
* DEPENDING ON DESIRED OUTPUT
VOLTAGE, R8 MUST BE SPLIT
INTO MULTIPLE RESISTORS TO
MEET MANUFACTURER’S VOLTAGE
SPECIFICATION.
C5
10nF
RBG
3751 TA08
C1: 25V X5R OR X7R CERAMIC CAPACITOR
C2: 25V X5R OR X7R CERAMIC CAPACITOR
C3: 25V ELECTROLYTIC
C4: 330V RUBYCON PHOTOFLASH CAPACITOR
D1: VISHAY US1M 1000V
M1: FAIRCHILD FQP34N20L
R1 THROUGH R4: USE 1% 0805 RESISTORS
R5: IRC LR SERIES 2512 RESISTOR
T1: SUMIDA PS07-299, 20A TRANSFORMER
Related Parts
PART NUMBER
DESCRIPTION
COMMENTS
LTC3225
150mA Supercapacitor Charger
VIN: 2.75V to 5.5V, Charges Two Supercapacitors in Series to 4.8V or 5.3V
LT3420/LT3420-1
1.4A/1A, Photoflash Capacitor Charger
with Automatic Top-Off
Charges 220µF to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V, ISD < 1µA,
10-Lead MS Package
LT3468/LT3468-1/
LT3468-2
1.4A, 1A, 0.7A, Photoflash Capacitor Charger
VIN: 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100µF,
VIN = 3.6V), ISD < 1µA, ThinSOT™ Package
LT3484-0/LT3484-1/
LT3484-2
1.4A, 0.7A, 1A Photoflash Capacitor Charger
VIN: 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100µF,
VIN = 3.6V), ISD < 1µA, 2mm × 3mm 6-Lead DFN Package
LT3485-0/LT3485-1/
LT3485-2/LT3485-3
1.4A, 0.7A, 1A, 2A Photoflash Capacitor
Charger with Output Voltage Monitor and
Integrated IGBT
VIN: 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100µF,
VIN = 3.6V), ISD < 1µA, 3mm × 3mm 10-Lead DFN Package
LT3585-0/LT3585-1/
LT3585-2/LT3585-3
1.2A, 0.55A, 0.85A, 1.7A Photoflash
Capacitor Charger with Adjustable Input
Current and IGBT Drivers
VIN: 1.5V to 16V, Charge Time: 3.3 Seconds for LT3585-3 (0V to 320V, 100µF,
VIN = 3.6V), ISD < 1µA, 3mm × 2mm DFN-10 Package
LT3750
Capacitor Charger Controller
VIN: 3V to 24V, Charge Time: 300ms for (0V to 300V, 100µF) MSOP-10 Package
3751fc
34 Linear Technology Corporation
LT 0612 REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
 LINEAR TECHNOLOGY CORPORATION 2008