ISL9N315AD3 / ISL9N315AD3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description
Features
This device employs a new advanced trench MOSFET
technology and features low gate charge while maintaining
low on-resistance.
• Fast switching
Optimized for switching applications, this device improves
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies.
• rDS(ON) = 0.022Ω (Typ), VGS = 4.5V
Formerly developmental type 83337
• Qgd (Typ) = 3.4nC
Applications
• CISS (Typ) = 900pF
• rDS(ON) = 0.012Ω (Typ), VGS = 10V
• Qg (Typ) = 18nC, VGS = 5V
• DC/DC converters
DRAIN (FLANGE)
SOURCE
DRAIN
GATE
DRAIN
(FLANGE)
D
GATE
G
SOURCE
TO-252
S
TO-251
MOSFET Maximum Ratings TA=25°C unless otherwise noted
Symbol
VDSS
Parameter
Drain to Source Voltage
VGS
Gate to Source Voltage
Ratings
30
Units
V
±20
V
Drain Current
ID
Continuous (TC = 25oC, VGS = 10V)
30
A
Continuous (TC = 100oC, VGS = 4.5V)
23
A
10
A
Continuous (TC = 25oC, VGS = 10V, RθJA= 52oC/W)
Pulsed
PD
Power dissipation
Derate above 25oC
TJ, TSTG
Operating and Storage Temperature
Figure 4
A
55
0.37
W
W/oC
o
-55 to 175
C
Thermal Characteristics
RθJC
Thermal Resistance Junction to Case TO-251, TO-252
2.73
o
C/W
RθJA
Thermal Resistance Junction to Ambient TO-251, TO-252
100
o
C/W
RθJA
Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area
52
o
C/W
Package Marking and Ordering Information
Device Marking
N315AD
Device
ISL9N315AD3ST
Package
TO-252AA
Reel Size
330mm
Tape Width
16mm
Quantity
2500 units
N315AD
ISL9N315AD3
TO-251AA
Tube
N/A
75 units
©2003 Fairchild Semiconductor Corporation
ISL9N315AD3/ISL9N315AD3ST Rev. A1
ISL9N315AD3 / ISL9N315AD3ST
February 2003
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
IDSS
Zero Gate Voltage Drain Current
IGSS
Gate to Source Leakage Current
ID = 250µA, VGS = 0V
VDS = 25V
VGS = 0V
TC = 150oC
VGS = ±20V
30
-
-
V
-
-
1
-
-
250
µA
-
-
±100
nA
On Characteristics
VGS(TH)
rDS(ON)
Gate to Source Threshold Voltage
Drain to Source On Resistance
VGS = VDS, ID = 250µA
1
-
3
V
ID = 30A, VGS = 10V
-
0.012
0.015
ID = 23A, VGS = 4.5V
-
0.022
0.028
Ω
-
900
-
pF
-
210
-
pF
-
90
-
pF
VGS = 0V to 10V
-
18
28
nC
VGS = 0V to 5V V = 15V
DD
ID = 23A
Ig = 1.0mA
-
9.6
14
nC
-
1.0
1.5
nC
-
3.4
-
nC
-
3.4
-
nC
ns
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
Qg(TOT)
Total Gate Charge at 10V
Qg(5)
Total Gate Charge at 5V
Qg(TH)
Threshold Gate Charge
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
VDS = 15V, VGS = 0V,
f = 1MHz
VGS = 0V to 1V
Switching Characteristics (VGS = 4.5V)
tON
Turn-On Time
-
-
90
td(ON)
Turn-On Delay Time
-
11
-
ns
tr
Rise Time
-
49
-
ns
td(OFF)
Turn-Off Delay Time
-
27
-
ns
tf
Fall Time
-
28
-
ns
tOFF
Turn-Off Time
-
-
83
ns
VDD = 15V, ID = 10A
VGS = 4.5V, RGS = 18 Ω
Switching Characteristics (VGS = 10V)
tON
Turn-On Time
-
-
48
ns
td(ON)
Turn-On Delay Time
-
6
-
ns
tr
Rise Time
-
26
-
ns
td(OFF)
Turn-Off Delay Time
-
52
-
ns
tf
Fall Time
-
28
-
ns
tOFF
Turn-Off Time
-
-
120
ns
180
-
-
µs
V
VDD = 15V, ID = 10A
VGS = 10V, R GS = 18 Ω
Unclamped Inductive Switching
tAV
Avalanche Time
ID = 2.7 A, 3.0 mH
Drain-Source Diode Characteristics
ISD = 23A
-
-
1.25
ISD = 12A
-
-
1.0
V
Reverse Recovery Time
ISD = 23A, dISD /dt = 100A/µs
-
-
29
ns
Reverse Recovered Charge
ISD = 23A, dISD /dt = 100A/µs
-
-
18
nC
V SD
Source to Drain Diode Voltage
trr
QRR
©2003 Fairchild Semiconductor Corporation
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
Electrical Characteristics TA = 25°C unless otherwise noted
40
1.0
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
1.2
0.8
0.6
0.4
30
20
VGS = 10V
VGS = 4.5V
10
0.2
0
0
0
25
50
75
100
150
125
175
25
50
75
TC , CASE TEMPERATURE (oC)
100
125
150
175
TC, CASE TEMPERATURE (oC)
Figure 1. Normalized Power Dissipation vs
Ambient Temperature
Figure 2. Maximum Continuous Drain Current vs
Case Temperature
2
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t , RECTANGULAR PULSE DURATION (s)
Figure 3. Normalized Maximum Transient Thermal Impedance
500
TC = 25 oC
IDM, PEAK CURRENT (A)
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES
ABOVE 25o C DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
175 - TC
I = I25
150
100
VGS = 5V
20
10-5
10-4
10-3
10 -2
10 -1
100
101
t , PULSE WIDTH (s)
Figure 4. Peak Current Capability
©2003 Fairchild Semiconductor Corporation
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
Typical Characteristic
60
60
VGS = 10V
TJ = 25o C
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)
VGS = 4.5V
40
20
TJ = 175oC
40
VGS = 3.5V
VGS = 3.0V
20
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
TJ = -55oC
0
0
1
2
3
4
5
0
0.5
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics
1.5
2.0
2.5
Figure 6. Saturation Characteristics
50
2.0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
PULSE DURATION = 80µs
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
1.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
40
ID = 30A
ID = 15A
30
20
DUTY CYCLE = 0.5% MAX
1.5
1.0
VGS = 10V, ID = 30A
0.5
10
2
4
6
8
-80
10
-40
0
40
80
120
Figure 7. Drain to Source On Resistance vs Gate
Voltage and Drain Current
1.2
VGS = VDS, ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
ID = 250µA
1.2
NORMALIZED GATE
200
Figure 8. Normalized Drain to Source On
Resistance vs Junction Temperature
1.4
THRESHOLD VOLTAGE
160
TJ, JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
1.0
0.8
0.6
0.4
1.1
1.0
0.9
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
Figure 9. Normalized Gate Threshold Voltage vs
Junction Temperature
©2003 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
200
TJ , JUNCTION TEMPERATURE (oC)
Figure 10. Normalized Drain to Source
Breakdown Voltage vs Junction Temperature
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
Typical Characteristic (Continued)
10
2000
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = C GS + CGD
C, CAPACITANCE (pF)
1000
COSS ≅ CGS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
70
VDD = 15V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 30A
ID = 15A
2
0
0.1
1
30
10
0
3
6
9
Qg, GATE CHARGE (nC)
VDS , DRAIN TO SOURCE VOLTAGE (V)
Figure 11. Capacitance vs Drain to Source
Voltage
140
tr
VGS = 10V, VDD = 15V, ID = 9A
120
tf
60
td(OFF)
40
SWITCHING TIME (ns)
SWITCHING TIME (ns)
80
20
15
Figure 12. Gate Charge Waveforms for Constant
Gate Currents
100
VGS = 4.5V, VDD = 15V, ID = 9A
12
td(OFF)
100
80
60
tf
40
tr
td(ON)
20
0
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
Figure 13. Switching Time vs Gate Resistance
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
Figure 14. Switching Time vs Gate Resistance
Test Circuits and Waveforms
BVDSS
VDS
tP
VDS
L
IAS
VDD
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
Figure 15. Unclamped Energy Test Circuit
©2003 Fairchild Semiconductor Corporation
Figure 16. Unclamped Energy Waveforms
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
Typical Characteristic (Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
-
VGS = 1V
DUT
0
Ig(REF)
Qg(TH)
Qgs
Qgd
Ig(REF)
0
Figure 17. Gate Charge Test Circuit
Figure 18. Gate Charge Waveforms
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
Figure 19. Switching Time Test Circuit
©2003 Fairchild Semiconductor Corporation
50%
10%
50%
PULSE WIDTH
Figure 20. Switching Time Waveforms
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
Test Circuits and Waveforms (Continued)
(T
–T )
JM
A
P D M = ----------------------------Z θJ A
125
RθJA = 33.32 + 23.84/(0.268+Area)
100
RθJA (oC/W)
The maximum rated junction temperature, TJM , and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM , in an
application.
Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
75
(EQ. 1)
50
In using surface mount devices such as the TO-252
package, the environment in which it is applied will have a
significant influence on the part’s current and maximum
power dissipation ratings. Precise determination of P DM is
complex and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
25
0.01
0.1
1
10
AREA, TOP COPPER AREA (in2)
Figure 21. Thermal Resistance vs Mounting
Pad Area
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM .
Thermal resistances corresponding to other copper areas
can be obtained from Figure 21 or by calculation using
Equation 2. R θJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
23.84
( 0.268 + Area )
Rθ JA = 33.32 + -------------------------------------
©2003 Fairchild Semiconductor Corporation
(EQ. 2)
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
Thermal Resistance vs. Mounting Pad Area
rev October 02
LDRAIN
DPLCAP
10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RSLC2
5
51
-
EVTEMP
RGATE +
GATE
1
9
20
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.2e-3
RGATE 9 20 2.8
RLDRAIN 2 5 10
RLGATE 1 9 45.3
RLSOURCE 3 7 5.4
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 1.0e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
ESLC
11
+
50
21
EBREAK
16
17
18
-
DBODY
MWEAK
6
18 22
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
S1A
S1B
S2A
S2B
EVTHRES
+ 19 8
+
LGATE
DBREAK
RDRAIN
6
8
ESG
LDRAIN 2 5 1.0e-9
LGATE 1 9 4.53e-9
LSOURCE 3 7 5.38e-10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 31.0
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
DRAIN
2
5
+
.SUBCKT ISL9N315AD3 2 1 3 ;
CA 12 8 5.0e-10
CB 15 14 3.9e-10
CIN 6 8 7.8e-10
RLSOURCE
S1A
12
S2A
S1B
CA
15
14
13
13
8
RBREAK
17
18
RVTEMP
S2B
13
CB
6
8
EGS
-
19
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*120),3.5))}
.MODEL DBODYMOD D (IS = 3.5e-11 N=1.12 RS = 6.4e-3 TRS1 = 1e-3 TRS2 = 2.0e-6 XTI=2.3 CJO = 6.1e-10 TT = 1e-8
M=0.62)
.MODEL DBREAKMOD D (RS = 6.0e-1 TRS1 = 1e-3 TRS2 = -8.5e-6)
.MODEL DPLCAPMOD D (CJO = 3.4e-10 IS = 1e-30 N = 10 M = 0.45)
.MODEL MMEDMOD NMOS (VTO = 1.68 KP = 3.5 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.8)
.MODEL MSTROMOD NMOS (VTO = 2.00 KP = 35 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.36 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 28 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = -1e-7)
.MODEL RDRAINMOD RES (TC1 = 3.4e-2 TC2 = 6.0e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -8e-6)
.MODEL RVTEMPMOD RES (TC1 = -2e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4.0 VOFF= -1.5)
VON = -1.5 VOFF= -4.0)
VON = -0.5 VOFF= 0.3)
VON = 0.3 VOFF= -0.5)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.
©2003 Fairchild Semiconductor Corporation
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
PSPICE Electrical Model
REV October 2002
template ISL9N315AD3 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 3.5e-11, nl=1.12, rs = 6.4e-3, trs1 = 1e-3, trs2 = 2e-6, xti=2.3, cjo = 6.1e-10, tt = 1e-8, m = 0.62)
dp..model dbreakmod = (rs = 6e-1, trs1 = 1e-3, trs2 = -8.5e-6)
dp..model dplcapmod = (cjo = 3.4e-10, isl=10e-30, nl=10, m=0.45)
m..model mmedmod = (type=_n, vto = 1.68, kp=3.5, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.00, kp = 35, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.36, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -1.5)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1.5, voff = -4.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3)
LDRAIN
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5)
DPLCAP 5
DRAIN
RLDRAIN
RSLC1
51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
RDRAIN
6
8
ESG
GATE
1
EVTEMP
RGATE + 18 22
9
20
6
CIN
8
LSOURCE
7
RSOURCE
S1A
12
13
8
S2A
14
13
S1B
CA
EBREAK
+
17
18
-
MMED
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
DBODY
MWEAK
MSTRO
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -1e-7
res.rdrain n50 n16 = 1.2e-3, tc1 = 3.4e-2, tc2 = 6e-5
res.rgate n9 n20 = 2.8
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 45.3
res.rlsource n3 n7 = 5.4
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 1e-2, tc1 = 1e-3, tc2 =1e-6
res.rvtemp n18 n19 = 1, tc1 = -2e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -8e-6
11
EVTHRES
16
21
+ 19 8
+
LGATE
DBREAK
50
-
i.it n8 n17 = 1
l.ldrain n2 n5 = 1.00e-9
l.lgate n1 n9 = 4.53e-9
l.lsource n3 n7 = 5.38e-10
2
10
c.ca n12 n8 = 5.0e-10
c.cb n15 n14 = 3.9e-10
c.cin n6 n8 = 7.8e-10
RLSOURCE
RBREAK
15
17
18
RVTEMP
S2B
13
CB
+
+
6
8
EGS
-
SOURCE
3
19
IT
14
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 31.0
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/120))** 3.5))
}
}
©2003 Fairchild Semiconductor Corporation
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
SABER Electrical Model
th
JUNCTION
REV October 2002
ISL9N315AD3T
CTHERM1 th 6 1.3e-3
CTHERM2 6 5 1.5e-3
CTHERM3 5 4 1.6e-3
CTHERM4 4 3 1.7e-3
CTHERM5 3 2 5.8e-3
CTHERM6 2 tl 4.0e-2
RTHERM1
CTHERM1
6
RTHERM1 th 6 2.7e-3
RTHERM2 6 5 3.7e-3
RTHERM3 5 4 5.3e-2
RTHERM4 4 3 6.3e-1
RTHERM5 3 2 7.4e-1
RTHERM6 2 tl 7.6e-1
RTHERM2
CTHERM2
5
SABER Thermal Model
SABER thermal model ISL9N315AD3T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 1.3e-3
ctherm.ctherm2 6 5 = 1.5e-3
ctherm.ctherm3 5 4 = 1.6e-3
ctherm.ctherm4 4 3 = 1.7e-3
ctherm.ctherm5 3 2 = 5.8e-3
ctherm.ctherm6 2 tl = 4.0e-2
rtherm.rtherm1 th 6 = 2.7e-3
rtherm.rtherm2 6 5 = 3.7e-3
rtherm.rtherm3 5 4 = 5.3e-2
rtherm.rtherm4 4 3 = 6.3e-1
rtherm.rtherm5 3 2 = 7.4e-1
rtherm.rtherm6 2 tl = 7.6e-1
}
CTHERM3
RTHERM3
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2003 Fairchild Semiconductor Corporation
CASE
ISL9N315AD3/ISL9N315AD3ST Rev.A1
ISL9N315AD3 / ISL9N315AD3ST
SPICE Thermal Model
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Rev. I2