IDT IDT70V06S High-speed 3.3v 16k x 8 dual-port static ram Datasheet

HIGH-SPEED 3.3V
16K x 8 DUAL-PORT
STATIC RAM
IDT70V06S/L
Features
◆
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
– Commercial: 15/20/25/35/55ns (max.)
– Industrial: 20/25ns (max.)
Low-power operation
– IDT70V06S
Active: 400mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V06L
Active: 380mW (typ.)
Standby: 660µW (typ.)
IDT70V06 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
◆
◆
◆
◆
◆
◆
◆
◆
◆
◆
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CEL
R/WL
CER
R/WR
,
I/O0L- I/O7L
I/O
Control
I/O
Control
BUSYL
I/O0R-I/O7R
(1,2)
A13L
A0L
(1,2)
BUSYR
Address
Decoder
MEMORY
ARRAY
14
CEL
OEL
R/WL
SEML
(2)
INTL
Address
Decoder
A13R
A0R
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
M/S
CER
OER
R/WR
SEMR
INTR(2)
2942 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
AUGUST 2015
1
©2015 Integrated Device Technology, Inc.
DSC-2942/10
6.07
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using CMOS high-performance technology, these devices typically operate on only 400mW of power.
The IDT70V06 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
The IDT70V06 is a high-speed 16K x 8 Dual-Port Static RAM. The
IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port
Static RAM or as a combination MASTER/SLAVE Dual-Port Static
RAM for 16-bit-or-more word systems. Using the IDT MASTER/
SLAVE Dual-Port Static RAM approach in 16-bit or wider memory
system applications results in full-speed, error-free operation without
the need for additional discrete logic.
I/O1L
I/O0L
N/C
OEL
R/WL
SEML
CEL
N/C
A13L
VDD
A12L
A11L
A10L
A9L
A8L
A7L
A6L
Pin Configurations(1,2,3)
56
14
15
16
17
18
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
VSS
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
IDT70V06J
J68(4)
68-Pin PLCC
Top View(5)
55
54
53
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
2942 drw 02
I/O1L
I/O0L
OEL
R/WL
I/O7R
N/C
OER
R/WR
SEMR
CER
N/C
A13R
Vss
A12R
A11R
A10R
A9R
A8R
A7R
A6R
A5R
44
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A7L
A6L
A5L
2
A12L
A11L
A10L
A9L
A8L
57
3
56
55
58
13
4
CEL
12
5
A13L
VDD
59
6
58
57
11
7
SEML
1 68 67 66 65 64 63 62 61
60
8
59
10
9
I/O2L
I/O3L
I/O4L
I/O5L
VSS
I/O6L
I/O7L
VDD
VSS
I/O0R
I/O1R
I/O2R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
61
60
INDEX
49
51
50
54
5
6
53
52
VSS
I/O6L
I/O7L
64
1
2
3
48
A4L
47
46
A3L
45
44
A1L
4
VDD
7
8
VSS
9
I/O0R
I/O1R
I/O2R
VDD
10
43
A0L
INTL
42
BUSYL
64-Pin TQFP
Top View(5)
41
VSS
40
M/S
BUSYR
A4R
A0R
A2R
A5R
2942 drw 03
A6R
A9R
A8R
A7R
A10R
A11R
A12R
CER
A13R
VSS
SEMR
OER
R/WR
32
A3R
33
29
30
31
34
27
28
15
26
A1R
25
36
35
23
24
13
14
20
21
22
INTR
17
18
19
38
37
16
2
70V06PF
PN-64(4)
39
I/O7R
I/O3R
I/O4R
I/O5R
A2L
11
12
I/O6R
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in
PN-64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
I/O2L
I/O3L
I/O4L
I/O5L
63
62
INDEX
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
11
51
A5L
50
A4L
48
A2L
46
44
42
A0L BUSYL M/S
40
38
INTR A1R
36
A3R
49
A3L
47
A1L
45
43
INTL VSS
41
39
37
BUSYR A0R A2R
35
A4R
34
A5R
32
A7R
33
A6R
31
A8R
10
53
A7L
52
A6L
09
55
A9L
54
A8L
08
57
56
A11L A10L
30
A9R
59
VDD
58
07
28
29
A11R A10R
06
61
N/C
60
A13L
05
63
62
SEML CEL
04
65
64
OEL R/WL
22
23
SEMR CER
03
67
66
I/O0L N/C
20
OER
IDT70V06G
G68(4)
A12L
68-Pin PGA
Top View(5)
68
02 I/O1L
1
3
5
I/O2L I/O4L VSS
01
2
4
I/O3L I/O5L
A
B
C
7
9
I/O7L VSS
11
13
I/O1R VDD
E
F
G
27
A12R
24
N/C
25
A13R
21
R/WR
15
18
19
I/O4R I/O7R N/C
6
8
10
12
14
16
I/O6L
VDD I/O0R I/O2R I/O3R I/O5R
D
26
VSS
H
17
I/O6R
J
K
L
INDEX
2942 drw 04
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Left Port
Right Port
Names
CEL
CER
Chip Enable
R/WL
R/WR
Read/Write Enable
OEL
OER
Output Enable
A0L - A13L
A0R - A13R
Address
I/O0L - I/O7L
I/O0R - I/O7R
Data Input/Output
SEML
SEMR
Semaphore Enable
INTL
INTR
Interrupt Flag
BUSYL
BUSYR
Busy Flag
M/S
Master or Slave Select
VDD
Power (3.3V)
VSS
Ground (0V)
2942 tbl 01
6.42
3
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
Outputs
Mode
CE
R/W
OE
SEM
I/O0-7
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATAIN
Write to Memory
L
H
L
H
DATAOUT
X
X
H
X
High-Z
Read Memory
Outputs Disabled
2942 tbl 02
NOTE:
1. A0L — A13L ≠ A0R — A13R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
CE
R/W
OE
SEM
I/O0-7
Mode
H
H
L
L
DATAOUT
Read Data in Semaphore Flag
H
↑
X
L
DATAIN
Write I/O0 into Semaphore Flag
L
X
X
L
____
Not Allowed
2942 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.
4
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
TBIAS
Temperature
Under Bias
-55 to +125
o
C
TSTG
Storage
Temperature
-65 to +150
o
C
IOUT
DC Output
Current
Maximum Operating Temperature
and Supply Voltage(1)
Grade
COUT
Output Capacitance
0V
3.3V + 0.3V
-40OC to +85OC
0V
3.3V + 0.3V
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
mA
Recommended DC Operating
Conditions
Symbol
Capacitance (TA = +25°C, f = 1.0MHz)
Input Capacitance
0OC to +70OC
2942 tbl 05
2942 tbl 04
CIN
VDD
Industrial
50
Parameter(1)
GND
Commercial
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. VTERM must not exceed VDD + 0.3V.
Symbol
Ambient Temperature
Conditions
Max.
Unit
VIN = 3dV
9
pF
VOUT = 3dV
10
pF
Parameter
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
0
0
0
VDD
Supply Voltage
VSS
Ground
VIH
Input High Voltage
2.0
____
VIL
Input Low Voltage
-0.3(1)
____
V
(2)
VDD+0.3
0.8
V
V
2942 tbl 06
NOTES:
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD +0.3V.
2942 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V06S
Symbol
Parameter
Test Conditions
70V06L
Min.
Max.
Min.
Max.
Unit
|ILI|
Input Leakage Current(1)
VDD = 3.6V, VIN = 0V to VDD
___
10
___
5
µA
|ILO|
Output Leakage Current
VOUT = 0V to VDD
___
10
___
5
µA
VOL
Output Low Voltage
IOL = +4mA
___
0.4
___
0.4
V
VOH
Output High Voltage
IOH = -4mA
2.4
___
2.4
___
V
2942 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
6.42
5
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)
70V06X15
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
CEL or CER = VIH
Active Port Outputs Disabled,
f=fMAX(3)
Both Ports CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VDD - 0.2V
One Port CEL or
CER > VDD - 0.2V
SEMR = SEML > VDD - 0.2V
VIN > VDD - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
140
130
200
175
130
125
190
165
mA
mA
COM'L
S
L
150
140
215
185
IND
S
L
____
____
____
____
____
____
____
____
130
195
125
180
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
IND
S
L
____
____
____
____
____
____
____
____
15
40
13
40
mA
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
mA
IND
S
L
____
____
____
____
____
____
____
____
75
115
72
110
mA
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
IND
S
L
____
____
____
____
____
____
____
____
0.2
5
0.2
5
mA
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
mA
IND
S
L
____
____
____
____
____
____
____
____
75
115
70
105
mA
2942 tbl 09a
70V06X35
Com'l Only
Symbol
IDD
ISB1
ISB2
ISB3
ISB4
Parameter
Dynamic Operating
Current
(Both Ports Active)
Standby Current
(Both Ports - TTL
Level Inputs)
Standby Current
(One Port - TTL
Level Inputs)
Full Standby Current
(Both Ports CMOS Level Inputs)
Full Standby Current
(One Port CMOS Level Inputs)
Test Condition
Version
70V06X55
Com'l Only
Typ.(2)
Max.
Typ.(2)
Max.
Unit
COM'L
S
L
120
115
180
155
120
115
180
155
mA
IND
S
L
____
____
____
____
____
____
____
____
mA
COM'L
S
L
13
11
25
20
13
11
25
20
mA
IND
S
L
____
____
____
____
____
____
____
____
mA
COM'L
S
L
70
65
100
90
70
65
100
90
mA
IND
S
L
____
____
____
____
____
____
____
____
mA
Both Ports CEL and
CER > VDD - 0.2V,
VIN > VDD - 0.2V or
VIN < 0.2V, f = 0(4)
SEMR = SEML > VDD - 0.2V
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
IND
S
L
____
____
____
____
____
____
____
____
mA
One Port CEL or
CER > VDD - 0.2V
SEMR = SEML > VDD - 0.2V
VIN > VDD - 0.2V or V IN < 0.2V
Active Port Outputs Disabled,
f = fMAX(3)
COM'L
S
L
65
60
100
85
65
60
100
85
mA
IND
S
L
____
____
____
____
____
____
____
____
mA
CE = VIL, Outputs Disabled
SEM = VIH
f = fMAX(3)
CER = CEL = VIH
SEMR = SEML = VIH
f = fMAX(3)
CEL or CER = VIH
Active Port Outputs Disabled,
f=fMAX(3)
2942 tbl 09b
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3, TA = +25°C, and are not production tested. IDD DC = 115mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
6
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
3.3V
3.3V
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
590Ω
590Ω
3ns Max.
DATAOUT
BUSY
INT
DATAOUT
435Ω
435Ω
30pF
5pF*
Figures 1 and 2
,
2942 tbl 10
2942 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Timing of Power-Up Power-Down
CE
ICC
tPU
tPD
ISB
2942 drw 06
6.42
7
,
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V06X15
Com'l Only
Symbol
Parameter
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
15
____
20
____
25
____
ns
tAA
Address Access Time
____
15
____
20
____
25
ns
tACE
Chip Enable Access Time (3)
____
15
____
20
____
25
ns
tAOE
Output Enable Access Time (3)
____
10
____
12
____
13
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time (1,2)
3
____
3
____
3
____
ns
tHZ
Output High-Z Time (1,2)
____
10
____
12
____
15
ns
tPU
Chip Enable to Power Up Time (1,2)
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time (1,2)
____
15
____
20
____
25
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
10
____
10
____
10
____
ns
tSAA
Semaphore Address Access (3)
____
15
____
20
____
25
ns
2942 tbl 11a
70V06X35
Com'l Only
Symbol
Parameter
70V06X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
ns
tAA
Address Access Time
____
35
____
55
ns
tACE
Chip Enable Access Time (3)
____
35
____
55
ns
____
20
____
30
ns
3
____
3
____
ns
3
____
3
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
35
____
50
ns
15
____
15
____
ns
____
35
____
55
ns
(3)
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
(1,2)
tLZ
Output Low-Z Time
tHZ
Output High-Z Time (1,2)
tPU
Chip Enable to Power Up Time (1,2)
(1,2)
tPD
Chip Disable to Power Down Time
tSOP
Semaphore Flag Update Pulse (OE or SEM)
tSAA
Semaphore Address Access
(3)
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed but not tested.
3. To access SRAM, CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
8
2942 tbl 11b
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
CE
tAA
(4)
tACE
tAOE
(4)
OE
R/W
tLZ
tOH
(1)
(4)
DATAOUT
VALID DATA
tHZ (2)
BUSYOUT
tBDD(3,4)
2942 drw 07
NOTES:
1. Timing depends on which signal is asserted las OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
70V06X15
Com'l Only
Symbol
Parameter
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
15
____
20
____
25
____
ns
tEW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
ns
tAW
Address Valid to End-of-Write
12
____
15
____
20
____
ns
0
____
0
____
0
____
ns
ns
WRITE CYCLE
tWC
Write Cycle Time
(3)
tAS
Address Set-up Time
tWP
Write Pulse Width
12
____
15
____
20
____
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tDW
Data Valid to End-of-Write
10
____
15
____
15
____
ns
____
10
____
12
____
15
ns
0
____
0
____
ns
12
____
15
ns
ns
tHZ
Output High-Z Time
Data Hold Time
tDH
tWZ
(1,2)
(4)
0
____
(1,2)
____
10
____
(1,2,4)
0
____
0
____
0
____
SEM Flag Write to Read Time
5
____
5
____
5
____
ns
SEM Flag Contention Window
5
____
5
____
5
____
ns
Write Enable to Output in High-Z
tOW
tSWRD
tSPS
Output Active from End-of-Write
2942 tbl 12a
70V06X35
Com'l Only
Symbol
Parameter
70V06X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
tWC
Write Cycle Time
35
____
55
____
ns
tEW
Chip Enable to End-of-Write (3)
30
____
45
____
ns
tAW
Address Valid to End-of-Write
30
____
45
____
ns
tAS
Address Set-up Time (3)
0
____
0
____
ns
tWP
Write Pulse Width
25
____
40
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
15
____
30
____
ns
____
15
____
25
ns
0
____
0
____
ns
____
15
____
25
ns
tHZ
tDH
Output High-Z Time
Data Hold Time
(1,2)
(4)
(1,2)
tWZ
Write Enable to Output in High-Z
tOW
Output Active from End-of-Write (1,2,4)
0
____
0
____
ns
tSWRD
SEM Flag Write to Read Time
5
____
5
____
ns
SEM Flag Contention Window
5
____
5
____
ns
tSPS
2942 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed but not tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
10
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
tWC
ADDRESS
tHZ
(7)
OE
tAW
CE or SEM
(9)
tAS
(6)
tWP
(2)
tWR
(3)
R/W
tWZ
(7)
tOW
(4)
DATAOUT
(4)
tDW
tDH
DATAIN
2942 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
tWC
ADDRESS
tAW
CE or SEM
(9)
(6)
tAS
tWR (3)
tEW (2)
R/W
tDW
tDH
DATAIN
2942 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
11
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
tAW
tOH
VALID ADDRESS
tWR
tACE
tEW
SEM
tDW
DATA0
tSOP
DATA OUT
VALID(2)
DATAIN VALID
tAS
tWP
tDH
R/W
tSWRD
OE
tAOE
tSOP
Write Cycle
Read Cycle
2942 drw 10
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0 - I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
(2)
SIDE
"A"
MATCH
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
(2)
SIDE
"B"
MATCH
R/W"B"
SEM"B"
2942 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
12
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V06X15
Com'l Ony
Symbol
Parameter
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
15
____
20
____
20
ns
tBDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable LOW
____
15
____
20
____
20
ns
BUSY Disable Time from Chip Enable HIGH
____
15
____
17
____
17
ns
5
____
5
____
5
____
ns
tBDC
(2)
tAPS
Arbitration Priority Set-up Time
tBDD
BUSY Disable to Valid Data(3)
____
18
____
30
____
30
ns
tWH
Write Hold After BUSY(5)
12
____
15
____
17
____
ns
0
____
0
____
0
____
ns
12
____
15
____
17
____
ns
____
30
____
45
____
50
ns
____
25
____
35
____
35
ns
BUSY TIMING (M/S = VIL)
BUSY Input to Write (4)
tWB
(5)
Write Hold After BUSY
tWH
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
2942 tbl 13a
70V06X35
Com'l Only
Symbol
Parameter
70V06X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH)
tBAA
BUSY Access Time from Address Match
____
20
____
45
ns
tBDA
BUSY Disable Time from Address Not Matched
____
20
____
40
ns
tBAC
BUSY Access Time from Chip Enable LOW
____
20
____
40
ns
tBDC
BUSY Disable Time from Chip Enable HIGH
____
20
____
35
ns
5
____
5
____
ns
____
35
____
40
ns
25
____
25
____
ns
tAPS
tBDD
tWH
Arbitration Priority Set-up Time
(2)
(3)
BUSY Disable to Valid Data
(5)
Write Hold After BUSY
BUSY TIMING (M/S = VIL)
tWB
BUSY Input to Write (4)
0
____
0
____
ns
tWH
Write Hold After BUSY(5)
25
____
25
____
ns
____
60
____
80
ns
____
45
____
65
ns
PORT-TO-PORT DELAY TIMING
tWDD
tDDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay
(1)
2942 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH) or "Timing Waveform of Write With
Port-To-Port Delay (M/S=VIL)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. "X" is part numbers indicates power rating (S or L).
6.42
13
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-To-Port Read and BUSY(2,4,5)
(M/S = VIH)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDW
tDH
VALID
DATAIN "A"
tAPS
(1)
MATCH
ADDR"B"
tBDA
tBAA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
tDDD
(3)
2942 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL(slave) then BUSY is input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right port. Port "A" may be either left or right port. Port "B" is the port opposite from Port "A".
14
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
tWB(3)
BUSY"B"
tWH (1)
R/W"B"
(2)
,
2942 drw 13
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on Port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
tAPS
(2)
CE"B"
tBAC
tBDC
BUSY"B"
2942 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
tAPS
(2)
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
2942 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
70V06X15
Com'l Only
Symbol
Parameter
70V06X20
Com'l
& Ind
70V06X25
Com'l
& Ind
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
0
____
ns
tINS
Interrupt Set Time
____
15
____
20
____
20
ns
tINR
Interrupt Reset Time
____
15
____
20
____
20
ns
2942 tbl 14a
70V06X35
Com'l Only
Symbol
Parameter
70V06X55
Com'l Only
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tINS
Interrupt Set Time
____
25
____
40
ns
tINR
Interrupt Reset Time
____
25
____
40
ns
2942 tbl 14b
NOTE:
1. 'X' in part number indicates power rating (S or L).
Waveform of Interrupt Timing(1)
tWC
ADDR"A"
INTERRUPT SET ADDRESS
tAS
(3)
(2)
tWR (4)
CE"A"
R/W"A"
tINS
(3)
INT"B"
2942 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
16
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1) (con't.)
tRC
ADDR"B"
INTERRUPT CLEAR ADDRESS
tAS
(2)
(3)
CE"B"
OE"B"
tINR
(3)
INT"B"
2942 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
R/WL
CEL
OEL
A13L-A0L
INTL
R/WR
CER
OER
A13R-A0R
L
L
X
3FFF
X
X
X
X
X
INTR
L(2)
(3)
Function
Set Right INTR Flag
X
X
X
X
X
X
L
L
3FFF
H
Reset Right INTR Flag
X
X
X
X
L(3)
L
L
X
3FFE
X
Set Left INTL Flag
X
L
L
3FFE
H(2)
X
X
X
X
X
Reset Left INTL Flag
2942 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
6.42
17
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
CEL
CER
A13L-A0L
A13R-A0R
BUSYL(1)
BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
H
X
MATCH
H
H
Normal
X
H
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
2942 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V06 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable
inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0 - D7 Left
D0 - D7 Right
Status
No Action
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
1
Semaphore free
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V06.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0 - I/O7). These eight semaphores are addressed by A0 -A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70V06 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V06 has an automatic power down
feature controlled by CE. The CE controls on-chip power down circuitry
that permits the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (INTL) is set when the right port writes to memory location 3FFE
2942 tbl 17
(HEX). The left port clears the interrupt by reading address location 3FFE.
Likewise, the right port interrupt flag (INTR) is set when the left port writes
to memory location 3FFF (HEX) and to clear the interrupt flag (INTR), the
right port must read the memory location 3FFF. The message (8 bits) at
3FFE or 3FFF is user-defined. If the interrupt function is not used, address
locations 3FFE and 3FFF are not used as mail boxes, but as part of the
random access memory. Refer to Truth Table III for the interrupt
operation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
18
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
BUSY (L)
CE
MASTER
Dual Port
SRAM
BUSY (L) BUSY (R)
CE
SLAVE
Dual Port
SRAM
BUSY (L) BUSY (R)
MASTER
CE
Dual Port
SRAM
BUSY (L) BUSY (R)
SLAVE
CE
Dual Port
SRAM
BUSY (L) BUSY (R)
DECODER
Industrial and Commercial Temperature Ranges
BUSY (R)
2942 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V06 SRAMs.
allows one of the two accesses to proceed and signals the other side that
the SRAM is “busy”. The BUSY pin can then be used to stall the access
until the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of an
illegal or illogical operation. If the write inhibit function of BUSY logic is not
desirable, the BUSY logic can be disabled by placing the part in slave mode
with the M/S pin. Once in slave mode the BUSY pin operates solely as
an input. Normal operation can be programmed by tying the BUSY pins
HIGH. If desired, unintended write operations can be prevented to a port
by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT 70V06 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the busy indication
for the resulting array requires the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V06 SRAM array in width while using
BUSY logic, one master part is used to decide which side of the SRAM array
will receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master use
the BUSY signal as a write inhibit signal. Thus on the IDT70V06 RAM the
BUSY pin is an output if the part is used as a master (M/S pin = VIH), and
the BUSY pin is an input if the part used as a slave (M/S pin = VIL) as shown
in Figure 3.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for part of
the other word.
The BUSY arbitration, on a master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with the R/W signal. Failure to observe this timing
can result in a glitched internal write inhibit signal and corrupted data in the
slave.
Semaphores
The IDT70V06 is an extremely fast Dual-Port 16K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAM to claim a privilege over the other processor
for functions defined by the system designer’s software. As an example, the semaphore can be used by one processor to inhibit the
other from accessing a portion of the Dual-Port SRAM or any other shared
resource.
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are protected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic powerdown feature controlled by CE, the Dual-Port SRAM enable, and SEM,
the semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
I where CE and SEM are both HIGH.
Systems which can best use the IDT70V06 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V06's
hardware semaphores without requiring complex programming.
Software handshaking between processors offers the maximum in
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V06 does not use its semaphore flags
to control any resources through hardware, thus allowing the system
6.42
19
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are independent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignment method called “Token Passing Allocation.” In this method,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource, it requests the token by setting the latch. This processor then
verifies its success in setting the latch by reading it. If it was successful,
it assumes control over the shared resource. If it was not successful
in setting the latch, it determines that the right side processor has set
the latch first, has the token and is using the shared resource. The left
processor can then either repeatedly request that semaphore’s status
or remove its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the set and
test sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V06 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which
acts as a chip select for the semaphore flags) and using the other
control pins (Address, OE, and R/W) as they would be used in
accessing a standard Static RAM. Each of the flags has a unique
address which can be accessed by either side through address pins
A0 – A2. When accessing the semaphores, none of the other address
pins has any effect.
When writing to a semaphore, only data pin D0 is used. If a low is written
into an unused semaphore location, that flag will be set to a zero on that
side and a one on the other side (see Truth Table V). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.
When a semaphore flag is read, its value is spread into all data bits so
that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side’s output
register when that side's semaphore select (SEM) and output enable (OE)
signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Industrial and Commercial Temperature Ranges
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written successfully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
fact that a one will be read from that semaphore on the right side during
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two semaphore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
both requests arrive at the same time, the assignment will be arbitrarily
made to one port or the other.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any semaphore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
20
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Using Semaphores-Some Examples
Perhaps the simplest application of semaphores is their application as
resource markers for the IDT70V06’s Dual-Port SRAM. Say the 16K x 8
SRAM was to be divided into two 8K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control the
lower section of memory, and Semaphore 1 could be defined as the
indicator for the upper section of memory.
To take a resource, in this example the lower 8K of Dual-Port SRAM,
the processor on the left port could write and then read a zero in to
Semaphore 0. If this task were successfully completed (a zero was read
back rather than a one), the left processor would assume control of the
lower 8K. Meanwhile the right processor was attempting to gain control of
the resource after the left processor, it would read back a one in response
to the zero it had attempted to write into Semaphore 0. At this point, the
software could choose to try and gain control of the second 8K section by
writing, then reading a zero into Semaphore 1. If it succeeded in gaining
control, it would lock out the left side.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performs a similar task with Semaphore 0, this protocol would allow the
two processors to swap 8K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
semaphore flags. All eight semaphores could be used to divide the DualPort SRAM or other shared resources into eight parts. Semaphores can
even be assigned different meanings on different sides rather than being
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continuously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Another application is in the area of complex data structures. In this
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
go in and update the data structure. When the update is completed, the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaranteeing a consistent data structure.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
D0
D
SEMAPHORE
REQUEST FLIP FLOP
Q
Q
WRITE
D
D0
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
Figure 4. IDT70V06 Semaphore Logic
6.42
21
2942 drw 19
,
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
999
A
Device
Type
Power
Speed
Package
A
A
A
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Blank Commercial (0°C to +70°C)
I(1)
Industrial (-40°C to +85°C)
G(2)
Green
PF
G
J
64-pin TQFP (PN64)
68-pin PGA (G68)
68-pin PLCC (J68)
15
20
25
35
55
Commercial Only
Commercial & Industrial
Commercial & Industrial Speed in Nanoseconds
Commercial Only
Commercial Only
S
L
Standard Power
Low Power
70V06 128K (16K x 8) 3.3V Dual-Port RAM
2942 drw 20
NOTES:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. Green parts are available, for specific speeds, packages, and powers, contact your local sales office.
Datasheet Document History
3/10/99:
6/9/99:
11/10/99:
3/10/00:
5/30/00:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changed drawing format
Replaced IDT logo
Added 15 & 20ns speed grades
Upgraded DC parameters
Added Industrial Temperature information
Changed ±200mV to 0mV
Page 5 Increased storage temperature parameter
Clarified TA parameter
Page 6 DC Electrical parameters–changed wording from "open" to "disabled"
22
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History (cont'd)
11/20/01:
10/23/08:
08/20/15:
Page 1 Corrected standby power designation from mW to µW
Page 2 & 3 Added date revision for pin configurations
Page 2, 3, 5 & 6 Changed naming conventions from VCC to VDD and from GND to VSS
Page 6 Removed Industrial temp for standard power for 20ns and 25ns speeds from DC Electrical Characteristics
Removed Industrial temp for 35ns and 55ns speeds from DC Electrical Characteristics
Pages 8,13 & 16 Removed Industrial temp for 35ns and 55ns speeds from AC Electrical Characteristics
Page 8 Replaced table 11 with table 11a to show AC Electrical Characteristics for READ CYCLE for 15, 20 & 25ns
Page 22 Removed Industrial temp from 35ns and 55ns in ordering information
Page 22 Removed "IDT" from orderable part number
Page 1 In Features: Added text: “Green parts available, see ordering information”.
Page 2 In Description: Removed IDT in reference to fabrication
Page 2 ,3 & 22 The package codes PN64-1, G68-1 & J68-1 changed to PN64, G68 & J68 respectively to match standard
package codes
Page 2 & 3 Removed date from all of the pin configurations 64-pin TQFP, 68-pin PGA & 68-pin PLCC configurations
Page 19 & 20 Corrected miscellaneous typo's
Page 22 Added Green and Tape & Reel indicators to the Ordering Information and updated footnotes
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6.42
23
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