ADS8320 SBAS108D – MAY 2000 – REVISED MARCH 2007 16-Bit, High-Speed, 2.7V to 5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION ● 100kHz SAMPLING RATE ● microPOWER: 1.8mW at 100kHz and 2.7V 0.3mW at 10kHz and 2.7V ● POWER-DOWN: 3µA max ● MSOP-8 PACKAGE ● PIN-COMPATIBLE TO ADS7816 AND ADS7822 ● SERIAL (SPI™/SSI) INTERFACE The ADS8320 is a 16-bit, sampling analog-to-digital (A/D) converter with ensured specifications over a 2.7V to 5.25V supply range. It requires very little power even when operating at the full 100kHz data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode—the average power dissipation is less than 100mW at 10kHz data rate. APPLICATIONS The ADS8320 also features operation from 2.0V to 5.25V, a synchronous serial (SPI/SSI compatible) interface, and a differential input. The reference voltage can be set to any level within the range of 500mV to VCC. Ultra-low power and small size make the ADS8320 ideal for portable and battery-operated systems. It is also a perfect fit for remote data acquisition modules, simultaneous multi-channel systems, and isolated data acquisition. The ADS8320 is available in an MSOP-8 package. ● ● ● ● BATTERY-OPERATED SYSTEMS REMOTE DATA ACQUISITION ISOLATED DATA ACQUISITION SIMULTANEOUS SAMPLING, MULTICHANNEL SYSTEMS ● INDUSTRIAL CONTROLS ● ROBOTICS ● VIBRATION ANALYSIS Control SAR VREF DOUT +In CDAC Serial Interface –In S/H Amp DCLOCK CS/SHDN Comparator Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. Copyright © 2000-2007, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. www.ti.com SPECIFICATIONS: +VCC = +5V At –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. ADS8320E PARAMETER CONDITIONS MIN TYP ADS8320EB MAX RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range +In – (–In) +In –In 0 –0.1 –0.1 VREF VCC + 0.1 +1.0 Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Offset Error Offset Temperature Drift Gain Error Gain Temperature Drift Noise Power-Supply Rejection Ratio REFERENCE INPUT Voltage Range Resistance ±0.006 ±0.5 ✻ ±0.05 +4.7V < VCC < 5.25V V V V pF nA ±0.012 ±1 ✻ ✻ 100 2.4 0.024 VIN = 5VPP at 10kHz VIN = 5VPP at 10kHz VIN = 5VPP at 10kHz –86 84 86 92 0.5 VCC 5 5 40 0.8 0.1 ✻ 80 3 ✻ ✻ ✻ CS = VCC –40 ✻ ✻ ✻ ✻ 0.4 V GΩ GΩ µA µA µA V V V V ✻ Straight Binary 900 200 4.5 0.3 Clk Cycles Clk Cycles kHz MHz ✻ VCC + 0.3 0.8 4.75 2.0 Bits % of FSR mV µV/°C % ppm/°C µVrms LSB(1) dB dB dB dB ✻ ✻ ✻ ✻ ✻ ✻ CMOS 3.0 –0.3 4.0 ✻ ✻ ✻ –84 82 84 90 CS = GND, fSAMPLE = 0Hz CS = VCC TEMPERATURE RANGE Specified Performance ✻ ✻ ✻ ±0.024 16 Specified Performance Bits ✻ ✻ ✻ 4.5 fSAMPLE = 10kHz(3, 4) Power Dissipation Power-Down ±0.018 ±2 ±0.3 20 3 fSAMPLE = 10kHz CS = VCC POWER-SUPPLY REQUIREMENTS VCC VCC Range(2) Quiescent Current UNITS ✻ 15 ±0.008 ±1 ±3 IIH = +5µA IIL = +5µA IOH = –250µA IOL = 250µA MAX ✻ ✻ 14 Current Drain DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format TYP ✻ ✻ ✻ 45 1 SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Clock Frequency Range DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious-Free Dynamic Range SNR MIN 16 5.25 5.25 1700 ✻ ✻ ✻ ✻ ✻ ✻ 8.5 3 +85 ✻ ✻ ✻ ✻ ✻ ✻ V V µA µA mW µA ✻ °C ✻ Specifications same as ADS8320E. NOTES: (1) (2) (3) (4) 2 LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 0.076mV. See Typical Performance Curves for more information. fCLK = 2.4MHz, CS = VCC for 216 clock cycles out of every 240. See the Power Dissipation section for more information regarding lower sample rates. ADS8320 www.ti.com SBAS108D SPECIFICATIONS: +VCC = +2.7V At –40°C to +85°C, VREF = 2.5V, –IN = GND, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. ADS8320E PARAMETER CONDITIONS MIN TYP ADS8320EB MAX RESOLUTION ANALOG INPUT Full-Scale Input Span Absolute Input Range +In – (–In) +In –In 0 –0.1 –0.1 Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Offset Error Offset Temperature Drift Gain Error Gain Temperature Drift Noise Power-Supply Rejection Ratio REFERENCE INPUT Voltage Range Resistance ±0.018 ±2 ±0.006 ±0.5 ✻ ±0.05 ±0.3 20 3 +2.7V < VCC < +3.3V ✻ ✻ ✻ 100 2.4 VCC 5 5 20 0.1 ✻ 50 3 2.0 –0.3 2.1 VCC + 0.3 0.8 ✻ ✻ ✻ 2.7 2.0 2.0 650 100 1.8 0.3 CS = VCC TEMPERATURE RANGE Specified Performance –40 Clk Cycles Clk Cycles kHz MHz dB dB dB dB ✻ ✻ ✻ ✻ ✻ 0.4 fSAMPLE = 10kHz(4,5) Bits % of FSR mV µV/°C ±0.024 % of FSR ppm/°C µVrms LSB(1) ±0.012 ±1 V GΩ GΩ µA µA ✻ V V V V ✻ Straight Binary See Note 2 V V V pF nA ✻ ✻ ✻ ✻ ✻ CMOS Specified Performance ✻ ✻ ✻ –88 86 88 90 0.5 IIH = +5µA IIL = +5µA IOH = –250µA IOL = 250µA Bits ✻ ✻ ✻ –86 84 86 88 CS = GND, fSAMPLE = 0Hz CS = VCC UNITS ✻ ✻ 0.024 VIN = 2.7Vp-p at 1kHz VIN = 2.7Vp-p at 1kHz VIN = 2.7Vp-p at 1kHz MAX ✻ 16 4.5 Quiescent Current Power Dissipation Power-Down ✻ ✻ ✻ 15 ±0.008 ±1 ±3 CS = VCC POWER-SUPPLY REQUIREMENTS VCC VCC Range(3) TYP ✻ ✻ 14 Current Drain DIGITAL INPUT/OUTPUT Logic Family Logic Levels: VIH VIL VOH VOL Data Format VREF VCC + 0.1 +0.5 45 1 SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Clock Frequency Range DYNAMIC CHARACTERISTICS Total Harmonic Distortion SINAD Spurious-Free Dynamic Range SNR MIN 16 3.3 5.25 2.7 1300 ✻ ✻ ✻ ✻ ✻ ✻ ✻ 3.8 3 +85 ✻ ✻ ✻ ✻ ✻ ✻ ✻ V V V µA µA mW µA ✻ °C ✻ Specifications same as ADS8320E. NOTES: (1) (2) (3) (4) (5) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 0.038mV. The maximum clock rate of the ADS8320 is less than 2.4MHz in this power supply range. See the Typical Performance Curves for more information. fCLK = 2.4MHz, CS = VCC for 216 clock cycles out of every 240. See the Power Dissipation section for more information regarding lower sample rates. ADS8320 SBAS108D www.ti.com 3 ELECTROSTATIC DISCHARGE SENSITIVITY PIN CONFIGURATION Top View MSOP VREF 1 +In 2 8 +VCC 7 DCLOCK Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Texas Instruments recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ADS8320 –In 3 6 DOUT GND 4 5 CS/SHDN ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. ABSOLUTE MAXIMUM RATINGS(1) PIN ASSIGNMENTS PIN NAME 1 VREF DESCRIPTION 2 +In Noninverting Input. 3 –In Inverting Input. Connect to ground or to remote ground sense point. Reference Input. 4 GND 5 CS/SHDN Chip Select when LOW, Shutdown Mode when HIGH. Ground. 6 DOUT The serial output data word is comprised of 16 bits of data. In operation the data is valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit the data is valid for the next 16 edges. 7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed. 8 +VCC VCC ....................................................................................................... +6V Analog Input .............................................................. –0.3V to (VCC + 0.3V) Logic Input ............................................................................... –0.3V to 6V Case Temperature ......................................................................... +100°C Junction Temperature .................................................................... +150°C Storage Temperature ..................................................................... +125°C External Reference Voltage .............................................................. +5.5V Input current to any pin except supply ............................................ ±10mA NOTE: (1) Stresses above these ratings may permanently damage the device. Power Supply. PACKAGE/ORDERING INFORMATION(1) PRODUCT ADS8320E ADS8320E ADS8320EB ADS8320EB MAXIMUM INTEGRAL LINEARITY ERROR (%) NO MISSING CODE ERROR (LSB) 0.018 " PACKAGE PACKAGE DESIGNATOR SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING(2) ORDERING NUMBER(3) 14 MSOP-8 DGK –40°C to +85°C A20 " " " " " 0.012 15 MSOP-8 DGK –40°C to +85°C A20 " " " " " " ADS8320E/250 ADS8320E/2K5 ADS8320EB/250 ADS8320EB/2K5 TRANSPORT MEDIA Tape Tape Tape Tape and and and and Reel Reel Reel Reel NOTES: (1) For the most current product and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI website at www.ti.com. (2) Performance Grade information is marked on the reel. (3) Models with a slash(/) are available only in tape and reel in quantities indicated (for example, /250 indicates 250 units per reel, /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of ”ADS8320E/2K5“ will get a single 2500-piece tape and reel. 4 ADS8320 www.ti.com SBAS108D TYPICAL PERFORMANCE CURVES At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. INTEGRAL LINEARITY ERROR vs CODE (+25°C) DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) 20 3.0 Differential Linearity Error (LSB) Integral Linearity Error (LSB) 1.0 0.0 –1.0 –2.0 –3.0 –4.0 –5.0 –6.0 0000H 4000H 8000H Hex Code C000H 2.0 1.0 0.0 –1.0 –2.0 –3.0 0000H FFFFH C000H FFFFH POWER-DOWN SUPPLY CURRENT vs TEMPERATURE 1200 600 1000 500 Supply Current (nA) 5V 800 2.7V 600 400 200 400 5V 300 200 100 0 0 –50 –25 0 25 50 75 100 –50 –25 0 Temperature (°C) 25 50 75 100 Temperature (°C) QUIESCENT CURRENT vs VCC MAXIMUM SAMPLE RATE vs VCC 1200 1000 1000 Sample Rate (kHz) Quiescent Current (µA) 8000H Hex Code SUPPLY CURRENT vs TEMPERATURE Supply Current (µA) 4000H 800 600 100 10 400 200 1 1 2 3 4 5 1 VCC (V) ADS8320 SBAS108D www.ti.com 2 3 VCC (V) 4 5 5 TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = +2.7V, VREF = +2.5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. CHANGE IN OFFSET vs TEMPERATURE CHANGE IN OFFSET vs REFERENCE VOLTAGE 3 6 VCC = 5V 2 4 Delta from +25 C (LSB) Change in Offset (LSB) 5 3 2 1 0 –1 1 5V 0 2.7V −1 −2 –2 −3 –3 1 2 3 Reference Voltage (V) 4 −50 5 −25 0 25 50 75 100 Temperature (°C) CHANGE IN GAIN vs REFERENCE VOLTAGE CHANGE IN GAIN vs TEMPERATURE 5 6 VCC = 5V 4 Delta from 25°C (LSB) Change in Gain (LSB) 4 3 2 1 0 –2 5V –2 2.7V –6 1 2 3 Reference Voltage (V) 4 5 –50 –25 0 25 50 75 100 Temperature (°C) FREQUENCY SPECTRUM (8192 Point FFT, FIN = 10.120kHz, –0.3dB) 0 PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE 10 VCC = 5V 9 Peak-to-Peak Noise (LSB) –20 –40 Amplitude (dB) 0 –4 –1 –60 –80 –100 –120 8 7 6 5 4 3 2 1 –140 0 0 6 2 10 20 30 Frequency (kHz) 40 0.1 50 1 Reference Voltage (V) 10 ADS8320 www.ti.com SBAS108D TYPICAL PERFORMANCE CURVES (Cont.) At TA = +25°C, VCC = +5V, VREF = +5V, fSAMPLE = 100kHz, and fCLK = 24 • fSAMPLE, unless otherwise specified. SPURIOUS-FREE DYNAMIC RANGE AND SIGNAL-TO-NOISE RATIO vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 0 Signal-to-Noise Ratio 90 80 Spurious-Free Dynamic Range 70 –10 Total Harmonic Distortion (dB) Spurious-Free Dynamic Range and Signal-to-Noise Ratio (dB) 100 60 50 40 30 20 –20 –30 –40 –50 –60 –70 –80 10 –90 0 –100 1 10 Frequency (kHz) 50 100 1 SIGNAL-TO-(NOISE + DISTORTION) vs FREQUENCY 90 Signal-to-(Noise + Distortion) (dB) Signal-to-(Noise + Distortion) (dB) 100 SIGNAL-TO-(NOISE + DISTORTION) vs INPUT LEVEL 100 90 80 70 60 50 40 30 20 10 1 10 Frequency (kHz) 50 80 70 60 50 40 30 20 –40 0 100 REFERENCE CURRENT vs SAMPLE RATE 70 60 60 50 40 5V 30 20 –35 –30 –25 –20 –15 Input Level (dB) –10 –5 0 REFERENCE CURRENT vs TEMPERATURE 70 Reference Current (µA) Reference Current (µA) 10 Frequency (kHz) 2.7V 50 5V 40 30 2.7V 20 10 0 0 20 40 60 Sample Rate (kHz) 80 10 –50 100 0 25 50 75 100 Temperature (°C) ADS8320 SBAS108D –25 www.ti.com 7 THEORY OF OPERATION The ADS8320 is a classic successive approximation register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution, which inherently includes a sample/hold function. The converter is fabricated on a 0.6µ CMOS process. The architecture and process allow the ADS8320 to acquire and convert an analog signal at up to 100,000 conversions per second while consuming less than 4.5mW from +VCC. The ADS8320 requires an external reference, an external clock, and a single power source (VCC). The external reference can be any voltage between 500mV and VCC. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8320. The external clock can vary between 24kHz (1kHz throughput) and 2.4MHz (100kHz throughput). The duty cycle of the clock is essentially unimportant, as long as the minimum high and low times are at least 200ns (VCC = 2.7V or greater). The minimum clock frequency is set by the leakage on the capacitors internal to the ADS8320. The analog input is provided to two input pins: +In and –In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. It is possible to continue to clock the ADS8320 after the conversion is complete and to obtain the serial data least significant bit first. See the digital timing section for more information. ANALOG INPUT The +In and –In input pins allow for a differential input signal. Unlike some converters of this type, the –In input is not re-sampled later in the conversion cycle. When the converter goes into the hold mode, the voltage difference between +In and –In is captured on the internal capacitor array. The range of the –In input is limited to –0.1V to +1V (–0.1V to +0.5V when using a 2.7V supply). Because of this, the differential input can be used to reject only small signals that are common to both inputs. Thus, the –In input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. Essentially, the current into the ADS8320 8 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (45pF) to a 16-bit settling level within 4.5 clock cycles. When the converter goes into the hold mode or while it is in the powerdown mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –In input should not drop below GND – 100mV or exceed GND + 1V. The +In input should always remain within the range of GND – 100mV to VCC + 100mV. Outside of these ranges, the converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with lowpass filters should be used. REFERENCE INPUT The external reference sets the analog input range. The ADS8320 operates with a reference in the range of 500mV to VCC. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the Least Significant Bit (LSB) size and is equal to the reference voltage divided by 65,536. This means that any offset or gain error inherent in the A/D converter will appear to increase, in terms of LSB size, as the reference voltage is reduced. The noise inherent in the converter also appears to increase with lower LSB size. With a +5V reference, the internal noise of the converter typically contributes only 1.5 LSB peak-to-peak of potential error to the output code. When the external reference is 500mV, the potential error contribution from the internal noise will be 10 times larger—15 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult the typical performance curve “Peak-to-Peak Noise vs Reference Voltage.” Note that the Effective Number of Bits (ENOB) figure is calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 • ENOB + 1.76 With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter is also more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. ADS8320 www.ti.com SBAS108D NOISE The noise floor of the ADS8320 itself is extremely low, as can be seen from Figures 1 and 2, and is much lower than competing A/D converters. It was tested by applying a lownoise DC input and a 5.0V reference to the ADS8320 and initiating 5000 conversions. The digital output of the A/D 2510 0 0 1 2 2490 3 4 0 0 5 6 Code FIGURE 1. Histogram of 5000 Conversions of a DC Input at the Code Transition. 4864 converter varies in output code due to the internal noise of the ADS8320. This is true for all 16-bit SAR-type A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions represents the 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6 and this yields the ±3σ distribution or 99.7% of all codes. Statistically, up to 3 codes could fall outside the distribution when executing 1000 conversions. The ADS8320, with < 3 output codes for the ±3σ distribution, yields a < ±0.5LSB transition noise. Remember, to achieve this low noise performance, the peak-to-peak noise of the input signal and reference must be < 50µV. AVERAGING The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√n, where n is the number of averages. For example, averaging four conversion results reduces the transition noise by 1/2 to ±0.25 LSBs. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signalto-noise ratio improves 3dB. DIGITAL INTERFACE 0 0 72 1 2 3 4 64 0 5 6 SIGNAL LEVELS The digital inputs of the ADS8320 can accommodate logic levels up to 5.5V regardless of the value of VCC. Thus, the ADS8320 can be powered at 3V and still accept inputs from logic powered at 5V. The CMOS digital output (DOUT) swings 0V to VCC. If VCC is 3V and this output is connected to a 5V CMOS logic input, then that IC may require more supply current than normal and may have a slightly longer propagation delay. Code FIGURE 2. Histogram of 5000 Conversions of a DC Input at the Code Center. ADS8320 SBAS108D www.ti.com 9 SERIAL INTERFACE The ADS8320 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as shown in Figure 3 and Table I. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and outputs a LOW value for one clock period. For the next 16 DCLOCK periods, DOUT outputs the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks repeat the output data but in a least significant bit first format. After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken HIGH and returned LOW. SYMBOL DESCRIPTION MIN tSMPL Analog Input Sample Time 4.5 TYP MAX UNITS 5.0 Clk Cycles tCONV Conversion Time tCYC Throughput Rate 100 kHz tCSD CS Falling to DCLOCK LOW 0 ns tSUCS CS Falling to DCLOCK Rising 20 thDO DCLOCK Falling to Current DOUT Not Valid 5 tdDO DCLOCK Falling to Next DOUT Valid tdis ten 16 Clk Cycles ns 15 ns 30 50 ns CS Rising to DOUT Tri-State 70 100 ns DCLOCK Falling to DOUT Enabled 20 50 ns tf DOUT Fall Time 5 25 ns tr DOUT Rise Time 7 25 ns DATA FORMAT The output data from the ADS8320 is in Straight Binary format, as shown in Table II. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. DESCRIPTION ANALOG VALUE Full-Scale Range VREF Least Significant Bit (LSB) VREF/65,536 DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE HEX CODE Full-Scale VREF – 1 LSB 1111 1111 1111 1111 FFFF Midscale VREF/2 1000 0000 0000 0000 8000 VREF/2 – 1 LSB 0111 1111 1111 1111 7FFF 0V 0000 0000 0000 0000 0000 Midscale – 1LSB Zero TABLE II. Ideal Input Voltages and Output Codes. POWER DISSIPATION The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS8320 to convert at up to a 100kHz rate while requiring very little power. Still, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS8320 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that satisfies the requirements of the system. In addition, the ADS8320 is in power-down mode under two conditions: when the conversion is complete and whenever CS is HIGH (as shown in Figure 3). Ideally, each conversion should occur as quickly as possible, preferably at a 2.4MHz clock rate. This way, the converter spends the longest possible time in the power-down mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until the power-down mode is entered. TABLE I. Timing Specifications (VCC = 2.7V and above, –40°C to +85°C. Complete Cycle CS/SHDN tSUCS Sample Power Down Conversion DCLOCK tCSD DOUT Use positive clock edge for data transfer Hi-Z 0 tSMPL B15 B14 B13 B12 B11 B10 B9 B8 (MSB) tCONV B7 B6 B5 B4 B3 B2 B1 B0 (LSB) Hi-Z NOTE: Minimum 22 clock cycles required for 16-bit conversion. Shown are 24 clock cycles. If CS remains LOW at the end of conversion, a new datastream with LSB-first is shifted out again. FIGURE 3. ADS8320 Basic Timing Diagrams. 10 ADS8320 www.ti.com SBAS108D 1.4V 3kΩ DOUT VOH DOUT VOL Test Point tr 100pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK VIL VCC DOUT tdDO VOH DOUT tdis Waveform 2, ten 3kΩ tdis Waveform 1 100pF CLOAD VOL thDO Load Circuit for tdis and ten Voltage Waveforms for DOUT Delay Times, tdDO VIH CS/SHDN DOUT Waveform 1(1) CS/SHDN 90% DCLOCK 1 4 5 tdis DOUT Waveform 2(2) VOL DOUT 10% B11 ten Voltage Waveforms for tdis Voltage Waveforms for ten NOTES: (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. FIGURE 4. Timing Diagrams and Test Circuits for the Parameters in Table I. ADS8320 SBAS108D www.ti.com 11 LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8320 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. At a 100kHz conversion rate, the ADS8320 makes a bit decision every 416ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level all within one clock cycle. 12 Supply Current (µA) TA = 25°C fCLK = 2.4MHz 100 VCC = 2.7V VREF = 2.5V VCC = 5.0V VREF = 5.0V 10 1 0.1 1 10 100 Sample Rate (kHz) FIGURE 5. Maintaining fCLK at the Highest Possible Rate Allows Supply Current to Drop Linearly with Sample Rate. 1000 Supply Current (µA) SHORT CYCLING Another way of saving power is to utilize the CS signal to short cycle the conversion. Because the ADS8320 places the latest data bit on the DOUT line as it is generated, the converter can easily be short cycled. This term means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling CS HIGH) after the 14th bit has been clocked out. This technique can be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system, as they spend more time in the power-down mode. 1000 100 10 TA = 25°C VCC = 5.0V VREF = 5.0V fCLK = 24 • fSAMPLE 1 0.1 1 10 100 Sample Rate (kHz) FIGURE 6. Scaling fCLK Reduces Supply Current Only Slightly with Sample Rate. 1000 TA = 25°C VCC = 5.0V VREF = 5.0V fCLK = 24 • fSAMPLE 800 Supply Current (µA) Figure 5 shows the current consumption of the ADS8320 versus sample rate. For this graph, the converter is clocked at 2.4MHz regardless of the sample rate—CS is HIGH for the remaining sample period. Figure 6 also shows current consumption versus sample rate. However, in this case, the DCLOCK period is 1/24th of the sample period—CS is HIGH for one DCLOCK cycle out of every 16. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode which is enabled when CS is HIGH. CS LOW will shut down only the analog section. The digital section is completely shut down only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption will not be as low as when CS is HIGH. Figure 7 shows more information. Power dissipation can also be reduced by lowering the power-supply voltage and the reference voltage. The ADS8320 operates over a VCC range of 2.0V to 5.25V. However, at voltages below 2.7V, the converter will not run at a 100kHz sample rate. See the typical performance curves for more information regarding power supply voltage and maximum sample rate. 600 CS LOW (GND) 400 200 0.0 CS HIGH (VCC) 0.250 0.00 0.1 1 10 100 Sample Rate (kHz) FIGURE 7. Shutdown Current with CS HIGH is 50nA Typically, Regardless of the Clock. Shutdown Current with CS LOW Varies with Sample Rate. ADS8320 www.ti.com SBAS108D The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter DCLOCK signal—as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS8320 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the ADS8320 package as possible. In addition, a 1µF to 10µF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. The reference should be similarly bypassed with a 0.1µF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, be careful that the op amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS8320 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. Texas Instruments' OPA627 op amp provides optimum performance for buffering both the signal and reference inputs. For low-cost, low-voltage, single-supply applications, the OPA2350 or OPA2340 dual op amps are recommended. Also, keep in mind that the ADS8320 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50Hz or 60Hz), can be difficult to remove. The GND pin on the ADS8320 should be placed on a clean ground point. In many cases, this will be the “analog” ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply connection point. The ideal layout includes an analog ground plane for the converter and associated analog circuitry. APPLICATION CIRCUITS Figure 8 shows a basic data acquisition system. The ADS8320 input range is 0V to VCC, as the reference input is connected directly to the power supply. The 5Ω resistor and 1µF to 10µF capacitor filter the microcontroller “noise” on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of the noise. +2.7V to +5.25V 5Ω + 1µF to 10µF ADS8320 VREF VCC 0.1µF +In CS –In DOUT GND + 1µF to 10µF Microcontroller DCLOCK FIGURE 8. Basic Data Acquisition System. ADS8320 SBAS108D www.ti.com 13 Revision History DATE REVISION PAGE SECTION 3/07 D 4 Absolute Max Ratings 7/06 C 6 Typ Performance Curves DESCRIPTION Added last row, Input current to any pin except supply...±10mA Changed CHANGE IN OFFSET vs TEMPERATURE plot NOTE: Page numbers for previous revisions may differ from page numbers in the current version. 14 ADS8320 www.ti.com SBAS108D PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) ADS8320E/250 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 A20 ADS8320E/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 A20 ADS8320E/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 A20 ADS8320E/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 A20 ADS8320EB/250 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 A20 ADS8320EB/250G4 ACTIVE VSSOP DGK 8 250 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 A20 ADS8320EB/2K5 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 A20 ADS8320EB/2K5G4 ACTIVE VSSOP DGK 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) -40 to 85 A20 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. 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OTHER QUALIFIED VERSIONS OF ADS8320 : NOTE: Qualified Version Definitions: Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant ADS8320E/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8320E/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8320EB/250 VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8320EB/2K5 VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8320E/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS8320E/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8320EB/250 VSSOP DGK 8 250 210.0 185.0 35.0 ADS8320EB/2K5 VSSOP DGK 8 2500 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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