Cirrus CS42426 114 db, 192 khz 6-ch codec with pll Datasheet

CS42426
114 dB, 192 kHz 6-Ch Codec with PLL
Features
General Description
! Six 24-bit D/A, two 24-bit A/D Converters
The CS42426 codec provides two analog-to-digital and
six digital-to-analog delta-sigma converters, as well as
an integrated PLL.
! 114 dB DAC / 114 dB ADC Dynamic Range
! -100 dB THD+N
The CS42426 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of
independent channel gain control for single-ended or
differential analog inputs. All six channels of DAC provide digital volume control and differential analog
outputs. The general-purpose outputs may be driven
high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.
! System Sampling Rates up to 192 kHz
! Integrated Low-Jitter PLL for Increased System
Jitter Tolerance
! PLL Clock or System Clock Selection
! 7 Configurable General-Purpose Outputs
! ADC High-Pass Filter for DC Offset Calibration
The CS42426 is ideal for audio systems requiring wide
dynamic range, negligible distortion and low noise, such
as A/V receivers, DVD receivers, digital speaker and
automotive audio systems.
! Expandable ADC Channels and One-Line
Mode Support
! Digital Output Volume Control with Soft Ramp
The CS42426 is available in a 64-pin LQFP package in
both Commercial (-10° to +70° C) and Automotive
(-40° to +85° C) grades. The CDB42428 Customer
Demonstration board is also available for device evaluation. Refer to “Ordering Information” on page 71.
! Digital +/-15 dB Input Gain Adjust for ADC
! Differential Analog Architecture
! Supports Logic Levels between 1.8 V and 5 V
VA AGND
GPO1
GPO2
GPO3
GPO4
GPO5
GPO6
GPO7
REFGND VQ FILT+
OMCK
RMCK
LPFLT
VLC
DGND VD
INT
Mult/Div
RST
AD0/CS
AD1/CDIN
SDA/CDOUT
SCL/CCLK
Control
Port
GPO
Mute
Internal Voltage
Reference
PLL
AINL+
AINL-
ADC#1
Digital Filter
Gain & Clip
AINR+
AINR-
ADC#2
Digital Filter
Gain & Clip
AOUTB2+
AOUTB2-
DAC#3
DAC#4
AOUTA3+
AOUTA3-
DAC#5
AOUTB3+
AOUTB3-
DAC#6
http://www.cirrus.com
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
Level Translator
AOUTA2+
AOUTA2-
DAC Serial Audio Port
DAC#2
Volume Control
AOUTB1+
AOUTB1-
ADC
Serial
Audio
Port
ADCIN1
ADCIN2
ADC_SDOUT
ADC_LRCK
ADC_SCLK
VLS
Digital Filter
DAC#1
Analog Filter
AOUTA1+
AOUTA1-
Level Translator
MUTEC
DAC_LRCK
DAC_SCLK
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
NOVEMBER '05
DS604F1
CS42426
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
SPECIFIED OPERATING CONDITIONS ............................................................................................... 6
ABSOLUTE MAXIMUM RATINGS ......................................................................................................... 6
ANALOG INPUT CHARACTERISTICS .................................................................................................. 7
A/D DIGITAL FILTER CHARACTERISTICS .......................................................................................... 8
ANALOG OUTPUT CHARACTERISTICS .............................................................................................. 9
D/A DIGITAL FILTER CHARACTERISTICS ........................................................................................ 10
SWITCHING CHARACTERISTICS ...................................................................................................... 11
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT .............................................. 12
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT .......................................... 13
DC ELECTRICAL CHARACTERISTICS .............................................................................................. 14
DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 15
2. PIN DESCRIPTIONS ............................................................................................................................ 16
3. TYPICAL CONNECTION DIAGRAMS .............................................................................................. 18
4. APPLICATIONS ................................................................................................................................... 20
4.1 Overview ......................................................................................................................................... 20
4.2 Analog Inputs .................................................................................................................................. 20
4.2.1 Line-Level Inputs ................................................................................................................... 20
4.2.2 High-Pass Filter and DC Offset Calibration ........................................................................... 21
4.3 Analog Outputs ............................................................................................................................... 21
4.3.1 Line-Level Outputs and Filtering ........................................................................................... 21
4.3.2 Interpolation Filter .................................................................................................................. 21
4.3.3 Digital Volume and Mute Control ........................................................................................... 22
4.3.4 ATAPI Specification ............................................................................................................... 22
4.4 Clock Generation ............................................................................................................................ 23
4.4.1 PLL and Jitter Attenuation ..................................................................................................... 23
4.4.2 OMCK System Clock Mode ................................................................................................... 24
4.4.3 Master Mode ......................................................................................................................... 24
4.4.4 Slave Mode ........................................................................................................................... 24
4.5 Digital Interfaces ............................................................................................................................. 25
4.5.1 Serial Audio Interface Signals ............................................................................................... 25
4.5.2 Serial Audio Interface Formats .............................................................................................. 27
4.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................................... 30
4.5.4 One-Line Mode (OLM) Configurations .................................................................................. 31
4.5.4.1 OLM Config #1 ........................................................................................................... 31
4.5.4.2 OLM Config #2 ........................................................................................................... 32
4.5.4.3 OLM Config #3 ........................................................................................................... 33
4.5.4.4 OLM Config #4 ........................................................................................................... 34
4.6 Control Port Description and Timing ............................................................................................... 35
4.6.1 SPI Mode ............................................................................................................................... 35
4.6.2 I²C Mode ................................................................................................................................ 36
4.7 Interrupts ........................................................................................................................................ 37
4.8 Reset and Power-Up ...................................................................................................................... 37
4.9 Power Supply, Grounding, and PCB Layout .................................................................................. 38
5. REGISTER QUICK REFERENCE ........................................................................................................ 39
6. REGISTER DESCRIPTION .................................................................................................................. 42
6.1 Memory Address Pointer (MAP) ..................................................................................................... 42
6.2 Chip I.D. and Revision Register (address 01h) (Read Only) .......................................................... 42
6.3 Power Control (address 02h) .......................................................................................................... 43
6.4 Functional Mode (address 03h) ...................................................................................................... 43
6.5 Interface Formats (address 04h) .................................................................................................... 45
6.6 Misc Control (address 05h) ............................................................................................................ 46
2
DS604F1
CS42426
6.7 Clock Control (address 06h) ........................................................................................................... 48
6.8 OMCK/PLL_CLK Ratio (address 07h) (Read Only) ....................................................................... 49
6.9 Clock Status (address 08h) (Read Only) ........................................................................................ 50
6.10 Volume Transition Control (address 0Dh) .................................................................................... 51
6.11 Channel Mute (address 0Eh) ........................................................................................................ 52
6.12 Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h) ...................................................... 53
6.13 Channel Invert (address 17h) ....................................................................................................... 53
6.14 Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah) ............................................................. 53
6.15 ADC Left Channel Gain (address 1Ch) ........................................................................................ 55
6.16 ADC Right Channel Gain (address 1Dh) ...................................................................................... 55
6.17 Interrupt Control (address 1Eh) .................................................................................................... 55
6.18 Interrupt Status (address 20h) (Read Only) ................................................................................. 56
6.19 Interrupt Mask (address 21h) ....................................................................................................... 57
6.20 Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h) ............................................................................................... 57
6.21 Mutec Pin Control (address 28h) .................................................................................................. 57
6.22 General-Purpose Pin Control (addresses 29h to 2Fh) ................................................................. 58
7. PARAMETER DEFINITIONS ................................................................................................................ 60
8. APPENDIX A: EXTERNAL FILTERS ................................................................................................... 61
8.1 ADC Input Filter .............................................................................................................................. 61
8.2 DAC Output Filter ........................................................................................................................... 61
9. APPENDIX B: PLL FILTER .................................................................................................................. 62
9.1 External Filter Components ............................................................................................................ 62
9.1.1 General .................................................................................................................................. 62
9.1.2 Capacitor Selection ............................................................................................................... 62
9.1.3 Circuit Board Layout .............................................................................................................. 63
10. APPENDIX C: ADC FILTER PLOTS .................................................................................................. 64
11. APPENDIX D: DAC FILTER PLOTS .................................................................................................. 66
12. PACKAGE DIMENSIONS ............................................................................................................... 70
THERMAL CHARACTERISTICS .......................................................................................................... 70
13. ORDERING INFORMATION .............................................................................................................. 71
14. REFERENCES .................................................................................................................................... 71
15. REVISION HISTORY ......................................................................................................................... 72
LIST OF FIGURES
Figure 1.Serial Audio Port Master Mode Timing ....................................................................................... 11
Figure 2.Serial Audio Port Slave Mode Timing ......................................................................................... 11
Figure 3.Control Port Timing - I²C Format ................................................................................................. 12
Figure 4.Control Port Timing - SPI Format ................................................................................................ 13
Figure 5.Typical Connection Diagram ....................................................................................................... 18
Figure 6.Typical Connection Diagram using the PLL ................................................................................ 19
Figure 7.Full-Scale Analog Input ............................................................................................................... 20
Figure 8.Full-Scale Output ........................................................................................................................ 21
Figure 9.ATAPI Block Diagram (x = channel pair 1, 2, 3) ......................................................................... 22
Figure 10.Clock Generation ...................................................................................................................... 23
Figure 11.Right-Justified Serial Audio Formats ......................................................................................... 27
Figure 12.I²S Serial Audio Formats ........................................................................................................... 28
Figure 13.Left-Justified Serial Audio Formats ........................................................................................... 28
Figure 14.One-Line Mode #1 Serial Audio Format ................................................................................... 29
Figure 15.One-Line Mode #2 Serial Audio Format ................................................................................... 29
Figure 16.ADCIN1/ADCIN2 Serial Audio Format ...................................................................................... 30
DS604F1
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CS42426
Figure 17.OLM Configuration #1 ............................................................................................................... 31
Figure 18.OLM Configuration #2 ............................................................................................................... 32
Figure 19.OLM Configuration #3 ............................................................................................................... 33
Figure 20.OLM Configuration #4 ............................................................................................................... 34
Figure 21.Control Port Timing in SPI Mode .............................................................................................. 35
Figure 22.Control Port Timing, I²C Write ................................................................................................... 36
Figure 23.Control Port Timing, I²C Read ................................................................................................... 36
Figure 24.Recommended Analog Input Buffer .......................................................................................... 61
Figure 25.Recommended Analog Output Buffer ....................................................................................... 61
Figure 26.Recommended Layout Example ............................................................................................... 63
Figure 27.Single-Speed Mode Stopband Rejection .................................................................................. 64
Figure 28.Single-Speed Mode Transition Band ........................................................................................ 64
Figure 29.Single-Speed Mode Transition Band (Detail) ............................................................................ 64
Figure 30.Single-Speed Mode Passband Ripple ...................................................................................... 64
Figure 31.Double-Speed Mode Stopband Rejection ................................................................................. 64
Figure 32.Double-Speed Mode Transition Band ....................................................................................... 64
Figure 33.Double-Speed Mode Transition Band (Detail) .......................................................................... 65
Figure 34.Double-Speed Mode Passband Ripple ..................................................................................... 65
Figure 35.Quad-Speed Mode Stopband Rejection ................................................................................... 65
Figure 36.Quad-Speed Mode Transition Band ......................................................................................... 65
Figure 37.Quad-Speed Mode Transition Band (Detail) ............................................................................. 65
Figure 38.Quad-Speed Mode Passband Ripple ....................................................................................... 65
Figure 39.Single-Speed (fast) Stopband Rejection ................................................................................... 66
Figure 40.Single-Speed (fast) Transition Band ......................................................................................... 66
Figure 41.Single-Speed (fast) Transition Band (detail) ............................................................................. 66
Figure 42.Single-Speed (fast) Passband Ripple ....................................................................................... 66
Figure 43.Single-Speed (slow) Stopband Rejection ................................................................................. 66
Figure 44.Single-Speed (slow) Transition Band ........................................................................................ 66
Figure 45.Single-Speed (slow) Transition Band (detail) ............................................................................ 67
Figure 46.Single-Speed (slow) Passband Ripple ...................................................................................... 67
Figure 47.Double-Speed (fast) Stopband Rejection ................................................................................. 67
Figure 48.Double-Speed (fast) Transition Band ........................................................................................ 67
Figure 49.Double-Speed (fast) Transition Band (detail) ............................................................................ 67
Figure 50.Double-Speed (fast) Passband Ripple ...................................................................................... 67
Figure 51.Double-Speed (slow) Stopband Rejection ................................................................................ 68
Figure 52.Double-Speed (slow) Transition Band ...................................................................................... 68
Figure 53.Double-Speed (slow) Transition Band (detail) .......................................................................... 68
Figure 54.Double-Speed (slow) Passband Ripple .................................................................................... 68
Figure 55.Quad-Speed (fast) Stopband Rejection .................................................................................... 68
Figure 56.Quad-Speed (fast) Transition Band .......................................................................................... 68
Figure 57.Quad-Speed (fast) Transition Band (detail) .............................................................................. 69
Figure 58.Quad-Speed (fast) Passband Ripple ........................................................................................ 69
Figure 59.Quad-Speed (slow) Stopband Rejection ................................................................................... 69
Figure 60.Quad-Speed (slow) Transition Band ......................................................................................... 69
Figure 61.Quad-Speed (slow) Transition Band (detail) ............................................................................. 69
Figure 62.Quad-Speed (slow) Passband Ripple ....................................................................................... 69
4
DS604F1
CS42426
LIST OF TABLES
Table 1. Common OMCK Clock Frequencies ............................................................................................ 24
Table 2. Common PLL Output Clock Frequencies..................................................................................... 24
Table 3. Slave Mode Clock Ratios ............................................................................................................. 25
Table 4. Serial Audio Port Channel Allocations ......................................................................................... 26
Table 5. DAC De-Emphasis ....................................................................................................................... 44
Table 6. Digital Interface Formats .............................................................................................................. 45
Table 7. ADC One-Line Mode.................................................................................................................... 45
Table 8. DAC One-Line Mode.................................................................................................................... 45
Table 9. RMCK Divider Settings ................................................................................................................ 48
Table 10. OMCK Frequency Settings ........................................................................................................ 48
Table 11. Master Clock Source Select....................................................................................................... 49
Table 12. PLL Clock Frequency Detection................................................................................................. 50
Table 13. Example Digital Volume Settings ............................................................................................... 53
Table 14. ATAPI Decode ........................................................................................................................... 54
Table 15. Example ADC Input Gain Settings ............................................................................................. 55
Table 16. PLL External Component Values ............................................................................................... 62
DS604F1
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CS42426
1. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and specifications are derived from measurements taken at nominal supply voltages
and TA = 25° C.)
SPECIFIED OPERATING CONDITIONS
(AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)
Parameter
DC Power Supply
Analog
Digital
Serial Port Interface
Control Port Interface
Ambient Operating Temperature (power applied)
CS42426-CQZ
CS42426-DQZ
Symbol
Min
Typ
Max
Units
VA
VD
VLS
VLC
4.75
3.13
1.8
1.8
5.0
3.3
5.0
5.0
5.25
5.25
5.25
5.25
V
V
V
V
TA
-10
-40
-
+70
+85
°C
°C
ABSOLUTE MAXIMUM RATINGS
(AGND = DGND = 0 V; all voltages with respect to ground.)
Parameters
Symbol
Min
Max
Units
Analog
Digital
Serial Port Interface
Control Port Interface
Input Current
(Note 1)
Analog Input Voltage
(Note 2)
Digital Input Voltage
Serial Port Interface
(Note 2)
Control Port Interface
Ambient Operating Temperature(power applied)
CS42426-CQZ
CS42426-DQZ
Storage Temperature
VA
VD
VLS
VLC
Iin
-0.3
-0.3
-0.3
-0.3
-
6.0
6.0
6.0
6.0
±10
V
V
V
V
mA
DC Power Supply
VIN
AGND-0.7
VA+0.7
V
VIND-S
VIND-C
-0.3
-0.3
VLS+ 0.4
VLC+ 0.4
V
V
TA
TA
Tstg
-20
-50
-65
+85
+95
+150
°C
°C
°C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation
is not guaranteed at these extremes.
Notes:
1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause
SCR latch-up.
2. The maximum over/under voltage is limited by the input current.
6
DS604F1
CS42426
ANALOG INPUT CHARACTERISTICS
(TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5 V; Measurement
Bandwidth is 10 Hz to 20 kHz unless otherwise specified. Full-scale input sine wave, 997 Hz.; PDN_PLL = 1;
OMCK = 12.288 MHz; Single-Speed Mode DAC_SCLK = 3.072 MHz; Double-Speed Mode DAC_SCLK =
6.144 MHz; Quad-Speed Mode DAC_SCLK = 12.288 MHz.)
Parameter
Symbol
Single-Speed Mode
Dynamic Range
(Fs=48 kHz)
A-weighted
unweighted
Total Harmonic Distortion + Noise
(Note 3)
-1 dB
-20 dB
-60 dB
Double-Speed Mode (Fs=96 kHz)
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion + Noise
(Note 3)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
Quad-Speed Mode
(Fs=192 kHz)
Dynamic Range
A-weighted
unweighted
40 kHz bandwidth unweighted
Total Harmonic Distortion+ Noise
(Note 3)
-1 dB
-20 dB
-60 dB
40 kHz bandwidth
-1 dB
THD+N
THD+N
THD+N
Min
CS42426-CQZ
Typ
Max
Min
CS42426-DQZ
Typ
Max
Unit
108
105
114
111
-
106
103
114
111
-
dB
dB
-
-100
-91
-51
-94
-
-
-100
-91
-51
-92
-
dB
dB
dB
108
105
-
114
111
108
-
106
103
-
114
111
108
-
dB
dB
dB
-
-100
-91
-51
-97
-94
-
-
-100
-91
-51
-97
-92
-
dB
dB
dB
dB
108
105
-
114
111
108
-
106
103
-
114
111
108
-
dB
dB
dB
-
-100
-91
-51
-97
-94
-
-
-100
-91
-51
-97
-92
-
dB
dB
dB
dB
-
110
0.0001
-
-
110
0.0001
-
dB
Degree
-
0.1
+/-100
0
100
-
-
0.1
+/-100
0
100
-
dB
ppm/°C
LSB
LSB
1.05 VA
17
-
1.10 VA
82
1.16 VA
-
0.99 VA
17
-
1.10 VA
82
1.21 VA
-
Vpp
kΩ
dB
Dynamic Performance for All Modes
Interchannel Isolation
Interchannel Phase Deviation
DC Accuracy
Interchannel Gain Mismatch
Gain Drift
Offset Error
HPF_FREEZE disabled
HPF_FREEZE enabled
Analog Input
Full-scale Differential Input Voltage
Input Impedance (Differential) (Note 4)
Common Mode Rejection Ratio
CMRR
Notes:
3. Referred to the typical full-scale voltage.
4. Measured between AIN+ and AIN-
DS604F1
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CS42426
A/D DIGITAL FILTER CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Unit
(Note 5)
0
-
0.47
Fs
-
-
±0.035
dB
(Note 5)
0.58
-
-
Fs
Single-Speed Mode (2 to 50 kHz sample rates)
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
-95
-
-
dB
tgd
-
12/Fs
-
s
∆tgd
-
-
0.0
µs
(Note 5)
0
-
0.45
Fs
-
-
±0.035
dB
(Note 5)
0.68
-
-
Fs
Total Group Delay (Fs = Output Sample Rate)
Group Delay Variation vs. Frequency
Double-Speed Mode (50 to 100 kHz sample rates)
Passband
(-0.1 dB)
Passband Ripple
Stopband
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
Group Delay Variation vs. Frequency
-92
-
-
dB
tgd
-
9/Fs
-
s
∆tgd
-
-
0.0
µs
0
-
0.24
Fs
-
-
±0.035
dB
0.78
-
-
Fs
-97
-
-
dB
tgd
-
5/Fs
-
s
∆tgd
-
-
0.0
µs
-
1
20
-
Hz
Hz
-
10
-
Deg
-
-
0
dB
-
105/Fs
-
s
Quad-Speed Mode (100 to 192 kHz sample rates)
Passband
(-0.1 dB)
(Note 5)
Passband Ripple
Stopband
(Note 5)
Stopband Attenuation
Total Group Delay (Fs = Output Sample Rate)
Group Delay Variation vs. Frequency
High-Pass Filter Characteristics
Frequency Response
Phase Deviation
-3.0 dB
-0.13 dB
(Note 6)
@ 20 Hz
(Note 6)
Passband Ripple
Filter Setting Time
Notes:
5. The filter frequency response scales precisely with Fs.
6. Response shown is for Fs equal to 48 kHz. Filter characteristics scale with Fs.
8
DS604F1
CS42426
ANALOG OUTPUT CHARACTERISTICS
(TA = 25° C; VA = 5 V, VD = 3.3 V, Logic “0” = DGND =AGND = 0 V; Logic “1” = VLS = VLC = 5V; Measurement
Bandwidth 10 Hz to 20 kHz unless otherwise specified.; Full-scale output 997 Hz sine wave, Test load RL = 3 kΩ,
CL = 30 pF; PDN_PLL = 1; OMCK = 12.288 MHz; Single-Speed Mode, DAC_SCLK = 3.072 MHz; Double-Speed
Mode, DAC_SCLK = 6.144 MHz; Quad-Speed Mode, DAC_SCLK = 12.288 MHz.)
Parameter
Symbol
Dynamic performance for all modes
Dynamic Range (Note 7)
24-bit A-Weighted
unweighted
16-bit A-Weighted
(Note 8) unweighted
Total Harmonic Distortion + Noise
24-bit
0 dB
-20 dB
-60 dB
16-bit
0 dB
(Note 8) -20 dB
-60 dB
Idle Channel Noise/Signal-to-Noise
Ratio (A-Weighted)
Interchannel Isolation
(1 kHz)
Min
CS42426-CQZ
Typ
Max
Min
CS42426-DQZ
Typ
Max
Unit
108
105
-
114
111
97
94
-
106
103
-
114
111
97
94
-
dB
dB
dB
dB
-
-100
-91
-51
-94
-74
-34
-94
-
-
-100
-91
-51
-94
-74
-34
-92
-
dB
dB
dB
dB
dB
dB
-
114
-
-
114
-
dB
-
90
-
-
90
-
dB
VFS
.89 VA
.94 VA
.99 VA
.84 VA
.94 VA
1.04 VA
Vpp
ZOUT
RL
CL
3
-
0.1
300
150
-
30
3
-
0.1
300
150
-
30
dB
ppm/°C
Ω
kΩ
pF
THD+N
Analog Output Characteristics for all modes
Unloaded Full-Scale Differential Output
Voltage
Interchannel Gain Mismatch
Gain Drift
Output Impedance
AC-Load Resistance
Load Capacitance
Notes:
7. One-half LSB of triangular PDF dither is added to data.
8. Performance limited by 16-bit quantization noise.
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CS42426
D/A DIGITAL FILTER CHARACTERISTICS
Fast Roll-Off
Slow Roll-Off
Parameter
Min
Typ
Max
Min
Typ
Max
Combined Digital and On-chip Analog Filter Response - Single-Speed Mode - 48 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response 10 Hz to 20 kHz
-0.01
StopBand
0.5465
StopBand Attenuation
(Note 10)
90
Group Delay
Passband Group Delay Deviation
0 - 20 kHz
De-emphasis Error (Note 11)
Fs = 32 kHz
(Relative to 1 kHz)
Fs = 44.1 kHz
Fs = 48 kHz
-
12/Fs
-
0.4535
0.4998
+0.01
±0.41/Fs
±0.23
±0.14
±0.09
0
0
-0.01
0.5834
64
-
6.5/Fs
-
Unit
0.4166
0.4998
+0.01
±0.14/Fs
±0.23
±0.14
±0.09
Fs
Fs
dB
Fs
dB
s
s
dB
dB
dB
0.2083
0.4998
0.01
±0.01/Fs
Fs
Fs
dB
Fs
dB
s
s
0.1042
0.4813
0.01
±0.01/Fs
Fs
Fs
dB
Fs
dB
s
s
Combined Digital and On-chip Analog Filter Response - Double-Speed Mode - 96 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response 10 Hz to 20 kHz
-0.01
StopBand
0.5834
StopBand Attenuation
(Note 10)
80
Group Delay
Passband Group Delay Deviation
0 - 20 kHz
-
4.6/Fs
-
0.4166
0.4998
0.01
±0.03/Fs
0
0
-0.01
0.7917
70
-
3.9/Fs
-
Combined Digital and On-chip Analog Filter Response - Quad-Speed Mode - 192 kHz
Passband (Note 9)
to -0.01 dB corner
0
to -3 dB corner
0
Frequency Response 10 Hz to 20 kHz
-0.01
StopBand
0.6355
StopBand Attenuation
(Note 10)
90
Group Delay
Passband Group Delay Deviation
0 - 20 kHz
-
4.7/Fs
-
0.1046
0.4897
0.01
±0.01/Fs
0
0
-0.01
0.8683
75
-
4.2/Fs
-
Notes:
9. Response is clock dependent and will scale with Fs. Note that the response plots (Figures 39 to 62) have
been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.
10. Single- and Double-Speed Mode Measurement Bandwidth is from stopband to 3 Fs.
Quad-Speed Mode Measurement Bandwidth is from stopband to 1.34 Fs.
11. De-emphasis is available only in Single-Speed Mode.
10
DS604F1
CS42426
SWITCHING CHARACTERISTICS
(For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C;
VA = 5 V, VD =VLC= 3.3 V, VLS = 1.8 V to 5.25 V; Inputs: Logic 0 = DGND, Logic 1 = VLS, CL = 30 pF)
Parameters
Symbol
RST Pin Low Pulse Width
Min
Typ
Max
Units
1
-
-
ms
30
-
200
kHz
-
200
-
ps RMS
(Note 12)
PLL Clock Recovery Sample Rate Range
RMCK Output Jitter
(Note 14)
RMCK Output Duty Cycle
(Note 15)
45
50
55
%
OMCK Frequency
(Note 13)
1.024
-
25.600
MHz
OMCK Duty Cycle
(Note 13)
40
50
60
%
DAC_SCLK, ADC_SCLK Duty Cycle
45
50
55
%
DAC_LRCK, ADC_LRCK Duty Cycle
45
50
55
%
Master Mode
RMCK to DAC_SCLK, ADC_SCLK active edge delay
tsmd
0
-
15
ns
RMCK to DAC_LRCK, ADC_LRCK delay
tlmd
0
-
15
ns
-
(Note 16)
ns
Slave Mode
DAC_SCLK, ADC_SCLK Falling Edge to ADC_SDOUT,
ADC_SDOUT Output Valid
tdpd
DAC_LRCK, ADC_LRCK Edge to MSB Valid
tlrpd
-
26.5
ns
DAC_SDIN Setup Time Before DAC_SCLK Rising Edge
tds
10
-
-
ns
tdh
30
-
-
ns
DAC_SCLK, ADC_SCLK High Time
tsckh
20
-
-
ns
DAC_SCLK, ADC_SCLK Low Time
tsckl
20
-
-
ns
DAC_SCLK, ADC_SCLK falling to DAC_LRCK, SAI_LRCK
Edge
tlrck
-25
-
+25
ns
DAC_SDIN Hold Time After DAC_SCLK Rising Edge
Notes:
12. After powering-up the CS42426, RST should be held low after the power supplies and clocks are settled.
13. See Table 1 on page 24 for suggested OMCK frequencies
14. Limit the loading on RMCK to 1 CMOS load if operating above 24.576 MHz.
15. Not valid when RMCK_DIV in “Clock Control (address 06h)” on page 48 is set to Multiply by 2.
16. 76.5 ns for Single-Speed and Double-Speed modes, 23 ns for Quad-Speed Mode.
DAC_SCLK
ADC_SCLK
(output)
DAC_LRCK
ADC_LRCK
(output)
DAC_LRCK
ADC_LRCK
(input)
t lrcks
t sckh
t sckl
DAC_SCLK
ADC_SCLK
(input)
t
DAC_SDINx
smd
t
lmd
RMCK
Figure 1. Serial Audio Port Master Mode Timing
DS604F1
t lrckd
t lrpd
ADC_SDOUT
t ds
t dh
M SB
t dpd
MSB-1
Figure 2. Serial Audio Port Slave Mode Timing
11
CS42426
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT
(For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Max
Unit
SCL Clock Frequency
fscl
-
100
kHz
RST Rising Edge to Start
tirs
500
-
ns
Bus Free Time Between Transmissions
tbuf
4.7
-
µs
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
-
µs
Clock Low time
tlow
4.7
-
µs
Clock High Time
thigh
4.0
-
µs
tsust
4.7
-
µs
thdd
0
-
µs
tsud
250
-
ns
trc
-
1
µs
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
(Note 17)
SDA Setup time to SCL Rising
Rise Time of SCL and SDA
Fall Time SCL and SDA
Setup Time for Stop Condition
Acknowledge Delay from SCL Falling
(Note 18)
tfc
-
300
ns
tsusp
4.7
-
µs
tack
-
(Note 19)
ns
Notes:
17. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
18. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.
19.
15 15
15
-------------------for Single-Speed Mode, --------------------- for Double-Speed Mode, ------------------ for Quad-Speed Mode
256 × Fs
128 × Fs
64 × Fs
RST
t
irs
Stop
R e p e ate d
Sta rt
Sta rt
t rd
t fd
Stop
SDA
t
buf
t
t
hdst
t
high
t fc
hdst
t susp
SCL
t
lo w
t
hdd
t sud
t ack
t sust
t rc
Figure 3. Control Port Timing - I²C Format
12
DS604F1
CS42426
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ FORMAT
(For CQZ, TA = -10 to +70° C; For DQZ, TA = -40 to +85° C; VA = 5 V, VD =VLS= 3.3 V; VLC = 1.8 V to 5.25 V;
Inputs: Logic 0 = DGND, Logic 1 = VLC, CL = 30 pF)
Parameter
Symbol
Min
Typ
Max
Units
CCLK Clock Frequency
fsck
0
-
6.0
MHz
CS High Time Between Transmissions
tcsh
1.0
-
-
µs
CS Falling to CCLK Edge
tcss
20
-
-
ns
CCLK Low Time
tscl
66
-
-
ns
CCLK High Time
tsch
66
-
-
ns
CDIN to CCLK Rising Setup Time
tdsu
40
-
-
ns
tdh
15
-
-
ns
CCLK Falling to CDOUT Stable
tpd
-
-
50
ns
Rise Time of CDOUT
tr1
-
-
25
ns
Fall Time of CDOUT
tf1
-
-
25
ns
CCLK Rising to DATA Hold Time
(Note 20)
Rise Time of CCLK and CDIN
(Note 21)
tr2
-
-
100
ns
Fall Time of CCLK and CDIN
(Note 21)
tf2
-
-
100
ns
Notes:
20. Data must be held for sufficient time to bridge the transition time of CCLK.
21. For fsck <1 MHz.
CS
t scl
t css
t sch
t csh
CCLK
t r2
t f2
CDIN
t dsu
t dh
t pd
CDOUT
Figure 4. Control Port Timing - SPI Format
DS604F1
13
CS42426
DC ELECTRICAL CHARACTERISTICS
(TA = 25° C; AGND=DGND=0, all voltages with respect to ground; OMCK=12.288 MHz; Master Mode)
Parameter
Symbol
Min
Typ
Max
Units
IA
ID
ID
ILC
ILS
Ipd
-
75
85
51
250
13
250
-
mA
mA
mA
µA
mA
µA
-
587
1.25
866
1.25
650
960
-
mW
mW
mW
mW
-
60
40
-
dB
dB
VQ Nominal Voltage
VQ Output Impedance
VQ Maximum allowable DC current
-
2.7
50
0.01
-
V
kΩ
mA
FILT+ Nominal Voltage
FILT+ Output Impedance
FILT+ Maximum allowable DC current
-
5.0
35
0.01
-
V
kΩ
mA
Power Supply Current
(Note 22)
normal operation, VA = 5 V
VD = 5 V
VD = 3.3 V
Interface current, VLC=5 V (Note 23)
VLS=5 V
power-down state (all supplies) (Note 24)
Power Consumption
VA=5 V, VD=VLS=VLC=3.3 V
VA=5 V, VD=VLS=VLC=5 V
Power Supply Rejection Ratio (Note 25)
(Note 22)
normal operation
power-down (Note 24)
normal operation
power-down (Note 24)
(1 kHz)
(60 Hz)
PSRR
Notes:
22. Current consumption increases with increasing FS and increasing OMCK. Max values are based on
highest FS and highest OMCK. Variance between speed modes is negligible.
23. ILC measured with no external loading on the SDA pin.
24. Power-Down Mode is defined as RST pin = Low with all clock and data lines held static.
25. Valid with the recommended capacitor values on FILT+ and VQ as shown in Figure 5.
14
DS604F1
CS42426
DIGITAL INTERFACE CHARACTERISTICS
(For CQZ, TA = +25° C; For DQZ, TA = -40 to +85° C)
Parameters (Note 26)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage at Io=2 mA
Low-Level Output Voltage at Io=2 mA
Serial Port, Control Port, MUTEC, GPOx
Input Leakage Current
Input Capacitance
MUTEC Drive Current
Symbol
Serial Port
Control Port
Serial Port
Control Port
(Note 27)Serial Port
Control Port
MUTEC, GPOx
(Note 27)
VIH
VIL
VOH
VOL
Iin
Min
Typ
Max
Units
0.7xVLS
0.7xVLC
VLS-1.0
VLC-1.0
VA-1.0
-
0.2xVLS
0.2xVLC
-
V
V
V
V
V
V
V
-
8
3
0.4
±10
-
V
µA
pF
mA
Notes:
26. Serial Port signals include: RMCK, OMCK, ADC_SCLK, ADC_LRCK, DAC_SCLK, DAC_LRCK,
ADC_SDOUT, DAC_SDIN1-3, ADCIN1/2
Control Port signals include: SCL/CCLK, SDA/CDOUT, AD0/CS, AD1/CDIN, INT, RST
27. When operating RMCK above 24.576 MHz, limit the loading on the signal to 1 CMOS load.
DS604F1
15
CS42426
NC
NC
VD
DGND
VLS
RMCK
NC
ADCIN2
ADC_SDOUT
ADCIN1
ADC_LRCK
OMCK
TEST
ADC_SCLK
DAC_SDIN2
DAC_SDIN3
2. PIN DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DAC_SDIN1
1
48
GPO1
DAC_SCLK
2
47
GPO2
DAC_LRCK
3
46
GPO3
VD
4
45
GPO4
DGND
5
44
GPO5
VLC
6
43
GPO6
SCL/CCLK
7
42
GPO7
SDA/CDOUT
8
AD1/CDIN
CS42426
41
VA
9
40
AGND
AD0/CS
10
39
LPFLT
MUTEC
INT
11
38
RST
12
37
AOUTA1-
AINR-
13
36
AOUTA1+
AINR+
14
35
AOUTB1+
AINL+
15
34
AOUTB1-
AINL-
16
33
AOUTA2-
AOUTA2+
AOUTB2+
AOUTB2-
AOUTA3-
AOUTA3+
AOUTB3-
AOUTB3+
AGND
VA
NC
NC
NC
NC
REFGND
VQ
FILT+
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Pin Name
#
Pin Description
DAC_SDIN1
DAC_SDIN2
DAC_SDIN3
1
64
63
DAC Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
DAC_SCLK
2
DAC_LRCK
3
VD
4
51
Digital Power (Input) - Positive power supply for the digital section.
DGND
5
52
Digital Ground (Input) - Ground reference. Should be connected to digital ground.
VLC
6
SCL/CCLK
7
SDA/CDOUT
8
AD1/CDIN
9
AD0/CS
10
INT
11
16
DAC Serial Clock (Input/Output) - Serial clock for the DAC serial audio interface.
DAC Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the DAC serial audio data line.
Control Port Power (Input) - Determines the required signal level for the control port.
Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external pull-up
resistor to the logic interface voltage in I²C mode as shown in the Typical Connection Diagram.
Serial Control Data (Input/Output) - SDA is a data I/O line in I²C mode and requires an external pull-up
resistor to the logic interface voltage, as shown in the Typical Connection Diagram. CDOUT is the output
data line for the control port interface in SPI mode.
Address Bit 1 (I²C)/Serial Control Data (SPI) (Input) - AD1 is a chip address pin in I²C mode; CDIN is
the input data line for the control port interface in SPI mode.
Address Bit 0 (I²C)/Control Port Chip Select (SPI) (Input) - AD0 is a chip address pin in I²C mode; CS
is the chip select signal in SPI mode.
Interrupt (Output) - The CS42426 will generate an interrupt condition as per the Interrupt Mask register.
See “Interrupts” on page 37 for more details.
DS604F1
CS42426
RST
12
AINRAINR+
13
14
Reset (Input) - The device enters a low power mode and all internal registers are reset to their default
settings when low.
Differential Right Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINR+/- pins.
AINL+
AINL-
15
16
Differential Left Channel Analog Input (Input) - Signals are presented differentially to the delta-sigma
modulators via the AINL+/- pins.
VQ
17
Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage.
FILT+
18
Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits.
REFGND
19
Reference Ground (Input) - Ground reference for the internal sampling circuits.
AOUTA1 +,AOUTB1 +,AOUTA2 +,AOUTB2 +,AOUTA3 +,AOUTB3 +,VA
AGND
36,37
35,34
32,33 Differential Analog Output (Output) - The full-scale differential analog output level is specified in the
31,30 Analog Characteristics specification table.
28,29
27,26
24
41
Analog Power (Input) - Positive power supply for the analog section.
25
40
Analog Ground (Input) - Ground reference. Should be connected to analog ground.
Mute Control (Output) - The Mute Control pin outputs high impedance following an initial power-on condition or whenever the PDN bit is set to a ‘1’, forcing the codec into power-down mode. The signal will
remain in a high impedance state as long as the part is in power-down mode. The Mute Control pin goes
to the selected “active” state during reset, muting, or if the master clock to left/right clock frequency ratio
is incorrect. This pin is intended to be used as a control for external mute circuits to prevent the clicks
and pops that can occur in any single supply system. The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops.
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground.
MUTEC
38
LPFLT
39
GPO7
GPO6
GPO5
GPO4
GPO3
GPO2
GPO1
42
43
44
45
46
47
48
VLS
53
RMCK
55
ADC_SDOUT
56
ADCIN1
ADCIN2
58
57
OMCK
59
ADC_LRCK
60
ADC_SCLK
61
Serial Port Interface Power (Input) - Determines the required signal level for the serial port interfaces.
Recovered Master Clock (Output) - Recovered master clock output from the External Clock Reference
(OMCK, pin 59) or the PLL which is locked to the incoming ADC_LRCK.
ADC Serial Data Output (Output) - Output for two’s complement serial audio PCM data from the output
of the internal and external ADCs.
External ADC Serial Input (Input) - The CS42426 provides for up to two external stereo analog to digital
converter inputs to provide a maximum of six channels on one serial data output line when the CS42426
is placed in One-Line Mode.
External Reference Clock (Input) - External clock reference that must be within the ranges specified in
the register “OMCK Frequency (OMCK Freqx)” on page 48.
ADC Left/Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on
the ADC serial audio data line.
ADC Serial Clock (Input/Output) - Serial clock for the ADC serial audio interface.
TEST
62
Test Pin (Input) - This pin must be connected to DGND.
DS604F1
General Purpose Output (Output) - These pins can be configured as general purpose output pins, an
ADC overflow interrupt or Mute Control outputs according to the General Purpose Pin Control registers.
17
CS42426
3. TYPICAL CONNECTION DIAGRAMS
+3.3 V to +5 V
10 µF
10 µF
+
+
0.1 µF
0.1 µF
0.01 µF
0.01 µF
0.01 µF
0.01 µF
51
4
VD
VD
41
48
47
S/PDIF
46
RMCK
45
44
43
42
AOUTA1-
GPO1
GPO2
AOUTB1+
GPO3
AOUTB1-
GPO4
GPO5
AOUTA2+
GPO6
AOUTA2-
GPO7
53
0.1 µF
59
OSC
AOUTB2+
VLS
AOUTB2OMCK
AOUTA3+
58
CS5361
A/D Converter
CS5361
A/D Converter
57
55
ADCIN1
AOUTA3-
36
Analog Output Buffer 2
and
Mute Circuit (optional)
37
35
Analog Output Buffer 2
and
Mute Circuit (optional)
34
32
Analog Output Buffer 2
and
Mute Circuit (optional)
33
31
Analog Output Buffer 2
and
Mute Circuit (optional)
30
28
Analog Output Buffer 2
and
Mute Circuit (optional)
29
AOUTB3+
RMCK
27
Analog Output Buffer 2
and
Mute Circuit (optional)
26
CS42426
60
Digital Audio
Processor
61
ADC_SDOUT
ADC_LRCK
+VA
ADC_SCLK
MUTEC
3
2
1
64
63
11
MicroController
7
8
9
10
**
2 kΩ
Mute
Drive
(optional)
*
*
DAC_LRCK
* Pull up or down as
required on startup if the
Mute Control is used.
DAC_SDIN1
AINL+
DAC_SDIN2
15
DAC_SDIN3
INT
AINR+
16
SCL/CCLK
AINR-
Analog
2700
InputpF*
Buffer 1
Left Analog Input
Analog
2700
InputpF*
Buffer 1
Right Analog Input
14
RST
13
SDA/CDOUT
AD1/CDIN
AD0/CS
VQ
**
FILT+
17
18
+
+
2 kΩ
6
+1.8V
to +5V
38
DAC_SCLK
AINL-
12
10 µF
ADCIN2
AOUTB3-
56
+
+5 V
10 µF
VA
AOUTA1+
CS8416
Receiver
0.1 µF
+
24
VA
Optional
+3.3 V
to +5.0 V
0.1 µF
REFGND
VLC
0.1 µF
LPFLT
19
0.1 µF
0.1 µF
4.7 µF
100 µF
39
RFILT 3
** Resistors are required for
I2C control port operation
DGND DGND
52
5
AGND
25
AGND
40
CFILT 3
CRIP 3
Connect DGND and AGND at single point near Codec
1. See the ADC Input Filter section in the Appendix.
2. See the DAC Output Filter section in the Appendix.
3. See the PLL Filter section in the Appendix.
Figure 5. Typical Connection Diagram
18
DS604F1
CS42426
+ 3 .3 V to + 5 V
10 µF
10 µF
0 .1 µ F
+
0 .1 µ F
+
0 .0 1 µ F
0 .0 1 µ F
0 .0 1 µ F
0 .0 1 µ F
51
4
VD
41
VD
VA
47
46
45
44
43
42
+ 1 .8 V
to + 5 .0 V
GPO2
AO UTB1+
GPO3
A O U TB 1-
GPO4
GPO5
AO UTA2+
GPO6
A O U TA 2-
GPO7
53
0 .1 µ F
59
AO UTB2+
VLS
A O U TB 2OMCK
AO UTA3+
58
57
A D C IN 1
A O U TA 3-
A O U TB 355
60
DVD
P ro c e s s o r
61
36
A n a lo g O u tp u t B u ffe r 2
and
M u te C irc u it (o p tio n a l)
37
35
A n a lo g O u tp u t B u ffe r 2
and
M u te C irc u it (o p tio n a l)
34
32
A n a lo g O u tp u t B u ffe r 2
and
M u te C irc u it (o p tio n a l)
33
31
A n a lo g O u tp u t B u ffe r 2
and
M u te C irc u it (o p tio n a l)
30
28
A n a lo g O u tp u t B u ffe r 2
and
M u te C irc u it (o p tio n a l)
29
RMCK
27
A n a lo g O u tp u t B u ffe r 2
and
M u te C irc u it (o p tio n a l)
26
CS42426
A DC _S D O U T
+VA
A D C _LR C K
M UTEC
A DC _S C LK
38
M u te
D riv e
(o p tio n a l)
*
*
3
27 M Hz
2
1
64
63
11
12
7
8
9
10
**
2 kΩ
* P u ll u p o r d o w n a s
re q u ire d o n s ta rtu p if th e
M u te C o n tro l is u s e d .
DA C _LR C K
D AC _S C LK
D A C _ S D IN 1
A IN L +
15
D A C _ S D IN 2
D A C _ S D IN 3
A IN L -
A IN R +
16
14
IN T
RST
A IN R -
13
A n a lo g
2In
7 0p0u tp F *
B u ffe r 1
L e ft A n a lo g In p u t
A n a lo g
2 In
7 0p0u tp F *
B u ffe r 1
R ig h t A n a lo g In p u t
S C L /C C L K
S D A /C D O U T
A D 1 /C D IN
A D 0 /C S
VQ
**
F IL T +
17
18
+
+
2 kΩ
6
REFGND
V LC
0 .1 µ F
LP FLT
19
DGND DGND
52
5
AGND
25
AGND
40
0 .1 µ F
0 .1 µF
4 .7 µ F
100 µF
39
R F IL T
* * R e s is to rs a re re q u ire d fo r
I 2 C c o n tro l p o rt o p e ra tio n
10 µF
A D C IN 2
AO UTB3+
56
+
+5 V
10 µF
VA
A O U TA 1-
GPO1
0 .1 µ F
+
24
AO UTA1+
48
0 .1 µ F
C F IL T
3
3
C R IP
3
C o n n e c t D G N D a n d A G N D a t s in g le p o in t n e a r C o d e c
1 . S e e th e A D C In p u t F ilte r s e c tio n in th e A p p e n d ix .
2 . S e e th e D A C O u tp u t F ilte r s e c tio n in th e A p p e n d ix .
3 . S e e th e P L L F ilte r s e c tio n in th e A p p e n d ix .
Figure 6. Typical Connection Diagram using the PLL
DS604F1
19
CS42426
4. APPLICATIONS
4.1
Overview
The CS42426 is a highly integrated mixed-signal 24-bit audio codec comprised of 2 analog-to-digital converters (ADC), implemented using multi-bit delta-sigma techniques, and 6 digital-to-analog converters
(DAC). Other functions integrated within the codec include independent digital volume controls for each
DAC, digital de-emphasis filters for DAC, digital gain control for ADC channels, ADC high-pass filters, and
an on-chip voltage reference. All serial data is transmitted through one configurable serial audio interface
for the ADC with enhanced one-line modes of operation, allowing up to 6 channels of serial audio data on
one data line. All functions are configured through a serial control port operable in SPI mode or in I²C mode.
Figure 5 and Figure 6 show the recommended connections for the CS42426.
The CS42426 operates in one of three oversampling modes based on the input sample rate. Mode selection
is determined by the FM bits in register “Functional Mode (address 03h)” on page 43. Single-Speed Mode
(SSM) supports input sample rates up to 50 kHz and uses a 128x oversampling ratio. Double-Speed Mode
(DSM) supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x. Quad-Speed
Mode (QSM) supports input sample rates up to 192 kHz and uses an oversampling ratio of 32x.
Using the integrated PLL, a low-jitter clock is recovered from the ADC LRCK input signal. The recovered
clock or an externally supplied clock attached to the OMCK pin can be used as the System Clock.
4.2
4.2.1
Analog Inputs
Line-Level Inputs
AINR+, AINR-, AINL+, and AINL- are the line-level differential analog inputs. The analog signal must be
externally biased to VQ, approximately 2.7 V, before being applied to these inputs. The level of the signal
can be adjusted for the left and right ADC independently through the ADC Left and Right Channel Gain
Control Registers on page 55. The ADC output data is in two’s complement binary format. For inputs
above positive full scale or below negative full scale, the ADC will output 7FFFFFH or 800000H, respectively and cause the ADC Overflow bit in the register “Interrupt Status (address 20h) (Read Only)” on
page 56 to be set to a ‘1’. The GPO pins may also be configured to indicate an overflow condition has
occurred in the ADC. See “General-Purpose Pin Control (addresses 29h to 2Fh)” on page 58 for proper
configuration. Figure 7 shows the full-scale analog input levels. See “ADC Input Filter” on page 61 for a
recommended input buffer.
4.1 V
2.7 V
AIN+
1.3 V
4.1 V
AIN-
2.7 V
1.3 V
Full-Scale Input Level= (AIN+) - (AIN-)= 5.6 Vpp
Figure 7. Full-Scale Analog Input
20
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CS42426
4.2.2
High-Pass Filter and DC Offset Calibration
The high-pass filter continuously subtracts a measure of the DC offset from the output of the decimation
filter. The high-pass filter can be independently enabled and disabled. If the HPF_Freeze bit is set during
normal operation, the current value of the DC offset for the corresponding channel is frozen and this DC
offset will continue to be subtracted from the conversion result. This feature makes it possible to perform
a system DC offset calibration by:
1. Running the CS42426 with the high-pass filter enabled until the filter settles. See the Digital Filter
Characteristics for filter settling time.
2. Disabling the high-pass filter and freezing the stored DC offset.
The high-pass filters are controlled using the HPF_FREEZE bit in the register “Misc Control (address
05h)” on page 46.
4.3
Analog Outputs
4.3.1
Line-Level Outputs and Filtering
The CS42426 contains on-chip buffer amplifiers capable of producing line-level differential outputs. These
amplifiers are biased to a quiescent DC level of approximately VQ.
The delta-sigma conversion process produces high-frequency noise beyond the audio passband, most of
which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using
an off-chip low-pass filter. See “DAC Output Filter” on page 61 for a recommended output buffer. This filter
configuration accounts for the normally differing AC loads on the AOUT+ and AOUT- differential output
pins. It also shows an AC coupling configuration which minimizes the number of required AC coupling capacitors. Figure 8 shows the full-scale analog output levels.
3.95 V
2.7 V
AOUT+
1.45 V
3.95 V
AOUT-
2.7 V
1.45 V
Full-Scale Output Level= (AIN+) - (AIN-)= 5 Vpp
Figure 8. Full-Scale Output
4.3.2
Interpolation Filter
To accommodate the increasingly complex requirements of digital audio systems, the CS42426 incorporates selectable interpolation filters for each mode of operation. A “fast” and a “slow” roll-off filter is available in Single-, Double-, and Quad-Speed Modes. These filters have been designed to accommodate a
variety of musical tastes and styles. The FILT_SEL bit found in the register “Misc Control (address 05h)”
on page 46 selects which filter is used. Filter response plots can be found in Figures 39 to 62.
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CS42426
4.3.3
Digital Volume and Mute Control
Each DAC’s output level is controlled via the Volume Control registers operating over the range of 0 to
-127 dB attenuation with 0.5 dB resolution. See “Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h,
14h)” on page 53. Volume control changes are programmable to ramp in increments of 0.125 dB at the
rate controlled by the SZC[1:0] bits in the Digital Volume Control register. See “Volume Transition Control
(address 0Dh)” on page 51.
Each output can be independently muted via mute control bits in the register “Channel Mute (address
0Eh)” on page 52. When enabled, each XX_MUTE bit attenuates the corresponding DAC to its maximum
value (-127 dB). When the XX_MUTE bit is disabled, the corresponding DAC returns to the attenuation
level set in the Volume Control register. The attenuation is ramped up and down at the rate specified by
the SZC[1:0] bits.
The Mute Control pin, MUTEC, is typically connected to an external mute control circuit. The Mute Control
pin outputs high impedance during Power-Up or in Power-Down Mode by setting the PDN bit in the register “Power Control (address 02h)” on page 43 to a ‘1’. Once out of Power-Down Mode, the pin can be
controlled by the user via the control port, or automatically asserted high when zero data is present on all
DAC inputs, or when serial port clock errors are present. To prevent large transients on the output, it is
desirable to mute the DAC outputs before the Mute Control pin is asserted. Please see the MUTEC pin
in the Pin Descriptions section for more information.
Each of the GPO1-GPO7 can be programmed to provide a hardware MUTE signal to individual circuits.
Each pin can be programmed as an output, with specific muting capabilities as defined by the function
bits in the register “General-Purpose Pin Control (addresses 29h to 2Fh)” on page 58.
4.3.4
ATAPI Specification
The CS42426 implements the channel-mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 14 on page 54 and Figure 9 for additional information.
A Channel
Volum e
Control
Left Channel
Audio Data
Σ
DAC_SDINx
Right Channel
Audio Data
MUTE
AOUTAx
MUTE
AOUTBx
Σ
B Channel
Volum e
Control
Figure 9. ATAPI Block Diagram (x = channel pair 1, 2, 3)
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CS42426
4.4
Clock Generation
The clock generation for the CS42426 is shown in the figure below. The internal MCLK is derived from the
output of the PLL or a master clock source attached to OMCK. The mux selection is controlled by the
SW_CTRLx bits and can be configured to manual switch mode only, or automatically switch on loss of PLL
lock to the other source input.
RMCK_DIVx bits
00
2
01
4
10
X2
11
Internal
MCLK
ADC_LRCK
(slave mode)
PLL (256Fs)
8.192 49.152 MHz
00
01
PLL_LRCK bit
single
speed
256
Auto Detect
Input Clock
1,1.5, 2, 4
double
speed
00
01
DAC_LRCK
10
128
DAC_FMx bits
quad
speed
SW _CTRLx bits
(manual or auto
switch)
OMCK
RMCK
64
DAC_OLx
or ADC_OLx bits
00
01
10
not OLM
128FS
single
speed
256FS
OLM #1
DAC_SCLK
OLM #2
4
double
speed
2
00
01
quad
speed
1
ADC_LRCK
10
ADC_FMx bits
ADC_OLx and
ADC_SP SELx bits
00
01
10
not OLM
128FS
256FS
OLM #1
ADC_SCLK
OLM #2
Figure 10. Clock Generation
4.4.1
PLL and Jitter Attenuation
The PLL can be configured to lock onto the incoming ADC_LRCK signal from the ADC Serial Port and
generate the required internal master clock frequency. There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is important. For this reason, the PLL has been designed
to have good jitter-attenuation characteristics. By setting the PLL_LRCK bit to a ‘1’ in the register “Clock
Control (address 06h)” on page 48, the PLL will lock to the incoming ADC_LRCK and generate an output
master clock (RMCK) of 256Fs. Table 2 shows the output of the PLL with typical input Fs values for
ADC_LRCK.
See “Appendix B: PLL Filter” on page 62 for more information concerning PLL operation, required filter
components, optimal layout guidelines, and jitter-attenuation characteristics.
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CS42426
4.4.2
OMCK System Clock Mode
A special clock-switching mode is available that allows the clock that is input through the OMCK pin to be
used as the internal master clock. This feature is controlled by the SW_CTRLx bits in register “Clock Control (address 06h)” on page 48. An advanced auto-switching mode is also implemented to maintain master clock functionality. The clock auto-switching mode allows the clock input through OMCK to be used as
a clock in the system without any disruption when the PLL loses lock, for example, when the LRCK is removed from ADC_LRCK. This clock-switching is done glitch-free. A clock adhering to the specifications
detailed in the Switching Characteristics table on page 11 must be applied to the OMCK pin at all times
that the FRC_PLL_LK bit is set to ‘0’ (See “Force PLL Lock (FRC_PLL_LK)” on page 49).
Sample
Rate
(kHz)
48
96
192
Single-Speed
(4 to 50 kHz)
256x
384x
512x
OMCK (MHz)
Double-Speed
(50 to 100 kHz)
128x
192x
256x
Quad-Speed
(100 to 192 kHz)
64x
96x
128x
12.2880 18.4320 24.5760
12.2880 18.4320 24.5760
12.2880 18.4320 24.5760
Table 1. Common OMCK Clock Frequencies
4.4.3
Master Mode
In Master Mode, the serial interface timings are derived from an external clock attached to OMCK or from
the output of the PLL with an input reference to the ADC_LRCK input from the ADC serial port. The DAC
Serial Port and ADC Serial Port can both be masters only when OMCK is used as the clock source. When
using the PLL output, the ADC Serial Port must be slave and the DAC Serial Port can operate in Master
Mode. Master clock selection and operation is configured with the SW_CTRL1:0 bits in the Clock Control
Register (See “Clock Control (address 06h)” on page 48).
4.4.4
Slave Mode
In Slave Mode, DAC_LRCK, DAC_SCLK and/or ADC_LRCK and ADC_SCLK operate as inputs. The
Left/Right clock signal must be equal to the sample rate, Fs, and must be synchronously derived from the
supplied master clock, OMCK, or must be synchronous to the supplied ADC_LRCK used as the input to
the PLL. In this latter scenario, the PLL output becomes the internal master clock. The supported PLL output frequencies are shown in Table 2.
Sample
Rate
(kHz)
32
44.1
48
64
88.2
96
176.4
192
Single-Speed
(4 to 50kHz)
256x
8.1920
11.2896
12.2880
-
PLL Output (MHz)
Double-Speed
Quad-Speed
(50 to 100kHz)
(100 to 192kHz)
256x
256x
16.3840
22.5792
24.5760
-
45.1584
49.1520
The serial bit clock, DAC_SCLK and/or ADC_SCLK, must be synchronous to the corresponding
DAC_LRCK/ADC_LRCK and be equal to 128x, 64x, 48x or 32x Fs, depending on the interface format selected and desired speed mode.
24
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CS42426
When the device is clocked from OMCK, the frequency of OMCK must be at least twice the frequency of
the fastest Slave Mode, SCLK. For example, if both serial ports are in Slave Mode with one SCLK running
at 32x Fs and the other at 64x Fs, the slowest OMCK signal that can be used to clock the device is
128x Fs.
When either serial port is in Slave Mode, its respective LRCK signal must be present for proper device
operation.
In Slave Mode, One-Line Mode #1 is supported; One-Line Mode #2 is not.
The sample rate to OMCK ratios and OMCK frequency requirements for Slave Mode operation are shown
in Table 1. Refer to Table 3 for required clock ratios.
Single-Speed
Double-Speed
Quad-Speed
One-Line Mode #1
OMCK/LRCK Ratio
256x, 384x, 512x
128x, 192x, 256x
64x, 96x, 128x
256x
SCLK/LRCK Ratio
32x, 48x, 64x, 128x
32x, 48x, 64x
32x, 48x, 64x
128x
Table 3. Slave Mode Clock Ratios
4.5
Digital Interfaces
4.5.1
Serial Audio Interface Signals
The CS42426 interfaces to an external Digital Audio Processor via two independent serial ports, the
DAC serial port, DAC_SP, and the ADC serial port, ADC_SP. The digital output of the internal ADCs use
the ADC_SDOUT pin and can be configured to use either the ADC or DAC serial port timings.These configuration bits and the selection of Single-, Double- or Quad-Speed Mode for DAC_SP and ADC_SP are
found in register “Functional Mode (address 03h)” on page 43.
The serial interface clocks, ADC_SCLK for ADC_SP and DAC_SCLK for DAC_SP, are used for transmitting and receiving audio data. Either ADC_SCLK or DAC_SCLK can be generated by the CS42426 (Master Mode), or it can be input from an external source (Slave Mode). Master or Slave Mode selection is
made using bits DAC_SP M/S and ADC_SP M/S in register “Misc Control (address 05h)” on page 46.
The Left/Right clock (ADC_LRCK or DAC_LRCK) is used to indicate left and right data frames and the
start of a new sample period. It may be an output of the CS42426 (Master Mode), or it may be generated
by an external source (Slave Mode). As described in later sections, particular modes of operation do allow
the sample rate, Fs, of the ADC_SP and the DAC_SP to be different, but must be multiples of each other.
The serial data interface format selection (Left/Right-Justified, I²S or One-Line Mode) for the ADC serial
port data out pin, ADC_SDOUT, and the DAC input pins, DAC_SDIN1:3, is configured using the appropriate bits in the register “Interface Formats (address 04h)” on page 45. The serial audio data is presented
in two's complement binary form with the MSB first in all formats.
DAC_SDIN1, DAC_SDIN2, and DAC_SDIN3 are the serial data input pins supplying the internal DAC.
ADC_SDOUT, the ADC data output pin, carries data from the two internal 24-bit ADCs and, when configured for one-line mode, up to four additional ADC channels attached externally to the signals ADCIN1 and
ADCIN2 (typically two CS5361 stereo ADCs). When operated in One-Line Mode, 6 channels of DAC data
are input on DAC_SDIN1 and 6 channels of ADC data are output on ADC_SDOUT. Table 4 on page 26
outlines the serial port channel allocations.
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CS42426
Serial Inputs / Outputs
left channel DAC #1
right channel DAC #2
One-Line Mode DAC channels 1,2,3,4,5,6
DAC_SDIN2
left channel DAC #3
right channel DAC #4
One-Line Mode not used
DAC_SDIN3
left channel DAC #5
right channel DAC #6
One-Line Mode not used
ADC_SDOUT
left channel ADC #1
right channel ADC #2
One-Line Mode ADC channels 1,2,3,4,5,6
ADCIN1
left channel External ADC #3
right channel External ADC #4
ADCIN2
left channel External ADC #5
right channel External ADC #6
DAC_SDIN1
Table 4. Serial Audio Port Channel Allocations
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CS42426
4.5.2
Serial Audio Interface Formats
The DAC_SP and ADC_SP digital audio serial ports support five formats with varying bit depths from 16
to 24 as shown in Figures 11 to 15. These formats are selected using the configuration bits in the registers,
“Functional Mode (address 03h)” on page 43 and “Interface Formats (address 04h)” on page 45. For the
diagrams below, Single-Speed Mode is equivalent to Fs = 32, 44.1, 48 kHz; Double-Speed Mode is for
Fs = 64, 88.2, 96 kHz; and Quad-Speed Mode is for Fs = 176.4, 196 kHz.
DAC_LRCK
AD C_LRCK
R igh t C han nel
Left C hannel
DAC_SCLK
ADC_SCLK
DAC_SDIN x
ADC_SDOUT
15 1 4 13 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Right-Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Master
16
24
Notes
Slave
64 Fs
48, 64, 128 Fs
Single-Speed Mode
64 Fs
64 Fs
Double-Speed Mode
64 Fs
64 Fs
Quad-Speed Mode
64, 128, 256 Fs
64, 128 Fs
Single-Speed Mode
64 Fs
64 Fs
Double-Speed Mode
64 Fs
64 Fs
Quad-Speed Mode
Figure 11. Right-Justified Serial Audio Formats
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27
CS42426
DAC_LRCK
ADC_LRCK
Left C ha nnel
Rig ht C ha nnel
DAC_SCLK
ADC_SCLK
DAC_SDINx
ADC_SDOUT
MSB
+5 +4 +3 +2 +1
-1 -2 -3 -4 -5
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
I²S Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Master
16
18 to 24
Notes
Slave
64 Fs
48, 64, 128 Fs
Single-Speed Mode
64 Fs
64 Fs
Double-Speed Mode
64 Fs
64 Fs
Quad-Speed Mode
64, 128, 256 Fs
48, 64, 128 Fs
Single-Speed Mode
64 Fs
64 Fs
Double-Speed Mode
64 Fs
64 Fs
Quad-Speed Mode
Figure 12. I²S Serial Audio Formats
DAC_LRCK
ADC_LRCK
Left Channel
R ight C hannel
DAC_SCLK
ADC_SCLK
DAC_SDINx
ADC_SDOUT
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Left-Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Master
16
18 to 24
Notes
Slave
64 Fs
32, 48, 64, 128 Fs
Single-Speed Mode
64 Fs
32, 64 Fs
Double-Speed Mode
64 Fs
32, 64 Fs
Quad-Speed Mode
64, 128, 256 Fs
48, 64, 128 Fs
Single-Speed Mode
64 Fs
64 Fs
Double-Speed Mode
64 Fs
64 Fs
Quad-Speed Mode
Figure 13. Left-Justified Serial Audio Formats
28
DS604F1
CS42426
DAC_LRCK
ADC_LRCK
64 clks
64 clks
Left Channel
Right C hannel
DAC_SCLK
ADC_SCLK
DAC_SDIN1
M SB
ADC_SDOUT
LS B M SB
LS B M SB
LS B
M SB
LS B M SB
LSB M SB
D AC 1
DAC3
D AC5
DAC2
D AC4
20 clks
20 clks
20 clks
20 clks
20 clks
A DC1
A DC3
A DC5
A DC2
A DC4
A DC6
20 clks
20 clks
20 clks
20 clks
20 clks
20 clks
LS B
M SB
LSB
MSB
D AC6
20 clks
One Line Data Mode #1, Data Valid on Rising Edge of SCLK
SCLK Rate(s)
Bits/Sample
Notes
Master
20
Slave
128 Fs
128 Fs
Single-Speed Mode
128 Fs
128Fs
Double-Speed Mode
Figure 14. One-Line Mode #1 Serial Audio Format
DAC_LRCK
ADC_LRCK
128 clks
128 clks
Left Channel
Right Channel
DAC_SCLK
ADC_SCLK
DAC_SDIN1
MSB
LSB MSB
LSB MSB
LSB
MSB
LSB MSB
LSB MSB
DAC1
DAC3
DAC5
DAC2
DAC4
DAC6
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
ADC1
ADC3
ADC5
ADC2
ADC4
ADC6
24 clks
24 clks
24 clks
24 clks
24 clks
24 clks
ADC_SDOUT
One Line Data Mode #2, Data Valid on Rising Edge of SCLK
Bits/Sample
SCLK Rate(s)
Master
24
256 Fs
Notes
Slave
not supported
Single-Speed Mode
Figure 15. One-Line Mode #2 Serial Audio Format
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CS42426
4.5.3
ADCIN1/ADCIN2 Serial Data Format
The two serial data lines which interface to the optional external ADCs, ADCIN1 and ADCIN2, support
only left-justified, 24-bit samples at 64Fs or 128Fs. This interface is not affected by any of the serial port
configuration register bit settings. These serial data lines are used when supporting One-Line Mode of
operation with external ADCs attached. If these signals are not being used, they should be tied together
and wired to GND via a pull-down resistor.
DAC_LRCK
ADC_LRCK
Left Cha nnel
R ight C han nel
DAC_SCLK
ADC_SCLK
ADCIN1/2
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
MSB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Left-Justified Mode, Data Valid on Rising Edge of SCLK
Bits/Sample
24
SCLK Rate(s)
Notes
64, 128 Fs
Single-Speed Mode, Fs= 32, 44.1, 48 KHz
64 Fs
Double-Speed Mode, Fs= 64, 88.2, 96 KHz
not supported
Quad-Speed Mode, Fs= 176.4, 192 KHz
Figure 16. ADCIN1/ADCIN2 Serial Audio Format
For proper operation, the CS42426 must be configured to select which SCLK/LRCK is being used to clock
the external ADCs. The EXT ADC SCLK bit in register “Misc Control (address 05h)” on page 46 must be
set accordingly. Set this bit to ‘1’ if the external ADCs are wired using the DAC_SP clocks. If the ADCs
are wired to use the ADC_SP clocks, set this bit to ‘0’.
30
DS604F1
CS42426
4.5.4
One-Line Mode (OLM) Configurations
4.5.4.1
OLM Config #1
One-Line Mode Configuration #1 can support up to 6 channels of DAC data, and 6 channels of ADC data.
This is the only configuration which will support up to 24-bit samples at a sampling frequency of 48 kHz on
all channels for both the DAC and ADC.
Register / Bit Settings
Description
Functional Mode Register (addr = 03h)
Set DAC_FMx = ADC_FMx = 00,01,10
DAC_LRCK must equal ADC_LRCK; sample rate conversion not supported
Set ADC_CLK_SEL = 0
Configure ADC_SDOUT to be clocked from the DAC_SP clocks.
Interface Format Register (addr = 04h)
Select the digital interface format when not in One-Line Mode
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01,10
Select ADC operating mode, see table below for valid combinations
Set DAC_OLx bits = 00,01,10
Select DAC operating mode, see table below for valid combinations
Misc. Control Register (addr = 05h)
Set DAC_SP M/S = 1
Configure DAC Serial Port to Master Mode.
Set ADC_SP M/S = 1
Configure ADC Serial Port to Master Mode.
Identify external ADC clock source as SAI Serial Port.
Set EXT ADC SCLK = 0
DAC Mode
Not One-Line Mode
One-Line Mode #1
One-Line Mode #2
DAC_SCLK=64Fs
DAC_SCLK=128Fs
Not One- DAC_LRCK=SSM/DSM/QSM DAC_LRCK=SSM/DSM
Line Mode
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
ADC Mode
One-Line
Mode #1
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
One-Line
Mode #2
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
not valid
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
not valid
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=DAC_LRCK
not valid
MCLK
64Fs
LRCK
ADC_SCLK
SCLK
ADC_LRCK
MCLK
RMCK
SDOUT1
ADCIN1
SDOUT2
ADCIN2
CS5361
64Fs,128Fs, 256Fs
DAC_SCLK
SCLK_PORT1
DAC_LRCK
LRCK_PORT1
ADC Data
ADC_SDOUT
CS5361
SDIN_PORT1
SCLK_PORT2
LRCK_PORT2
DAC_SDIN1
DAC_SDIN2
SDOUT1_PORT2
DAC_SDIN3
SDOUT3_PORT2
CS42426
SDOUT2_PORT2
DIGITAL AUDIO
PROCESSOR
Figure 17. OLM Configuration #1
DS604F1
31
CS42426
4.5.4.2
OLM Config #2
This configuration will support up to 6 channels of DAC data or 6 channels of ADC data and will handle up
to 20-bit samples at a sampling-frequency of 96 kHz on all channels for both the DAC and ADC. The output
data stream of the internal and external ADCs is configured to use the ADC_SDOUT output and run at the
DAC Serial Port sample frequency.
Register / Bit Settings
Description
Functional Mode Register (addr = 03h)
Set DAC_FMx = 00,01,10
DAC_LRCK can run at SSM, DSM or QSM independent of ADC_LRCK
Set ADC_FMx = 00,01,10
ADC_LRCK can run at SSM, DSM or QSM independent of DAC_LRCK
Configure ADC_SDOUT to be clocked from the ADC_SP clocks.
Set ADC_CLK_SEL = 1
Interface Format Register (addr = 04h)
Select the digital interface format when not in One-Line Mode
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01,10
Select ADC operating mode, see table below for valid combinations
Set DAC_OLx bits = 00,01
Select DAC operating mode, see table below for valid combinations
Misc. Control Register (addr = 05h)
Set DAC_SP M/S = 1
Set DAC Serial Port to Master Mode.
Set ADC_SP M/S = 1
Set ADC Serial Port to Master Mode.
Identify external ADC clock source as DAC Serial Port.
Set EXT ADC SCLK = 1
DAC Mode
Not One-Line Mode
One-Line Mode #1
DAC_SCLK=64Fs
DAC_SCLK=128Fs
Not One- DAC_LRCK=SSM/DSM/QSM DAC_LRCK=SSM
Line Mode ADC_SCLK=64Fs
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM ADC_LRCK=SSM/DSM/QSM
ADC Mode
One-Line
Mode #1
DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=128Fs
ADC_LRCK=DAC_LRCK
One-Line
Mode #2
DAC_SCLK=64Fs
DAC_LRCK=SSM
ADC_SCLK=256Fs
ADC_LRCK=DAC_LRCK
DAC_SCLK=128Fs
DAC_LRCK=SSM
ADC_SCLK=128Fs
ADC_LRCK=DAC_LRCK
not valid
One-Line Mode #2
not valid
not valid
not valid
MCLK
LRCK
ADC_SCLK
SCLK
MCLK
ADC_LRCK
RMCK
SDOUT1
ADCIN1
SDOUT2
ADCIN2
64Fs,128Fs,
256Fs
SCLK_PORT1
LRCK_PORT1
ADC Data
ADC_SDOUT
SDIN_PORT1
CS5361
CS5361
64Fs,128Fs
DAC_SCLK
SCLK_PORT2
DAC_LRCK
LRCK_PORT2
DAC_SDIN1
DAC_SDIN2
SDOUT1_PORT2
DAC_SDIN3
SDOUT3_PORT2
CS42426
SDOUT2_PORT2
DIGITAL AUDIO
PROCESSOR
Figure 18. OLM Configuration #2
32
DS604F1
CS42426
4.5.4.3
OLM Config #3
This configuration will support up to 6 channels of DAC data and 6 channels of ADC data. OLM Config #3
will handle up to 20-bit ADC samples at an Fs of 48 kHz and 24-bit DAC samples at an Fs of 48 kHz. Since
the ADC’s data stream is configured to use the ADC_SDOUT output and the internal and external ADCs
are clocked from the ADC_SP, the sample rate for the DAC Serial Port can be different from the sample
rate of the ADC serial port.
Register / Bit Settings
Description
Functional Mode Register (addr = 03h)
Set DAC_FMx = 00,01,10
DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK
Set ADC_FMx = 00,01,10
ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK
Configure ADC_SDOUT to be clocked from the ADC_SP clocks.
Set ADC_CLK_SEL = 1
Interface Format Register (addr = 04h)
Select the digital interface format when not in One-Line Mode
Set DIFx bits to proper serial format
Set ADC_OLx bits = 00,01
Select ADC operating mode, see table below for valid combinations
Set DAC_OLx bits = 00,01,10
Select DAC operating mode, see table below for valid combinations
Misc. Control Register (addr = 05h)
Set DAC Serial Port to Master Mode.
Set DAC_SP M/S = 1
Set ADC Serial Port to Master Mode or Slave Mode.
Set ADC_SP M/S = 0 or 1
Identify external ADC clock source as ADC Serial Port.
Set EXT ADC SCLK = 0
DAC Mode
Not One-Line Mode
DAC_SCLK=64Fs
Not One- DAC_LRCK=SSM/DSM/QSM
Line Mode ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
ADC Mode
One-Line
Mode #1
DAC_SCLK=64Fs
DAC_LRCK=SSM/DSM/QSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
One-Line
Mode #2
One-Line Mode #1
One-Line Mode #2
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs
ADC_LRCK=SSM/DSM/QSM
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=128Fs
ADC_LRCK=SSM
not valid
not valid
not valid
M CLK
64Fs,128Fs
LRCK
ADC_SCLK
SCLK
ADC_LRCK
MCLK
RM CK
SDOUT1
ADCIN1
SDOUT2
ADCIN2
SCLK_PORT1
LRCK_PORT1
SDIN_PORT1
ADC_SDOUT
CS5361
CS5361
64Fs,128Fs,256Fs
DAC_SCLK
SCLK_PORT2
DAC_LRCK
LRCK_PORT2
DAC_SDIN1
DAC_SDIN2
SDOUT1_PORT2
DAC_SDIN3
SDOUT3_PORT2
CS42426
SDOUT2_PORT2
DIGITAL AUDIO
PROCESSOR
Figure 19. OLM Configuration #3
DS604F1
33
CS42426
4.5.4.4
OLM Config #4
This One-Line Mode configuration can support up to 6 channels of DAC data on 2 DAC_SDIN pins and 2
channels of ADC data and will handle up to 24-bit samples at a sampling frequency of 48 kHz on all channels for both the DAC and ADC. The output data stream of the internal ADCs can be configured to run at
the DAC_SP clock speeds or to run at the ADC_SP rate. The DAC_SP and ADC_SP can operate at different Fs rates.
Register / Bit Settings
Description
Functional Mode Register (addr = 03h)
Set DAC_FMx = 00,01,10
DAC_LRCK can run at SSM, DSM, or QSM independent of ADC_LRCK
Set ADC_FMx = 00,01,10
ADC_LRCK can run at SSM, DSM, or QSM independent of DAC_LRCK
Configure ADC_SDOUT to be clocked from the ADC_SP or DAC_SP
clocks.
Set ADC_CLK_SEL = 0 or 1
Interface Format Register (addr = 04h)
Set DIFx bits to proper serial format
Select the digital interface format when not in One-Line Mode
Set ADC operating mode to Not One-Line Mode since only 2 channels of
ADC are supported
Set ADC_OLx bits = 00
Set DAC_OLx bits = 00,01,10
Select DAC operating mode, see table below for valid combinations
Misc. Control Register (addr = 05h)
Set DAC_SP M/S = 0 or 1
Set DAC Serial Port to Master Mode or Slave Mode.
Set ADC_SP M/S = 0 or 1
Set ADC Serial Port to Master Mode or Slave Mode.
Set EXT ADC SCLK = 0
External ADCs are not used. Leave bit in default state.
DAC Mode
Not One-Line Mode
DAC_SCLK=64Fs/128Fs
Not One- DAC_LRCK=SSM/DSM/QSM
Line Mode ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
ADC Mode
One-Line Mode #1
DAC_SCLK=128Fs
DAC_LRCK=SSM/DSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
One-Line Mode #2
DAC_SCLK=256Fs
DAC_LRCK=SSM
ADC_SCLK=64Fs/128Fs
ADC_LRCK=SSM/DSM/QSM
One-Line
Mode #1
not valid
not valid
not valid
One-Line
Mode #2
not valid
not valid
not valid
M CLK
64Fs,128Fs
SCLK_PORT1
ADC_SCLK
LRCK_PORT1
ADC_LRCK
RMCK
SDIN_PORT1
ADC_SDOUT
ADCIN1
ADCIN2
SDIN_PORT2
64Fs,128Fs, 256Fs
DAC_SCLK
SCLK_PORT2
DAC_LRCK
DAC_SDIN1
DAC_SDIN2
LRCK_PORT2
DAC_SDIN3
SDOUT3_PORT2
CS42426
SDOUT1_PORT2
SDOUT2_PORT2
DIGITAL AUDIO
PROCESSOR
Figure 20. OLM Configuration #4
34
DS604F1
CS42426
4.6
Control Port Description and Timing
The control port is used to access the registers, allowing the CS42426 to be configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio sample rates. However, to avoid potential interference problems, the control port pins
should remain static if no operation is required.
The control port has two modes: SPI and I²C, with the CS42426 acting as a slave device. SPI mode is selected if there is a high-to-low transition on the AD0/CS pin after the RST pin has been brought high. I²C
mode is selected by connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently
selecting the desired AD0 bit address state.
4.6.1
SPI Mode
In SPI mode, CS is the CS42426 chip-select signal; CCLK is the control port bit clock (input into the
CS42426 from the microcontroller); CDIN is the input data line from the microcontroller, and CDOUT is
the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the
falling edge.
Figure 21 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The
first seven bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits form the Memory Address Pointer (MAP),
which is set to the address of the register that is to be updated. The next eight bits are the data which will
be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z
state. It may be externally pulled high or low with a 47 kΩ resistor, if desired.
There is a MAP auto-increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero,
the MAP will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment
after each byte is read or written, allowing block reads or writes of successive registers.
To read a register, the MAP has to be set to the correct address by executing a partial write cycle which
finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not,
as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high.
The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high
impedance state). If the MAP auto-increment bit is set to 1, the data for successive registers will appear
consecutively.
CS
CC LK
C H IP
ADDRESS
C D IN
1001111
MAP
MSB
R/W
C H IP
ADDRESS
DATA
b y te 1
LSB
1001111
R/W
b y te n
High Impedance
CDOUT
MSB
LSB MSB
LSB
MAP = Memory Address Pointer, 8 bits, MSB first
Figure 21. Control Port Timing in SPI Mode
DS604F1
35
CS42426
4.6.2
I²C Mode
In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by the clock, SCL.
There is no CS pin. Pins AD0 and AD1 form the two least-significant bits of the chip address and should
be connected through a resistor to VLC or DGND as desired. The state of the pins is sensed while the
CS42426 is being reset.
The signal timings for a read and write cycle are shown in Figure 22 and Figure 23. A Start condition is
defined as a falling transition of SDA while the clock is high. A Stop condition is a rising transition while
the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the
CS42426 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low
for a write). The upper 5 bits of the 7-bit address field are fixed at 10011. To communicate with a CS42426,
the chip address field, which is the first byte sent to the CS42426, should match 10011, followed by the
settings of the AD1 and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the
next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an
acknowledge bit. The ACK bit is output from the CS42426 after each input byte is read and is input to the
CS42426 from the microcontroller after each transmitted byte.
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
24 25 26 27 28
19
SCL
CHIP ADDRESS (WRITE)
1
SDA
0
0
1
MAP BYTE
1 AD1 AD0 0
INCR
6
5
4
3
DATA +1
DATA
2
1
0
ACK
7
6
1
ACK
0
7
6
1
DATA +n
0
7
6
1
0
ACK
ACK
STOP
START
Figure 22. Control Port Timing, I²C Write
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
17 18
19
20 21 22 23 24 25 26 27 28
SCL
CHIP ADDRESS (WRITE)
SDA
1
0
0
1
STOP
MAP BYTE
1 AD1 AD0 0
INCR
6
5
4
3
ACK
START
2
1
CHIP ADDRESS (READ)
1
0
0
0
1
DATA
1 AD1 AD0 1
ACK
START
7
ACK
DATA +1
0
7
ACK
0
DATA + n
7
0
NO
ACK
STOP
Figure 23. Control Port Timing, I²C Read
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 23, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
36
DS604F1
CS42426
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4.7
Interrupts
The CS42426 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with
no active pull-up transistor. This last mode is used for active low, wired-OR hook-ups, with multiple peripherals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt
Status (address 20h) (Read Only)” on page 56). Each source may be masked off through mask register bits.
In addition, each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option
of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are possible, depending on the needs of the equipment designer.
4.8
Reset and Power-Up
Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks and
configuration pins are stable. It is also recommended that reset be activated if the analog or digital supplies
drop below the recommended operating condition to prevent power-glitch-related issues.
When RST is low, the CS42426 enters a low-power mode and all internal states are reset, including the
control port and registers, and the outputs are muted. When RST is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the
Power Control Register will then cause the part to leave the low-power state and begin operation. If the internal PLL is selected as the clock source, the serial audio outputs will be enabled after the PLL has settled
(see “Power Control (address 02h)” on page 43 for more details).
The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either
through the application of power or by setting the RST pin high. However, the voltage reference will take
much longer to reach a final value due to the presence of external capacitance on the FILT+ pin. A time
delay of approximately 80 ms is required after applying power to the device or after exiting a reset state.
During this voltage reference ramp delay, all serial ports and DAC outputs will be automatically muted.
DS604F1
37
CS42426
4.9
Power Supply, Grounding, and PCB Layout
As with any high-resolution converter, the CS42426 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 5 and 6 show the recommended power
arrangements, with VA connected to clean supplies. VD, which powers the digital circuitry, may be run from
the system logic supply. Alternatively, VD may be powered from the analog supply via a ferrite bead. In this
case, no additional devices should be powered from VD.
For applications where the output of the PLL is required to be low jitter, use a separate, low-noise analog
+5 V supply for VA, decoupled to AGND. In addition, a separate region of analog ground plane around the
FILT+, VQ, LPFLT, REFGND, AGND, and VA pins is recommended.
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling
capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42426 as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on the same
side of the board as the CS42426 to minimize inductance effects. All signals, especially clocks, should be
kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the modulators and
PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned to minimize the
electrical path from FILT+ and REFGND. The CDB42428 evaluation board demonstrates the optimum layout and power supply arrangements.
38
DS604F1
CS42426
5. REGISTER QUICK REFERENCE
Addr Function
01h
02h
03h
04h
05h
06h
07h
08h
09h0Ch
0Dh
0Eh
0Fh
10h
11h
12h
ID
page 42
default
Power Control
page 43
default
Functional
Mode
page 43
default
Interface
Formats
page 45
default
Misc Control
7
6
5
4
3
2
1
0
Chip_ID3
Chip_ID2
Chip_ID1
Chip_ID0
Rev_ID3
Rev_ID2
Rev_ID1
Rev_ID0
1
1
1
1
X
X
X
X
Reserved
PDN_PLL
PDN_ADC
Reserved
PDN_DAC3
PDN_DAC2
PDN_DAC1
PDN
0
0
0
0
0
0
0
1
DAC_FM1
DAC_FM0
ADC_FM1
ADC_FM0
Reserved
ADC_CLK
SEL
DAC_DEM
Reserved
0
0
0
0
0
0
0
0
DIF1
DIF0
ADC_OL1
ADC_OL0
DAC_OL1
DAC_OL0
Reserved
CODEC_RJ16
0
1
0
0
0
0
0
0
Ext ADC
SCLK
HiZ_RMCK
Reserved
FREEZE
FILTSEL
HPF_
FREEZE
DAC_SP
M/S
ADC_SP
M/S
0
0
0
0
0
0
0
RMCK_DIV0
OMCK
Freq1
OMCK
Freq0
PLL_LRCK
SW_CTRL1
SW_CTRL0
FRC_PLL_LK
0
0
0
0
0
0
0
RATIO6
RATIO5
RATIO4
RATIO3
RATIO2
RATIO1
RATIO0
X
X
X
X
X
X
X
Reserved
Reserved
Reserved
Active_CLK
PLL_CLK2
PLL_CLK1
PLL_CLK0
X
X
X
X
X
X
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
page 46
0
default
Clock ConRMCK_DIV1
trol
page 48
0
default
OMCK/PLL_
RATIO7
CLK Ratio
page 49
X
default
Clock Status
Reserved
page 50
X
default
Reserved
default
Volume
Control
page 51
default
Channel
Mute
page 52
default
Vol. Control
A1
page 53
default
Vol. Control
B1
page 53
default
Vol. Control
A2
page 53
default
Vol. Control
B2
page 53
default
DS604F1
Reserved
X
X
X
X
X
X
X
X
Reserved
SNGVOL
SZC1
SZC0
AMUTE
Reserved
RAMP_UP
RAMP_DN
0
0
0
0
1
0
0
0
Reserved
Reserved
B3_MUTE
A3_MUTE
B2_MUTE
A2_MUTE
B1_MUTE
A1_MUTE
0
0
0
0
0
0
0
0
A1_VOL7
A1_VOL6
A1_VOL5
A1_VOL4
A1_VOL3
A1_VOL2
A1_VOL1
A1_VOL0
0
0
0
0
0
0
0
0
B1_VOL7
B1_VOL6
B1_VOL5
B1_VOL4
B1_VOL3
B1_VOL2
B1_VOL1
B1_VOL0
0
0
0
0
0
0
0
0
A2_VOL7
A2_VOL6
A2_VOL5
A2_VOL4
A2_VOL3
A2_VOL2
A2_VOL1
A2_VOL0
0
0
0
0
0
0
0
0
B2_VOL7
B2_VOL6
B2_VOL5
B2_VOL4
B2_VOL3
B2_VOL2
B2_VOL1
B2_VOL0
0
0
0
0
0
0
0
0
39
CS42426
Addr Function
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
40
Vol. Control
A3
page 53
default
Vol. Control
B3
page 53
default
Reserved
page 53
default
Reserved
page 53
default
Channel
Invert
page 53
default
Mixing Ctrl
Pair 1
page 53
default
Mixing Ctrl
Pair 2
page 53
default
Mixing Ctrl
Pair 3
page 53
default
Reserved
page 53
default
ADC Left
Ch. Gain
page 55
default
ADC Right
Ch. Gain
page 55
default
Interrupt
Control
page 55
default
Reserved
default
Interrupt
Status
page 56
default
Interrupt
Mask
page 57
default
Interrupt
Mode MSB
page 57
default
7
6
5
4
3
2
1
0
A3_VOL7
A3_VOL6
A3_VOL5
A3_VOL4
A3_VOL3
A3_VOL2
A3_VOL1
A3_VOL0
0
0
0
0
0
0
0
0
B3_VOL7
B3_VOL6
B3_VOL5
B3_VOL4
B3_VOL3
B3_VOL2
B3_VOL1
B3_VOL0
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved
INV_B3
INV_A3
INV_B2
INV_A2
INV_B1
INV_A1
0
0
0
0
0
0
0
0
P1_A=B
Reserved
Reserved
P1_ATAPI4
P1_ATAPI3
P1_ATAPI2
P1_ATAPI1
P1_ATAPI0
0
0
0
0
1
0
0
1
P2_A=B
Reserved
Reserved
P2_ATAPI4
P2_ATAPI3
P2_ATAPI2
P2_ATAPI1
P2_ATAPI0
0
0
0
0
1
0
0
1
P3_A=B
Reserved
Reserved
P3_ATAPI4
P3_ATAPI3
P3_ATAPI2
P3_ATAPI1
P3_ATAPI0
0
0
0
0
1
0
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
1
0
0
1
Reserved
Reserved
LGAIN5
LGAIN4
LGAIN3
LGAIN2
LGAIN1
LGAIN0
0
0
0
0
0
0
0
0
Reserved
Reserved
RGAIN5
RGAIN4
RGAIN3
RGAIN2
RGAIN1
RGAIN0
0
0
0
0
0
0
0
0
SP_SYNC
Reserved
DE-EMPH1
DE-EMPH0
INT1
INT0
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
UNLOCK
Reserved
Reserved
Reserved
Reserved
Reserved
OverFlow
Reserved
X
X
X
X
X
X
X
X
UNLOCKM
Reserved
Reserved
Reserved
Reserved
Reserved
OverFlowM
Reserved
0
0
0
0
0
0
0
0
UNLOCK1
Reserved
Reserved
Reserved
Reserved
Reserved
OF1
Reserved
0
0
0
0
0
0
0
0
DS604F1
CS42426
Addr Function
23h
24h27h
Interrupt
Mode LSB
page 57
default
Reserved
default
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
MUTEC
page 57
default
GPO7
page 58
default
GPO6
page 58
default
GPO5
page 58
default
GPO4
page 58
default
GPO3
page 58
default
GPO2
page 58
default
GPO1
page 58
default
DS604F1
7
6
5
4
3
2
1
0
UNLOCK0
Reserved
Reserved
Reserved
Reserved
Reserved
OF0
Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
Reserved
Reserved
MCPolarity
M_AOUTA1
M_AOUTB1
M_AOUTA2
M_AOUTB2
M_AOUTA3
M_AOUTB3
Reserved
0
0
0
1
1
1
1
1
Mode1
Mode0
Polarity
Function4
Function3
Function2
Function1
Function0
0
0
0
0
0
0
0
0
Mode1
Mode0
Polarity
Function4
Function3
Function2
Function1
Function0
0
0
0
0
0
0
0
0
Mode1
Mode0
Polarity
Function4
Function3
Function2
Function1
Function0
0
0
0
0
0
0
0
0
Mode1
Mode0
Polarity
Function4
Function3
Function2
Function1
Function0
0
0
0
0
0
0
0
0
Mode1
Mode0
Polarity
Function4
Function3
Function2
Function1
Function0
0
0
0
0
0
0
0
0
Mode1
Mode0
Polarity
Function4
Function3
Function2
Function1
Function0
0
0
0
0
0
0
0
0
Mode1
Mode0
Polarity
Function4
Function3
Function2
Function1
Function0
0
0
0
0
0
0
0
0
41
CS42426
6. REGISTER DESCRIPTION
All registers are read/write except for the I.D. and Revision Register, OMCK/PLL_CLK Ratio Register, Clock Status
and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after a power-up sequence or reset is listed in each bit description.
6.1
Memory Address Pointer (MAP)
Not a register
7
INCR
6.1.1
6
MAP6
5
MAP5
4
MAP4
3
MAP3
2
MAP2
1
MAP1
0
MAP0
INCREMENT (INCR)
Default = 1
Function:
Memory Address Pointer auto increment control
0MAP is not incremented automatically.
1Internal MAP is automatically incremented after each read or write.
6.1.2
MEMORY ADDRESS POINTER (MAPX)
Default = 0000001
Function:
Memory Address Pointer (MAP). Sets the register address that will be read or written by the control
port.
6.2
Chip I.D. and Revision Register (address 01h) (Read Only)
7
Chip_ID3
6.2.1
6
Chip_ID2
5
Chip_ID1
4
CHIP_ID0
3
Rev_ID3
2
Rev_ID2
1
Rev_ID1
0
Rev_ID0
CHIP I.D. (CHIP_IDX)
Default = 1111
Function:
I.D. code for the CS42426. Permanently set to 1111.
6.2.2
CHIP REVISION (REV_IDX)
Default = xxxx
Function:
CS42426 revision level.
Revision C1 is coded as 0101
Revision C is coded as 0011.
42
DS604F1
CS42426
6.3
Power Control (address 02h)
7
Reserved
6.3.1
6
PDN_PLL
5
PDN_ADC
4
Reserved
3
PDN_DAC3
2
PDN_DAC2
1
PDN_DAC1
0
PDN
POWER DOWN PLL (PDN_PLL)
Default = 0
Function:
When enabled, the PLL is held in a reset state. It is advised that any change of this bit be made while
the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility of audible
artifacts.
6.3.2
POWER DOWN ADC (PDN_ADC)
Default = 0
Function:
When enabled the stereo analog to digital converter will remain in a reset state. It is advised that any
change of this bit be made while the DACs are muted or the power-down bit (PDN) is enabled to eliminate the possibility of audible artifacts.
6.3.3
POWER DOWN DAC PAIRS (PDN_DACX)
Default = 0
Function:
When enabled the respective DAC channel pair x (AOUTAx and AOUTBx) will remain in a reset state.
6.3.4
POWER DOWN (PDN)
Default = 1
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the
control registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and
must be disabled before normal operation can occur.
6.4
Functional Mode (address 03h)
7
DAC_FM1
6.4.1
6
DAC_FM0
5
ADC_FM1
4
ADC_FM0
3
Reserved
2
ADC_SP SEL
1
DAC_DEM
0
Reserved
DAC FUNCTIONAL MODE (DAC_FMX)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:
Selects the required range of sample rates for all converters clocked from the DAC serial port (DAC_SP).
Bits must be set to the corresponding sample rate range when the DAC_SP is in Master or Slave Mode.
DS604F1
43
CS42426
6.4.2
ADC FUNCTIONAL MODE (ADC_FMX)
Default = 00
00 - Single-Speed Mode (4 to 50 kHz sample rates)
01 - Double-Speed Mode (50 to 100 kHz sample rates)
10 - Quad-Speed Mode (100 to 192 kHz sample rates)
11 - Reserved
Function:
Selects the required range of sample rates for the ADC serial port (ADC_SP). These bits must be set
to the corresponding sample rate range when the ADC_SP is in Master or Slave Mode.
6.4.3
ADC CLOCK SOURCE SELECT (ADC_CLK SEL)
Default = 0
0 - ADC_SDOUT clocked from the DAC_SP.
1 - ADC_SDOUT clocked from the ADC_SP.
Function:
Selects the desired clocks for the ADC serial output.
6.4.4
DAC DE-EMPHASIS CONTROL (DAC_DEM)
Default = 0
Function:
Enables the digital filter to maintain the standard 15µs/50µs digital de-emphasis filter response at the
auto-detected sample rate of either 32, 44.1, or 48 kHz. De-emphasis will not be enabled, regardless
of this register setting, at any other sample rate. If the FRC_PLL_LK bit is set to a ‘1’b, the auto-detect
sample rate feature is disabled. To apply the correct de-emphasis filter, use the DE-EMPH bits in the
Interrupt Control (address 1Eh) register to set the appropriate sample rate.
DAC_DEM
reg03h[1]
FRC_PLL_LK
reg06h[0]
DE-EMPH[1:0]
reg1Eh[5:4]
De-Emphasis
Mode
0
1
1
X
0
1
XX
XX
00
01
10
11
No De-Emphasis
Auto-Detect Fs
Reserved
32 kHz
44.1 kHz
48 kHz
Table 5. DAC De-Emphasis
44
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CS42426
6.5
Interface Formats (address 04h)
7
DIF1
6.5.1
6
DIF0
5
ADC_OL1
4
ADC_OL0
3
DAC_OL1
2
DAC_OL0
1
Reserved
0
CODEC_RJ16
DIGITAL INTERFACE FORMAT (DIFX)
Default = 01
Function:
These bits select the digital interface format used for the ADC & DAC Serial Port when not in One-Line
Mode. The required relationship between the Left/Right clock, serial clock, and serial data is defined by
the Digital Interface Format and the options are detailed in Figures 11-13.
DIF1
DIF0
0
0
1
1
0
1
0
1
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit or 24-bit data
Reserved
Format
Figure
0
1
2
-
13
12
11
-
Table 6. Digital Interface Formats
6.5.2
ADC ONE_LINE MODE (ADC_OLX)
Default = 00
Function:
These bits select which mode the ADC will use. By default, One-Line Mode is disabled, but it can be
selected using these bits. Please see Figures 14 and 15 to see the format of One-Line Mode 1 and
One-Line Mode 2.
ADC_OL1
ADC_OL0
0
0
0
1
1
0
1
1
Description
DIF: take the DIF setting from reg04h[7:6]
One-Line #1
One-Line #2
Reserved
Format
3
Figure
-
4
14
15
-
-
Table 7. ADC One-Line Mode
6.5.3
DAC ONE_LINE MODE (DAC_OLX)
Default = 00
Function:
These bits select which mode the DAC will use. By default, One-Line Mode is disabled, but it can be
selected using these bits. Please see Figures 14 and 15 to see the format of One-Line Mode 1 and
One-Line Mode 2.
DAC_OL1
DAC_OL0
0
0
0
1
1
0
1
1
Description
DIF: take the DIF setting from reg04h[7:6]
One-Line #1
One-Line #2
Reserved
Format
Figure
3
-
4
14
15
-
-
Table 8. DAC One-Line Mode
DS604F1
45
CS42426
6.5.4
CODEC RIGHT-JUSTIFIED BITS (CODEC_RJ16)
Default = 0
Function:
This bit determines how many bits to use during Right-Justified Mode for the DAC and ADC. By default, the DAC and ADC will be in RJ24 bits, but can be set to RJ16 bits.
0 - 24 bit mode.
1 - 16 bit mode.
6.6
Misc Control (address 05h)
7
Ext ADC SCLK
6.6.1
6
HiZ_RMCK
5
Reserved
4
FREEZE
3
FILT_SEL
2
HPF_FREEZE
1
DAC_SP
M/S
0
ADC_SP
M/S
EXTERNAL ADC SCLK SELECT (EXT ADC SCLK)
Default = 0
Function:
This bit identifies the SCLK source for the external ADCs attached to the ADCIN1/2 ports when using
One-Line Mode of operation.
0 - ADC_SCLK is used as external ADC SCLK.
1 - DAC_SCLK is used as external ADC SCLK.
6.6.2
RMCK HIGH IMPEDANCE (HIZ_RMCK)
Default = 0
Function:
This bit is used to create a high-impedance output on RMCK when the clock signal is not required.
6.6.3
FREEZE CONTROLS (FREEZE)
Default = 0
Function:
This function will freeze the previous output of, and allow modifications to be made to, the Volume
Control (address 0Fh-16h), Channel Invert (address 17h), and Mixing Control Pair (address 18h-1Bh)
registers without the changes taking effect until the FREEZE is disabled. To make multiple changes
in these control port registers take effect simultaneously, enable the FREEZE bit, make all register
changes, then disable the FREEZE bit.
46
DS604F1
CS42426
6.6.4
INTERPOLATION FILTER SELECT (FILT_SEL)
Default = 0
Function:
This feature allows the user to select whether the DAC interpolation filter has a fast- or slow roll-off.
For filter characteristics, please See “D/A Digital Filter Characteristics” on page 10.
0 - Fast roll-off.
1 - Slow roll-off.
6.6.5
HIGH-PASS FILTER FREEZE (HPF_FREEZE)
Default = 0
Function:
When this bit is set, the internal high-pass filter for the selected channel will be disabled. The current
DC offset value will be frozen and continue to be subtracted from the conversion result. See “A/D Digital Filter Characteristics” on page 8.
6.6.6
DAC SERIAL PORT MASTER/SLAVE SELECT (DAC_SP M/S)
Default = 0
Function:
In Master Mode, DAC_SCLK and DAC_LRCK are outputs. Internal dividers will divide the master
clock to generate the serial clock and left/right clock. In Slave Mode, DAC_SCLK and DAC_LRCK
become inputs.
If the DAC_SP is in Slave Mode, DAC_LRCK must be present for proper device operation.
6.6.7
ADC SERIAL PORT MASTER/SLAVE SELECT (ADC_SP M/S)
Default = 0
Function:
In Master Mode, ADC_SCLK and ADC_LRCK are outputs. Internal dividers will divide the master
clock to generate the serial clock and left/right clock. In Slave Mode, ADC_SCLK and ADC_LRCK
become inputs.
If the ADC_SP is in Slave Mode, ADC_LRCK must be present for proper device operation.
To use the PLL to lock to ADC_LRCK, the ADC_SP must be in Slave Mode. When using the PLL to
lock to LRCK, if ADC_SDOUT is configured to be clocked by the ADC_SP, both ADC_SCLK and
ADC_LRCK must be present. If ADC_SDOUT is configured to be clocked by the DAC_SP, only the
ADC_LRCK signal must be applied.
DS604F1
47
CS42426
6.7
Clock Control (address 06h)
7
RMCK_DIV1
6.7.1
6
RMCK_DIV0
5
OMCK Freq1
4
OMCK Freq0
3
PLL_LRCK
2
SW_CTRL1
1
SW_CTRL0
0
FRC_PLL_LK
RMCK DIVIDE (RMCK_DIVX)
Default = 00
Function:
Divides/multiplies the internal MCLK, either from the PLL or OMCK, by the selected factor.
RMCK_DIV1 RMCK_DIV0
0
0
1
1
0
1
0
1
Description
Divide by 1
Divide by 2
Divide by 4
Multiply by 2
Table 9. RMCK Divider Settings
6.7.2
OMCK FREQUENCY (OMCK FREQX)
Default = 00
Function:
Sets the appropriate frequency for the supplied OMCK.
OMCK Freq1 OMCK Freq0
0
0
1
1
0
1
0
1
Description
11.2896 MHz or 12.2880 MHz
16.9344 MHz or 18.4320 MHz
22.5792 MHz or 24.5760 MHz
Reserved
Table 10. OMCK Frequency Settings
6.7.3
PLL LOCK TO LRCK (PLL_LRCK)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, the internal PLL of the CS42426 will lock to the ADC_LRCK of the ADC serial port
(ADC_LRCK) while the ADC_SP is in Slave Mode.
48
DS604F1
CS42426
6.7.4
MASTER CLOCK SOURCE SELECT (SW_CTRLX)
Default = 00
Function:
These two bits, along with the UNLOCK bit in register “Interrupt Status (address 20h) (Read Only)”
on page 56, determine the master clock source for the CS42426. When SW_CTRL1 and SW_CTRL0
are set to '00'b, selecting the output of the PLL as the internal clock source, and the PLL becomes
unlocked, RMCK will equal OMCK, but all internal and serial port timings are not valid.
When the FRC_PLL_LK bit is set to ‘1’b, the SW_CTRLX bits must be set to ‘00’b. If the PLL becomes
unlocked when the FRC_PLL_LK bit is set to ‘1’b, RMCK will not equal OMCK.
SW_CTRL1 SW_CTRL0
0
0
0
1
1
0
1
1
UNLOCK
X
X
0
1
0
1
Description
Manual setting, MCLK sourced from PLL.
Manual setting, MCLK sourced from OMCK.
Hold, keep same MCLK source.Auto switch, MCLK
sourced from OMCK.
Auto switch, MCLK sourced from PLL.
Auto switch, MCLK sourced from OMCK.
Table 11. Master Clock Source Select
6.7.5
FORCE PLL LOCK (FRC_PLL_LK)
Default = 0
Function:
This bit is used to enable the PLL to lock to the ADC_LRCK with the absence of a clock signal on
OMCK. When set to a ‘1’b, the auto-detect sample frequency feature will be disabled and the
SW_CTRLX bits must be set to ‘00’b. The OMCK/PLL_CLK Ratio (address 07h) (Read Only) register
contents are not valid, and the PLL_CLK[2:0] bits will be set to ‘111’b. Use the DE-EMPH[1:0] bits to
properly apply de-emphasis filtering.
6.8
OMCK/PLL_CLK Ratio (address 07h) (Read Only)
7
RATIO7(21)
6.8.1
6
RATIO6(20)
5
RATIO5(2-1)
4
RATIO4(2-2)
3
RATIO3(2-3)
2
RATIO2(2-4)
1
RATIO1(2-5)
0
RATIO0(2-6)
OMCK/PLL_CLK RATIO (RATIOX)
Default = xxxxxxxx
Function:
This register allows the user to find the exact absolute frequency of the recovered MCLK coming from
the PLL. This value is represented as an integer (RATIO7:6) and a fractional (RATIO5:0) part. For
example, an OMCK/PLL_CLK ratio of 1.5 would be displayed as 60h.
DS604F1
49
CS42426
6.9
Clock Status (address 08h) (Read Only)
7
Reserved
6.9.1
6
Reserved
5
Reserved
4
Reserved
3
Active_CLK
2
PLL_CLK2
1
PLL_CLK1
0
PLL_CLK0
SYSTEM CLOCK SELECTION (ACTIVE_CLK)
Default = x
0 - Output of PLL
1 - OMCK
Function:
This bit identifies the source of the internal system clock (MCLK).
6.9.2
PLL CLOCK FREQUENCY (PLL_CLKX)
Default = xxx
Function:
The CS42426 detects the ratio between the OMCK and the recovered clock from the PLL. Given the
absolute frequency of OMCK, this ratio may be used to determine the absolute frequency of the PLL
clock.
If a 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz clock is applied to OMCK and the OMCK_FREQX
bits are set accordingly (see “OMCK Frequency (OMCK Freqx)” on page 48), the absolute frequency
of the PLL clock is reflected in the PLL_CLKX bits according to Table 14. If the absolute frequency of
the PLL clock does not match one of the frequencies given in Table 14, these bits will reflect the closest available value.
If the frequency of OMCK is not equal to 12.2880 MHz, 18.4320 MHz, or 24.5760 MHz, the contents
of the PLL_CLKX bits will be inaccurate and should be disregarded. In this case, an external controller
may use the contents of the OMCK/PLL_CLK ratio register and the known OMCK frequency to determine the absolute frequency of the PLL clock.
Note:
These bits are set to ‘111’b when the FRC_PLL_LK bit is ‘1’b.
PLL_CLK2
PLL_CLK1
PLL_CLK0
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
8.1920 MHz
11.2896 MHz
12.288 MHz
16.3840 MHz
22.5792 MHz
24.5760 MHz
45.1584 MHz
49.1520 MHz
Table 12. PLL Clock Frequency Detection
50
DS604F1
CS42426
6.10
Volume Transition Control (address 0Dh)
7
Reserved
6
SNGVOL
5
SZC1
4
SZC0
3
AMUTE
2
MUTE
ADC_SP
1
RAMP_UP
0
RAMP_DN
6.10.1 SINGLE VOLUME CONTROL (SNGVOL)
Default = 0
Function:
The individual channel volume levels are independently controlled by their respective Volume Control
registers when this function is disabled. When enabled, the volume on all channels is determined by
the A1 Channel Volume Control register and the other Volume Control registers are ignored.
6.10.2 SOFT RAMP AND ZERO CROSS CONTROL (SZCX)
Default = 00
00 - Immediate Change
01 - Zero Cross
10 - Soft Ramp
11 - Soft Ramp on Zero Crossings
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross
Zero Cross Enable dictates that signal-level changes, either by attenuation changes or muting, will
occur on a signal zero crossing to minimize audible artifacts. The requested level-change will occur
after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms at 48 kHz sample
rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and implemented for each channel.
Soft Ramp
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally
ramping, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock
periods.
Soft Ramp on Zero Crossing
Soft Ramp and Zero Cross Enable dictates that signal level changes, either by attenuation changes
or muting, will occur in 1/8 dB steps and be implemented on a signal zero crossing. The 1/8 dB level
change will occur after a timeout period between 512 and 1024 sample periods (10.7 ms to 21.3 ms
at 48 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is
independently monitored and implemented for each channel.
DS604F1
51
CS42426
6.10.3
AUTO-MUTE (AMUTE)
Default = 1
0 - Disabled
1 - Enabled
Function:
The digital-to-analog converters of the CS42426 will mute the output following the reception of 8192
consecutive audio samples of static 0 or -1. A single sample of non-static data will release the mute.
Detection and muting is done independently for each channel. The quiescent voltage on the output
will be retained, and the MUTEC pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits (SZC[1:0]).
6.10.4 SOFT VOLUME RAMP-UP AFTER ERROR (RMP_UP)
Default = 0
0 - Disabled
1 - Enabled
Function:
An un-mute will be performed after executing a filter mode change, after a MCLK/LRCK ratio change
or error, and after changing the Functional Mode. When this feature is enabled, this un-mute is affected, similar to attenuation changes, by the Soft and Zero Cross bits (SZC[1:0]). When disabled, an
immediate un-mute is performed in these instances.
Note:
For best results, it is recommended that this bit be used in conjunction with the RMP_DN bit.
6.10.5 SOFT RAMP-DOWN BEFORE FILTER MODE CHANGE (RMP_DN)
Default = 0
0 - Disabled
1 - Enabled
Function:
A mute will be performed prior to executing a filter mode or de-emphasis mode change. When this
feature is enabled, this mute is affected, similar to attenuation changes, by the Soft and Zero Cross
bits (SZC[1:0]). When disabled, an immediate mute is performed prior to executing a filter mode or
de-emphasis mode change.
Note:
6.11
For best results, it is recommended that this bit be used in conjunction with the RMP_UP bit.
Channel Mute (address 0Eh)
7
Reserved
6
Reserved
5
B3_MUTE
4
A3_MUTE
3
B2_MUTE
2
A2_MUTE
1
B1_MUTE
0
A1_MUTE
6.11.1 INDEPENDENT CHANNEL MUTE (XX_MUTE)
Default = 0
0 - Disabled
1 - Enabled
Function:
The digital-to-analog converter outputs of the CS42426 will mute when enabled. The quiescent voltage on the outputs will be retained. The muting function is affected, similar to attenuation changes,
by the Soft and Zero Cross bits (SZC[1:0]).
52
DS604F1
CS42426
6.12
Volume Control (addresses 0Fh, 10h, 11h, 12h, 13h, 14h)
7
xx_VOL7
6
xx_VOL6
5
xx_VOL5
4
xx_VOL4
3
xx_VOL3
2
xx_VOL2
1
xx_VOL1
0
xx_VOL0
6.12.1 VOLUME CONTROL (XX_VOL)
Default = 0
Function:
The Digital Volume Control registers allow independent control of the signal levels in 0.5 dB increments from 0 to -127 dB. Volume settings are decoded as shown in Table 13. The volume changes
are implemented as dictated by the Soft and Zero Cross bits (SZC[1:0]). All volume settings less than
-127 dB are equivalent to enabling the MUTE bit for the given channel.
Binary Code
Decimal Value
Volume Setting
00000000
00101000
01010000
01111000
10110100
0
40
80
120
180
0 dB
-20 dB
-40 dB
-60 dB
-90 dB
Table 13. Example Digital Volume Settings
6.13
Channel Invert (address 17h)
7
Reserved
6
Reserved
5
INV_B3
4
INV_A3
3
INV_B2
2
INV_A2
1
INV_B1
0
INV_A1
6.13.1 INVERT SIGNAL POLARITY (INV_XX)
Default = 0
0 - Disabled
1 - Enabled
Function:
When enabled, these bits will invert the signal polarity of their respective channels.
6.14
Mixing Control Pair 1 (Channels A1 & B1)(address 18h)
Mixing Control Pair 2 (Channels A2 & B2)(address 19h)
Mixing Control Pair 3 (Channels A3 & B3)(address 1Ah)
7
Px_A=B
6
Reserved
5
Reserved
4
Px_ATAPI4
3
Px_ATAPI3
2
Px_ATAPI2
1
Px_ATAPI1
0
Px_ATAPI0
6.14.1 CHANNEL A VOLUME = CHANNEL B VOLUME (PX_A=B)
Default = 0
0 - Disabled
1 - Enabled
Function:
The AOUTAx and AOUTBx volume levels are independently controlled by the A and the B Channel
Volume Control registers when this function is disabled. The volume on both AOUTAx and AOUTBx
are determined by the A Channel Volume Control registers (per A-B pair), and the B Channel Volume
Control registers are ignored when this function is enabled.
DS604F1
53
CS42426
6.14.2 ATAPI CHANNEL-MIXING AND MUTING (PX_ATAPIX)
Default = 01001
Function:
The CS42426 implements the channel-mixing functions of the ATAPI CD-ROM specification. The
ATAPI functions are applied per A-B pair. Refer to Table 14 and Figure 9 for additional information.
ATAPI4
ATAPI3
ATAPI2
ATAPI1
ATAPI0
AOUTAx
AOUTBx
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
a[(L+R)/2]
MUTE
MUTE
MUTE
MUTE
aR
aR
aR
aR
aL
aL
aL
aL
[(aL+bR)/2]
[(aL+bR)/2]
[(bL+aR)/2]
[(aL+bR)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
b[(L+R)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(bL+aR)/2]
MUTE
bR
bL
[(aL+bR)/2]
MUTE
bR
bL
[(aL+bR)/2]
Table 14. ATAPI Decode
54
DS604F1
CS42426
6.15
ADC Left Channel Gain (address 1Ch)
7
Reserved
6
Reserved
5
LGAIN5
4
LGAIN4
3
LGAIN3
2
LGAIN2
1
LGAIN1
0
LGAIN0
6.15.1 ADC LEFT CHANNEL GAIN (LGAINX)
Default = 00h
Function:
The level of the left analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 15.
6.16
ADC Right Channel Gain (address 1Dh)
7
Reserved
6
Reserved
5
RGAIN5
4
RGAIN4
3
RGAIN3
2
RGAIN2
1
RGAIN1
0
RGAIN0
6.16.1 ADC RIGHT CHANNEL GAIN (RGAINX)
Default = 00h
Function:
The level of the right analog channel can be adjusted in 1 dB increments as dictated by the Soft and
Zero Cross bits (SZC[1:0]) from +15 to -15 dB. Levels are decoded in two’s complement, as shown
in Table 15.
Binary Code
Decimal Value
Volume Setting
001111
001010
000101
000000
111011
110110
110001
+15
+10
+5
0
-5
-10
-15
+15 dB
+10 dB
+5 dB
0 dB
-5 dB
-10 dB
-15 dB
Table 15. Example ADC Input Gain Settings
6.17
Interrupt Control (address 1Eh)
7
SP_SYNC
6
Reserved
5
DE-EMPH1
4
DE-EMPH0
3
INT1
2
INT0
1
Reserved
0
Reserved
6.17.1 SERIAL PORT SYNCHRONIZATION (SP_SYNC)
Default = 0
0 - DAC & ADC Serial Port timings not in phase
1 - DAC & ADC Serial Port timings are in phase
Function:
Forces the LRCK and SCLK from the DAC & ADC Serial Ports to align and operate in phase. This
function will operate when both ports are running at the same sample rate or when operating at different sample rates.
DS604F1
55
CS42426
6.17.2 DE-EMPHASIS SELECT BITS (DE-EMPHX)
Default = 00
00 - Reserved
01 - De-Emphasis for 32 kHz sample rate.
10 - De-Emphasis for 44.1 kHz sample rate.
11 - De-Emphasis for 48 kHz sample rate.
Function:
Used to specify which de-emphasis filter to apply when the “Force PLL Lock (FRC_PLL_LK)” on
page 49 is enabled.
6.17.3 INTERRUPT PIN CONTROL (INTX)
Default = 00
00 - Active high; high output indicates interrupt condition has occurred
01 - Active low; low output indicates an interrupt condition has occurred
10 - Open drain, active low. Requires an external pull-up resistor on the INT pin.
11 - Reserved
Function:
Determines how the interrupt pin (INT) will indicate an interrupt condition.
6.18
Interrupt Status (address 20h) (Read Only)
7
UNLOCK
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
OverFlow
0
Reserved
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the
register. Reading the register resets all bits to 0. Status bits that are masked off in the associated mask register will
always be “0” in this register.
6.18.1 PLL UNLOCK (UNLOCK)
Default = 0
Function:
PLL unlock status bit. This bit will go high if the PLL becomes unlocked.
6.18.2 ADC OVERFLOW (OVERFLOW)
Default = 0
Function:
Indicates that there is an over-range condition anywhere in the CS42426 ADC signal path.
56
DS604F1
CS42426
6.19
Interrupt Mask (address 21h)
7
UNLOCKM
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
OverFlowM
0
Reserved
Default = 00000000
Function:
The bits of this register serve as a mask for the interrupt sources found in the register “Interrupt Status
(address 20h) (Read Only)” on page 56. If a mask bit is set to 1, the error is unmasked, meaning that
its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is
masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions
align with the corresponding bits in the Interrupt Status register.
6.20
Interrupt Mode MSB (address 22h)
Interrupt Mode LSB (address 23h)
7
UNLOCK1
UNLOCK0
6
Reserved
Reserved
5
Reserved
Reserved
4
Reserved
Reserved
3
Reserved
Reserved
2
Reserved
Reserved
1
OF1
OF0
0
Reserved
Reserved
Default = 00000000
Function:
The two Interrupt Mode registers form a 2-bit code for each Interrupt Status register function. There
are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge
active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge
active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active
mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active
level (Active High or Low) only depends on the INT(1:0) bits located in the register “Interrupt Control
(address 1Eh)” on page 55.
00 - Rising edge active
01 - Falling edge active
10 - Level active
11 - Reserved
6.21
Mutec Pin Control (address 28h)
7
Reserved
6
Reserved
5
MCPolarity
4
M_AOUTA1
3
M_AOUTB1
2
M_AOUTA2
M_AOUTB2
1
M_AOUTA3
M_AOUTB3
0
Reserved
6.21.1 MUTEC POLARITY SELECT (MCPOLARITY)
Default = 0
0 - Active low
1 - Active high
Function:
Determines the polarity of the MUTEC pin.
DS604F1
57
CS42426
6.21.2 CHANNEL MUTES SELECT (M_AOUTXX)
Default = 1111
0 - Channel mute is not mapped to the MUTEC pin
1 - Channel mute is mapped to the MUTEC pin
Function:
Determines which channel mutes will be mapped to the MUTEC pin. If no channel mute bits are
mapped, then the MUTEC pin is driven to the “active” state as defined by the POLARITY bit. These
Channel Mute Select bits are “ANDed” together in order for the MUTEC pin to go active. This means
that if multiple Channel Mutes are selected to be mapped to the MUTEC pin, all corresponding channels must be muted before the MUTEC will go active.
6.22
General-Purpose Pin Control (addresses 29h to 2Fh)
7
Mode1
6
Mode0
5
Polarity
4
Function4
3
Function3
2
Function2
1
Function1
0
Function0
6.22.1 MODE CONTROL (MODEX)
Default = 00
00 - Reserved
01 - Mute Mode
10 - GPO/Overflow Mode
11 - GPO, Drive High Mode
Function:
Mute Mode - The pin is configured as a dedicated mute pin. The muting function is controlled by the
Function bits.
GPO, Drive Low / ADC Overflow Mode - The pin is configured as a general-purpose output driven low
or as a dedicated ADC overflow pin indicating an over-range condition anywhere in the ADC signal
path for either the left or right channel. The Functionx bits determine the operation of the pin. When
configured as a GPO with the output driven low, the driver is a CMOS driver. When configured to identify an ADC Overflow condition, the driver is an open drain driver requiring a pull-up resistor.
GPO, Drive High Mode - The pin is configured as a general purpose output driven high.
6.22.2 POLARITY SELECT (POLARITY)
Default = 0
Function:
Mute Mode - If the pin is configured as a dedicated mute output pin, the polarity bit determines the
polarity of the mapped pin according to the following
0 - Active low
1 - Active high
GPO, Drive Low / ADC Overflow Mode - If the pin is configured as a GPO, Drive Low / ADC Overflow
Mode pin, the polarity bit is ignored. It is recommended that in this mode this bit be set to 0.
GPO, Drive High - If the pin is configured as a general-purpose output driven high, the polarity bit is
ignored. It is recommended that in this mode this bit be set to 0.
58
DS604F1
CS42426
6.22.3 FUNCTIONAL CONTROL (FUNCTIONX)
Default = 00000
Function:
Mute Mode - If the pin is configured as a dedicated mute pin, the functional bits determine which channel mutes will be mapped to this pin according to the following table.
0 - Channel mute is not mapped to the GPOx pin
1 - Channel mute is mapped to the GPOx pin:
GPOx
GPO7
pin 42
GPO6
pin 43
GPO5
pin 44
GPO4
pin 45
GPO3
pin 46
GPO2
pin 47
GPO1
pin 48
Reg Address
Function4
Function3
29h
M_AOUTA1
M_AOUTB1
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
M_AOUTA1
M_AOUTB1
Function2
M_AOUTA2
M_AOUTB2
Function1
M_AOUTA3
M_AOUTB3
M_AOUTA3
M_AOUTB3
M_AOUTA3
M_AOUTB3
Function0
M_AOUTA3
M_AOUTB3
Reserved
M_AOUTA3
M_AOUTB3
Reserved
Reserved
Reserved
Reserved
Reserved
M_AOUTA2
M_AOUTB2
M_AOUTA2
M_AOUTB2
M_AOUTA2
M_AOUTB2
M_AOUTA2
M_AOUTB2
M_AOUTA2
M_AOUTB2
M_AOUTA2
M_AOUTB2
M_AOUTA3
M_AOUTB3
M_AOUTA3
M_AOUTB3
Reserved
Reserved
Reserved
GPO, Drive Low / ADC Overflow Mode - If the pin is configured as a GPO, Drive Low / ADC Overflow
Mode pin, the Function1 and Function0 bits determine how the output will behave according to the
following table. It is recommended that in this mode the remaining functional bits be set to 0.
Function1
0
1
Function0
0
1
GPOx
Drive Low
OVFL R or L
Driver Type
CMOS
Open Drain
GPO, Drive High - If the pin is configured as a general-purpose output, the functional bits are ignored
and the pin is driven high. It is recommended that in this mode all the functional bits be set to 0.
DS604F1
59
CS42426
7. PARAMETER DEFINITIONS
Dynamic Range
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made
with a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale.
This technique ensures that the distortion components are below the noise level and do not effect the
measurement. This measurement technique has been accepted by the Audio Engineering Society,
AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307. Expressed in decibels.
Total Harmonic Distortion + Noise
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified
band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured
at -1 and -20 dBFS as suggested in AES17-1991 Annex A.
Frequency Response
A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response
at 1 kHz. Units in decibels.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's
output with no signal to the input under test and a full-scale signal applied to the other channel. Units in
decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full-scale analog output for a full-scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/°C.
Offset Error
The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.
60
DS604F1
CS42426
8. APPENDIX A: EXTERNAL FILTERS
8.1
ADC Input Filter
The analog modulator samples the input at 6.144 MHz (internal MCLK=12.288 MHz). The digital filter will
reject signals within the stopband of the filter. However, there is no rejection for input signals which are
(n × 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to Figure 24 for a recommended
analog input buffer that will attenuate any noise energy at 6.144 MHz, in addition to providing the optimum
source impedance for the modulators. The use of capacitors that have a large voltage coefficient (such as
general-purpose ceramics) must be avoided since these can degrade signal linearity.
634 Ω
470 pF
C0G
-
100 µ F
AINL
91 Ω
A INL1+
+
634 Ω
634 Ω
100 kΩ
VA
2700 pF
C0G
470 pF
10 kΩ
C0G
2.8 kΩ
91 Ω
-
A INL1+
0.1 µ F
3.32 kΩ
100 µ F
332 Ω
634 Ω
470 pF
C0G
AINR
91 Ω
-
100 µ F
A INR1+
+
634 Ω
634 Ω
100 kΩ
VA
2700 pF
C0G
470 pF
10 kΩ
C0G
2.8 kΩ
91 Ω
-
A INR1-
+
3.32 kΩ
0.1 µ F
100 µ F
332 Ω
Figure 24. Recommended Analog Input Buffer
8.2
DAC Output Filter
The CS42426 is a linear phase design and does not include phase or amplitude compensation for an external filter. Therefore, the DAC system phase and amplitude response will be dependent on the external analog circuitry.
1800 pF
6.19 k Ω
390 pF
C0G
AOUT -
5.49 k Ω
2.94 k Ω
AOUT +
C0G
+
1.65 k Ω
887 Ω
1200 pF
5800 pF
C0G
22 µ F
1 kΩ
Analog
Out
47.5 k Ω
C0G
1.87 k Ω
22 µ F
Figure 25. Recommended Analog Output Buffer
DS604F1
61
CS42426
9. APPENDIX B: PLL FILTER
9.1
9.1.1
External Filter Components
General
The PLL behavior is affected by the external filter component values in the Typical Connection Diagrams.
Figure 5 and Figure 6 show the recommended configuration of the two capacitors and one resistor that
comprise the PLL filter. The external PLL component values listed in Table 16 have a high corner-frequency jitter-attenuation curve, take a short time to lock, and offer good output jitter performance. Lock times
are worst case for an Fsi transition of 192 kHz.
RFILT (kΩ) CFILT (µF) CRIP (pF)
2.55
0.047
2200
Table 16. PLL External Component Values
It is important to treat the LPFILT pin as a low-level analog input. It is suggested that the ground end of
the PLL filter be returned directly to the AGND pin independently of the digital ground plane.
9.1.2
Capacitor Selection
The type of capacitors used for the PLL filter can have a significant effect on PLL performance. Large or
exotic film capacitors are not necessary because their leads, and the required longer circuit board traces,
add undesirable inductance to the circuit. Surface-mount ceramic capacitors are a good choice because
their own inductance is low, and they can be mounted close to the LPFLT pin to minimize trace inductance. For CRIP, a C0G or NPO dielectric is recommended; and for CFILT, an X7R dielectric is preferred.
Avoid capacitors with large temperature co-coefficient, or capacitors with high dielectric constants, that
are sensitive to shock and vibration. These include the Z5U and Y5V dielectrics.
62
DS604F1
CS42426
9.1.3
Circuit Board Layout
RFILT
CRIP
VA
AGND
LPFLT
Board layout and capacitor choice affect each other and determine the performance of the PLL. Figure
26 illustrates a suggested layout for the PLL filter components and for bypassing the analog supply voltage. The 10 µF bypass capacitor is an electrolytic in a surface-mount case A or thru-hole package. RFILT,
CFILT, CRIP, and the 0.1 µF decoupling capacitor are in an 0805 form factor. The 0.01 µF decoupling
capacitor is in the 0603 form factor. The traces are on the top surface of the board with the IC so that there
is no via inductance. The traces themselves are short to minimize the inductance in the filter path. The
VA and AGND traces extend back to their origin and are shown only in truncated form in the drawing.
0.01 µF
0.1 µF
CFILT
10 µF
= via to ground plane
Figure 26. Recommended Layout Example
DS604F1
63
CS42426
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
Amplitude (dB)
Amplitude (dB)
10.APPENDIX C: ADC FILTER PLOTS
-60
-70
-80
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-140
0.40
1.0
Frequency (normalized to Fs)
0.42
0.44
0.46
0.48
0.50
0.52
0.54
0.56
0.58
0.60
Frequency (normalized to Fs)
Figure 27. Single-Speed Mode Stopband Rejection
Figure 28. Single-Speed Mode Transition Band
0.10
0
-1
0.08
-2
0.05
0.03
-4
Amplitude (dB)
Amplitude (dB)
-3
-5
-6
0.00
-0.03
-7
-0.05
-8
-9
-0.08
-10
0.45
0.46
0.47
0.48
0.49
0.50
0.51
0.52
0.53
0.54
0.55
Frequency (normalized to Fs)
-0.10
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
0
0
-10
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-70
-80
-60
-70
-80
-90
-90
-100
-100
-110
-110
-120
-120
-130
-130
-140
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
Frequency (normalized to Fs)
Figure 31. Double-Speed Mode Stopband Rejection
64
Figure 30. Single-Speed Mode Passband Ripple
Amplitude (dB)
Amplitude (dB)
Figure 29. Single-Speed Mode Transition Band (Detail)
1.0
-140
0.40
0.43
0.45
0.48
0.50
0.53
0.55
0.58
0.60
0.63
0.65
0.68
0.70
Frequency (normalized to Fs)
Figure 32. Double-Speed Mode Transition Band
DS604F1
CS42426
‘
0.10
0
-1
0.08
-2
0.05
-3
0.03
Amplitude (dB)
Amplitude (dB)
-4
-5
-6
0.00
-0.03
-7
-0.05
-8
-0.08
-9
-10
0.40
0.43
0.45
0.48
0.50
0.53
-0.10
0.00
0.55
Frequency (normalized to Fs)
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Frequency (normalized to Fs)
Figure 33. Double-Speed Mode Transition Band (Detail)
Figure 34. Double-Speed Mode Passband Ripple
0
0
-10
-10
-20
-20
-30
-30
-40
Amplitude (dB)
Amplitude (dB)
-40
-50
-60
-70
-50
-60
-70
-80
-80
-90
-90
-100
-100
-110
-110
-120
-130
-120
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.2
1.0
0.25
0.3
0
0.10
-1
0.08
-2
0.06
-3
0.04
-4
0.02
-5
-6
-0.04
-0.06
-9
-0.08
-10
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
Frequency (normalized to Fs)
Figure 37. Quad-Speed Mode Transition Band (Detail)
DS604F1
0.5
0.55
0.6
0.65
0.7
0.75
0.8
-0.02
-8
0.2
0.45
0.00
-7
0.15
0.4
Figure 36. Quad-Speed Mode Transition Band
Amplitude (dB)
Amplitude (dB)
Figure 35. Quad-Speed Mode Stopband Rejection
0.1
0.35
Frequency (normalized to Fs)
Frequency (normalized to Fs)
-0.10
0.00
0.05
0.10
0.15
0.20
0.25
Frequency (normalized to Fs)
Figure 38. Quad-Speed Mode Passband Ripple
65
CS42426
11.APPENDIX D: DAC FILTER PLOTS
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0
60
60
80
80
100
100
120
120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 39. Single-Speed (fast) Stopband Rejection
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 40. Single-Speed (fast) Transition Band
0.02
0
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
Figure 41. Single-Speed (fast) Transition Band (detail)
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
60
80
60
80
100
100
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 43. Single-Speed (slow) Stopband Rejection
66
0.05
Figure 42. Single-Speed (fast) Passband Ripple
0
120
0
120
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 44. Single-Speed (slow) Transition Band
DS604F1
CS42426
0.02
0
1
0.015
2
0.01
3
Amplitude (dB)
Amplitude (dB)
0.005
4
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.02
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 45. Single-Speed (slow) Transition Band (detail)
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0.05
Figure 46. Single-Speed (slow) Passband Ripple
0
60
60
80
80
100
100
120
0
120
0.4
0.5
0.6
0.7
0.8
Frequency(normalized to Fs)
0.9
1
Figure 47. Double-Speed (fast) Stopband Rejection
0.4
0.42
0.44
0.46
0.48
0.5
0.52
Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 48. Double-Speed (fast) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 49. Double-Speed (fast) Transition Band (detail)
DS604F1
0.02
0
0.05
0.1
0.15
0.2
0.25
0.3
Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 50. Double-Speed (fast) Passband Ripple
67
CS42426
0
20
20
40
40
Amplitude (dB)
Amplitude (dB)
0
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 51. Double-Speed (slow) Stopband Rejection
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 52. Double-Speed (slow) Transition Band
0
0.02
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.02
0.55
Figure 53. Double-Speed (slow) Transition Band (detail)
40
40
Amplitude (dB)
Amplitude (dB)
20
60
0.15
0.2
Frequency(normalized to Fs)
0.25
0.3
0.35
60
80
80
100
100
120
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 55. Quad-Speed (fast) Stopband Rejection
68
0.1
0
20
0.2
0.05
Figure 54. Double-Speed (slow) Passband Ripple
0
120
0
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
Figure 56. Quad-Speed (fast) Transition Band
DS604F1
CS42426
0.2
0
1
0.15
2
0.1
3
Amplitude (dB)
Amplitude (dB)
0.05
4
5
6
0
0.05
7
0.1
8
0.15
9
10
0.45
0.2
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 57. Quad-Speed (fast) Transition Band (detail)
0
0.05
0.1
0.15
Frequency(normalized to Fs)
0.2
0.25
Figure 58. Quad-Speed (fast) Passband Ripple
0
0
20
40
40
Amplitude (dB)
Amplitude (dB)
20
60
60
80
80
100
100
120
120
0.1
0.2
0.3
0.4
0.5
0.6
0.7
Frequency(normalized to Fs)
0.8
0.9
1
Figure 59. Quad-Speed (slow) Stopband Rejection
0.1
0.2
0.3
0.4
0.5
0.6
Frequency(normalized to Fs)
0.7
0.8
0.9
Figure 60. Quad-Speed (slow) Transition Band
0.02
0
1
0.015
2
0.01
0.005
4
Amplitude (dB)
Amplitude (dB)
3
5
6
0
0.005
7
0.01
8
0.015
9
10
0.45
0.46
0.47
0.48
0.49
0.5
0.51
Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
Figure 61. Quad-Speed (slow) Transition Band (detail)
DS604F1
0.02
0
0.02
0.04
0.06
0.08
Frequency(normalized to Fs)
0.1
0.12
Figure 62. Quad-Speed (slow) Passband Ripple
69
CS42426
12.PACKAGE DIMENSIONS
64L LQFP PACKAGE DRAWING
E
E1
D D1
1
e
B
∝
A
A1
L
DIM
A
A1
B
D
D1
E
E1
e*
L
MIN
--0.002
0.007
0.461
0.390
0.461
0.390
0.016
0.018
0.000°
∝
* Nominal pin pitch is 0.50 mm
INCHES
NOM
0.55
0.004
0.008
0.472 BSC
0.393 BSC
0.472 BSC
0.393 BSC
0.020 BSC
0.024
4°
MAX
0.063
0.006
0.011
0.484
0.398
0.484
0.398
0.024
0.030
7.000°
MILLIMETERS
NOM
1.40
0.10
0.20
12.0 BSC
10.0 BSC
12.0 BSC
10.0 BSC
0.50 BSC
0.60
4°
MIN
--0.05
0.17
11.70
9.90
11.70
9.90
0.40
0.45
0.00°
MAX
1.60
0.15
0.27
12.30
10.10
12.30
10.10
0.60
0.75
7.00°
Controlling dimension is mm.
JEDEC Designation: MS026
THERMAL CHARACTERISTICS
Parameter
Symbol
Allowable Junction Temperature
Junction to Ambient Thermal Impedance
70
θJA
Min
Typ
Max
Units
-
-
+135
°C
-
48
-
°C/Watt
DS604F1
CS42426
13.ORDERING INFORMATION
Product
CS42426
Description
Package
Pb-Free
114 dB, 192 kHz
6-Ch Codec
with PLL
64-pin
LQFP
YES
CDB42428 CS42426 Evaluation Board
No
Grade
Temp Range
Commercial
-10° to +70° C
Automotive
-40° to +85° C
-
-
Container
Tray
Tape & Reel
Tray
Tape & Reel
-
Order #
CS42426-CQZ
CS42426-CQZR
CS42426-DQZ
CS42426-DQZR
CDB42428
14.REFERENCES
1) Cirrus Logic, Audio Quality Measurement Specification, Version 1.0, 1997.
http://www.cirrus.com/products/papers/meas/meas.html
2) Cirrus Logic, AN18: Layout and Design Rules for Data Converters and Other Mixed Signal Devices,
Version 6.0, February 1998.
3) Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 1997.
4) Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del
Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th
Convention of the Audio Engineering Society, November 1988.
5) Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters,
and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention
of the Audio Engineering Society, October 1989.
6) Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering
Society, October 1989.
7) Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters,by
Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 1992.
8) Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori,
K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering
Society, October 1992.
9) Philips Semiconductor, The I2C-Bus Specification: Version 2.1, January 2000. http://www.semiconductors.philips.com
DS604F1
71
CS42426
15.REVISION HISTORY
Release
A1
A2
F1
72
Date
May 2003
August 2004
November 2005
Changes
Advance Release
Added lead free part numbers.
Final Release
– Added Revision History table on page 71.
– Updated registers 6.6.6 and 6.6.7 on page 47.
– Updated registers 6.7.4 and 6.7.5 on page 49.
– Updated PLL components in Table 16 on page 62.
– Added OMCK Frequency specification in the Switching Characteristics
table on page 11.
– Updated ADC Input Impedance and Offset Error specifications in the
Analog Input Characteristics table on page 7.
– Updated the DAC Full-Scale Voltage, Output Impedance, and Gain Drift
specifications in the Analog Output Characteristics table on page 9.
– Updated specification conditions for the analog input characteristics on
page 7.
– Updated specification conditions for the analog output characteristics on
page 9.
– Updated specification of tds, tdh, tdpd, and tlrpd in the Switching
Characteristics table on page 11.
– Corrected reference to the SW_CTRL[1:0] bits in section 4.4.3 on page 24.
– Moved the VQ and FILT+ specifications from the Analog Input
Characteristics table on page 7 to the DC Electrical Characteristics table
on page 14.
– Updated the Power Supply Current and Power Consumption
specifications in the DC Electrical Characteristics table on page 14.
– Updated section 4.4.4 on page 24.
– Corrected default value of the Chip_ID[3:0] bits in register 01h on
pages 39 and 42.
– Updated default value of the Rev_ID[3:0] bits in register 01h on pages 39
and 42.
– Updated PLL_CLK[2:0] bit description on page 49.
DS604F1
CS42426
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find the one nearest to you go to www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject
to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant
information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale
supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third
parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights,
copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent
does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE
IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD
TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED
IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER
AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH
THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks
or service marks of their respective owners.
SPI is a trademark of Motorola, Inc.
DS604F1
73