ON NB2304AC1HDR2G 3.3 v zero delay clock buffer Datasheet

NB2304A
3.3 V Zero Delay
Clock Buffer
The NB2304A is a versatile, 3.3 V zero delay buffer designed to
distribute high−speed clocks in PC, workstation, datacom, telecom
and other high−performance applications. It is available in an 8 pin
package. The part has an on−chip PLL which locks to an input clock
presented on the REF pin. The PLL feedback is required to be driven
to FBK pin, and can be obtained from one of the outputs. The
input−to−output propagation delay is guaranteed to be less than
250 ps, and the output−to−output skew is guaranteed to be less than
200 ps.
The NB2304A has two Banks of two outputs each. Multiple
NB2304A devices can accept the same input clock and distribute it. In
this case, the skew between the outputs of the two devices is
guaranteed to be less than 500 ps.
The NB2304A is available in two different configurations (Refer to
NB2304A Configurations Table). The NB2304Ax1* is the base part,
where the output frequencies equal the reference if there is no counter
in the feedback path. The NB2304Ax1H is the high−drive version of
the −1 and the rise and fall times on this device are much faster.
The NB2304Ax2 allows the user to obtain REF, 1/2 X and 2X
frequencies on each output Bank. The exact configuration and output
frequencies depend on which output drives the feedback pin.
Features
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MARKING
DIAGRAM*
8
SOIC−8
D SUFFIX
CASE 751
8
1
1
XXXX
A
L
Y
W
G
XXXX
ALYW
G
= Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
• Zero Input − Output Propagation Delay, Adjustable by Capacitive
•
•
•
•
•
•
•
•
•
•
•
•
Load on FBK Input
Multiple Configurations − Refer to NB2304A Configurations Table
Input Frequency Range: 15 MHz to 133 MHz
Multiple Low−Skew Outputs
Output−Output Skew < 200 ps
Device−Device Skew < 500 ps
Two Banks of Four Outputs
Less than 200 ps Cycle−to−Cycle Jitter (−1, −1H, −5H)
Available in Space Saving, 8 pin 150 mil SOIC Package
3.3 V Operation
Advanced 0.35 m CMOS Technology
Industrial Temperature Available
These are Pb−Free Devices
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
*x = C for Commercial; I for Industrial.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 5
1
Publication Order Number:
NB2304A/D
NB2304A
FBK
CLKA1
PLL
REF
CLKA2
Extra Divider (−2)
B2
CLKB1
CLKB2
Figure 1. Basic Block Diagram
(see Figures 11 and 12 for device specific Block Diagrams)
Table 1. CONFIGURATIONS (x = C for Commercial; I for Industrial)
Device
Feedback From
Bank A Frequency
Bank B Frequency
NB2304Ax1
Bank A or Bank B
Reference
Reference
NB2304Ax1H
Bank A or Bank B
Reference
Reference
NB2304Ax2
Bank A
Reference
Reference B2
NB2304Ax2
Bank B
2 X Reference
Reference
REF
1
CLKA1
2
8
FBK
7
VDD
NB2304A
Table 2. PIN DESCRIPTION
CLKA2
3
6
CLKB2
GND
4
5
CLKB1
Figure 2. Pin Configuration
Pin #
Pin Name
Description
1
REF (Note 1)
Input reference frequency, 5 V
tolerant input.
2
CLKA1 (Note 2)
Buffered clock output, Bank A.
3
CLKA2 (Note 2)
Buffered clock output, Bank A.
4
GND
5
CLKB1 (Note 2)
Buffered clock output, Bank B.
6
CLKB2 (Note 2)
Buffered clock output, Bank B.
Ground.
7
VDD
3.3 V supply.
8
FBK
PLL feedback input.
1. Weak pulldown.
2. Weak pulldown on all outputs.
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2
NB2304A
Table 3. MAXIMUM RATINGS
Parameter
Min
Max
Unit
Supply Voltage to Ground Potential
−0.5
+7.0
V
DC Input Voltage (Except REF)
−0.5
VDD + 0.5
V
DC Input Voltage (REF)
−0.5
7
V
Storage Temperature
−65
+150
°C
Maximum Soldering Temperature (10 sec)
260
°C
Junction Temperature
150
°C
> 2000
V
Static Discharge Voltage (per MIL−STD−883, Method 3015)
Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit
values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,
damage may occur and reliability may be affected.
Table 4. OPERATING CONDITIONS FOR COMMERCIAL AND INDUSTRIAL TEMPERATURE DEVICES
Parameter
Description
Min
Max
Unit
3.0
3.6
V
0
−40
70
85
°C
VDD
Supply Voltage
TA
Operating Temperature (Ambient Temperature)
CL
Load Capacitance, 15 MHz to 100 MHz
30
pF
CL
Load Capacitance, from 100 MHz to 133 MHz
15
pF
CIN
Input Capacitance (Note 3)
7
pF
Commercial
Industrial
3. Applies to both REF Clock and FBK.
Table 5. ELECTRICAL CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0 V
50.0
mA
IIH
Input HIGH Current
VIN = VDD
100.0
mA
VOL
Output LOW Voltage
IOL = 8 mA (−1, −2)
IOL = 12 mA (−1H)
0.4
V
VOH
Output HIGH Voltage
IOH = −8 mA (−1, −2)
IOH = −12 mA (−1H)
IDD
Supply Current
Unloaded outputs 100 MHz REF
Select inputs at VDD or GND
45
Unloaded outputs, 66 MHz REF (−1, −2)
32
Unloaded outputs, 33 MHz REF (−1, −2)
18
2.0
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3
V
2.4
V
mA
NB2304A
Table 6. SWITCHING CHARACTERISTICS FOR COMMERCIAL TEMPERATURE DEVICES
Parameter
t1
t3
Description
Test Conditions
Min
Output Frequency
30 pF load (all devices)
15 pF load (−1, −2)
Duty Cycle = (t2 / t1) * 100
(all devices)
Measured at 1.4 V, FOUT = 66.66 MHz
30 pF load
40.0
Measured at 1.4 V, FOUT v 50 MHz
15 pF load
45.0
Output Rise Time
(−1, −2)
Typ
Max
Unit
133
133.3
MHz
50.0
60.0
%
50.0
55.0
15
15
ns
Measured between 0.8 V and 2.0 V
30 pF load
2.20
Measured between 0.8 V and 2.0 V
15 pF load
1.50
Output Rise Time
(−1H)
Measured between 0.8 V and 2.0 V
30 pF load
1.50
Output Fall Time
(−1, −2)
Measured between 2.0 V and 0.8 V
30 pF load
2.20
Measured between 2.0 V and 0.8 V
15 pF load
1.50
Output Fall Time
(−1H)
Measured between 2.0 V and 0.8 V
30 pF load
1.25
Output−to−Output Skew on same Bank
(−1, −2)
All outputs equally loaded
200
Output−to−Output Skew
(−1H)
All outputs equally loaded
200
Output Bank A−to−Output Bank B Skew
(−1)
All outputs equally loaded
200
Output Bank A−to−Output Bank B Skew
(−2)
All outputs equally loaded
400
t6
Delay, REF Rising Edge to FBK Rising
Edge
Measured at VDD/2
0
±250
ps
t7
Device−to−Device Skew
Measured at VDD/2 on the FBK pins of the
device
0
500
ps
t8
Output Slew Rate
Measured between 0.8 V and 2.0 V using
Test Circuit #2
tJ
Cycle−to−Cycle Jitter
(−1, −1H)
Measured at 66.67 MHz, loaded outputs,
15 pF load
175
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
Measured at 66.67 MHz, loaded outputs,
30 pF load
400
Measured at 66.67 MHz, loaded outputs,
15 pF load
375
Stable power supply, valid clock presented
on REF and FBK pins
1.0
t4
t5
Cycle−to−Cycle Jitter
(−2)
tLOCK
PLL Lock Time
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4
1
ns
ps
V/ns
ps
ps
ms
NB2304A
Table 7. ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL TEMPERATURE DEVICES
Parameter
Description
Test Conditions
Min
Max
Unit
0.8
V
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
IIL
Input LOW Current
VIN = 0 V
50.0
mA
IIH
Input HIGH Current
VIN = VDD
100.0
mA
VOL
Output LOW Voltage
IOL = 8 mA (−1, −2)
IOL = 12 mA (−1H)
0.4
V
VOH
Output HIGH Voltage
IOH = −8 mA (−1, −2)
IOH = −12 mA (−1H)
IDD
Supply Current
Unloaded outputs 100 MHz REF
Select inputs at VDD or GND
45
Unloaded outputs, 66 MHz REF (−1, −2)
35
Unloaded outputs, 33 MHz REF (−1, −2)
20
2.0
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5
V
2.4
V
mA
NB2304A
Table 8. SWITCHING CHARACTERISTICS FOR INDUSTRIAL TEMPERATURE DEVICES
(All parameters are specified with loaded outputs)
Parameter
Description
Test Conditions
Min
Typ
Unit
100
133.3
MHz
%
t1
Output Frequency
30 pF load (all devices)
15 pF load (−1, −2)
t1
Duty Cycle = (t2 / t1) * 100
(all devices)
Measured at 1.4 V, FOUT v 66.66 MHz
30 pF load
40.0
50.0
60.0
Measured at 1.4 V, FOUT v 50 MHz
15 pF load
45.0
50.0
55.0
t3
Output Rise Time
(−1, −2)
15
15
Max
ns
Measured between 0.8 V and 2.0 V
30 pF load
2.50
Measured between 0.8 V and 2.0 V
15 pF load
1.50
Output Rise Time
(−1H)
Measured between 0.8 V and 2.0 V
30 pF load
1.50
Output Fall Time
(−1, −2)
Measured between 2.0 V and 0.8 V
30 pF load
2.50
Measured between 2.0 V and 0.8 V
15 pF load
1.50
Output Fall Time
(−1H)
Measured between 2.0 V and 0.8 V
30 pF load
1.25
Output−to−Output Skew on same Bank
(−1, −2)
All outputs equally loaded
200
Output−to−Output Skew
(−1H)
All outputs equally loaded
200
Output Bank A−to−Output Bank B skew
(−1)
All outputs equally loaded
200
Output Bank A−to−Output Bank B skew
(−2)
All outputs equally loaded
400
t6
Delay, REF Rising Edge to FBK Rising
Edge
Measured at VDD/2
0
±250
ps
t7
Device−to−Device Skew
Measured at VDD/2 on the FBK pins of the
device
0
500
ps
t8
Output Slew Rate
Measured between 0.8 V and 2.0 V using
Test Circuit #2
tJ
Cycle−to−Cycle Jitter
(−1, −1H)
Measured at 66.67 MHz, loaded outputs,
15 pF load
180
Measured at 66.67 MHz, loaded outputs,
30 pF load
200
Measured at 133.3 MHz, loaded outputs,
15 pF load
100
Measured at 66.67 MHz, loaded outputs,
30 pF load
400
Measured at 66.67 MHz, loaded outputs,
15 pF load
380
Stable power supply, valid clock presented
on REF and FBK pins
1.0
t4
t5
Cycle−to−Cycle Jitter
(−2)
tLOCK
PLL Lock Time
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6
1
ns
ps
V/ns
ps
ps
ms
NB2304A
Zero Delay and Skew Control
To close the feedback loop of the NB2304A, the FBK pin
can be driven from any of the four available output pins. The
output driving the FBK pin will be driving a total load of
7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs)
can adjust the input output delay. This is shown in Figure 3.
For applications requiring zero input−output delay, all
outputs including the one providing feedback should be
equally loaded. If input−output delay adjustments are
required, use Figure 3 to calculate loading differences
between the feedback output and remaining outputs. For
zero output−output skew, be sure to load outputs equally.
For applications requiring zero input−output delay, all
outputs must be equally loaded.
REF INPUT TO CLKA/CLKB DELAY (ps)
1500
1000
500
0
−500
−1000
−1500
−30 −25 −20 −15 −10
−5
0
5
10
15
20
25
30
OUTPUT LOAD DIFFERENCE: FBK LOAD − CLKA/CLKB LOAD (pF)
Figure 3. REF Input to CLKA/CLKB Delay vs.
Difference in Loading between FBK Pin and
CLKA/CLKB Pins
SWITCHING WAVEFORMS
t1
t2
1.4 V
1.4 V
0.8 V
0.8 V
OUTPUT
t3
Figure 4. Duty Cycle Timing
OUTPUT
0V
t4
Figure 5. All Outputs Rise/Fall Time
1.4 V
V DD
2
INPUT
1.4 V
OUTPUT
3.3 V
2.0 V
2.0 V
1.4 V
V DD
2
OUTPUT
t6
t5
Figure 6. Output − Output Skew
Figure 7. Input − Output Propagation Delay
V DD
2
FBK_Device 1
V DD
2
FBK_Device 2
t7
Figure 8. Device − Device Skew
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NB2304A
TEST CIRCUITS
VDD
VDD
0.1 mF
VDD
OUTPUTS
0.1 mF
CLOAD
GND
OUTPUTS
1 kW
VDD
0.1 mF
1 kW
10 pF
VDD
0.1 mF
GND
Figure 9. Test Circuit #1
GND
GND
Figure 10. Test Circuit #2
For parameter t8 (output slew rate) on −1H devices
BLOCK DIAGRAMS
FBK
FBK
CLKA1
CLKA1
CLKA2
REF
CLKA2
REF
PLL
B2
PLL
CLKB1
CLKB1
CLKB2
CLKB2
Figure 11. NB2304Ax1 and NB2304Ax1H
Figure 12. NB2304Ax2
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NB2304A
ORDERING INFORMATION
Marking
Operating Range
Package
Shipping†
NB2304AC1DG
4C1
Commercial
SOIC−8
(Pb−Free)
98 Units / Rail
NB2304AC1DR2G
4C1
Commercial
SOIC−8
(Pb−Free)
2500 Tape & Reel
NB2304AI1DG
4I1
Industrial
SOIC−8
(Pb−Free)
98 Units / Rail
NB2304AI1DR2G
4I1
Industrial
SOIC−8
(Pb−Free)
2500 Tape & Reel
NB2304AC1HDG
4C1H
Commercial
SOIC−8
(Pb−Free)
98 Units / Rail
NB2304AC1HDR2G
4C1H
Commercial
SOIC−8
(Pb−Free)
2500 Tape & Reel
NB2304AI1HDG
4I1H
Industrial
SOIC−8
(Pb−Free)
98 Units / Rail
NB2304AI1HDR2G
4I1H
Industrial
SOIC−8
(Pb−Free)
2500 Tape & Reel
NB2304AC2DG
4C2
Commercial
SOIC−8
(Pb−Free)
98 Units / Rail
NB2304AC2DR2G
4C2
Commercial
SOIC−8
(Pb−Free)
2500 Tape & Reel
NB2304AI2DG
4I2
Industrial
SOIC−8
(Pb−Free)
98 Units / Rail
NB2304AI2DR2G
4I2
Industrial
SOIC−8
(Pb−Free)
2500 Tape & Reel
Device
Availability
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
Now
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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NB2304A
PACKAGE DIMENSIONS
SOIC−8 NB
CASE 751−07
ISSUE AG
−X−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
8
5
S
B
1
0.25 (0.010)
M
Y
M
4
−Y−
K
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 _
SEATING
PLANE
−Z−
H
0.10 (0.004)
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0_
8_
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0 _
8 _
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
Licensed under US patent Nos 5,488,627, 6,646,463 and 5,631,920.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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For additional information, please contact your local
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NB2304A/D