Freescale Semiconductor Data Sheet: Technical Data MCF51QE128 MCF51QE128 Series Covers: MCF51QE128, MCF51QE32 MCF51QE96, Document Number: MCF51QE128 Rev. 7, 10/2008 MCF51QE64, • 32-Bit Version 1 ColdFire® Central Processor Unit (CPU) – Up to 50.33-MHz ColdFire V1 CPU above 2.4V, 40-MHz CPU above 2.1V, and 20-MHz CPU above 1.8V, across temperature range – Provides 0.94 Dhrystone 2.1 MIPS per MHz performance when running from internal RAM (0.76 DMIPS/MHz from flash) – Implements Instruction Set Revision C (ISA_C) – Support for up to 30 peripheral interrupt requests and seven software interrupts • On-Chip Memory – Flash read/program/erase over full operating voltage and temperature – Random-access memory (RAM) – Security circuitry to prevent unauthorized access to RAM and flash contents • Power-Saving Modes – Two low power stop modes; reduced power wait mode – Peripheral clock enable register can disable clocks to unused modules, reducing currents; allows clocks to remain enabled to specific peripherals in stop3 mode – Very low power external oscillator can be used in stop3 mode to provide accurate clock to active peripherals – Very low power real time counter for use in run, wait, and stop modes with internal and external clock sources – 6 μs typical wake up time from stop modes • Clock Source Options – Oscillator (XOSC) — Loop-control Pierce oscillator; Crystal or ceramic resonator range of 31.25 kHz to 38.4 kHz or 1 MHz to 16 MHz – Internal Clock Source (ICS) — FLL controlled by internal or external reference; precision trimming of internal reference allows 0.2% resolution and 2% deviation; supports CPU freq. from 2 to 50.33 MHz • System Protection – Watchdog computer operating properly (COP) reset with option to run from dedicated 1-kHz internal clock source or bus clock – Low-voltage detection with reset or interrupt; selectable trip points – Illegal opcode and illegal address detection with programmable reset or exception response – Flash block protection 80-LQFP Case 917A 14 mm2 • Development Support – Single-wire background debug interface – 4 PC plus 2 address (optional data) breakpoint registers with programmable 1- or 2-level trigger response – 64-entry processor status and debug data trace buffer with programmable start/stop conditions • ADC — 24-channel, 12-bit resolution; 2.5 μs conversion time; automatic compare function; 1.7 mV/°C temperature sensor; internal bandgap reference channel; operation in stop3; fully functional from 3.6V to 1.8V • ACMPx — Two analog comparators with selectable interrupt on rising, falling, or either edge of comparator output; compare option to fixed internal bandgap reference voltage; outputs can be optionally routed to TPM module; operation in stop3 • SCIx — Two SCIs with full duplex non-return to zero (NRZ); LIN master extended break generation; LIN slave extended break detection; wake up on active edge • SPIx— Two serial peripheral interfaces with Full-duplex or single-wire bidirectional; Double-buffered transmit and receive; MSB-first or LSB-first shifting • IICx — Two IICs with; Up to 100 kbps with maximum bus loading; Multi-master operation; Programmable slave address; Interrupt driven byte-by-byte data transfer; supports broadcast mode and 10 bit addressing • TPMx — One 6-channel and two 3-channel; Selectable input capture, output compare, or buffered edge- or center-aligned PWMs on each channel • RTC — 8-bit modulus counter with binary or decimal based prescaler; External clock source for precise time base, time-of-day, calendar or task scheduling functions; Free running on-chip low power oscillator (1 kHz) for cyclic wake-up without external components • Input/Output – 70 GPIOs and 1 input-only and 1 output-only pin – 16 KBI interrupts with selectable polarity – Hysteresis and configurable pull-up device on all input pins; Configurable slew rate and drive strength on all output pins. – SET/CLR registers on 16 pins (PTC and PTE) – 16 bits of Rapid GPIO connected to the CPU’s high-speed local bus with set, clear, and toggle functionality Freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. © Freescale Semiconductor, Inc., 2008. All rights reserved. 64-LQFP Case 840F 10 mm2 Table of Contents 1 2 3 MCF51QE128 Series Comparison . . . . . . . . . . . . . . . . . . . . . .4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .9 3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .9 3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .10 3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .11 3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .15 3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .18 3.9 Internal Clock Source (ICS) Characteristics . . . . . . . . .19 4 5 6 7 3.10 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 3.10.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . . 3.10.3 SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 Analog Comparator (ACMP) Electricals . . . . . . . . . . . 3.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . Product Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 21 23 24 27 27 30 31 31 31 36 36 MCF51QE128 Series Data Sheet, Rev. 7 2 Freescale Semiconductor PTA7/TPM2CH2/ADP9 PTA6/TPM1CH2/ADP8 PTA5/IRQ/TPM1CLK/RESET PTA4/ACMP1O/BKGD/MS PTA3/KBI1P3/SCL1/ADP3 PTA2/KBI1P2/SDA1/ADP2 PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ 3-CHANNEL TIMER/PWM TPM1CLK MODULE (TPM1) CPU ACMP1O ANALOG COMPARATOR (ACMP1) ACMP1+ ACMP1- IP Bus Bridge IIC MODULE (IIC1) ANALOG COMPARATOR (ACMP2) USER FLASH 128K / 64K USER RAM SERIAL COMMUNICATIONS INTERFACE (SCI1) Rapid GPIO SERIAL PERIPHERAL INTERFACE MODULE (SPI2) REAL TIME COUNTER (RTC) VOLTAGE REGULATOR PTJ7 PTJ6 PTJ5 PTJ4 PTJ3 PTJ2 PTJ1 PTJ0 SERIAL COMMUNICATIONS SERIAL PERIPHERAL INTERFACE MODULE (SPI1) TxD1 RxD1 SS2 MISO2 MOSI2 SPSCK2 PTE7/RGPIO7/TPM3CLK PTE6/RGPIO6 PTE5/RGPIO5 PTE4/RGPIO4 PTE3/RGPIO3/SS1 PTE2/RGPIO2/MISO1 PTE1/RGPIO1/MOSI1 PTE0/RGPIO0/TPM2CLK/SPSCK1 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTF3/ADP13 PTF2/ADP12 PTF1/ADP11 PTF0/ADP10 TxD2 RxD2 SS1 MISO1 MOSI1 SPSCK1 24-CHANNEL,12-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) VREFH VREFL VDDA VSSA SDA2 SCL2 IIC MODULE (IIC2) PORT G PORT H PTH7/SDA2 PTH6/SCL2 PTH5 PTH4 PTH3 PTH2 PTH1 PTH0 PTD7/KBI2P7 PTD6/KBI2P6 PTD5/KBI2P5 PTD4/KBI2P4 PTD3/KBI2P3/SS2 PTD2/KBI2P2/MISO2 PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 TPM3CLK INTERFACE (SCI2) PORT J VSS VSS SCL1 SDA1 ACMP2+ ACMP2O ACMP2- 16 8K / 6K / 4K VDD VDD PTC7/RGPIO15/TxD2/ACMP2PTC6/RGPIO14/RxD2/ACMP2+ PTC5/RGPIO13/TPM3CH5/ACMP2O PTC4/RGPIO12/TPM3CH4/RSTO PTC3/RGPIO11/TPM3CH3 PTC2/RGPIO10/TPM3CH2 PTC1/RGPIO9/TPM3CH1 PTC0/RGPIO8/TPM3CH0 TPM2CLK TPM3CH5-0 6-CHANNEL TIMER/PWM MODULE (TPM3) PORT B - MODULE (TPM2) PORT C INTC 3 3-CHANNEL TIMER/PWM IRQ LVD TPM2CH2-0 PORT D OSCILLATOR (XOSC) RESETS AND INTERRUPTS MODES OF OPERATION POWER MANAGEMENT PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6 PTB1/KBI1P5/TxD1/ADP5 PTB0/KBI1P4/RxD1/ADP4 PORT E SYSTEM CONTROL COP EXTAL XTAL INTERNAL CLOCK SOURCE (ICS) PORT F BDC / Debug PORT A BKGD/MS V1 ColdFire CORE RESET TPM1CH2-0 PTG7/ADP23 PTG6/ADP22 PTG5/ADP21 PTG4/ADP20 PTG3/ADP19 PTG2/ADP18 PTG1 PTG0 Figure 1. MCF51QE128 Series Block Diagram MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 3 MCF51QE128 Series Comparison 1 MCF51QE128 Series Comparison The following table compares the various device derivatives available within the MCF51QE128 series. Table 1. MCF51QE128 Series Features by MCU and Package Feature MCF51QE128 MCF51QE96 MCF51QE64 MCF51QE32 Flash size (bytes) 131072 98304 65536 32768 RAM size (bytes) 8192 8192 8192 8192 64 64 20 20 54 54 Pin quantity 80 64 80 64 Version 1 ColdFire core yes ACMP1 yes ACMP2 yes ADC channels 24 20 24 20 DBG yes ICS yes IIC1 yes IIC2 yes KBI 16 Port I/O1, 2 70 54 70 54 Rapid GPIO yes RTC yes SCI1 yes SCI2 yes SPI1 yes SPI2 yes External IRQ yes TPM1 channels 3 TPM2 channels 3 TPM3 channels 6 XOSC yes 1 Port I/O count does not include the input-only PTA5/IRQ/TPM1CLK/RESET or the output-only PTA4/ACMP1O/BKGD/MS. 2 16 bits associated with Ports C and E are shadowed with ColdFire Rapid GPIO module. MCF51QE128 Series Data Sheet, Rev. 7 4 Freescale Semiconductor Pin Assignments 2 Pin Assignments PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTH7/SDA2 PTH6/SCL2 PTH5 PTH4 PTE7/RGPIO7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTH3 PTH2 PTH1 PTH0 PTC7/RGPIO15 /TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1- PTE0/RGPIO0/TPM2CLK/SPSCK1 PTE1/RGPIO1/MOSI1 PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTE2/RGPIO2/MISO1 PTE3/RGPIO3/SS1 PTG4/ADP20 PTG5/ADP21 PTG6/ADP22 PTG7/ADP23 PTC6/RGPIO14/RxD2/ACMP2+ PTA5/IRQ/TPM1CLK/RESET PTC4/RGPIO12/TPM3CH4/RSTO PTC5/RGPIO13/TPM3CH5/ACMP2O 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PTA2/KBI1P2/SDA1/ADP2 PTA3/KBI1P3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTD4/KBI2P4 PTJ0 PTJ1 PTF0/ADP10 PTF1/ADP11 VSS VDD PTE4/RGPIO4 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTF2/ADP12 PTF3/ADP13 PTJ2 PTJ3 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5 PTD5/KBI2P5 PTJ7 PTJ6 PTJ5 PTJ4 PTC1/RGPIO9/TPM3CH1 PTC0/RGPIO8/TPM3CH0 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6 PTE5/RGPIO5 PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTC3/RGPIO11/TPM3CH3 PTC2/RGPIO10/TPM3CH2 PTD7/KBI2P7 PTD6/KBI2P6 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PTE6/RGPIO6 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PTA4/ACMP1O/BKGD/MS This section describes the pin assignments for the available packages. See Table 1 for pin availability by package pin-count. Pins in bold are added from the next smaller package. Figure 2. Pin Assignments in 80-Pin LQFP MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PTB7/SCL1/EXTAL PTB6/SDA1/XTAL PTH1 PTH0 PTE6/RGPIO6 6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PTD1/KBI2P1/MOSI2 PTD0/KBI2P0/SPSCK2 PTH7/SDA2 PTH6/SCL2 PTE7/RGPIO7/TPM3CLK VDD VDDAD VREFH VREFL VSSAD VSS PTD5/KBI2P5 PTC1/RGPIO9/TPM3CH1 PTC0/RGPIO8/TPM3CH0 PTF7/ADP17 PTF6/ADP16 PTF5/ADP15 PTF4/ADP14 PTB3/KBI1P7/MOSI1/ADP7 PTB2/KBI1P6/SPSCK1/ADP6 PTE5/RGPIO5 PTB5/TPM1CH1/SS1 PTB4/TPM2CH1/MISO1 PTC3/RGPIO11/TPM3CH3 PTC2/RGPIO10/TPM3CH2 PTD7/KBI2P7 PTD6/KBI2P6 PTC7/RGPIO15/TxD2/ACMP2PTA0/KBI1P0/TPM1CH0/ADP0/ACMP1+ PTA1/KBI1P1/TPM2CH0/ADP1/ACMP1- PTC6/RGPIO14/RxD2/ACMP2+ PTE0/RGPIO0/TPM2CLK/SPSCK1 PTE1/RGPIO1/MOSI1 PTG0 PTG1 PTG2/ADP18 PTG3/ADP19 PTE2/RGPIO2/MISO1 PTE3/RGPIO3/SS1 PTA5/IRQ/TPM1CLK/RESET PTC4/RGPIO12/TPM3CH4/RSTO PTC5/RGPIO13/TPM3CH5/ACMP2O PTA4/ACMP1O/BKGD/MS Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PTA2/KBI1P2/SDA11/ADP2 PTA3/KBI1P3/SCL1/ADP3 PTD2/KBI2P2/MISO2 PTD3/KBI2P3/SS2 PTD4/KBI2P4 PTF0/ADP10 PTF1/ADP11 VSS VDD PTE4/RGPIO4 PTA6/TPM1CH2/ADP8 PTA7/TPM2CH2/ADP9 PTF2/ADP12 PTF3/ADP13 PTB0/KBI1P4/RxD1/ADP4 PTB1/KBI1P5/TxD1/ADP5 Figure 3. Pin Assignments in 64-Pin LQFP Package MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor Pin Assignments Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority Pin Number Lowest ←⎯ Priority ⎯→ Highest Alt 2 Alt 3 Alt 4 80 64 Port Pin Alt 1 1 1 PTD1 KBI2P1 MOSI2 2 2 PTD0 KBI2P0 SPSCK2 3 3 PTH7 SDA2 4 4 PTH6 SCL2 5 — PTH5 6 — PTH4 7 5 PTE7 8 6 VDD 9 7 VDDAD 10 8 VREFH RGPIO7 TPM3CLK 11 9 VREFL 12 10 VSSAD 13 11 14 12 15 16 VSS PTB7 SCL1 EXTAL 13 PTB6 SDA1 XTAL — PTH3 17 — PTH2 18 14 PTH1 19 15 PTH0 20 16 PTE6 21 17 PTE5 RGPIO5 22 18 PTB5 TPM1CH1 23 19 PTB4 TPM2CH1 MISO1 24 20 PTC3 RGPIO11 TPM3CH3 TPM3CH2 RGPIO6 SS1 25 21 PTC2 RGPIO10 26 22 PTD7 KBI2P7 27 23 PTD6 KBI2P6 28 24 PTD5 KBI2P5 29 — PTJ7 30 — PTJ6 31 — PTJ5 32 — PTJ4 33 25 PTC1 RGPIO9 TPM3CH1 34 26 PTC0 RGPIO8 TPM3CH0 35 27 PTF7 ADP17 36 28 PTF6 ADP16 37 29 PTF5 ADP15 38 30 PTF4 ADP14 39 31 PTB3 KBI1P7 MOSI11 40 32 PTB2 KBI1P6 SPSCK1 ADP7 ADP6 MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 7 Pin Assignments Table 2. MCF51QE128 Series Pin Assignment by Package and Pin Sharing Priority (continued) Pin Number Lowest ←⎯ Priority ⎯→ Highest Alt 3 Alt 4 80 64 Port Pin Alt 1 Alt 2 41 33 PTB1 KBI1P5 TxD1 ADP5 42 34 PTB0 KBI1P4 RxD1 ADP4 43 — PTJ3 44 — PTJ2 45 35 PTF3 46 36 PTF2 47 37 PTA7 TPM2CH2 ADP9 ADP8 ADP13 ADP12 48 38 PTA6 TPM1CH2 49 39 PTE4 RGPIO4 50 40 VDD 51 41 VSS 52 42 PTF1 ADP11 53 43 PTF0 ADP10 54 — PTJ1 55 — PTJ0 56 44 PTD4 KBI2P4 57 45 PTD3 KBI2P3 SS2 58 46 PTD2 KBI2P2 MISO2 59 47 PTA3 KBI1P3 SCL12 60 48 PTA2 KBI1P2 SDA1 61 49 PTA1 KBI1P1 TPM2CH0 ADP1 ACMP1- ADP0 ACMP1+ ADP3 ADP2 62 50 PTA0 KBI1P0 TPM1CH0 63 51 PTC7 RGPIO15 TxD2 ACMP2- 64 52 PTC6 RGPIO14 RxD2 ACMP2+ 65 — PTG7 ADP23 66 — PTG6 ADP22 67 — PTG5 ADP21 68 — PTG4 69 53 PTE3 RGPIO3 SS1 70 54 PTE2 RGPIO2 MISO1 71 55 PTG3 ADP19 72 56 PTG2 ADP18 73 57 PTG1 74 58 PTG0 75 59 PTE1 ADP20 RGPIO1 MOSI1 76 60 PTE0 RGPIO0 TPM2CLK 77 61 PTC5 RGPIO13 TPM3CH5 SPSCK1 78 62 PTC4 RGPIO12 TPM3CH4 RSTO 79 63 PTA5 IRQ TPM1CLK RESET 80 64 PTA43 ACMP1O BKGD MS ACMP2O MCF51QE128 Series Data Sheet, Rev. 7 8 Freescale Semiconductor Electrical Characteristics 1 SPI1 pins (SS1, MISO1, MOSI1, and SPSCK2) can be repositioned using SPI1PS in SOPT2. Default locations are PTB5, PTB4, PTB3, and PTB2. 2 IIC1 pins (SCL1 and SDA1) can be repositioned using IIC1PS in SOPT2. Default locations are PTA3 and PTA2, respectively. 3 The PTA4/ACMP1O/BKGD/MS is limited to output only for the port I/O function. 3 Electrical Characteristics 3.1 Introduction This section contains electrical and timing specifications for the MCF51QE128 series of microcontrollers available at the time of publication. 3.2 Parameter Classification The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate: Table 3. Parameter Classifications P Those parameters are guaranteed during production testing on each individual device. C Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations. T Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. All values shown in the typical column are within this category. D Those parameters are derived mainly from simulations. NOTE The classification is shown in the column labeled “C” in the parameter tables where appropriate. 3.3 Absolute Maximum Ratings Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the limits specified in Table 4 may affect device reliability or cause permanent damage to the device. For functional operating conditions, refer to the remaining tables in this section. This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled. MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 9 Electrical Characteristics Table 4. Absolute Maximum Ratings Rating Symbol Value Unit Supply voltage VDD –0.3 to +3.8 V Maximum current into VDD IDD 120 mA Digital input voltage VIn –0.3 to VDD + 0.3 V Instantaneous maximum current Single pin limit (applies to all port pins)1, 2, 3 ID ± 25 mA Tstg –55 to 150 °C Storage temperature range 1 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp voltages, then use the larger of the two resistance values. 2 All functional non-supply pins are internally clamped to VSS and VDD. 3 Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock rate is very low (which would reduce overall power consumption). 3.4 Thermal Characteristics This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small. Table 5. Thermal Characteristics Rating Symbol Value Unit Operating temperature range (packaged): MCF51QE64, MCF51QE96, and MCF51QE128: MCF51QE32: Maximum junction temperature –40 to 85 TA 0 to 70 TJM 95 °C °C Thermal resistance Single-layer board 64-pin LQFP 80-pin LQFP θJA 69 60 °C/W Thermal resistance Four-layer board 64-pin LQFP 80-pin LQFP θJA 50 47 °C/W MCF51QE128 Series Data Sheet, Rev. 7 10 Freescale Semiconductor Electrical Characteristics The average chip-junction temperature (TJ) in °C can be obtained from: TJ = TA + (PD × θJA) Eqn. 1 where: TA = Ambient temperature, °C θJA = Package thermal resistance, junction-to-ambient, °C/W PD = Pint + PI/O Pint = IDD × VDD, Watts — chip internal power PI/O = Power dissipation on input and output pins — user determined For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K ÷ (TJ + 273°C) Eqn. 2 Solving Equation 1 and Equation 2 for K gives: K = PD × (TA + 273°C) + θJA × (PD)2 Eqn. 3 where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively for any value of TA. 3.5 ESD Protection and Latch-Up Immunity Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits, normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage. All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed for the human body model (HBM), the machine model (MM) and the charge device model (CDM). A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 6. ESD and Latch-up Test Conditions Model Human Body Machine Description Symbol Value Unit Series resistance R1 1500 Ω Storage capacitance C 100 pF Number of pulses per pin — 3 Series resistance R1 0 Ω Storage capacitance C 200 pF Number of pulses per pin — 3 Minimum input voltage limit – 2.5 V Maximum input voltage limit 7.5 V Latch-up MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 11 Electrical Characteristics Table 7. ESD and Latch-Up Protection Characteristics Rating1 No. 1 3.6 Symbol Min Max Unit 1 Human body model (HBM) VHBM ± 2000 — V 2 Machine model (MM) VMM ± 200 — V 3 Charge device model (CDM) VCDM ± 500 — V 4 Latch-up current at TA = 85°C ILAT ± 100 — mA Parameter is achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted. DC Characteristics This section includes information about power supply requirements and I/O pin characteristics. Table 8. DC Characteristics Num C 1 Symbol Output high voltage P All I/O pins, low-drive strength 1.8 V, ILoad = –2 mA VOH C 4 D Output high current C Output low voltage P Max total IOH for all ports VOL C Output low current Max total IOL for all ports 5 D P Input high voltage C all digital inputs 6 P Input low voltage all digital inputs VIL C C Input hysteresis 9 P Input leakage current 10 P 11 P Max Unit 3.6 V — — 2.7 V, ILoad = –10 mA VDD – 0.5 — — 2.3 V, ILoad = –6 mA VDD – 0.5 — — 1.8V, ILoad = –3 mA VDD – 0.5 — — — — 100 1.8 V, ILoad = 2 mA — — 0.5 2.7 V, ILoad = 10 mA — — 0.5 2.3 V, ILoad = 6 mA — — 0.5 1.8 V, ILoad = 3 mA — — 0.5 — — 100 VDD > 2.7 V 0.70 x VDD — — VDD > 1.8 V 0.85 x VDD — — VDD > 2.7 V — — 0.35 x VDD VDD >1.8 V — — 0.30 x VDD 0.06 x VDD — — mV IOLT VIH 7 8 Typ1 VDD – 0.5 IOHT All I/O pins, low-drive strength All I/O pins, high-drive strength T Min 1.82 All I/O pins, high-drive strength T 3 Condition Operating Voltage C 2 Characteristic V mA V mA V all digital inputs Vhys all input only pins (Per pin) |IIn| VIn = VDD or VSS — — 1 μA Hi-Z (off-state) leakage current all input/output (per pin) |IOZ| VIn = VDD or VSS — — 1 μA Pull-up resistors all digital inputs, when enabled RPU 17.5 — 52.5 kΩ MCF51QE128 Series Data Sheet, Rev. 7 12 Freescale Semiconductor Electrical Characteristics Table 8. DC Characteristics (continued) Num C 12 1 2 3 4 5 6 Characteristic DC injection 3, 4, 5 D current Min Typ1 Max Unit –0.2 — 0.2 mA –5 — 5 mA CIn — — 8 pF Symbol Condition IIC VIN < VSS, VIN > VDD Single pin limit Total MCU limit, includes sum of all stressed pins 13 C Input Capacitance, all pins 14 C RAM retention voltage VRAM — 0.6 1.0 V 15 C POR re-arm voltage6 VPOR 0.9 1.4 1.79 V 16 D POR re-arm time tPOR 10 — — μs 17 P Low-voltage detection threshold — high range7 VLVDH8 VDD falling VDD rising 2.11 2.16 2.16 2.21 2.22 2.27 V 18 P Low-voltage detection threshold — low range7 VLVDL VDD falling VDD rising 1.80 1.86 1.82 1.90 1.91 1.99 V 19 P Low-voltage warning threshold — high range7 VLVWH VDD falling VDD rising 2.36 2.36 2.46 2.46 2.56 2.56 V 20 P Low-voltage warning threshold — low range7 VLVWL VDD falling VDD rising 2.11 2.16 2.16 2.21 2.22 2.27 V 21 C Low-voltage inhibit reset/recover hysteresis7 Vhys — 50 — mV 22 P Bandgap Voltage Reference9 VBG 1.15 1.17 1.18 V Typical values are measured at 25°C. Characterized, not tested As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL. All functional non-supply pins are internally clamped to VSS and VDD. Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two values. Power supply must maintain regulation within operating VDD range during instantaneous and operating maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would reduce overall power consumption). Maximum is highest voltage that POR is guaranteed. 7 Low voltage detection and warning limits measured at 1 MHz bus frequency. 8 Run at 1 MHz bus frequency Factory trimmed at VDD = 3.0 V, Temp = 25°C 9 MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 13 Electrical Characteristics PULL-UP RESISTOR (kΩ) 35 PULL-DOWN RESISTANCE (kΩ) PULL-UP RESISTOR TYPICALS 85°C 25°C –40°C 40 30 25 20 1.8 2 2.2 2.4 2.6 2.8 VDD (V) 3 3.2 3.4 3.6 PULL-DOWN RESISTOR TYPICALS 85°C 25°C –40°C 40 35 30 25 20 1.8 2.3 2.8 VDD (V) 3.3 3.6 Figure 4. Pull-up and Pull-down Typical Resistor Values TYPICAL VOL VS IOL AT VDD = 3.0 V 1.2 1 0.15 VOL (V) 0.8 VOL (V) TYPICAL VOL VS VDD 0.2 85°C 25°C –40°C 0.6 0.4 0.1 85°C, IOL = 2 mA 25°C, IOL = 2 mA –40°C, IOL = 2 mA 0.05 0.2 0 0 0 5 10 IOL (mA) 15 1 20 2 3 4 VDD (V) Figure 5. Typical Low-Side Driver (Sink) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VOL VS VDD TYPICAL VOL VS IOL AT VDD = 3.0 V 1 0.8 85°C 25°C –40°C 0.3 0.6 VOL (V) VOL (V) 0.4 85°C 25°C –40°C 0.4 0.2 0.2 0.1 0 0 IOL = 10 mA IOL = 6 mA IOL = 3 mA 0 10 20 30 1 2 3 4 VDD (V) IOL (mA) Figure 6. Typical Low-Side Driver (Sink) Characteristics — High Drive (PTxDSn = 1) MCF51QE128 Series Data Sheet, Rev. 7 14 Freescale Semiconductor Electrical Characteristics TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V TYPICAL VDD – VOH VS VDD AT SPEC IOH 0.25 85°C 25°C –40°C 1 VDD – VOH (V) VDD – VOH (V) 1.2 0.8 0.6 0.4 85°C, IOH = 2 mA 25°C, IOH = 2 mA –40°C, IOH = 2 mA 0.2 0.15 0.1 0.05 0.2 0 0 0 –5 –10 IOH (mA)) –15 –20 1 2 VDD (V) 3 4 Figure 7. Typical High-Side (Source) Characteristics — Low Drive (PTxDSn = 0) TYPICAL VDD – VOH VS VDD AT SPEC IOH TYPICAL VDD – VOH VS IOH AT VDD = 3.0 V 0.8 85°C 25°C –40°C 0.6 0.4 0.2 85°C 25°C –40°C 0.3 VDD – VOH (V) VDD – VOH (V) 0.4 0.2 IOH = –10 mA IOH = –6 mA 0.1 0 IOH = –3 mA 0 0 –5 –10 –15 –20 IOH (mA) –25 –30 1 2 3 4 VDD (V) Figure 8. Typical High-Side (Source) Characteristics — High Drive (PTxDSn = 1) 3.7 Supply Current Characteristics This section includes information about power supply current in various operating modes. Table 9. Supply Current Characteristics Num C P P 1 Parameter Symbol Run supply current FEI mode, all modules on T Bus Freq VDD (V) Max 32 35 –40 to 25 32 35 85 28.0 — RIDD 20 MHz 3 8 MHz 13.2 — T 1 MHz 2.4 — 25.165 MHz 28.1 29.6 22.9 — 8 MHz 11.3 — 1 MHz 2.0 — T Run supply current FEI mode, all modules off 2 T T Unit 25.165 MHz T C Temp (°C) Typ1 20 MHz RIDD 3 mA –40 to 85 mA –40 to 85 MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 15 Electrical Characteristics Table 9. Supply Current Characteristics (continued) Num C T Parameter Symbol RIDD T T C T Run supply current LPS=1, all modules off, running from Flash RIDD T T 11 13.7 4.57 — 8 MHz 2 — 1 MHz 0.73 — 0.6 0.8 -40 to 25 3.0 11 70 8.0 20 0.6 0.8 -40 to 25 2.5 10 70 6.0 12 85 0.8 1.3 -40 to 25 6.0 18 70 18.0 28 0.8 1.3 -40 to 25 5.0 16 70 12.0 20 85 3 Stop3 mode supply current No clocks active 3 P C μA n/a C 2 C 1 μA n/a C S3IDD –-40 to 85 — 3 2 7 mA 50 16 kHz FBELP C C –40 to 85 — P P μA 154 3 16 kHz FBELP 3 C –40 to 85 — C S2IDD μA 203 Stop2 mode supply current 6 Temp (°C) Max 20 MHz WIDD Unit Typ1 25.165 MHz Wait mode supply current FEI mode, all modules off 5 P VDD (V) 16 kHz FBILP Run supply current LPS=0, all modules off 3 4 Bus Freq 85 85 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Table 10. Stop Mode Adders Temperature (°C) Num C Parameter 1 T LPO 2 T ERREFSTEN 3 T IREFSTEN1 4 T RTC T LVD1 5 6 7 T T 1 ACMP 1 ADC Condition Units -40 25 70 85 50 75 100 150 nA 1000 1000 1100 1500 nA 63 70 77 81 uA does not include clock source current 50 75 100 150 nA LVDSE = 1 90 100 110 115 uA not using the bandgap (BGBE = 0) 18 20 22 23 uA ADLPC = ADLSMP = 1 not using the bandgap (BGBE = 0) 95 106 114 120 uA RANGE = HGO = 0 MCF51QE128 Series Data Sheet, Rev. 7 16 Freescale Semiconductor Electrical Characteristics 1 Not available in stop2 mode. 35 30 25 FEI: 24 MHz 20 IDD (mA) FBELP: 24 MHz FEI: 8 MHz FBELP: 8 MHz FEI: 1 MHz 15 FBELP: 1 MHz 10 5 0 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) Figure 9. Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled) MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 17 Electrical Characteristics 3.8 External Oscillator (XOSC) Characteristics Reference Figure 10 and Figure 11 for crystal or resonator circuits. Table 11. XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient) Num C Characteristic 1 Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1) Low range (RANGE = 0) C High range (RANGE = 1), high gain (HGO = 1) High range (RANGE = 1), low power (HGO = 0) 2 D 3 Feedback resistor Low range, low power (RANGE=0, HGO=0)2 D Low range, High Gain (RANGE=0, HGO=1) High range (RANGE=1, HGO=X) 4 Series resistor — Low range, low power (RANGE = 0, HGO = 0)2 Low range, high gain (RANGE = 0, HGO = 1) High range, low power (RANGE = 1, HGO = 0) D High range, high gain (RANGE = 1, HGO = 1) ≥ 8 MHz 4 MHz 1 MHz 5 6 Load capacitors Low range (RANGE=0), low power (HGO=0) Other oscillator settings Crystal start-up time 4 Low range, low power Low range, high power C High range, low power High range, high power D Symbol Min Typ1 Max Unit flo fhi fhi 32 1 1 — — — 38.4 16 8 kHz MHz MHz RF RS t CSTL t CSTH Square wave input clock frequency (EREFS = 0, ERCLKEN = 1) FEE or FBE mode FBELP mode See Note2 See Note3 C1,C2 fextal — — — — 10 1 — — — — — — — 0 100 — — — — — — 0 0 0 0 10 20 — — — — 200 400 5 15 — — — — ms 0.03125 0 — — 40.0 50.33 MHz MHz MΩ kΩ 1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. Load capacitors (C1,C2), feedback resistor (RF) and series resistor (RS) are incorporated internally when RANGE=HGO=0. 3 See crystal or resonator manufacturer’s recommendation. 4 Proper PC board layout procedures must be followed to achieve specifications. 2 MCF51QE128 Series Data Sheet, Rev. 7 18 Freescale Semiconductor Electrical Characteristics XOSC EXTAL XTAL RF RS Crystal or Resonator C1 C2 Figure 10. Typical Crystal or Resonator Circuit: High Range and Low Range/High Gain XOSC EXTAL XTAL Crystal or Resonator Figure 11. Typical Crystal or Resonator Circuit: Low Range/Low Gain 3.9 Internal Clock Source (ICS) Characteristics Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) Symbol Min Typ1 Max Unit Average internal reference frequency — factory trimmed at VDD = 3.6 V and temperature = 25°C fint_ft — 32.768 — kHz P Internal reference frequency — user trimmed fint_ut 31.25 — 39.06 kHz T Internal reference start-up time tIRST — 60 100 μs 16 — 20 32 — 40 High range (DRS=10) 48 — 60 Low range (DRS=00) — 19.92 — — 39.85 — — 59.77 — Num C 1 P 2 3 Characteristic P 4 P Low range (DRS=00) DCO output frequency range — trimmed 2 P P 5 P P DCO output frequency 2 Reference = 32768 Hz and DMX32 = 1 Mid range (DRS=01) Mid range (DRS=01) fdco_u fdco_DMX32 High range (DRS=10) MHz MHz 6 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (using FTRIM) Δfdco_res_t — ± 0.1 ± 0.2 %fdco 7 C Resolution of trimmed DCO output frequency at fixed voltage and temperature (not using FTRIM) Δfdco_res_t — ± 0.2 ± 0.4 %fdco MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 19 Electrical Characteristics Table 12. ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient) (continued) Symbol Min Typ1 Max Unit Total deviation of trimmed DCO output frequency over voltage and temperature Δfdco_t — + 0.5 -1.0 ±2 %fdco Total deviation of trimmed DCO output frequency over fixed voltage and temperature range of 0°C to 70 °C Δfdco_t — ± 0.5 ±1 %fdco tAcquire — — 1 ms CJitter — 0.02 0.2 %fdco Num C Characteristic 8 C 9 C 10 C FLL acquisition time 3 11 C Long term jitter of DCO output clock (averaged over 2-ms interval) 4 1 Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value. The resulting bus clock frequency should not exceed the maximum specified bus clock frequency of the device. 3 This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 4 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f Bus. Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given interval. 2 0.60% 0.40% 0.20% 0.00% % deviation -40 -20 0 20 40 60 80 100 120 -0.20% -0.40% -0.60% -0.80% -1.00% VDD Figure 12. Deviation of DCO Output Across Temperature at VDD = 3.0 V MCF51QE128 Series Data Sheet, Rev. 7 20 Freescale Semiconductor Electrical Characteristics 0.50% 0.40% 0.30% 0.20% % deviation 0.10% 0.00% 2.1V 2.4V 2.7V 3.0V 3.3V 3.6V -0.10% -0.20% -0.30% -0.40% -0.50% VDD Figure 13. Deviation of DCO Output Across VDD at 25°C 3.10 AC Characteristics This section describes timing characteristics for each peripheral system. 3.10.1 Control Timing Table 13. Control Timing Num C Rating 1 D Bus frequency (tcyc = 1/fBus) VDD ≥ 1.8V VDD > 2.1V VDD > 2.4V 2 D Internal low power oscillator period width2 Typ1 Max — — — 10 20 25.165 700 — 1300 μs textrst 100 — — ns Symbol Min fBus dc tLPO Unit MHz 3 D External reset pulse 4 D Reset low drive trstdrv 34 x tcyc — — ns 5 D BKGD/MS setup time after issuing background debug force reset to enter user or BDM modes tMSSU 500 — — ns 6 D BKGD/MS hold time after issuing background debug force reset to enter user or BDM modes 3 tMSH 100 — — μs MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 21 Electrical Characteristics Table 13. Control Timing (continued) Num C 7 D 8 D 9 10 Symbol Min Typ1 Max Unit IRQ pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 2 x tcyc — — — — ns Keyboard interrupt pulse width Asynchronous path2 Synchronous path4 tILIH, tIHIL 100 2 x tcyc — — — — ns Port rise and fall time — Low output drive (PTxDS = 0) (load = 50 pF)5 Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 8 31 — — Port rise and fall time — High output drive (PTxDS = 1) (load = 50 pF) Slew rate control disabled (PTxSE = 0) Slew rate control enabled (PTxSE = 1) tRise, tFall — — 7 24 — — — 4 — Rating ns C Voltage regulator recovery time tVRR ns μs 1 Typical values are based on characterization data at VDD = 3.0V, 25°C unless otherwise stated. This is the shortest pulse that is guaranteed to be recognized as a reset or interrupt pin request. Shorter pulses are not guaranteed to override reset requests from internal sources. 3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of t MSH after VDD rises above VLVD. 4 This is the minimum assertion time in which the interrupt may be recognized. The correct protocol is to assert the interrupt request until it is explicitly negated by the interrupt service routine. 5 Timing is shown with respect to 20% V DD and 80% VDD levels. Temperature range –40°C to 85°C. 2 textrst RESET PIN Figure 14. Reset Timing tIHIL KBIPx IRQ/KBIPx tILIH Figure 15. IRQ/KBIPx Timing MCF51QE128 Series Data Sheet, Rev. 7 22 Freescale Semiconductor Electrical Characteristics 3.10.2 TPM Module Timing Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. These synchronizers operate from the current bus rate clock. Table 14. TPM Input Timing No. C Function Symbol Min Max Unit 1 D External clock frequency fTCLK 0 fBus/4 Hz 2 D External clock period tTCLK 4 — tcyc 3 D External clock high time tclkh 1.5 — tcyc 4 D External clock low time tclkl 1.5 — tcyc 5 D Input capture pulse width tICPW 1.5 — tcyc tTCLK tclkh TCLK tclkl Figure 16. Timer External Clock tICPW TPMCHn TPMCHn tICPW Figure 17. Timer Input Capture Pulse MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 23 Electrical Characteristics 3.10.3 SPI Timing Table 15 and Figure 18 through Figure 21 describe the timing requirements for the SPI system. Table 15. SPI Timing No. C Function Symbol Min Max Unit — D Operating frequency Master Slave fBus/2048 0 fBus/2 fBus/4 Hz Hz 1 D SPSCK period Master Slave 2 4 2048 — tcyc tcyc D Enable lead time Master Slave tLead 2 1/2 1 — — tSPSCK tcyc D Enable lag time Master Slave tLag 3 1/2 1 — — tSPSCK tcyc 4 D Clock (SPSCK) high or low time Master Slave tcyc – 30 tcyc – 30 1024 tcyc — ns ns D Data setup time (inputs) Master Slave tSU 5 15 15 — — ns ns D Data hold time (inputs) Master Slave tHI 6 0 25 — — ns ns 7 D Slave access time ta — 1 tcyc 8 D Slave MISO disable time tdis — 1 tcyc 9 D Data valid (after SPSCK edge) Master Slave — — 25 25 ns ns 10 D Data hold time (outputs) Master Slave 0 0 — — ns ns 11 D Rise time Input Output tRI tRO — — tcyc – 25 25 ns ns 12 D Fall time Input Output tFI tFO — — tcyc – 25 25 ns ns fop tSPSCK tWSPSCK tv tHO MCF51QE128 Series Data Sheet, Rev. 7 24 Freescale Semiconductor Electrical Characteristics SS1 (OUTPUT) 2 11 1 SPSCK (CPOL = 0) (OUTPUT) 3 4 4 12 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN2 BIT 6 . . . 1 10 9 9 MOSI (OUTPUT) LSB IN MSB OUT2 BIT 6 . . . 1 LSB OUT NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 18. SPI Master Timing (CPHA = 0) SS(1) (OUTPUT) 1 2 12 11 11 12 3 SPSCK (CPOL = 0) (OUTPUT) 4 4 SPSCK (CPOL = 1) (OUTPUT) 5 MISO (INPUT) 6 MSB IN(2) 9 MOSI (OUTPUT) PORT DATA BIT 6 . . . 1 LSB IN 10 MASTER MSB OUT(2) BIT 6 . . . 1 MASTER LSB OUT PORT DATA NOTES: 1. SS output mode (DDS7 = 1, SSOE = 1). 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. Figure 19. SPI Master Timing (CPHA =1) MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 25 Electrical Characteristics SS (INPUT) 1 12 11 11 12 3 SPSCK (CPOL = 0) (INPUT) 2 4 4 SPSCK (CPOL = 1) (INPUT) 8 7 MISO (OUTPUT) 9 MSB OUT SLAVE BIT 6 . . . 1 SLAVE LSB OUT SEE NOTE 6 5 MOSI (INPUT) 10 10 BIT 6 . . . 1 MSB IN LSB IN NOTE: 1. Not defined but normally MSB of character just received Figure 20. SPI Slave Timing (CPHA = 0) SS (INPUT) 1 3 2 12 11 11 12 SPSCK (CPOL = 0) (INPUT) 4 4 SPSCK (CPOL = 1) (INPUT) 9 MISO (OUTPUT) SEE NOTE 7 MOSI (INPUT) SLAVE 8 10 MSB OUT 5 BIT 6 . . . 1 SLAVE LSB OUT 6 MSB IN BIT 6 . . . 1 LSB IN NOTE: 1. Not defined but normally LSB of character just received Figure 21. SPI Slave Timing (CPHA = 1) MCF51QE128 Series Data Sheet, Rev. 7 26 Freescale Semiconductor Electrical Characteristics 3.11 Analog Comparator (ACMP) Electricals Table 16. Analog Comparator Electrical Specifications C Characteristic Symbol Min Typical Max Unit VDD 1.80 — 3.6 V IDDAC — 20 35 μA VSS – 0.3 — VDD V 20 40 mV D Supply voltage C Supply current (active) D Analog input voltage VAIN C Analog input offset voltage VAIO C Analog comparator hysteresis VH 3.0 9.0 15.0 mV P Analog input leakage current IALKG — — 1.0 μA C Analog comparator initialization delay tAINIT — — 1.0 μs 3.12 ADC Characteristics Table 17. 12-bit ADC Operating Conditions C Characteristic Supply voltage D Conditions Absolute Delta to VDD (VDD-VDDAD)2 Min Typ1 Max Unit VDDAD 1.8 — 3.6 V ΔVDDAD -100 0 +100 mV ΔVSSAD -100 0 +100 mV D Ground voltage D Ref Voltage High VREFH 1.8 VDDAD VDDAD V D Ref Voltage Low VREFL VSSAD VSSAD VSSAD V D Input Voltage VADIN VREFL — VREFH V C Input Capacitance CADIN — 4.5 5.5 C Input Resistance RADIN — 5 7 — — — — 2 5 10 bit mode fADCK > 4MHz fADCK < 4MHz — — — — 5 10 8 bit mode (all valid fADCK) — — 10 0.4 — 8.0 0.4 — 4.0 Analog Source Resistance C D Delta to VSS (VSS-VSSAD)2 Symb 12 bit mode fADCK > 4MHz fADCK < 4MHz ADC Conversion High Speed (ADLPC=0) Clock Freq. Low Power (ADLPC=1) Comment pF kΩ External to MCU RAS kΩ fADCK MHz 1 Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 DC potential difference. MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 27 Electrical Characteristics SIMPLIFIED INPUT PIN EQUIVALENT ZADIN CIRCUIT SIMPLIFIED CHANNEL SELECT CIRCUIT Pad leakage due to input protection ZAS RAS RADIN ADC SAR ENGINE + VADIN VAS + – – CAS RADIN INPUT PIN RADIN INPUT PIN RADIN INPUT PIN CADIN Figure 22. ADC Input Impedance Equivalency Diagram Table 18. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) C Symb Min Typ1 Max Supply Current ADLPC=1 ADLSMP=1 ADCO=1 T IDDAD — 120 — Supply Current ADLPC=1 ADLSMP=0 ADCO=1 T Supply Current ADLPC=0 ADLSMP=1 ADCO=1 T Supply Current ADLPC=0 ADLSMP=0 ADCO=1 D Characteristic Conditions Unit Comment μA IDDAD — 202 — μA IDDAD — 288 — μA IDDAD — 0.532 1 mA Supply Current Stop, Reset, Module Off T IDDAD — 0.007 0.8 ADC Asynchronous Clock Source High Speed (ADLPC=0) P fADACK 2 3.3 5 Low Power (ADLPC=1) P 1.25 2 3.3 μA tADACK = 1/fADACK MHz MCF51QE128 Series Data Sheet, Rev. 7 28 Freescale Semiconductor Electrical Characteristics Table 18. 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) (continued) C Symb Min Typ1 Max Unit Comment P tADC — 20 — — 40 — ADCK cycles — 3.5 — — 23.5 — See the ADC chapter in the MCF51QE128 Reference Manual for conversion time variances — ±3.0 — P — ±1 ±2.5 8 bit mode T — ±0.5 ±1.0 12 bit mode T — ±1.75 — 10 bit mode3 P — ±0.5 ±1.0 8 bit mode3 T — ±0.3 ±0.5 12 bit mode T — ±1.5 — 10 bit mode T — ±0.5 ±1.0 8 bit mode T — ±0.3 ±0.5 — ±1.5 — Characteristic Conditions Conversion Time Short Sample (ADLSMP=0) (Including Long Sample (ADLSMP=1) sample time) Sample Time Short Sample (ADLSMP=0) P Long Sample (ADLSMP=1) C Total Unadjusted 12 bit mode Error 10 bit mode Differential Non-Linearity Integral Non-Linearity C T tADS ETUE DNL INL Zero-Scale Error 12 bit mode T 10 bit mode P — ±0.5 ±1.5 8 bit mode T — ±0.5 ±0.5 12 bit mode T — ±1.0 — 10 bit mode P — ±0.5 ±1 8 bit mode T — ±0.5 ±0.5 12 bit mode D — -1 to 0 — 10 bit mode — — ±0.5 8 bit mode — — ±0.5 — ±2 — 10 bit mode — ±0.2 ±4 8 bit mode — ±0.1 ±1.2 — 1.646 — — 1.769 — — 701.2 — Full-Scale Error Quantization Error Input Leakage Error 12 bit mode Temp Sensor Slope -40°C to 25°C Temp Sensor Voltage 25°C D D EZS EFS EQ EIL m 25°C to 85°C D VTEMP25 ADCK cycles LSB2 Includes Quantization LSB2 LSB2 LSB2 VADIN = VSSAD LSB2 VADIN = VDDAD LSB2 LSB2 Pad leakage4 * RAS mV/°C mV 1 Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only and are not tested in production. 2 1 LSB = (V N REFH - VREFL)/2 3 Monotonicity and No-Missing-Codes guaranteed in 10 bit and 8 bit modes 4 Based on input pad leakage current. Refer to pad electricals. MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 29 Electrical Characteristics 3.13 Flash Specifications This section provides details about program/erase times and program-erase endurance for the flash memory. Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed information about program/erase operations, see the Memory section of the MCF51QE128 Reference Manual. Table 19. Flash Characteristics C Characteristic Symbol Min Typical Max Unit D Supply voltage for program/erase -40°C to 85°C Vprog/erase 1.8 3.6 V D Supply voltage for read operation VRead 1.8 3.6 V fFCLK 150 200 kHz tFcyc 5 6.67 μs frequency1 D Internal FCLK D Internal FCLK period (1/FCLK) P Longword program time (random location)(2) mode)(2) tprog 9 tFcyc P Longword program time (burst tBurst 4 tFcyc P Page erase time2 tPage 4000 tFcyc Mass erase time(2) tMass 20,000 tFcyc P Longword program current3 Page erase current 3 RIDDBP — 9.7 — mA RIDDPE — 7.6 — mA 10,000 — — 100,000 — — cycles 15 100 — years endurance4 C Program/erase TL to TH = –40°C to + 85°C T = 25°C C Data retention5 tD_ret 1 The frequency of this clock is controlled by a software setting. These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for calculating approximate time to program and erase. 3 The program and erase currents are additional to the standard run IDD. These values are measured at room temperatures with VDD = 3.0 V, bus frequency = 4.0 MHz. 4 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory. 5 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory. 2 MCF51QE128 Series Data Sheet, Rev. 7 30 Freescale Semiconductor Ordering Information 4 Ordering Information This section contains ordering information for MCF51QE128MCF51QE96, and MCF51QE64 devices. Table 20. Ordering Information Memory Freescale Part Number1 Temperature range (°C) Flash MCF51QE128CLK 128K 8K -40 to +85 80 LQFP 128K 8K -40 to +85 64 LQFP 96K 8K MCF51QE96CLK 2 RAM MCF51QE128CLH MCF51QE96CLH 1 Package2 -40 to +85 80 LQFP -40 to +85 64 LQFP MCF51QE64CLH 64K 8K -40 to +85 64 LQFP MCF51QE32CLH 32K 8K -40 to +85 64 LQFP MCF51QE32LH 32K 8K 0 to +70 64 LQFP See the reference manual, MCF51QE128RM, for a complete description of modules included on each device. See Table 21 for package information. 5 Package Information The below table details the various packages available. Table 21. Package Descriptions Pin Count 5.1 Package Type Abbreviation Designator Case No. Document No. 80 Low Quad Flat Package LQFP LK 917A 98ASS23237W 64 Low Quad Flat Package LQFP LH 840F 98ASS23234W Mechanical Drawings The following pages are mechanical drawings for the packages described in Table 21. For the latest available drawings please visit our web site (http://www.freescale.com) and enter the package’s document number into the keyword search box. MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 31 Package Information 4X –X– 4X 20 TIPS 0.20 (0.008) H L–M N X= L, M, N 0.20 (0.008) T L–M N 80 61 1 P CL 60 AB AB G –M– VIEW Y B –L– 3X VIEW Y B1 V PLATING J V1 41 20 21 0.13 (0.005) A1 U T L–M S N S ROTATED 90 CLOCKWISE A S C 8X 2 0.10 (0.004) T –H– –T– SEATING PLANE VIEW AA (W) C2 S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE –H– IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS –L–, –M– AND –N– TO BE DETERMINED AT DATUM PLANE –H–. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE –T–. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE –H–. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.460 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). 1 2X R R1 0.25 (0.010) GAGE PLANE (K) C1 E (Z) VIEW AA DATE 09/21/95 M BASE METAL SECTION AB–AB S1 0.05 (0.002) ÇÇÇ ÍÍÍÍ ÍÍÍÍ ÇÇÇ D 40 –N– F CASE 917A-02 ISSUE C DIM A A1 B B1 C C1 C2 D E F G J K P R1 S S1 U V V1 W Z 0 01 02 MILLIMETERS MIN MAX 14.00 BSC 7.00 BSC 14.00 BSC 7.00 BSC ––– 1.60 0.04 0.24 1.30 1.50 0.22 0.38 0.40 0.75 0.17 0.33 0.65 BSC 0.09 0.27 0.50 REF 0.325 BSC 0.10 0.20 16.00 BSC 8.00 BSC 0.09 0.16 16.00 BSC 8.00 BSC 0.20 REF 1.00 REF 0 10 0 ––– 9 14 INCHES MIN MAX 0.551 BSC 0.276 BSC 0.551 BSC 0.276 BSC ––– 0.063 0.002 0.009 0.051 0.059 0.009 0.015 0.016 0.030 0.007 0.013 0.026 BSC 0.004 0.011 0.020 REF 0.013 REF 0.004 0.008 0.630 BSC 0.315 BSC 0.004 0.006 0.630 BSC 0.315 BSC 0.008 REF 0.039 REF 0 10 0 ––– 9 14 Figure 23. 80-pin LQFP Package Drawing (Case 917A, Doc #98ASS23237W) MCF51QE128 Series Data Sheet, Rev. 7 32 Freescale Semiconductor Package Information Figure 24. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 1 of 3 MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 33 Package Information Figure 25. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 2 of 3 MCF51QE128 Series Data Sheet, Rev. 7 34 Freescale Semiconductor Package Information Figure 26. 64-pin LQFP Package Drawing (Case 840F, Doc #98ASS23234W), Sheet 3 of 3 MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 35 Product Documentation 6 Product Documentation Find the most current versions of all documents at: http://www.freescale.com Reference Manual (MCF51QE128RM) Contains extensive product information including modes of operation, memory, resets and interrupts, register definition, port pins, CPU, and all module information. 7 Revision History To provide the most up-to-date information, the revision of our documents on the World Wide Web are the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://www.freescale.com The following revision history table summarizes changes contained in this document. Table 22. Revision History Revision 3 4 Date Description of Changes 25 Jun 2007 Table 8: Changed Condition entires in specs #6 (VIH) and #7 (VIL) from VDD ≥ 1.8V to VDD > 2.7V and VDD ≤ 1.8V to VDD > 1.8V. Table 8: Changed VDD rising and VDD falling min/typ/max specs in row #19 (Low-voltage warning threshold—high range) from 2.35, 2.40, and 2.50 to 2.36, 2.46, and 2.56 respectively. 17 Sep 2007 Added information about the MCF51QE32 device. Changed the SRAM size for the MCF51QE64 device (was 4 Kbytes, is 8 Kbytes). Corrected the number of ADC channels for the MCF51QE64 device (was 22, is 20). Corrected the number of ADC channels for the 64-pin package of the MCF51QE64 device (was 22, is 20). Changed ACMP electricals, VAIO specification’s test category from P to C. 5 6 7 28 May 2008 Updated the tables Thermal Characteristics, DC Characteristics, Supply Current Characteristics, XOSC and ICS Specifications (Temperature Range = –40 to 85°C Ambient), ICS Frequency Specifications (Temperature Range = –40 to 85°C Ambient), Control Timing, and Analog Comparator Electrical Specifications, 12-bit ADC Characteristics (VREFH = VDDAD, VREFL = VSSAD) Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD (ACMP and ADC off, All Other Modules Enabled), Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 3.0 V), and Deviation of DCO Output from Trimmed Frequency (50.33 MHz, 25°C) 24 Jun 2008 Updated the table Thermal Characteristics Updated the row corresponding to Num 18 in the table DC Characteristics Updated the tables MCF51QE128 Series Features by MCU and Package, DC Characteristics, Supply Current Characteristics, Thermal Characteristics, Control Timing, and Ordering Information Updated the figures Typical Run IDD for FBE and FEI, IDD vs. VDD (ADC off, All Other Modules Enabled), Deviation of DCO Output Across Temperature at VDD = 3.0 V, and Deviation of DCO Output Across VDD at 25×C 14 Oct 2008 Updated the Stop2 and Stop3 mode supply current in the Supply Current Characteristics table. Replaced the stop mode adders section from the Supply Current Characteristics with its own Stop Mode Adders table with new specifications. MCF51QE128 Series Data Sheet, Rev. 7 36 Freescale Semiconductor Revision History MCF51QE128 Series Data Sheet, Rev. 7 Freescale Semiconductor 37 How to Reach Us: Home Page: www.freescale.com E-mail: [email protected] USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 [email protected] Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 [email protected] Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics as their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale’s Environmental Products program, go to http://www.freescale.com/epp. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008. All rights reserved. For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 [email protected] Document Number: MCF51QE128 Rev. 7 10/2008