CMOS Single-Supply, Rail-to-Rail Input/Output Operational Amplifiers with Shutdown AD8591/AD8592/AD8594 FEATURES PIN CONFIGURATIONS Single-supply operation: 2.5 V to 6 V High output current: ±250 mA Extremely low shutdown supply current: 100 nA Low supply current: 750 μA/Amp Wide bandwidth: 3 MHz Slew rate: 5 V/μs No phase reversal Very low input bias current High impedance outputs when in shutdown mode Unity-gain stable OUT A 1 6 5 SD TOP VIEW (Not to Scale) +IN A 3 4 Figure 1. 6-Lead SOT-23 (RJ Suffix) OUT A 1 10 V+ –IN A 2 AD8592 9 +IN A 3 TOP VIEW (Not to Scale) 8 –IN B 7 +IN B 6 SDB Figure 2. 10-Lead MSOP (RM Suffix) OUT A 1 16 OUT D –IN A 2 +IN A 3 V+ 4 15 –IN D AD8594 14 +IN D 13 V– TOP VIEW +IN B 5 (Not to Scale) 12 +IN C –IN B 6 11 –IN C OUT B 7 NC 8 9 SD The AD8591, AD8592, and AD8594 are single, dual, and quad rail-to-rail, input and output single-supply amplifiers featuring 250 mA output drive current and a power saving shutdown mode. The AD8592 includes an independent shutdown function for each amplifier. When both amplifiers are in shutdown mode, the total supply current is reduced to less than 1 μA. The AD8591 and AD8594 include a single master shutdown function that reduces the total supply current to less than 1 μA. All amplifier outputs are in a high impedance state when in shutdown mode. These amplifiers have very low input bias currents, making them suitable for integrators and diode amplification. Outputs are stable with virtually any capacitive load. Supply current is less than 750 μA per amplifier in active mode. Applications for these amplifiers include audio amplification for portable computers, portable phone headsets, sound ports, sound cards, and set-top boxes. The AD859x family is capable of driving heavy capacitive loads, such as LCD panel reference levels. The ability to swing rail to rail at both the input and output enables designers to buffer CMOS DACs, ASICs, and other wide output swing devices in single-supply systems. 01106-003 10 OUT C NC = NO CONNECT GENERAL DESCRIPTION 01106-002 V– 4 OUT B Figure 3. 16-Lead Narrow SOIC (R Suffix) 16 OUT D OUT A 1 –IN A 15 –IN D 2 +IN A 3 AD8594 TOP VIEW (Not to Scale) V+ 4 14 +IN D 13 V– +IN B 5 –IN B 6 11 –IN C OUT B 7 10 OUT C NC 8 12 +IN C 9 SD NC = NO CONNECT 01106-004 Mobile communication handset audio PC audio PCMCIA/modem line driving Battery-powered instrumentation Data acquisition ASIC input or output amplifiers LCD display reference level drivers –IN A 01106-001 V– 2 SDA 5 APPLICATIONS V+ AD8591 Figure 4. 16-Lead TSSOP (RU Suffix) The AD8591, AD8592, and AD8594 are specified over the industrial temperature range (−40°C to +85°C). The AD8591, single, is available in the tiny 6-lead SOT-23 package. The AD8592, dual, is available in the 10-lead surface-mount MSOP package. The AD8594, quad, is available in 16-lead narrow SOIC and 16-lead TSSOP packages. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. AD8591/AD8592/AD8594 TABLE OF CONTENTS Features .............................................................................................. 1 Output Short-Circuit Protection .............................................. 11 Applications ....................................................................................... 1 Power Dissipation....................................................................... 11 General Description ......................................................................... 1 Capacitive Loading..................................................................... 12 Pin Configurations ........................................................................... 1 PC98-Compliant Headphone/Speaker Amplifier .................. 12 Revision History ............................................................................... 2 Specifications..................................................................................... 3 A Combined Microphone and Speaker Amplifier for Cellphone and Portable Headsets ............................................ 13 Electrical Characteristics ............................................................. 3 An Inexpensive Sample-and-Hold Circuit ............................. 13 Absolute Maximum Ratings............................................................ 5 Direct Access Arrangement for PCMCIA Modems (Telephone Line Interface) ........................................................ 14 Thermal Resistance ...................................................................... 5 ESD Caution .................................................................................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ...................................................................... 11 Single-Supply Differential Line Driver .................................... 14 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 16 Input Voltage Protection............................................................ 11 Output Phase Reversal ............................................................... 11 REVISION HISTORY 1/09—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Deleted Spice Model for AD8591/AD8592/AD8594 Amplifiers Sections ............................................................................................ 12 Changes to PC98-Compliant Headphone/Speaker Amplifier Section and Figure 38 ..................................................................... 12 Changes to Figure 39 ...................................................................... 13 Changes to Figure 42 and Figure 43 ............................................. 14 Updated Outline Dimensions ....................................................... 15 Changes to Ordering Guide .......................................................... 16 Rev. B | Page 2 of 16 AD8591/AD8592/AD8594 SPECIFICATIONS ELECTRICAL CHARACTERISTICS VS = 2.7 V, VCM = 1.35 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Test Conditions Min Typ VOS −40°C < TA < +85°C Input Bias Current IB 5 −40°C < TA < +85°C Input Offset Current IOS 1 −40°C < TA < +85°C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier Supply Current Shutdown Mode SHUTDOWN INPUTS Logic High Voltage Logic Low Voltage Logic Input Current DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density CMRR AVO ΔVOS/ΔT ΔIB/ΔT ΔIOS/ΔT VCM = 0 V to 2.7 V RL = 2 kΩ, VO = 0.3 V to 2.4 V −40°C < TA < +85°C −40°C < TA < +85°C −40°C < TA < +85°C VOH IL = 10 mA −40°C to +85°C IL = 10 mA −40°C to +85°C VOL IOUT ZOUT PSRR ISY 0 38 2.55 2.5 25 30 50 60 25 30 2.7 mV mV pA pA pA pA V dB V/mV μV/°C fA/°C fA/°C 2.61 100 125 ±250 60 f = 1 MHz, AV = 1 45 ISD1 ISD2 VINH VINL IIN −40°C < TA < +85°C −40°C < TA < +85°C −40°C < TA < +85°C 1.6 SR tS GBP Φo CS RL = 2 kΩ To 0.01% en in Unit 45 25 20 50 20 60 VS = 2.5 V to 6 V VO = 0 V −40°C < TA < +85°C All amplifiers shut down −40°C < TA < +85°C Amplifier 1 shut down (AD8592) Amplifier 2 shut down (AD8592) ISD Max 55 0.1 V V mV mV mA Ω 1 1.25 1 1 1.4 1.4 dB mA mA μA μA mA mA 0.5 1 V V μA f = 1 kHz, RL = 2 kΩ 3.5 1.4 2.2 67 65 V/μs μs MHz Degrees dB f = 1 kHz f = 10 kHz f = 1 kHz 45 30 0.05 nV/√Hz nV/√Hz pA/√Hz Rev. B | Page 3 of 16 AD8591/AD8592/AD8594 VS = 5.0 V, VCM = 2.5 V, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Test Conditions Min VOS Typ Max Unit 2 25 30 50 60 25 30 5 mV mV pA pA pA pA V dB V/mV μV/°C fA/°C fA/°C −40°C < TA < +85°C Input Bias Current IB 5 −40°C < TA < +85°C Input Offset Current IOS 1 −40°C < TA < +85°C Input Voltage Range Common-Mode Rejection Ratio Large Signal Voltage Gain Offset Voltage Drift Bias Current Drift Offset Current Drift OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Output Current Open-Loop Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier Supply Current Shutdown Mode SHUTDOWN INPUTS Logic High Voltage Logic Low Voltage Logic Input Current DYNAMIC PERFORMANCE Slew Rate Full Power Bandwidth Settling Time Gain Bandwidth Product Phase Margin Channel Separation NOISE PERFORMANCE Voltage Noise Density Current Noise Density CMRR AVO ΔVOS/ΔT ΔIB/ΔT ΔIOS/ΔT VCM = 0 V to 5 V RL = 2 kΩ, VO = 0.5 V to 4.5 V −40°C < TA < +85°C −40°C < TA < +85°C −40°C < TA < +85°C VOH IL = 10 mA −40°C to +85°C IL = 10 mA −40°C to +85°C VOL IOUT ZOUT PSRR ISY 0 38 15 4.9 4.85 100 125 ±250 40 f = 1 MHz, AV = 1 45 ISD1 ISD2 VINH VINL IIN −40°C < TA < +85°C −40°C < TA < +85°C −40°C < TA < +85°C 2.4 SR BWP tS GBP Φo CS RL = 2 kΩ 1% distortion To 0.01% en in 4.94 50 VS = 2.5 V to 6 V VO = 0 V −40°C < TA < +85°C All amplifiers shut down −40°C < TA < +85°C Amplifier 1 shut down (AD8592) Amplifier 2 shut down (AD8592) ISD 47 30 20 50 20 55 0.1 V V mV mV mA Ω 1.25 1.75 1 1 1.6 1.6 dB mA mA μA μA mA mA 0.8 1 V V μA f = 1 kHz, RL = 10 kΩ 5 325 1.6 3 70 65 V/μs kHz μs MHz Degrees dB f = 1 kHz f = 10 kHz f = 1 kHz 45 30 0.05 nV/√Hz nV/√Hz pA/√Hz Rev. B | Page 4 of 16 AD8591/AD8592/AD8594 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 3. Parameter Supply Voltage Input Voltage Differential Input Voltage Output Short-Circuit Duration to GND1 Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) 1 Rating 6V GND to VS ±6 V Observe Derating Curves −65°C to +150°C −40°C to +85°C −65°C to +150°C 300°C For supplies less than ±5 V, the differential input voltage is limited to the supplies. θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Package Type 6-Lead SOT-23 (RJ) 10-Lead MSOP (RM) 16-Lead SOIC (R) 16-Lead TSSOP (RU) ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 5 of 16 θJA 230 200 120 180 θJC 92 44 36 35 Unit °C/W °C/W °C/W °C/W AD8591/AD8592/AD8594 TYPICAL PERFORMANCE CHARACTERISTICS 0.8 100 SOURCE 10 SINK 1 0.1 1 10 100 1k LOAD CURRENT (mA) 0.3 0.2 0.1 1.25 2.25 2.75 3.00 –2 VS = 5V VCM = 2.5V SINK SOURCE 10 1 10 100 1k LOAD CURRENT (mA) –4 –5 –6 –7 –8 –50 01106-006 0.1 –3 –35 –15 5 25 45 65 85 01106-009 INPUT OFFSET VOLTAGE (mV) 100 1 85 TEMPERATURE (°C) Figure 6. Output Voltage to Supply Rail vs. Load Current Figure 9. Input Offset Voltage vs. Temperature 8 0.90 VS = 2.7V, 5V VCM = VS/2 0.85 7 INPUT BIAS CURRENT (pA) 0.80 0.75 VS = 5V 0.70 0.65 0.60 VS = 2.7V 0.50 –40 –20 0 20 6 5 4 3 0.55 40 60 80 TEMPERATURE (°C) 100 01106-007 SUPPLY CURRENT/AMPLIFIER (mA) 1.75 Figure 8. Supply Current per Amplifier vs. Supply Voltage 1k ΔOUTPUT VOLTAGE (mV) 0.4 SUPPLY VOLTAGE (±V) VS = 5V TA = 25°C 0.1 0.01 0.5 0 0.75 Figure 5. Output Voltage to Supply Rail vs. Load Current 10k 0.6 01106-010 0.1 0.01 TA = 25°C 0.7 01106-008 SUPPLY CURRENT/AMPLIFIER (mA) VS = 2.7V TA = 25°C 01106-005 ΔOUTPUT VOLTAGE (mV) 1k 2 –50 –35 –15 5 25 45 65 TEMPERATURE (°C) Figure 10. Input Bias Current vs. Temperature Figure 7. Supply Current per Amplifier vs. Temperature Rev. B | Page 6 of 16 AD8591/AD8592/AD8594 VS = 2.7V, 5V VCM = VS/2 60 3 INPUT OFFSET CURRENT (pA) VS = 5V RL = NO LOAD TA = 25°C 45 40 90 20 135 0 180 GAIN (dB) 2 1 0 PHASE SHIFT (Degrees) 80 4 –1 –15 5 25 45 65 85 TEMPERATURE (°C) 1k 100k 1M 100M Figure 14. Open-Loop Gain and Phase vs. Frequency 5 VS = 5V TA = 25°C VS = 2.7V RL = 2kΩ TA = 25°C VIN = 2.5V p-p 7 4 INPUT BIAS CURRENT (pA) 10M FREQUENCY (Hz) Figure 11. Input Offset Current vs. Temperature 8 10k 01106-014 –35 01106-011 –2 –50 OUTPUT SWING (V p-p) 6 5 4 3 3 2 1 1 2 3 4 5 COMMON-MODE VOLTAGE (V) 0 1k VS = 2.7V RL = NO LOAD TA = 25°C 60 100k VS = 5V RL = 2kΩ TA = 25°C VIN = 2.5V p-p 45 0 180 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) OUTPUT SWING (V p-p) 135 PHASE SHIFT (Degrees) 20 3 2 1 01106-013 GAIN (dB) 4 90 10M Figure 15. Closed-Loop Output Voltage Swing vs. Frequency 5 40 1M FREQUENCY (Hz) Figure 12. Input Bias Current vs. Common-Mode Voltage 80 10k 0 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 16. Closed-Loop Output Voltage Swing vs. Frequency Figure 13. Open-Loop Gain and Phase vs. Frequency Rev. B | Page 7 of 16 01106-017 0 01106-012 1 01106-016 2 AD8591/AD8592/AD8594 140 VS = 5V TA = 25°C AV = 10 100 80 120 60 PSRR (dB) 140 100 80 AV = 1 20 0 –20 20 –40 100k 1M 10M 100M FREQUENCY (Hz) –60 100 110 60 SMALL SIGNAL OVERSHOOT (%) 100 CMRR (dB) 90 80 70 100k 1M 10M FREQUENCY (Hz) 50 SMALL SIGNAL OVERSHOOT (%) +PSRR 40 –PSRR 0 –20 20 10 100 1k 10k 50 10k VS = 5V RL = 2kΩ TA = 25°C 40 –OS +OS 30 20 10 –40 –60 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 01106-020 PSRR (dB) –OS 30 60 80 20 +OS Figure 21. Small Signal Overshoot vs. Load Capacitance 100 60 10M CAPACITANCE (pF) VS = 2.5V TA = 25°C 120 1M 40 Figure 18. Common-Mode Rejection Ratio vs. Frequency 140 100k VS = 2.5V RL = 2kΩ TA = 25°C 0 10 01106-019 60 10k 10k Figure 20. Power Supply Rejection Ratio vs. Frequency VS = 5V TA = 25°C 1k 1k FREQUENCY (Hz) Figure 17. Closed-Loop Output Impedance vs. Frequency 50 +PSRR 40 40 10k –PSRR 01106-021 60 01106-018 IMPEDANCE (Ω) 160 0 1k VS = 5V TA = 25°C 120 01106-022 180 01106-023 200 Figure 19. Power Supply Rejection Ratio vs. Frequency 0 10 100 1k CAPACITANCE (pF) Figure 22. Small Signal Overshoot vs. Load Capacitance Rev. B | Page 8 of 16 AD8591/AD8592/AD8594 VS = ±2.5V AV = +1 RL = 2kΩ TA = 25°C 100 20mV/DIV 90 VS = ±1.35V VIN = ±50mV AV = +1 RL = 2kΩ CL = 300pF TA = 25°C 0V 10 01106-024 500mV 500 ns/DIV 01106-027 0 500ns Figure 26. Large Signal Transient Response Figure 23. Small Signal Transient Response 1V 10µs 100 VS = ±2.5V VIN = ±50mV AV = +1 RL = 2kΩ CL = 300pF TA = 25°C 0V 10 0 Figure 24. Small Signal Transient Response 0 500ns VS = 5V TA = 25°C 0.1 0.01 10 100 1k 10k FREQUENCY (Hz) Figure 28. Current Noise Density vs. Frequency Figure 25. Large Signal Transient Response Rev. B | Page 9 of 16 100k 01106-029 10 CURRENT NOISE DENSITY (pA/√Hz) 1 90 500mV 01106-028 Figure 27. No Phase Reversal VS = ±1.35V AV = +1 RL = 2kΩ TA = 25°C 100 VS = ±2.5V AV = +1 TA = +25°C 1V 01106-025 500 ns/DIV 01106-026 20mV/DIV 90 AD8591/AD8592/AD8594 100 600 VS = 5V AV = +1000 TA = 25°C FREQUENCY = 1kHz VS = 2.7V VCM = 1.35V TA = 25°C 500 100µV/DIV QUANTITY (Amplifiers) 90 10 0 400 300 200 –12 –10 –8 –6 –4 –2 0 2 4 6 01106-032 0 –14 MARKER 41µV/√Hz 6 01106-033 01106-030 100 INPUT OFFSET VOLTAGE (mV) Figure 29. Voltage Noise Density vs. Frequency 100 Figure 31. Input Offset Voltage Distribution 600 VS = 5V AV = +1000 TA = 25°C FREQUENCY = 10kHz VS = 5V VCM = 2.5V TA = 25°C 500 200µV/DIV QUANTITY (Amplifiers) 90 10 400 300 200 0 01106-031 100 0 –14 MARKER 25.9 µV/√Hz –12 –10 –8 –6 –4 –2 0 2 INPUT OFFSET VOLTAGE (mV) Figure 30. Voltage Noise Density vs. Frequency Figure 32. Input Offset Voltage Distribution Rev. B | Page 10 of 16 4 AD8591/AD8592/AD8594 THEORY OF OPERATION The AD859x amplifiers are CMOS, high output drive, rail-torail input and output single-supply amplifiers designed for low cost and high output current drive. The parts include a power saving shutdown function that makes the AD8591/AD8592/ AD8594 op amps ideal for portable multimedia and telecommunications applications. OUTPUT PHASE REVERSAL Figure 33 shows the simplified schematic for the AD8591/AD8592/ AD8594 amplifiers. Two input differential pairs, consisting of an n-channel pair (M1, M2) and a p-channel pair (M3, M4), provide a rail-to-rail input common-mode range. The outputs of the input differential pairs are combined in a compound foldedcascode stage that drives the input to a second differential pair gain stage. The outputs of the second gain stage provide the gate voltage drive to the rail-to-rail output stage. The rail-to-rail output stage consists of M15 and M16, which are configured in a complementary common source configuration. As with any rail-to-rail output amplifier, the gain of the output stage, and thus the open-loop gain of the amplifier, is dependent on the load resistance. In addition, the maximum output voltage swing is directly proportional to the load current. The difference between the maximum output voltage to the supply rails, known as the dropout voltage, is determined by the on-channel resistance of the AD8591/AD8592/AD8594 output transistors. The output dropout voltage is given in Figure 5 and Figure 6. 100µA 50µA * M337 M5 M3 M12 M30 M4 M15 IN– OUT M2 M6 M9 20µA INV M340 * 50µA M7 M10 V– *ALL CURRENT SOURCES GO TO 0µA IN SHUTDOWN MODE. (2) +5V * AD8592 M13 M31 Although not shown in the simplified schematic, ESD protection diodes are connected from each input to each power supply rail. These diodes are normally reverse-biased, but turn on if either input voltage exceeds either supply rail by more than 0.6 V. If this condition occurs, limit the input current to less than ±5 mA. This is done by placing a resistor in series with the input(s). The minimum resistor value should be 5 mA VSY 250 mA VIN INPUT VOLTAGE PROTECTION VIN , MAX RX ≥ M14 Figure 33. Simplified Schematic RIN ≥ By placing a resistor in series with the output of the amplifier, as shown in Figure 34, the output current can be limited. The minimum value for RX is RX 20Ω VOUT 01106-035 VB3 To achieve high output current drive and rail-to-rail performance, the outputs of the AD859x family do not have internal shortcircuit protection circuitry. Although these amplifiers are designed to sink or source as much as 250 mA of output current, shorting the output directly to the positive supply could damage or destroy the device. To protect the output stage, limit the maximum output current to ±250 mA. M16 01106-034 IN+ OUTPUT SHORT-CIRCUIT PROTECTION For a 5 V single-supply application, RX should be at least 20 Ω. Because RX is inside the feedback loop, VOUT is not affected. The trade-off in using RX is a slight reduction in output voltage swing under heavy output current loads. RX also increases the effective output impedance of the amplifier to RO + RX, where RO is the output impedance of the device. 20µA M8 VB2 M1 * * 100µA M11 INV The technique recommended in the Input Voltage Protection section should be applied in applications where the possibility of input voltages exceeding the supply voltages exists. V+ * SD The AD8591/AD8592/AD8594 are immune to output voltage phase reversal with an input voltage within the supply voltages of the device. However, if either of the inputs of the device exceeds 0.6 V outside of the supply rails, the output could exhibit phase reversal. This is due to the ESD protection diodes becoming forward-biased, thus causing the polarity of the input terminals of the device to switch. (1) Figure 34. Output Short-Circuit Protection POWER DISSIPATION Although the AD859x amplifiers are able to provide load currents of up to 250 mA, proper attention should be given to not exceeding the maximum junction temperature for the device. The junction temperature equation is TJ = PDISS × θJA + TA (3) where: TJ is the AD859x junction temperature. PDISS is the AD859x power dissipation. θJA is the AD859x junction-to-ambient thermal resistance of the package. TA is the ambient temperature of the circuit. Rev. B | Page 11 of 16 AD8591/AD8592/AD8594 In any application, the absolute maximum junction temperature must be limited to 150°C. If the junction temperature is exceeded, the device could suffer premature failure. If the output voltage and output current are in phase, for example, with a purely resistive load, the power dissipated by the AD859x can be found as PDISS = ILOAD × (VSY − VOUT) 47nF LOAD ONLY (4) where: ILOAD is the AD859x output load current. VSY is the AD859x supply voltage. VOUT is the output voltage. CAPACITIVE LOADING The AD859x exhibits excellent capacitive load driving capabilities and can drive to 10 nF directly. Although the device is stable with large capacitive loads, there is a decrease in amplifier bandwidth as the capacitive load increases. Figure 35 shows a graph of the AD8592 unity-gain bandwidth under various capacitive loads. 4.0 VS = ±2.5V RL = 1kΩ TA = 25°C 3.5 3.0 50mV 10µs 01106-038 SNUBBER IN CIRCUIT By calculating the power dissipation of the device and using the thermal resistance value for a given package type, the maximum allowable ambient temperature for an application can be found using Equation 3. Figure 37. Snubber Network Reduces Overshoot and Ringing Caused by Driving Heavy Capacitive Loads The optimum values for the snubber network should be determined empirically based on the size of the capacitive load. Table 5 shows a few sample snubber network values for a given load capacitance. Table 5. Snubber Networks for Large Capacitive Loads Snubber Network RS (Ω) CS (μF) 300 0.1 30 1 5 1 Load Capacitance, CL (nF) 0.47 4.7 47 PC98-COMPLIANT HEADPHONE/SPEAKER AMPLIFIER 2.5 Because of its high output current performance and shutdown feature, the AD8592 makes an excellent amplifier for driving an audio output jack in a computer application. Figure 38 shows how the AD8592 can be interfaced with an AC’97 codec to drive headphones or speakers. 2.0 1.5 1.0 0.5 +5V 1 0.1 100 10 CAPACITIVE LOAD (nF) AVDD2 38 Figure 35. Unity-Gain Bandwidth vs. Capacitive Load When driving heavy capacitive loads directly from the AD859x output, a snubber network can be used to improve the transient response. This network consists of a series RC connected from the output of the amplifier to ground, placing it in parallel with the capacitive load. The configuration is shown in Figure 36. Although this network does not increase the bandwidth of the amplifier, it significantly reduces the amount of overshoot, as shown in Figure 37. LINE_OUT_L 35 U1-A 4 1 3 R4 20Ω R2 NC 2kΩ +5V R1 100kΩ AD1881A* (AC’97) 6 LINE_OUT_R 36 7 AVSS1 26 C2 100µF U1-B 9 8 R5 20Ω R3 2kΩ U1 = AD8592 RS 5Ω CS 1µF *ADDITIONAL PINS OMITTED FOR CLARITY. VOUT CL 47nF Figure 38. PC98-Compliant Headphone/Line Out Amplifier 01106-037 AD8592 C1 100µF 10 2 5 +5V VIN 100mV p-p +5V AVDD1 25 01106-036 0 0.01 Figure 36. Configuration for Snubber Network to Compensate for Capacitive Loads Rev. B | Page 12 of 16 01106-039 BANDWIDTH (MHz) 50mV AD8591/AD8592/AD8594 A COMBINED MICROPHONE AND SPEAKER AMPLIFIER FOR CELLPHONE AND PORTABLE HEADSETS The dual amplifiers in the AD8592 make an efficient design for interfacing with a headset containing a microphone and speaker. Figure 40 demonstrates a simple method for constructing an interface to a codec. If gain is required from the output amplifier, add four additional resistors, as shown in Figure 39. The gain of the AD8592 can be set as R7 R6 AVDD2 38 +5V R7 1kΩ U1-A 4 1 5 VREF 27 LINE_OUT_R 36 +5V U1 = AD8592 U1-B 9 8 R5 20Ω FROM CODEC MONO OUT (OR LEFT OUT) U1-A is used as a microphone preamplifier, where the gain of the preamplifier is set as R3/R2. R1 is used to bias an electret microphone, and C1 blocks any dc voltages from the amplifier. U1-B is the speaker amplifier, and its gain is set at R5/R4. To sum a stereo output, add R6, equal in value to R4. R3 2kΩ R6 = 6dB WITH VALUES SHOWN 01106-040 R7 U1 = AD8592 *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 39. PC98-Compliant Headphone/Line Out Amplifier with Gain Input coupling capacitors are not required for either circuit because the reference voltage is supplied from the AD1881A. R4 and R5 help protect the AD8592 output in case the output jack or headphone wires accidentally are shorted to ground. The output coupling capacitors, C1 and C2, block dc current from the headphones and create a high-pass filter with a corner frequency of = R4 10kΩ Figure 40. Speaker/Microphone Headset Amplifier Circuit R7 10kΩ − 3dB 7 (RIGHT OUT) R6 10kΩ (OPTIONAL) R5 10kΩ AVSS1 26 f U1-B 8 R1 100kΩ C2 100µF AV = 6 9 6 7 5 VREF FROM CODEC R4 20Ω R2 NC 2kΩ TO CODEC 1 R8 100kΩ C2 10µF C1 100µF 10 2 +5V MICROPHONE AND SPEAKER JACK 3 R6 10kΩ U1-A 3 R7 10kΩ AD1881A* (AC’97) 10 2 4 AVDD1 25 R6 10kΩ +5V R2 10kΩ NC (5) +5V LINE_OUT_L 35 C1 0.1µF R1 2.2kΩ 1 2π C1 (R 4 + R L ) where RL is the resistance of the headphones. (6) Using the same principle described in the PC98-Compliant Headphone/Speaker Amplifier section, the normalizing contact on the microphone/speaker jack can be used to put the AD8592 into shutdown when the headset is not plugged in. The AD8592 shutdown inputs can also be controlled with TTL- or CMOScompatible logic, allowing microphone or speaker muting, if desired. AN INEXPENSIVE SAMPLE-AND-HOLD CIRCUIT The independent shutdown control of each amplifier in the AD8592 allows a degree of flexibility in circuit design. One particular application for which this feature is useful is in designing a sample-and-hold circuit for data acquisition. Figure 41 shows a schematic of a simple, yet extremely effective, sampleand-hold circuit using a single AD8592 and one capacitor. 8 +5V 2 10 U1-B U1-A VIN 3 5 4 1 C1 1nF 7 6 9 +5V U1 = AD8592 SAMPLE CLOCK Figure 41. An Efficient Sample-and-Hold Circuit Rev. B | Page 13 of 16 SAMPLE AND HOLD OUTPUT 01106-042 AV = R3 100kΩ +5V 01106-041 When headphones are plugged into the jack, the normalizing contacts disconnect from the audio contacts. This allows the voltage to the AD8592 shutdown pins to be pulled to 5 V, activating the amplifiers. With no plug in the output jack, the shutdown voltage is pulled to 100 mV through the R1 and R3 + R5 voltage divider. This powers the AD8592 down when it is not needed, saving current from the power supply or battery. AD8591/AD8592/AD8594 The U1-B amplifier is used as a unity-gain buffer to prevent loading on C1. Because of the low input bias current of the U1-B CMOS input stage and the high impedance state of the U1-A output in shutdown, there is little voltage droop from C1 during the hold period. This circuit can be used with sample frequencies as high as 500 kHz and as low as 1 Hz. By increasing the C1 value, lower voltage droop is achieved for very low sample rates. SINGLE-SUPPLY DIFFERENTIAL LINE DRIVER Figure 43 shows a single-supply differential line driver circuit that can drive a 600 Ω load with less than 0.7% distortion from 20 Hz to 15 kHz with an input signal of 4 V p-p and a single 5 V supply. The design uses an AD8594 to mimic the performance of a fully balanced transformer-based solution. However, this design occupies much less board space, while maintaining low distortion, and can operate down to dc. Like the transformer-based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. R3 10kΩ 2 3 R2 10kΩ DIRECT ACCESS ARRANGEMENT FOR PCMCIA MODEMS (TELEPHONE LINE INTERFACE) P1 Tx GAIN ADJUST TO TELEPHONE LINE 1:1 2kΩ R3 360Ω 1 2 A1 9 R5 10kΩ 6.2V C1 R1 10kΩ 0.1µF R6 10kΩ 7 6 A2 5 TRANSMIT TxA R9 10kΩ R10 10kΩ 11 R11 10kΩ R12 10kΩ 12 9 A3 10 R14 R13 10kΩ 14.3kΩ 15 9 14 A4 P2 Rx GAIN ADJUST 2kΩ 16 10 A1 8 10 1 9 4 R1 10kΩ R11 10kΩ R10 10kΩ 8 7 A2 A1 R8 100kΩ 7 4 R9 100kΩ RL 600Ω C2 1µF R12 10kΩ 9 R14 50Ω C4 47µF VO2 R13 10kΩ The circuit can also be configured to provide additional gain, if desired. The gain of the circuit is AV = R8 10kΩ RECEIVE RxA C2 0.1µF +5V R8 and R9 set up the common-mode output voltage equal to half of the supply voltage. C1 is used to couple the input signal and can be omitted if the dc voltage of the input is equal to half of the supply voltage. R7 10kΩ 10µF R7 10kΩ Figure 43. Low Noise, Single-Supply Differential Line Driver SHUTDOWN 9 3 A1, A2 = 1/2 AD8592 GAIN = R3 R2 SET: R7, R10, R11 = R2 SET: R6, R12, R13 = R3 +5V T1 MIDCOM 671-8005 2 VO1 +5V VOUT R3 = VIN R2 where: VOUT = VO1 − VO2 R2 = R7 = R10 = R11 R3 = R6 = R12 = R1 3 6.2V A1, A2 = 1/4 AD8594 A3, A4 = 1/4 AD8594 VIN 01106-043 ZO 600Ω R2 9.09kΩ C1 22µF C3 47µF R6 10kΩ +5V Figure 42 illustrates a 5 V transmit/receive telephone line interface for 600 Ω systems. It allows full duplex transmission of signals on a transformer-coupled 600 Ω line in a differential manner. Amplifier A1 provides gain that can be adjusted to meet the modem output drive requirements. Both A1 and A2 are configured to apply the largest possible signal on a single supply to the transformer. Because of the high output current drive and low dropout voltages of the AD8594, the largest signal available on a single 5 V supply is approximately 4.5 V p-p into a 600 Ω transmission system. Amplifier A3 is configured as a difference amplifier for two reasons. It prevents the transmit signal from interfering with the receive signal, and it extracts the receive signal from the transmission line for amplification by A4. The gain of A4 can be adjusted in the same manner as the gain of A1 to meet the input signal requirements of the modem. Standard resistor values permit the use of single inline package (SIP) format resistor arrays. Couple this with the 16-lead TSSOP or SOIC footprint of the AD8594, and this circuit offers a compact, cost-effective solution. R5 50Ω 1 A2 01106-044 The U1-A amplifier is configured as a unity-gain buffer driving a 1 nF capacitor. The input signal is connected to the noninverting input, and the sample clock controls the shutdown for that amplifier. When the sample clock is high, the U1-A amplifier is active and the output follows VIN. When the sample clock goes low, U1-A shuts down with the output of the amplifier going to a high impedance state, holding the voltage on the C1 capacitor. Figure 42. Single-Supply Direct Access Arrangement for PCMCIA Modems Rev. B | Page 14 of 16 (7) AD8591/AD8592/AD8594 OUTLINE DIMENSIONS 2.90 BSC 6 5 4 1 2 3 2.80 BSC 1.60 BSC PIN 1 INDICATOR 0.95 BSC 1.90 BSC 1.30 1.15 0.90 1.45 MAX 0.50 0.30 0.15 MAX 0.22 0.08 10° 4° 0° SEATING PLANE 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 44. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters 3.10 3.00 2.90 10 3.10 3.00 2.90 1 6 5 5.15 4.90 4.65 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.05 0.33 0.17 SEATING PLANE 0.80 0.60 0.40 8° 0° 0.23 0.08 COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-BA Figure 45. 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 10.00 (0.3937) 9.80 (0.3858) 4.00 (0.1575) 3.80 (0.1496) 9 16 1 8 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 6.20 (0.2441) 5.80 (0.2283) 1.75 (0.0689) 1.35 (0.0531) SEATING PLANE 0.50 (0.0197) 0.25 (0.0098) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) Figure 46. 16-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-16) Dimensions shown in millimeters and (inches) Rev. B | Page 15 of 16 060606-A COMPLIANT TO JEDEC STANDARDS MS-012-AC CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. AD8591/AD8592/AD8594 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.30 0.19 0.65 BSC COPLANARITY 0.10 0.20 0.09 SEATING PLANE 0.75 0.60 0.45 8° 0° COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 47. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD8591ART-REEL AD8591ART-REEL7 AD8591ARTZ-REEL 1 AD8591ARTZ-REEL71 AD8592ARM-REEL AD8592ARMZ-REEL1 AD8594AR AD8594AR-REEL AD8594AR-REEL7 AD8594ARZ1 AD8594ARZ-REEL1 AD8594ARZ-REEL71 AD8594ARU-REEL AD8594ARUZ-REEL1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 6-Lead SOT-23 10-Lead MSOP 10-Lead MSOP 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead SOIC_N 16-Lead TSSOP 16-Lead TSSOP Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D01106-0-1/09(B) Rev. B | Page 16 of 16 Package Option RJ-6 RJ-6 RJ-6 RJ-6 RM-10 RM-10 R-16 R-16 R-16 R-16 R-16 R-16 RU-16 RU-16 Branding A9A A9A A9A# A9A# AQA AQA#