This version: Apr.22. 1999 Semiconductor MSC23V26407TD-xxBS8 2,097,152-Word x 64-Bit DYNAMIC RAM MODULE : FAST PAGE MODE TYPE DESCRIPTION The MSC23V26407TD-xxBS8 is a 2,097,152-word x 64-bit CMOS dynamic random access memory module which is composed of eight 16Mb(2Mx8) DRAMs in TSOP packages mounted with eight decoupling capacitors. This is an 168-pin dual in-line memory module. This module supports any application where high density and large capacity of storage memory are required. FEATURES · 2,097,152-word x 64-bit organization · 168-pin Dual In-line Memory Module · Gold tab · Single 3.3V power supply, ±0.3V tolerance · Input : LVTTL compatible · Output : LVTTL compatible, 3-state · Refresh : 2048cycles/ 32ms · /CAS before /RAS refresh, hidden refresh, /RAS only refresh capability · Fast page mode, read modify write capability · Multi-bit test mode capability · Serial Presence Detect PRODUCT FAMILY tRAC tAA tCAC tOEA Cycle Time (Min.) MSC23V26407TD-50BS8 50ns 25ns 13ns 13ns 90ns 2880mW MSC23V26407TD-60BS8 60ns 30ns 15ns 15ns 110ns 2592mW MSC23V26407TD-70BS8 70ns 35ns 20ns 20ns 130ns 2304mW Access Time (Max.) Family Power Dissipation (Max.) Operating Standby 14.4mW Semiconductor MSC23V26407TD MODULE OUTLINE MSC23V26407TD-xxBS8 (Unit : mm) 2.70Max. 133.35±0.7 *1 131.35 TYP 25.40±0.12 17.78±0.1 3.0±0.1 2 - R2.0 2 - φ3.0±0.1 A B C 1 4.0Min. 84 11.43±0.05 36.83±0.05 54.61±0.05 127.35±0.05 133.35±0.12 R1.0 1.0±0.03 2.0±0.1 2.0±0.1 6.35±0.05 6.35±0.05 Detail A Detail B Note: 1. Tolerance over 19.78mm from bottom edge is ±0.7. 2.54 MIN 3.12±0.1 3.175±0.13 3.12±0.1 4.175±0.13 0.25 MAX R1.0 1.27±0.1 1.27±0.03 Detail C Semiconductor MSC23V26407TD PIN CONFIGURATION Front Side Back Side Front Side Back Side Pin No. 1 2 3 Pin Name VSS DQ0 DQ1 Pin No. 85 86 87 Pin Name VSS DQ32 DQ33 Pin No. 43 44 45 Pin Name VSS /OE2 /RAS2 Pin No. 127 128 129 Pin Name VSS NC NC 4 5 DQ2 DQ3 88 89 DQ34 DQ35 46 47 /CAS2 /CAS3 130 131 /CAS6 /CAS7 6 7 VCC DQ4 90 91 VCC DQ36 48 49 /WE2 VCC 132 133 NC VCC 8 9 10 11 DQ5 DQ6 DQ7 DQ8 92 93 94 95 DQ37 DQ38 DQ39 DQ40 50 51 52 53 NC NC NC NC 134 135 136 137 NC NC NC NC 12 13 14 VSS DQ9 DQ10 96 97 98 VSS DQ41 DQ42 54 55 56 VSS DQ16 DQ17 138 139 140 VSS DQ48 DQ49 15 16 17 18 DQ11 DQ12 DQ13 VCC 99 100 101 102 DQ43 DQ44 DQ45 VCC 57 58 59 60 DQ18 DQ19 VCC DQ20 141 142 143 144 DQ50 DQ51 VCC DQ52 19 20 DQ14 DQ15 103 104 DQ46 DQ47 61 62 NC NC 145 146 NC NC 21 22 23 24 25 26 27 28 NC NC VSS NC NC VCC /WE0 /CAS0 105 106 107 108 109 110 111 112 NC NC VSS NC NC VCC NC /CAS4 63 64 65 66 67 68 69 70 NC VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 147 148 149 150 151 152 153 154 NC VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 29 30 31 /CAS1 /RAS0 /OE0 113 114 115 /CAS5 NC NC 71 72 73 DQ26 DQ27 VCC 155 156 157 DQ58 DQ59 VCC 32 VSS 116 VSS 74 DQ28 158 DQ60 33 34 35 36 A0 A2 A4 A6 117 118 119 120 A1 A3 A5 A7 75 76 77 78 DQ29 DQ30 DQ31 VSS 159 160 161 162 DQ61 DQ62 DQ63 VSS 37 38 39 40 41 42 A8 A10 NC VCC VCC NC 121 122 123 124 125 126 A9 NC NC VCC NC NC 79 80 81 82 83 84 NC NC NC SDA SCL VCC 163 164 165 166 167 168 NC NC SA0 SA1 SA2 VCC Semiconductor MSC23V26407TD Serial PD Matrix Byte No. Function described SPD Value (Hex) Note 0 Number of Byte used 80 128 Bytes 1 Total SPD Memory size 08 256 Bytes 2 Memory type 01 Fast Page 3 Number of Rows 0B 11 4 Number of Columns 0A 10 5 Number of Banks 01 1 6 Module Data Width 40 64 7 Module Data Width Continued 00 0 8 Supply Voltage 01 LVTTL 32 50ns 3C 60ns -70 46 70ns -50 0D 13ns 0F 15ns 14 20ns -50 9 -60 10 -60 /RAS Access Time /CAS Access Time -70 11 DIMM Configuration type 00 Non-Parity 12 Refresh Rate/Type 00 Normal Refresh 13 Primary DRAM Width 08 x8 14 Error Checking DRAM Width 00 Superset Information 00 Reserved SPD Data Revision Code 01 1 15-61 62 -50 63 -60 28 Checksum for Byte 0-62 -70 34 43 64-127 Reserved 00 128-255 Unused Storage Location (Reserved) FF Semiconductor MSC23V26407TD BLOCK DIAGRAM /OE0 /WE0 /OE2 /WE2 /RAS0 /CAS0 /RAS2 /CAS4 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 /CAS /RAS /WE /OE DQ DQ DQ DQ D0 DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 /CAS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 /CAS5 /CAS /RAS /WE /OE DQ DQ DQ DQ D1 DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 /CAS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 /CAS /RAS /WE /OE DQ DQ DQ DQ D2 DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 /CAS /RAS /WE /OE DQ DQ DQ DQ D6 DQ DQ DQ DQ /CAS7 /CAS /RAS /WE /OE DQ DQ DQ DQ D3 DQ DQ DQ DQ A0-A9 A10 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 A0-A9 : D0-D7 A10R VCC VSS /CAS /RAS /WE /OE DQ DQ DQ DQ D5 DQ DQ DQ DQ /CAS6 /CAS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 /CAS /RAS /WE /OE DQ DQ DQ DQ D4 DQ DQ DQ DQ D0-D7 C1-C8 D0-D7 SCL /CAS /RAS /WE /OE DQ DQ DQ DQ D7 DQ DQ DQ DQ Serial PD SCL SDA A0 A1 A2 SA0 SA1 SA2 SDA Semiconductor MSC23V26407TD ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VIN, VOUT -0.5 to 4.6 V Voltage on VCC Supply Relative to VSS VCC -0.5 to 4.6 V Short Circuit Output Current IOS 50 mA Power Dissipation PD * 8 W Operating Temperature TOPR 0 to 70 °C Storage Temperature TSTG -40 to 125 °C Voltage on Any Pin Relative to VSS * Ta = 25°C Recommended Operating Conditions ( Ta = 0°C to 70°C ) Parameter Symbol Min. Typ. Max. Unit VCC 3.0 3.3 3.6 V VSS 0 0 0 V Input High Voltage VIH 2.0 - VCC+0.3 V Input Low Voltage VIL -0.3 - 0.8 V Power Supply Voltage Capacitance ( VCC = 3.3V ±0.3V, Ta = 25°C, f = 1 MHz ) Parameter Symbol Typ. Max. Unit Input Capacitance (A0 - A10) CIN1 - 49 pF Input Capacitance (/RAS0, /RAS2, /WE0, /WE2, /OE0, /OE2) CIN2 - 35 pF Input Capacitance (/CAS0 - /CAS7) CIN3 - 13 pF I/O Capacitance (DQ0 - DQ63) CI/O - 13 pF Semiconductor MSC23V26407TD DC Characteristics (VCC = 3.3V ±0.3V, Ta = 0°C to 70°C ) Parameter Symbol Condition -50 -60 -70 Min. Max. Min. Max. Min. Max. Unit Output High Voltage VOH IOH = -2.0mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.0mA 0 0.4 0 0.4 0 0.4 V Input Leakage Current ILI 0V ≤ VIN ≤ VCC+0.3V; All other pins not under test = 0V -80 80 -80 80 -80 80 µA Output Leakage Current ILO DQ disable 0V ≤ VOUT ≤ VCC -10 10 -10 10 -10 10 µA Average Power Supply Current (Operating) ICC1 /RAS, /CAS cycling, tRC = Min. - 800 - 720 - 640 mA /RAS, /CAS = VIH - 16 - 16 - 16 mA /RAS, /CAS ≥ VCC -0.2V - 4 - 4 - 4 mA Note 1, 2 Power Supply Current (Standby) ICC2 Average Power Supply Current (/RAS only refresh) ICC3 /RAS cycling, /CAS = VIH, tRC = Min. - 800 - 720 - 640 mA 1, 2 Average Power Supply Current (/CAS before /RAS refresh) ICC6 /RAS cycling, /CAS before /RAS - 800 - 720 - 640 mA 1, 2 Average Power Supply Current (Fast Page Mode) ICC7 /RAS = VIL, /CAS cycling, tPC = Min. - 600 - 560 - 520 mA 1, 3 Notes: 1. ICC Max. is specified as ICC for output open condition. 2. The address can be changed once or less while /RAS = VIL. 3. The address can be changed once or less while /CAS = VIH. 1 Semiconductor MSC23V26407TD AC Characteristics (1/2) (VCC = 3.3V ±0.3V, Ta = 0°C to 70°C ) Note: 1, 2, 3, 11, 12 Parameter Symbol -50 -60 -70 Min. Max. Min. Max. Min. Max. Unit Note Random Read or Write Cycle Time tRC 90 - 110 - 130 - ns Read Modify Write Cycle Time tRWC 131 - 155 - 185 - ns Fast Page Mode Cycle Time tPC 35 - 40 - 45 - ns Fast Page Mode Read Modify Write Cycle Time tPRWC 76 - 85 - 100 - ns Access Time from /RAS tRAC - 50 - 60 - 70 ns 4, 5, 6 Access Time from /CAS tCAC - 13 - 15 - 20 ns 4, 5 Access Time from Column Address tAA - 25 - 30 - 35 ns 4, 6 Access Time from /CAS Precharge tCPA - 30 - 35 - 40 ns 4 Access Time from /OE tOEA - 13 - 15 - 20 ns 4 Output Low Impedance Time from /CAS tCLZ 0 - 0 - 0 - ns 4 /CAS to Data Output Buffer Turn-off Delay Time tOFF 0 13 0 15 0 20 ns 7 /OE to Data Output Buffer Turn-off Delay Time tOEZ 0 13 0 15 0 20 ns 7 Transition Time tT 3 50 3 50 3 50 ns 3 Refresh Period tREF - 32 - 32 - 32 ms /RAS Precharge Time tRP 30 - 40 - 50 - ns /RAS Pulse Width tRAS 50 10K 60 10K 70 10K ns /RAS Pulse Width (Fast Page Mode) tRASP 50 100K 60 100K 70 100K ns /RAS Hold Time tRSH 13 - 15 - 20 - ns /RAS Hold Time referenced to /OE tROH 13 - 15 - 20 - ns /CAS Precharge Time (Fast Page Mode) tCP 7 - 10 - 10 - ns /CAS Pulse Width tCAS 13 10K 15 10K 20 10K ns /CAS Hold Time tCSH 50 - 60 - 70 - ns /CAS to /RAS Precharge Time tCRP 5 - 5 - 5 - ns /RAS Hold Time from /CAS Precharge tRHCP 30 - 35 - 40 - ns /RAS to /CAS Delay Time tRCD 17 37 20 45 20 50 ns 5 /RAS to Column Address Delay Time tRAD 12 25 15 30 15 35 ns 6 Row Address Set-up Time tASR 0 - 0 - 0 - ns Row Address Hold Time tRAH 7 - 10 - 10 - ns Column Address Set-up Time tASC 0 - 0 - 0 - ns Column Address Hold Time tCAH 7 - 10 - 15 - ns Column Address to /RAS Lead Time tRAL 25 - 30 - 35 - ns Read Command Set-up Time tRCS 0 - 0 - 0 - ns Read Command Hold Time tRCH 0 - 0 - 0 - ns 8 Read Command Hold Time referenced to /RAS tRRH 0 - 0 - 0 - ns 8 Semiconductor MSC23V26407TD AC Characteristics (2/2) (VCC = 3.3V ±0.3V, Ta = 0°C to 70°C ) Note: 1, 2, 3, 11, 12 Parameter Symbol -50 -60 -70 Min. Max. Min. Max. Min. Max. Unit Note Write Command Set-up Time tWCS 0 - 0 - 0 - ns 9 Write Command Hold Time tWCH 7 - 10 - 15 - ns Write Command Pulse Width tWP 7 - 10 - 10 - ns /OE Command Hold Time tOEH 13 - 15 - 20 - ns Write Command to /RAS Lead Time tRWL 13 - 15 - 20 - ns Write Command to /CAS Lead Time tCWL 13 - 15 - 20 - ns Data-in Set-up Time tDS 0 - 0 - 0 - ns 10 Data-in Hold Time tDH 7 - 10 - 15 - ns 10 /OE to Data-in Delay Time tOED 13 - 15 - 20 - ns /CAS to /WE Delay Time tCWD 36 - 40 - 50 - ns 9 Column Address to /WE Delay Time tAWD 48 - 55 - 65 - ns 9 /RAS to /WE Delay Time tRWD 73 - 85 - 100 - ns 9 /CAS Precharge /WE Delay Time tCPWD 53 - 60 - 70 - ns 9 /CAS Active Delay Time from /RAS Precharge tRPC 5 - 5 - 5 - ns /RAS to /CAS Set-up Time (/CAS before /RAS) tCSR 10 - 10 - 10 - ns /RAS to /CAS Hold Time (/CAS before /RAS) tCHR 10 - 10 - 10 - ns /WE to /RAS Precharge Time (/CAS before /RAS) tWRP 10 - 10 - 10 - ns /WE Hold Time from /RAS (/CAS before /RAS) tWRH 10 - 10 - 10 - ns /RAS to /WE Set-up Time (Test Mode) tWTS 10 - 10 - 10 - ns /RAS to /WE Hold Time (Test Mode) tWTH 10 - 10 - 10 - ns Semiconductor MSC23V26407TD Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (/RAS only refresh or /CAS before /RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5ns. 3. VIH(Min.) and VIL(Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 100pF. The output timing reference levels are VOH = 2.0V and VOL = 0.8V. 5. Operation within the tRCD(Max.) limit ensures that tRAC(Max.) can be met. tRCD(Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD(Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD(Max.) limit ensures that tRAC(Max.) can be met. tRAD(Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD(Max.) limit, then the access time is controlled by tAA. 7. tOFF(Max.) and tOEZ(Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS(Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD(Min.), tRWD ≥ tRWD(Min.), tAWD ≥ tAWD(Min.) and tCPWD ≥ tCPWD(Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the /CAS leading edge in an early write cycle, and to the /WE leading edge in an /OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a /WE and /CAS before /RAS refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. The test mode specified in this data sheet is a 2-bit parallel test function. CA9 is not used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high level. If any internal bits are not equal, the DQ pin will indicate a low levels. The test mode is cleared and the memory device returned to its normal operating state by performing a /RAS only refresh cycle or a /CAS before /RAS refresh cycle. 12. In a test mode read cycle, the value of access time parameters is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet.