ICST ICS9FG107YGLNT Programmable ftg for differential cpu, pci express & sata clock Datasheet

ICS9FG107
Integrated
Circuit
Systems, Inc.
Recommended Application:
Pin Configuration
Frequency Timing Generator for Differential CPU, PCI Express
XIN/CLKIN
& SATA clocks
Features:
•
Generates common CPU/PCI Express frequencies from
14.318 MHz or 25 MHz
•
Crystal or reference input
•
7 - 0.7V current-mode differential output pairs
•
3 - 33MHz PCI outputs
•
1 - REFOUT
•
Supports Serial-ATA at 100 MHz
•
Two spread spectrum modes: 0 to -0.5 downspread and
+/-0.25% centerspread
•
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
Key Specifications:
•
Output cycle-to-cycle jitter for DIF outputs < 50 ps (<85ps
@ 266 MHz)
•
Output to output skew for DIF outputs < 85 ps
•
+/-300 ppm frequency accuracy on output clocks
Frequency Select Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.66
0
1
1
0
333.33
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.66
1
1
1
0
333.33
1
1
1
1
400.00
0863C—11/22/04
X2
VDD
GND
*FS2/REFOUT
GND
*FS0/PCICLK_F
PCICLK0
PCICLK1
VDD
**OE_6
DIF_6
DIF_6#
VDD
GND
**OE_5
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
*OE_4
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
ICS9FG107
Programmable FTG for Differential CPU, PCI Express* & SATA Clocks
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
*DWNSPRD#
**FS1
*OE_0
DIF_0
DIF_0#
VDD
DIF_1
DIF_1#
**OE_1
VDD
GND
**OE_2
DIF_2
DIF_2#
VDD
DIF_3
DIF_3#
*OE_3
**SEL14M_25M#
*SPREAD
DIF_STOP#
48-pin SSOP & TSSOP
Notes:
Pins preceeded by * have 120 Kohm pull DOWN resistors
Pins preceeded by ** have 120 Kohm pull UP resistors
*Other names and brands may be claimed as the property of others.
Integrated
Circuit
Systems, Inc.
ICS9FG107
Pin Description
PIN
#
1
2
3
4
5
6
XIN/CLKIN
X2
VDD
GND
*FS2/REFOUT
GND
7
*FS0/PCICLK_F
8
9
10
PCICLK0
PCICLK1
VDD
11
**OE_6
IN
12
13
14
15
DIF_6
DIF_6#
VDD
GND
OUT
OUT
PWR
PWR
16
**OE_5
IN
17
18
19
20
21
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
OUT
OUT
PWR
OUT
OUT
22
*OE_4
IN
23
24
SDATA
SCLK
I/O
IN
PIN NAME
PIN TYPE
IN
OUT
PWR
PWR
I/O
PWR
I/O
OUT
OUT
PWR
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Frequency select latch input pin / Reference clock output
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Power supply, nominal 3.3V
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
Ground pin.
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
0863C—11/22/04
2
Integrated
Circuit
Systems, Inc.
ICS9FG107
Pin Description (Continued)
PIN
PIN NAME
#
25
DIF_STOP#
PIN TYPE
DESCRIPTION
IN
Active low input to stop differential output clocks.
Asynchronous, active high input, with internal 120Kohm pull-up
resistor, to enable spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz,
0 = 25 MHz
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Ground pin.
Power supply, nominal 3.3V
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Frequency select latch input pin / 3.3V 66.66MHz clock output.
3.3V input that selects spread mode. This input is not latched at
power up.
0 = Down Spread, 1 = Center Spread
This pin establishes the reference current for the differential currentmode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
26
*SPREAD
IN
27
**SEL14M_25M#
IN
28
*OE_3
IN
29
30
31
32
33
DIF_3#
DIF_3
VDD
DIF_2#
DIF_2
OUT
OUT
PWR
OUT
OUT
34
**OE_2
IN
35
36
GND
VDD
37
**OE_1
IN
38
39
40
41
42
DIF_1#
DIF_1
VDD
DIF_0#
DIF_0
OUT
OUT
PWR
OUT
OUT
43
*OE_0
IN
44
**FS1
I/O
45
*DWNSPRD#
IN
46
IREF
OUT
47
48
GNDA
VDDA
PWR
PWR
PWR
PWR
Pins preceeded by * have 120 Kohm pull DOWN resistors
Pins preceeded by ** have 120 Kohm pull UP resistors
0863C—11/22/04
3
Integrated
Circuit
Systems, Inc.
ICS9FG107
General Description
ICS9FG107 is a Frequency Timing Generator that provides 7 differential output pairs that are compliant to the Intel CK409/
CK410 specification. It provides support for PCI-Express, next generation I/O, and SATA. The part synthesizes several output
frequencies from either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can also be driven by a reference input clock
instead of a crystal. It provides outputs with cycle-to-cycle jitter of less than 85 ps and output-to-output skew of less than 85 ps.
ICS9FG107 also provides a copy of the reference clock and 3 33 MHz PCI output clocks. Frequency selection can be
accomplished via strap pins or SMBus control.
Block Diagram
XIN/CLKIN
REFOUT
X2
PCICLK (1:0)
SCLK
Programmable
Spread
PLL1
SDATA
DIF_STOP#
SEL14M_25M#
SPREAD
Programmable
Frequency
Dividers
Control
Logic
PCICLK_F
DIF (6:0)
DIF# (6:0)
DWNSPRD#
OE (6:0)
FS (2:0)
I REF
Power Groups
Pin Number
VDD
GND
3
4
10
6
14,19,31,36,40
15,35
N/A
47
48
47
Description
REFOUT, Digital Inputs, SMBus
PCI Outputs
DIF Outputs
IREF
Analog VDD & GND for PLL Core
0863C—11/22/04
4
Integrated
Circuit
Systems, Inc.
ICS9FG107
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
VDD_In
3.3V Core Supply Voltage
3.3V Logic Input Supply Voltage
GND - 0.5
VDD + 0.5V
VDD + 0.5V
V
V
Ts
Tambient
Tcase
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
ESD prot
-65
0
°
150
70
115
C
°C
°C
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage V DD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
Input High Voltage
Input Low Voltage
Input High Current
VIH
VIL
IIH
3.3 V +/-5%
3.3 V +/-5%
VIN = VDD
V IN = 0 V; Inputs with no pullup resistors
2
VSS - 0.3
-5
IIL1
Input Low Current
IIL2
Operating Supply Current
IDD3.3OP
Input Frequency 3
Pin Inductance1
Input/Output
Capacitance1
Fi
Lpin
CIN
COUT
Clk Stabilization1,2
TSTAB
Modulation Frequency
f MOD
DIF output enable
tDIFOE
Input Rise and Fall times
t R/t F
V IN = 0 V; Inputs with pull-up
resistors
Full Active, CL = Full load;
f = 400 MHz
Full Active, CL = Full load;
f = 100 MHz
V DD = 3.3 V
Logic Inputs
Output pin capacitance
From V DD Power-Up and after
input clock stabilization to 1st
clock
Triangular Modulation
DIF output enable after
DIF_Stop# de-assertion
20% to 80% of VDD
1
TYP
MAX
VDD + 0.3
0.8
5
UNITS NOTES
V
V
uA
-5
uA
-200
uA
14
1.5
30
250
mA
200
mA
25
7
5
6
MHz
nH
pF
pF
3
1
1
1
1.8
ms
1,2
40
kHz
1
10
ns
1
5
ns
1
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
3
Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet
ppm frequency accuracy on PLL outputs.
2
0863C—11/22/04
5
Integrated
Circuit
Systems, Inc.
ICS9FG107
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2∠, RP=49.9∠ !!REF∠!!9,
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Zo1
VO = Vx
3000
Voltage High
VHigh
Statistical measurement on
single ended signal using
oscilloscope math function.
660
Voltage Low
VLow
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Crossing Voltage (var)
d-Vcross
Long Accuracy
ppm
Average period
Tperiod
Absolute min period
Tabsmin
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
tr
tf
d-t r
d-t f
Duty Cycle
dt3
Skew
t sk3
Jitter, Cycle to cycle
t jcyc-cyc
Measurement on single ended
signal using absolute value.
Variation of crossing over all
edges
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
VOL = 0.175V, VOH = 0.525V
VOH = 0.525V VOL = 0.175V
Measurement from differential
wavefrom
VT = 50%
Measurement from differential
wavefrom f not equal 266 MHz
Measurement from differential
wavefrom f = 266 MHz
TYP
MAX
-150
Figures are for down spread.
6
1
1
150
1150
1
550
mV
1
1
1
140
mV
1
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
175
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
700
700
125
125
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,2
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
45
55
%
1
85
ps
1
50
ps
1
85
ps
1
-300
250
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at
14.31818MHz or 25 MHz
0863C—11/22/04
∠
mV
Guaranteed by design and characterization, not 100% tested in production.
3
NOTES
850
1
2
UNITS
mV
Integrated
Circuit
Systems, Inc.
ICS9FG107
Electrical Characteristics - PCICLK/PCICLK_F
TA = 0 - 70°C; V DD = 3.3 V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Long Accuracy
ppm
see Tperiod min-max values
-300
33.33MHz output nominal
29.99100
Clock period
Tperiod
33.33MHz output spread
29.99100
Absolute Min/Max Clock
33.33MHz output nominal
29.49100
Tabs
period
33.33MHz output spread
29.49100
12
Clk High Time
t h1
12
Clock Low Time
t l1
Output High Voltage
V OH
I OH = -1 mA
2.4
Output Low Voltage
V OL
IOL = 1 mA
V OH @MIN = 1.0 V
-33
Output High Current
I OH
V [email protected] MAX = 3.135 V
V OL @ MIN = 1.95 V
30
Output Low Current
I OL
V OL @ MAX = 0.4 V
Edge Rate
Edge Rate
Rise Time
Fall Time
Duty Cycle
Skew
Jitter
1
t r1
t f1
dt1
t sk1
t jcyc-cyc
Rising edge rate
Falling edge rate
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4 V, VOL = 0.4 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
1
1
0.5
0.5
45
1.4
1.4
MAX
300
30.00900
30.15980
30.50900
30.65980
N/A
N/A
Notes
1,2
2
2
2
2
1
1
38
UNITS
ppm
ns
ns
ns
ns
ns
ns
V
V
mA
mA
mA
mA
4
4
2
2
55
500
250
V/ns
V/ns
ns
ns
%
ps
ps
1
1
1
1
1
1
1
0.55
-33
Guaranteed by design, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at
14.31818MHz or 25 MHz
Electrical Characteristics - REF-14.318/25 MHz
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL = 10-20 pF (unless otherwise specified)
SYMBO
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS Notes
L
Long Accuracy
ppm
see Tperiod min-max values
-300
0
300
ppm
1
14.318MHz output nominal
69.8270 69.8413 69.8550 ns
1,2
Clock period
Tperiod
25.000MHz output nominal
39.9880 40.0000 40.0120 ns
1,2
Output High Voltage
VOH
IOH = -1 mA
2.4
V
1
Output Low Voltage
VOL
IOL = 1 mA
0.4
V
1
VOH @MIN = 1.0 V,
Output High Current
IOH
-29
-23
mA
1
[email protected] = 3.135 V
VOL @MIN = 1.95 V,
29
27
mA
1
Output Low Current
IOL
VOL @MAX = 0.4 V
VOL = 0.4 V, VOH = 2.4 V
1
1.6
2
ns
1
Rise Time
tr1
Fall Time
t f1
VOH = 2.4 V, VOL = 0.4 V
1
1.6
2
ns
1
Duty Cycle
dt1
VT = 1.5 V
Jitter
tjcyc-cyc
VT = 1.5 V
1
45
160
55
%
1
250
ps
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818 or 25.00 MHz
2
0863C—11/22/04
7
Integrated
Circuit
Systems, Inc.
ICS9FG107
General SMBus serial interface information for the ICS9FG107
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address DC (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Read Operation
Index Block Write Operation
Controlle r (Host)
starT bit
T
Slave Address DC(H )
W Rite
WR
Controller (host) will send start bit.
Controller (host) sends the write address DC (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Controlle r (Host)
T
starT bit
Slave Address DC(H )
WR
W Rite
ICS (Sla ve /Re ce ive r)
ICS (Sla ve /Re ce ive r)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address DD(H )
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
0863C—11/22/04
8
Not acknowledge
stoP bit
Integrated
Circuit
Systems, Inc.
ICS9FG107
2
I C Table: Device Control Register, READ/WRITE ADDRESS (DC/DD)
Control
Pin #
Name
Type
0
1
Byte 0
Function
RW
27
Bit 7
FS31
See Frequency
5
RW
Bit 6
FS21
1
Selection
Table, Page 1
RW
44
Bit 5
FS1
1
RW
7
Bit 4
FS0
26
RW
Off
On
Bit 3
Spread Enable1
Enable Software Control of
Hardware
Software
Frequency, Spread Enable and
RW
Bit 2
Select
Select
Spread Type
Bit 1
Bit 0
DIF_STOP# drive mode
DWNSPRD#1
45
RW
RW
Driven
Down
Hi-Z
Center
PWD
Pin 27
Pin 5
Pin 44
Pin 7
Pin 26
0
0
Pin 45
Notes:
1. These bits reflect the latched state of the corresponding pins at power up, but may be written to
if Byte 0, bit 2 is set to '1'. FS3 is the SEL14M_25M# pin.
2
I C Table: Output Enable Register
Byte 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
8
12,13
17,18
20,21
30,29
33,32
39,38
42,41
Name
PCICLK0
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Control
Function
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Output Enable
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
Stop Low
Disable
Disable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Enable
1
1
1
1
1
1
1
1
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
Stop Low
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Free-run
Enable
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
Stop-able
1
0
0
0
0
0
0
0
2
I C Table: Output Stop Mode Register
Byte 2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
9
12,13
17,18
20,21
30,29
33,32
39,38
42,41
Name
PCICLK1
DIF_6
DIF_5
DIF_4
DIF_3
DIF_2
DIF_1
DIF_0
Control
Function
Output Enable
Stop Mode
Stop Mode
Stop Mode
Stop Mode
Stop Mode
Stop Mode
Stop Mode
0863C—11/22/04
9
Integrated
Circuit
Systems, Inc.
ICS9FG107
2
I C Table: Frequency Select Readback Register
Pin #
Byte 3
Name
Control
Function
SEL14M_25M#1
State of pin 27
(FS3)
Type
0
1
R
PWD
Pin 27
Bit 7
27
Bit 6
5
FS21
State of pin 6
R
Bit 5
44
FS11
State of pin 44
R
Pin 44
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
7
26
State of pin 7
FS01
1
State of pin 26
SPREAD
RESERVED
RESERVED
DWNSPRD1 State of pin 45
R
R
R
R
R
Pin 7
Pin 26
X
X
Pin 45
45
See Frequency
Selection Table, Page 1
Off
On
RESERVED
RESERVED
Down
Center
Pin 5
Notes:
1. These read-only bits always reflect the latched state of the corresponding pins at power up.
2
I C Table: Vendor & Revision ID Register
Pin #
Byte 4
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
RID3
RID2
RID1
RID0
VID3
VID2
VID1
VID0
-
Control
Function
REVISION ID
VENDOR ID
Type
0
1
PWD
R
R
R
R
R
R
R
R
-
-
0
0
0
0
0
0
0
1
Type
0
1
PWD
2
I C Table: DEVICE ID
Pin #
Byte 5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Name
Control
Function
R
R
R
R
R
R
R
R
Device ID = 07 Hex
Bit 7 is MSB
0863C—11/22/04
10
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0
0
0
0
0
1
1
1
Integrated
Circuit
Systems, Inc.
ICS9FG107
2
I C Table: Byte Count Register
Pin #
Byte 6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control
Function
Writing to this
register will
configure how
many bytes
will be read
back, default
is 07 = 7
bytes.
0863C—11/22/04
11
Type
0
1
PWD
RW
RW
RW
RW
RW
RW
RW
RW
-
-
0
0
0
0
0
1
1
1
Integrated
Circuit
Systems, Inc.
ICS9FG107
DIF_STOP# - Assertion (transition from '1' to '0')
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the I2C
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the I2C DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP#
DIF
DIF#
DIF_STOP# - De-assertion (transition from '0' to '1')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 10nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_Stop#
DIF
DIF#
DIF Internal
Tdrive_DIF_Stop, 10nS >200mV
0863C—11/22/04
12
Integrated
Circuit
Systems, Inc.
ICS9FG107
c
N
SYMBOL
L
E1
E
INDEX
AREA
1 2
α
h x 45°
D
A
A
A1
b
c
D
E
E1
e
h
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
A1
-Ce
b
SEATING
PLANE
.10 (.004) C
N
48
VARIATIONS
D mm.
MIN
MAX
15.75
16.00
D (inch)
MIN
.620
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
ICS9FG107yFLFT
Example:
ICS XXXX y F Lx T
Designation for tape and reel packaging
Lead Option (optional)
LF = Lead Free
LN = Lead Free Annealed
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0863C—11/22/04
13
MAX
.630
Integrated
Circuit
Systems, Inc.
ICS9FG107
c
N
48-Lead, 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
L
E1
INDEX
AREA
E
1 2
D
A
A2
A1
-Ce
SEATING
PLANE
b
aaa C
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
N
a
aaa
(20 mil)
In Millimeters
COMMON DIMENSIONS
MIN
MAX
-1.20
0.05
0.15
0.80
1.05
0.17
0.27
0.09
0.20
SEE VARIATIONS
8.10 BASIC
6.00
6.20
0.50 BASIC
0.45
0.75
SEE VARIATIONS
0°
8°
-0.10
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.011
.0035
.008
SEE VARIATIONS
0.319 BASIC
.236
.244
0.020 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
VARIATIONS
N
48
D mm.
MIN
12.40
D (inch)
MAX
12.60
Reference Doc.: JEDEC Publication 95, MO-153
10-0039
Ordering Information
ICS9FG107yGLFT
Example:
ICS XXXX y G Lx T
Designation for tape and reel packaging
Lead Option (optional)
LF = Lead Free
LN = Lead Free Annealed
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
0863C—11/22/04
14
MIN
.488
MAX
.496
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