ATMEL ATA6824C High temperature h-bridge motor driver Datasheet

ATA6824C
High Temperature H-bridge Motor Driver
DATASHEET
Features
● PWM and direction-controlled driving of four externally-powered NMOS transistors
● High temperature capability up to 200°C junction
● A programmable dead time is included to avoid peak currents within the H-bridge
● Integrated charge pump to provide gate voltages for high-side drivers and to supply
the gate of the external battery reverse protection NMOS
● 5V/3.3V regulator and current limitation function
● Reset derived from 5V/3.3V regulator output voltage
● A programmable window watchdog
● Battery overvoltage protection and battery undervoltage management
● Overtemperature warning and protection (Shutdown)
● High voltage serial interface for communication
● TPQFP package
Description
The Atmel® ATA6824C is designed for DC motor control application in automotive high
temperature environment like in mechatronic assemblies in the vicinity of the hot engine,
e.g. turbo charger. With a maximum junction temperature of 200°C, Atmel ATA6824C is
suitable for applications with an ambient temperature up to 150°C.
The IC includes 4 driver stages to control 4 external power MOSFETs. An external microcontroller provides the direction signal and the PWM frequency. In PWM operation, the
high-side switches are permanently on while the low-side switches are activated by the
PWM frequency. Atmel ATA6824C contains a voltage regulator to supply the microcontroller; via the input pin VMODE the output voltage can be set to 5V or 3.3V respectively.
The on-chip window watchdog timer provides a pin-programmable time window. The
watchdog is internally trimmed to an accuracy of 10%. For communication a high voltage
serial interface with a maximum data range of 20kBaud is integrated.
9212G-AUTO-09/13
Figure 1.
Block Diagram
M
CVRES
CP
VRES
RGATE
RGATE
H2
H1
S1
S2
RGATE
RGATE
L1
L2
PGND
CPLO
GND
Charge
Pump
CCP
HS Driver 2
HS Driver 1
LS Driver 1
LS Driver 2
VBAT
CPIH
DG3
OT
UV
12V
Regulator
VG
CVG
VBAT
PBAT
OTP
12 bit
VINT
DG2
DG1
CC
Logic Control
Vint 5V
Regulator
CVINT
Supervisor
OV
CCC
CC timer
RCC
Oscillator
WD timer
RRWD
VBAT
CP
TP1
VBG
VBATSW
VCC 5V
Regulator
Serial
Interface
Bandgap
CSIO
WD
VCC
VMODE
/RESET
TP2
DIR
PWM
Battery
CVCC
2
ATA6824C [DATASHEET]
9212G–AUTO–09/13
SIO
Microcontroller
RX
TX
Pin Configuration
TP2
VBATSW
VBAT
VCC
PGND
L1
L2
PBAT
Figure 1-1. Pinning TPQFP32
VMODE
VINT
RWD
CC
/RESET
WD
GND
SIO
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
Atmel YWW 22
21
ATA6824
20
ZZZZZ-AL
19
18
17
9 10 11 12 13 14 15 16
VG
CPLO
CPHI
VRES
H2
S2
H1
S1
TX
DIR
PWM
TP1
RX
DG3
DG2
DG1
1.
Note:
YWW
ATA6824C
ZZZZZ
AL
Date code (Y = Year - above 2000, WW = week number)
Product name
Wafer lot number
Assembly sub-lot number
Table 1-1.
Pin Description
Pin
Symbol
I/O
Function
1
VMODE
I
2
VINT
I/O
3
RWD
I
4
CC
I/O
RC combination to adjust cross conduction time
5
/RESET
O
Reset signal for microcontroller
6
WD
I
Watchdog trigger signal
7
GND
I
Ground for chip core
8
SIO
I/O
9
TX
I
Transmit signal to serial interface from microcontroller
10
DIR
I
Defines the rotation direction for the motor
Selector for VCC and interface logic voltage level
Blocking capacitor 220nF/10V/X7R
Resistor defining the watchdog interval
High Voltage (HV) serial interface
11
PWM
I
PWM input controls motor speed
12
TP1
–
Test pin to be connected to GND
13
RX
O
Receive signal from serial interface for microcontroller
14
DG3
O
Diagnostic output 3
15
DG2
O
Diagnostic output 2
16
DG1
O
Diagnostic output 1
17
S1
I/O
Source voltage H-bridge, high-side 1
18
H1
O
Gate voltage H-bridge, high-side 1
19
S2
I/O
Source voltage H-bridge, high-side 2
20
H2
O
Gate voltage H-bridge, high-side 2
21
VRES
I/O
Gate voltage for reverse protection NMOS, blocking capacitor 470nF/25V/X7R
22
CPHI
I
23
CPLO
O
Charge pump capacitor 220nF/25V/X7R
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3
Table 1-1.
2.
●
●
●
●
Symbol
I/O
Function
24
VG
I/O
Blocking capacitor 470nF/25V/X7R
25
PBAT
I
Power supply (after reverse protection) for charge pump and H-bridge
26
L2
O
Gate voltage H-bridge, low-side 2
27
L1
O
Gate voltage H-bridge, low-side 1
28
PGND
I
Power ground for H-bridge and charge pump
29
VCC
O
5V/100 mA supply for microcontroller, blocking capacitor 2.2µF/10V/X7R
30
VBAT
I
Supply voltage for IC core (after reverse protection)
31
VBATSW
O
100Ω PMOS switch from VVBAT
32
TP2
–
Test pin to be connected to GND
Parameter values given without tolerances are indicative only and not to be tested in production
Parameters given with tolerances but without a parameter number in the first column of parameter table are
“guaranteed by design” (mainly covered by measurement of other specified parameters). These parameters are not to
be tested in production. The tolerances are given if the knowledge of the parameter tolerances is important for the
application
The lowest power supply voltage is named GND
All voltage specifications are referred to GND if not otherwise stated
Sinking current means that the current is flowing into the pin (value is positive)
Sourcing current means that the current is flowing out of the pin (value is negative)
Related Documents
●
●
●
●
4
Pin
General Statement and Conventions
●
●
2.1
Pin Description (Continued)
Qualification of integrated circuits according to Atmel® HNO procedure based on AEC-Q100
AEC-Q100-004 and JESD78 (Latch-up)
ESD STM 5.1-1998
CEI 801-2 (only for information regarding ESD requirements of the PCB)
ATA6824C [DATASHEET]
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3.
Application
3.1
General Remark
This chapter describes the principal application for which the Atmel® ATA6824C was designed. Because Atmel cannot be
considered to understand fully all aspects of the system, application and environment, no warranties of fitness for a particular
purpose are given.
Table 3-1.
Typical External Components (See also Figure 1 on page 2)
Component
Function
Value
Tolerance
CVINT
Blocking capacitor at VINT
220nF, 10V, X7R
50%
CVCC
Blocking capacitor at VCC
2.2µF, 10V, X7R
50%
CCC
Cross conduction time definition capacitor
Typical 680pF, 100V, COG
RCC
Cross conduction time definition resistor
Typical 10kΩ
CVG
Blocking capacitor at VG
Typical 470nF, 25V, X7R
CCP
Charge pump capacitor
Typical 220nF, 25V, X7R
CVRES
Reservoir capacitor
Typical 470nF, 25V, X7R
RRWD
Watchdog time definition resistor
Typical 51kΩ
CSIO
Filter capacitor for SIO
Typical 220pF, 100V
4.
Functional Description
4.1
Power Supply Unit with Supervisor Functions
4.1.1
Power Supply
50%
The IC is supplied by a reverse-protected battery voltage. To prevent it from destruction, proper external protection circuitry
has to be added. It is recommended to use at least a capacitor combination of storage and HF caps behind the reverse
protection circuitry and closed to the VBAT pin of the IC (see Figure 1 on page 2).
An internal low-power and low drop regulator (VINT), stabilized by an external blocking capacitor, provides the necessary lowvoltage supply for all internal blocks except the digital IO pins. This voltage is also needed in the wake-up process. The lowpower band gap reference is trimmed and is used for the bigger VCC regulator, too. All internal blocks are supplied by the
internal regulator.
The internal supply voltage VINT must not be used for any other supply purpose!
Nothing inside the IC except the logic interface to the microcontroller is supplied by the 5V/3.3V VCC regulator.
A power-good comparator checks the output voltage of the VINT regulator and keeps the whole chip in reset as long as the
voltage is too low.
There is a high-voltage switch which brings out the battery voltage to the pin VBATSW for measurement purposes. This
switch is switched ON for VCC = HIGH and stays ON in case of a watchdog reset. The signal can be used to switch on
external voltage regulators, etc.
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4.1.2
Voltage Supervisor
This block is intended to protect the IC and the external power MOS transistors against overvoltage on battery level and to
manage undervoltage on it.
Function: in case of both overvoltage alarm (VTHOV) and of undervoltage alarm (VTHUV) the external NMOS motor bridge
transistors will be switched off. The failure state will be flagged via DG2. No other actions will be carried out. The
undervoltage comparator is connected to the pin VBAT while the overvoltage comparator is connected to pin PBAT. Both are
filtered by a first-order low pass with a corner frequency of typical 15kHz.
4.1.3
Temperature Supervisor
There is a temperature sensor integrated on-chip to prevent the IC from overheating due to a failure in the external circuitry
and to protect the external NMOSFET transistors.
In case of detected overtemperature (180°C), the diagnostic pin DG3 will be switched to “H” to signalize overtemperature
warning to the microcontroller. It should undertake actions to reduce the power dissipation in the IC. In case of detected
overtemperature (200°C), the VCC regulator and all drivers including the serial interface will be switched OFF immediately
and /RESET will go LOW.
Both temperature thresholds are correlated. The absolute tolerance is ±15K and there is a built-in hysteresis of about 10K to
avoid fast oscillations. After cooling down below the 170°C threshold; the IC will go into Active mode.
The occurrence of overtemperature shutdown is latched in DG3. DG3 stays on high until first WD trigger.
4.2
5V/3.3V VCC Regulator
The 5V/3.3V regulator is fully integrated on-chip. It requires only a 2.2µF ceramic capacitor for stability and has 100 mA
current capability. Using the VMODE pin, the output voltage can be selected to either 5V or 3.3V. Switching of the output
voltage during operation is not intended to be supported. The VMODE pin must be hard-wired to either VINT for 5V or to
GND for 3.3V. The logic HIGH level of the microcontroller interface will be adapted to the VCC regulator voltage.
The output voltage accuracy is in general < ±3%; in the 5V mode with VVBAT < 9V it is limited to < 5%.
To prevent destruction of the IC, the current delivered by the regulator is limited to maximum 100mA to 350mA. The
delivered voltage will break down and a reset may occur.
Please note that this regulator is the main heat source on the chip. The maximum output current at maximum battery voltage
and high ambient temperature can only guaranteed if the IC is mounted on an efficient heat sink.
A power-good comparator checks the output voltage of the VCC regulator and keeps the external microcontroller in reset as
long as the voltage is too low.
Figure 4-1. Voltage Dependence and Timing of VCC Controlled RESET
Tres
VCC
5V
VtHRES
/RESET
6
ATA6824C [DATASHEET]
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TdelayRESL
Figure 4-2. Correlation between VCC Output Voltage and Reset Threshold
VCC
5.15V
VCC1
4.9V
4.85V
Tracking voltage
VCC1-tHRESH
VtHRESH
4.1V
VCC1-VtHRESH = VCC1 - VtHRESH
The voltage difference between the regulator output voltage and the upper reset threshold voltage is bigger than 75mV
(VMODE = HIGH) and bigger than 50mV (VMODE = LOW).
4.3
Reset and Watchdog Management
The timing basis of the watchdog is provided by the trimmed internal oscillator. Its period TOSC is adjustable via the external
resistor RWD.
The watchdog expects a triggering signal (a rising edge) from the microcontroller at the WD input within a period time
window of TWD.
Figure 4-3. Timing Diagram of the Watchdog Function
tres
tresshort
/RESET
td
td
t1
t2
t1
t2
WD
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4.3.1
Timing Sequence
For example, with an external resistor RWD = 33 kΩ ±1% we get the following typical parameters of the watchdog.
TOSC = 12.32µs, t1 = 12.1ms, t2 = 9.61ms, TWD = 16.88ms ±10%
The times tres = 70ms and td = 70ms are fixed values with a tolerance of 10%.
After ramp-up of the battery voltage (power-on reset), the VCC regulator is switched on. The reset output, /RESET, stays low
for the time tres, then switches to high. For an initial lead time td (for setups in the controller) the watchdog waits for a rising
edge on WD to start its normal window watchdog sequence. If no rising edge is detected, the watchdog will reset the
microcontroller for tres and wait td for the rising edge on WD.
Times t1 (close window) and t2 (open window) form the window watchdog sequence. To avoid receiving a reset from the
watchdog, the triggering signal from the microcontroller must hit the timeframe of t2 = 9.61ms. The trigger event will restart
the watchdog sequence.
Figure 4-4. TWD versus RWD
60
TWD (ms)
50
typ
max
40
30
min
20
10
0
0
20
30
40
50
60
70
80
90
100
RWD (kΩ)
If triggering fails, /RESET will be pulled to ground for a shortened reset time of typically 2ms. The watchdog start sequence
is similar to the power-on reset.
The internal oscillator is trimmed to a tolerance of < ±10%. This means that t1 and t2 can also vary by ±10%. The following
calculation shows the worst case calculation of the watchdog period Twd which the microcontroller has to provide.
t1min = 0.90 × t1 = 10.87ms, t1max = 1.10 × t1 = 13.28ms
t2min = 0.90 × t2 = 8.65ms, t2max = 1.10 × t2 = 10.57ms
Twdmax = t1min + t2min = 10.87ms + 8.65ms = 19.52ms
Twdmin = t1max = 13.28ms
Twd = 16.42ms ±3.15ms (±19.1%)
Figure 4-4 on page 8 shows the typical watchdog period TWD depending on the value of the external resistor ROSC.
A reset will be active for VCC < VtHRESx; the level VtHRESx is realized with a hysteresis (HYSRESth).
8
ATA6824C [DATASHEET]
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4.4
High Voltage Serial Interface
A bi-directional bus interface is implemented for data transfer between hostcontroller and the local microcontroller (SIO).
The transceiver consists of a low side driver (1.2V at 40mA) with slew rate control, wave shaping, current limitation, and a
high-voltage comparator followed by a debouncing unit in the receiver.
4.4.1
Transmit Mode
During transmission, the data at the pin TX will be transferred to the bus driver to generate a bus signal on pin SIO. The pin
TX has a pull-down resistor included.
To minimize the electromagnetic emission of the bus line, the bus driver has an integrated slew rate control and waveshaping unit. In transmit mode, transmission will be interrupted in case of overheating at the SIO driver.
4.4.2
Reset Mode
In case of an active reset shown at pin /RESET the pin SIO is switched to low, independent of the temperature. The
maximum current is limited to ISIO_LIM_RESET.
Figure 4-5. Definition of Bus Timing Parameters
tBit
tBit
tBit
TX
(input to transmitting Node)
tSIO_dom(max)
tSIO_rec(min)
Thresholds of
receiving node 1
THRec(max)
VVBAT
(Transceiver
supply
of transmitting
node)
THDom(max)
SIO Signal
Thresholds of
receiving node 2
THRec(min)
THDom(min)
tSIO_dom(min)
tSIO_rec(max)
RX
(output of receiving Node 1)
trx_pdf(1)
trx_pdr(1)
RX
(output of receiving Node 2)
trx_pdr(2)
trx_pdf(2)
The recessive BUS level is generated from the integrated 30 kΩ pull-up resistor in series with an active diode. This diode
prevents the reverse current of VBUS during differential voltage between VSUP and BUS (VBUS > VSUP).
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4.5
Control Inputs DIR and PWM
4.5.1
Pin DIR
Logical input to control the direction of the external motor to be controlled by the IC. An internal pull-down resistor is
included.
4.5.2
Pin PWM
Logical input for PWM information delivered by external microcontroller. Duty cycle and frequency at this pin are passed
through to the H-bridge. An internal pull-down resistor is included.
Table 4-1.
Status of the IC Depending on Control Inputs and Detected Failures
Control Inputs
ON
DIR
0
1
1
Driver Stage for External Power MOS
H2
Comments
PWM
H1
L1
L2
X
X
OFF
OFF
OFF
OFF
DG1, DG2 fault or RESET
0
PWM
ON
OFF
/PWM
PWM
Motor PWM forward
1
PWM
/PWM
PWM
ON
OFF
Motor PWM reverse
The internal signal ON is high when
● At least one valid WD trigger has been accepted
●
●
●
●
No short circuit detected
VPBAT is inside the specified range (VPBAT_OV ≤ VPBAT ≤ VTHOV)
VVBAT is higher than VTHUV
The device temperature is not above shutdown threshold
In case of a short circuit, the appropriate transistor is switched off after a blanking time of tSC . In order to avoid cross current
through the bridge, a cross conduction timer is implemented. Its time constant is programmable by means of an RC
combination.
Table 4-2.
Status of the Diagnostic Outputs
Device Status
PBAT_UV
SC
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
Note:
10
VBAT_UV PBAT_OV
Diagnostic Outputs
CPOK
OT
DG1
DG2
DG3
X
1
–
–
1
Overtemperature warning
X
0
X
0
1
–
Charge pump failure
1
X
X
0
1
–
Overvoltage PBAT
1
X
X
X
0
1
–
Undervoltage VBAT
0
0
1
X
1
0
–
Short circuit
1
1
–
Undervoltage PBAT
0
0
0
1
X represents: don’t care – no effect)
PBAT_UV: Undervoltage PBAT pin
SC: Short circuit drain source monitoring
VBAT_UV: Undervoltage of VBAT pin
PBAT_OV: Overvoltage of PBAT pin
CPOK: Charge pump OK
OT: Overtemperature warning
ATA6824C [DATASHEET]
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Comments
X
– Status of the diagnostic outputs depends on device status
4.6
VG Regulator
The VG regulator is used to generate the gate voltage for the low-side driver. Its output voltage will be used as one input for
the charge pump, which generates the gate voltage for the high-side driver. The purpose of the regulator is to limit the gate
voltage for the external power MOS transistors to 12V. It needs a ceramic capacitor of 470nF for stability. The output voltage
is reduced if the supply voltage at VBAT falls below 12V.
4.7
Charge Pump
The integrated charge pump is needed to supply the gates of the external power MOS transistors. It needs a shuffle
capacitor of 220nF and a reservoir capacitor of 470nF. Without load, the output voltage on the reservoir capacitor is VVBAT
plus VG. The charge pump is clocked with a dedicated internal oscillator of 100KHz. The charge pump is designed to reach
a good EMC level. The charge pump will be switched off for VVBAT > VTHOV.
4.8
Thermal Shutdown
There is a thermal shutdown block implemented. With rising junction temperature, a first warning level will be reached at
180°C. At this point the IC stays fully functional and a warning will be sent to the microcontroller. At junction temperature
200°C the drivers for H1, H2, L1, L2, SIO and the VCC regulator will be switched off and a reset occurs.
4.9
H-bridge Driver
The IC includes two push-pull drivers for control of two external power NMOS used as high-side drivers and two push-pull
drivers for control of two external power NMOS used as low-side drivers. The drivers are able to be used with standard and
logic-level power NMOS.
The drivers for the high-side control use the charge pump voltage to supply the gates with a voltage of VG above the battery
voltage level. The low-side drivers are supplied by VG directly. It is possible to control the external load (motor) in the
forward and reverse direction (see Table 4-1 on page 10). The duty cycle of the PMW controls the speed. A duty cycle of
100% is possible in both directions.
4.9.1
Cross Conduction Time
To prevent high peak currents in the H-bridge, a non-overlapping phase for switching the external power NMOS is realized.
An external RC combination defines the cross conduction time in the following way:
tCC (µs) = 0.41 × RCC (kΩ) × CCC (nF) (tolerance: ±5% ±0.15µs)
The RC combination is charged to 5V and the switching level of the internal comparator is 67% of the start level.
The resistor RCC must be greater than 5kΩ and should be as close as possible to 10kΩ, the CCC value has to be ≤ 5nF. Use
of COG capacitor material is recommended.
The time measurement is triggered by the PWM or DIR signal crossing the 50% level.
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Figure 4-6. Timing of the Drivers
PWM or
DIR
50%
t
tLxHL
tLxf
tLxLH
tLxr
80%
tCC
Lx
20%
t
tHxLH
tCC
tHxr
tHxHL
tHxf
80%
Hx
20%
t
The delays tHxLH and tLxLH include the cross conduction time tCC.
4.10
Short Circuit Detection
To detect a short in H-bridge circuitry, internal comparators detect the voltage difference between source and drain of the
external power NMOS. If the transistors are switched ON and the source-drain voltage difference is higher than the value
VSC (4V with tolerances) the diagnosis pin DG1 will be set to ‘H’ and the drivers will be switched off. All gate driver outputs
(Hx and Lx) will be set to ‘L’. Releasing the gate driver outputs will set DG1 back to ‘L’. With the next transition on the pin
PWM, the corresponding drivers, depending on the DIR pin, will be switched on again.
There is a PBAT supervision block implemented to detect the possible voltage drop on PBAT during a short circuit. If the
voltage at PBAT falls under VPBAT_OK the drivers will be switched off and DG1 will be set to “H”. It will be cleared as soon as
the PBAT undervoltage condition disappears.
The detection of drain source voltage exceedances is activated after the short circuit blanking time tSC, the short circuit
detection of PBAT failures operates immediately.
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5.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Pin Description
Pin Name
Min
Max
Unit
GND
0
0
V
Power ground
PGND
–0.3
+0.3
V
Reverse protected battery voltage
VBAT
Reverse current out of pin
VBAT
Reverse protected battery voltage
PBAT
Reverse current out of pin
PBAT
–20
Digital output
/RESET
–0.3
VVCC + 0.3
V
Digital output
DG1, DG2, DG3
–0.3
VVCC + 0.3
V
4.9V output, external blocking capacitor
VINT
–0.3
+5.5
V
Cross conduction time capacitor/resistor
combination
CC
–0.3
VVCC + 0.3
V
Digital input coming from microcontroller
WD
–0.3
VVCC + 0.3
V
RWD
–0.3
VVCC + 0.3
V
DIR
–0.3
VVCC + 0.3
V
Digital input PWM control + Test mode
PWM
–0.3
VVCC + 0.3
V
5V regulator output
VCC
–0.3
+5.5
V
VMODE
–0.3
VVINT + 0.3
V
+16
V
Ground
Watchdog timing resistor
Digital input direction control
Digital input
+40
V
–1
mA
+40
V
mA
12V output, external blocking capacitor
VG
Digital output
RX
–0.3
VVCC + 0.3
V
Digital input
TX
–0.3
VVCC + 0.3
V
Serial interface data pin
SIO
–27
VVBAT + 2
V
Source external high-side NMOS
S1, S2
(–2)
+30
+40(3)
V
Gates external low-side NMOS
L1, L2
VPGND – 0.3
(2)
V
(2)
V
Gates of external high-side NMOS
H1, H2
Charge pump
CPLO
VPBAT + 0.3
V
Charge pump
CPHI
VVRES + 0.3
V
Charge pump output
VRES
+40(4)
V
VVBAT + 0.3
V
Switched VBAT
Power dissipation
Storage temperature
Reverse current
Notes:
1.
VBATSW
x = 1.2
3.
t < 0.5s
4.
Load dump of t < 0.5s tolerated
–0.3
Ptot
VSx + 16
(1)
1.4
W
+150
°C
ϑSTORE
–55
CPLO, CPHI, VG,
VRES, Sx
–2
mA
–1
mA
Lx, Hx
May be additionally limited by external thermal resistance
2.
VSx – 1
VVG + 0.3
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6.
Thermal Resistance
Parameters
Symbol
Value
Unit
Thermal resistance junction to heat slug
Rthjc
<5
K/W
Thermal resistance junction to ambient when heat
slug is soldered to PCB
Rthja
25
K/W
7.
Operating Range
The operating conditions define the limits for functional operation and parametric characteristics of the device. Functionality outside
these limits is not implied unless otherwise stated explicitly.
Parameters
Symbol
Min
Max
Unit
(1)
VVBAT1
VTHUV
VTHOV
V
(2)
Operating supply voltage
VVBAT2
6
< VTHUV
V
Operating supply voltage(3)
VVBAT3
4.5
<6
V
(4)
VVBAT4
0
< 4.5
V
(5)
VVBAT5
> VTHOV
40
V
Junction temperature range under bias
Tj
–40
+200
°C
Normal functionality
Ta
–40
+150
°C
Normal functionality, overtemperature warning set
Tj
165
195
°C
Tj
185
215
°C
Operating supply voltage
Operating supply voltage
Operating supply voltage
Switch-off temperatures of drivers for H1, H2, L1,
L2, SIO and of VCC regulator
Notes: 1. Full functionality
2. H-bridge drivers are switched off (undervoltage detection)
3. H-bridge drivers are switched off, 5V/3.3V regulator with reduced parameters, RESET works correctly
4. H-bridge drivers are switched off, 5V regulator not working, RESET not correct
5. H-bridge drivers are switched off
8.
Noise and Surge Immunity
Parameters
Test Conditions
Value
Conducted interferences
ISO 7637-1
Level 4(1)
Interference suppression
IEC-CISPR25
Level 5
ESD S 5.1
2kV
ESD STM5.3.
500V
ESD (Human Body Model)
CDM (Charge Device Model)
Note:
1. Test pulse 5: Vvbmax = 40V
14
ATA6824C [DATASHEET]
9212G–AUTO–09/13
9.
Electrical Characteristics
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise.
No.
1
Parameters
Test Conditions
Pin
Symbol
25, 30
IVBAT1
Min
Typ
Max
Unit
Type*
7
mA
A
5.1
V
A
V
A
Power Supply and Supervisor Functions
1.1
Current consumption VVBAT VVBAT = 13.5V(1)
1.2
Internal power supply
2
VINT
1.3
Band gap voltage
3
VBG
1.4
Overvoltage threshold Up
VPBAT
25
VTHOV_UP
21.2
22.7
V
A
1.4.1
Overvoltage threshold
Down VPBAT
25
VTHOV_DOWN
19.7
21.3
V
A
1.5
Overvoltage threshold
hysteresis VPBAT
25
VTOVhys
1
2.4
V
A
1.6
Undervoltage threshold Up
VVBAT
30
VTHUV_UP
6.8
7.4
V
A
1.6.1
Undervoltage threshold
Down VVBAT
30
VTHUV_DOWN
6.5
7.0
V
A
1.7
Undervoltage threshold
hysteresis VVBAT
Measured during
qualification only
30
VTUVhys
0.2
0.6
V
A
1.8
On resistance of VVBAT
switch
VVBAT = 13.5V
31
RON_VBATSW
100
Ω
A
1.9
Undervoltage threshold
PBAT
VVBAT = 13.5V
25
VPBAT_OK
6.1
7
V
A
1.10
Undervoltage threshold
hysteresis PBAT
VVBAT = 13.5V
25
VPBAT_OK_HYST
0
100
mV
A
2
4.8
4.94
1.235
5V/3.3V Regulator
2.1
Regulated output voltage
9V < VVBAT < 40V,
Iload = 0mA to 100mA
29
VCC1
4.85 (3.2)
5.15 (3.4)
V
A
2.2
Regulated output voltage
6V < VVBAT ≤ 9V
Iload = 0mA to 100mA
29
VCC2
4.75 (3.2)
5.25 (3.4)
V
A
2.2a Regulated output voltage
6V < VVBAT ≤ 9V
Iload = 0mA to 80mA
Ta > 125°C
29
VCC2
4.75 (3.2)
5.25 (3.4)
V
A
2.3
Iload = 0mA to 100mA
29
DC line
regulation
50
mV
A
Line regulation
<1
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on T100; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 4.9.1 “Cross Conduction Time” on page 11
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
11. See Figure 4-5 on page 9 “Definition of Bus Timing Parameters”
ATA6824C [DATASHEET]
9212G–AUTO–09/13
15
9.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise.
No.
Parameters
Test Conditions
Pin
Symbol
2.4
Load regulation
Iload = 0mA to 100mA
29
DC load
regulation
2.5
Output current limitation
VVBAT > 6V
29
IOS1
2.6
Serial inductance to CVCC
including PCB
29
2.7
Serial resistance to CVCC
including PCB
2.8
Blocking cap at VCC
Typ
Max
Unit
Type*
<10
50
mV
A
100
350
mA
A
ESL
1
20
nH
D
29
ESR
0
0.5
Ω
D
29
CVCC
1.1
3.3
µF
D
2.9
HIGH threshold VMODE
1
VMODE H
4.0
V
A
2.10 LOW threshold VMODE
1
VMODE L
0.7
V
A
3
(2), (3)
Min
VG Regulator
3.1
Regulated output voltage
VPBAT ≥ 14V
Imax = 20mA
24
VVG
11
14
V
A
3.2
Regulated output voltage
VPBAT = 9V
Imax = 20mA
24
VVG
7.0
9.0
V
A
VCC threshold voltage level VMODE = “H”
for /RESET
(VMODE = “L”)
29
VtHRESH
V
A
Tracking of reset thres-hold
VMODE = “H”
4.1a with regulated output
(VMODE = “L”)
voltage
29
VVCC1-VtHRESH
75
(50)
mV
A
4.2
VCC threshold voltage level VMODE = “H”
for /RESET
(VMODE = “L”)
29
VtHRESL
4.3 (2.86)
V
A
4.3
Hysteresis of /RESET level
29
HYSRESth
70
mV
A
4.4
Length of pulse at /RESET
(5)
pin
5
tres
7000
T100
A
4.5
Length of short pulse at
/RESET pin
(5)
5
tresshort
200
T100
A
4.6
Wait for the first WD trigger (5)
5
td
7000
T100
A
4.7
Time for VCC < VtHRESL
before activating /RESET
29
tdelayRESL
µs
C
4
4.1
Reset and Watchdog
VMODE = “H”
(VMODE = “L”)(4)
(4)
4.8 (3.15)
200
0.5
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on T100; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 4.9.1 “Cross Conduction Time” on page 11
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
11. See Figure 4-5 on page 9 “Definition of Bus Timing Parameters”
16
ATA6824C [DATASHEET]
9212G–AUTO–09/13
350
(240)
2
9.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise.
No.
Parameters
4.8
Test Conditions
Pin
Symbol
Min
Resistor defining internal
bias currents for watchdog
oscillator
3
RRWD
4.9
Watchdog oscillator period RRWD = 33kΩ
3
TOSC
4.11
Watchdog input
low-voltage threshold
6
VILWD
4.12
Watchdog input
high-voltage threshold
6
VIHWD
0.7 ×
VVCC
4.13
Hysteresis of watchdog
input voltage threshold
6
VhysWD
0.3
Typ
Max
Unit
Type*
10
91
kΩ
D
11.09
13.55
µs
A
0.3 ×
VVCC
V
A
V
A
V
A
0.8
4.14 Close window
(5)
6
t1
980 ×
TOSC
A
4.15 Open window
(5)
6
t2
780 ×
TOSC
A
At IOLRES = 1mA
5
VOLRES
5
RPURES
5
4.16
Output low-voltage of
/RESET
4.17
Internal pull-up resistor at
pin /RESET
5
10
0.4
V
A
15
kΩ
A
High Voltage Serial Interface
5.1
Low-level output current
Normal mode;
VSIO = 0V, VRX = 0.4V
13
ILRX
2
mA
A
5.2
High-level output current
Normal mode; VSIO = VVBAT
VRX = VCC – 0.4V
13
IHRX
0.8
mA
A
5.4
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVBAT = 7.3V
Rload = 500Ω
8
V_LoSUP
1.2
V
A
5.5
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVBAT = 18V
Rload = 500Ω
8
V_HiSUP
2
V
A
5.6
Driver dominant voltage
VBUSdom_DRV_LoSUP
VVBAT = 7.3V
Rload = 1000Ω
8
V_LoSUP_1k
0.6
V
A
5.7
Driver dominant voltage
VBUSdom_DRV_HiSUP
VVBAT = 18V
Rload = 1000Ω
8
V_HiSUP_1k_
0.8
V
A
5.8
Pull up resistor to VBAT
The serial diode is
mandatory
8
RSIO
20
60
kΩ
A
5.9
Current limitation
VSIO = VBAT_max
8
ISIO_LIM
40
250
mA
A
30
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on T100; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 4.9.1 “Cross Conduction Time” on page 11
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
11. See Figure 4-5 on page 9 “Definition of Bus Timing Parameters”
ATA6824C [DATASHEET]
9212G–AUTO–09/13
17
9.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise.
No.
Parameters
5.9a
Pin
Symbol
Min
Current limitation in case of VSIO = VBAT_max
RESET and SIO overheat RESET = high
8
ISIO_LIM_RESET
30
Input leakage current
Input leakage current at the
driver off
5.10 receiver including pull-up
VSIO = 0V
resistor as specified
VVBAT = 12V
8
ISIO_PAS_dom
–1
8
ISIO_PAS_rec
Leakage current at ground
loss
Control unit disconnected GNDDevice = VVBAT
5.12 from ground
VVBAT =12V
Loss of local ground must 0V < VSIO < 18V
not affect communication in
the residual network
8
ISIO_NO_gnd
Node has to sustain the
current that can flow under VVBAT disconnected
5.13 this condition. Bus must
VSUP_Device = GND
remain operational under 0V < VSIO < 18V
this condition
8
ISIO
VSIO_CNT =
(Vth_dom + Vth_rec)/2
8
VSIO_CNT
5.15 Receiver dominant state
VEN = 5V
8
VSIOdom
5.16 Receiver recessive state
VEN = 5V
8
VSIOrec
5.17 Receiver input hysteresis
VHYS = Vth_rec – Vth_dom
8
VSIOhys
5.18 Duty cycle 1
THRec(max) = 0.744 × VVBAT
THDom(max) = 0.581 × VVBAT
VVBAT = 7V to 18V
tBit = 50µs
D1 = tsio_rec(min) / 2 × tBit(11)
8
D1
Leakage current SIO
5.11
recessive
5.14
Center of receiver
threshold
Test Conditions
Driver off
8V < VVBAT < 18V
8V < VSIO < 18V
VSIO ≥ VVBAT
Typ
Max
Unit
Type*
100
mA
A
mA
A
30
µA
A
1
mA
A
100
µA
A
0.525 ×
VVBAT
V
A
0.4 ×
VVBAT
V
A
V
A
V
A
–1
0.475 ×
VVBAT
0.5 ×
VVBAT
0.6 ×
VVBAT
0.1 ×
VVBAT
0.175 ×
VVBAT
0.380
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on T100; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 4.9.1 “Cross Conduction Time” on page 11
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
11. See Figure 4-5 on page 9 “Definition of Bus Timing Parameters”
18
ATA6824C [DATASHEET]
9212G–AUTO–09/13
A
9.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise.
No.
Parameters
5.19 Duty cycle 2
Test Conditions
Pin
Symbol
THRec(min) = 0.422 × VVBAT
THDom(min) = 0.284 × VVBAT
VVBAT = 7V to 18V
tBit = 50µs
D2 = tsio_rec(max) / 2 × tBit(11)
8
D2
0.600
6
µs
A
+2
µs
A
0.3 ×
VVCC
V
A
V
A
5.20
Propagation delay of
receiver
trec_pd = max(trx_pdr, trx_pdf)(11)
7V < VVBAT < 18V
8
trx_pd
5.21
Symmetry of receiver
propagation delay
trx_sym = trx_pdr – trx_pdf(11)
7V < VVBAT < 18V
8
trx_sym
6
Min
Typ
Max
–2
Unit
Type*
A
Control Inputs DIR, PWM, WD, TX
6.1
Input low-voltage threshold
10, 11,
6, 9
VIL
6.2
Input high-voltage
threshold
10, 11,
6, 9
VIH
0.7 ×
VVCC
6.3
Hysteresis
10, 11,
6, 9
HYS
0.3
0.5
0.8
V
A
6.4
Pull-down resistor
10, 11,
6, 9
RPD
25
50
140
kΩ
A
6.5
Rise/fall time
10, 11,
6, 9
trf
100
ns
A
7
Charge Pump
VVBAT
+ VVG
V
A
V
A
11
µs
A
DIR, PWM, WD, TX
7.1
Charge pump voltage
Load = 0A
21
VCP
7.2
Charge pump voltage
Load = 3mA,
CCP = 100nF
21
VCP
VVBAT
+ VVG – 1
7.3
Period charge pump
oscillator
21
T100
9
7.4
CP load current in VG
without CP load
21
IVGCPz
600
µA
A
7.5
CP load current in VG with Load = 3mA,
CP load
CCP = 100nF
21
IVGCP
4
mA
A
7.6
Charge pump OK threshold
Reference: PBAT
UP
21
VCPOK_UP
6.3
V
A
Load = 0A
5.3
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on T100; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 4.9.1 “Cross Conduction Time” on page 11
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
11. See Figure 4-5 on page 9 “Definition of Bus Timing Parameters”
ATA6824C [DATASHEET]
9212G–AUTO–09/13
19
9.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise.
No.
Parameters
Test Conditions
Pin
Symbol
Min
7.7
Charge pump OK threshold
Reference: PBAT
DOWN
21
VCPOK_DOWN
7.8
Charge pump OK
hysteresis
21
8
Typ
Max
Unit
Type*
4.5
5.5
V
A
VCPOK_HYS
0.3
1.3
V
A
VVG
– 0.5V
VVG
V
A
H-bridge Driver
8.1
Low-side driver HIGH
output voltage
26, 27
VLxH
8.2
ON-resistance of sink
stage of pins L1, L2
26, 27
RDSON_LxL,
x = 1, 2
25
Ω
A
8.3
ON-resistance of source
stage of pins L1, L2
26, 27
RDSON_LxH,
x = 1, 2
25
Ω
A
8.4
Output peak current at pins
VLx = 3V
L1, L2, switched to LOW
26, 27
ILxL,
x = 1, 2
mA
A
8.5
Output peak current at pins
VLx = 3V
L1, L2, switched to HIGH
26, 27
ILxH,
x = 1, 2
–100
mA
A
8.6
Ohmic pull-down
resistance at pins L1, L2
Designed for
0V < VVBAT < 40V
26, 27
RPDLx
x = 1, 2
140
kΩ
A
8.7
ON-resistance of sink
stage of pins H1, H2
VSx = 0
18, 20
RDSON_HxL,
x = 1, 2
25
Ω
A
8.8
ON-resistance of source
stage of pins H1, H2
VSx = VVBAT
18, 20
RDSON_HxH,
x = 1, 2
25
Ω
A
8.9
V
= 13.5V
Output peak current at pins VBAT
VSx = VVBAT
Hx, switched to LOW
VHx = VVBAT + 3V
18, 20
IHxL,
x = 1, 2
mA
A
8.10
V
= 13.5V
Output peak current at pins VBAT
VSx = VVBAT
Hx, switched to HIGH
VHx = VVBAT + 3V
18, 20
IHxH,
x = 1, 2
–100
mA
A
8.11
Static switch output low
voltage at pins Hx and Lx
VSx = 0V
IHx = 1mA, ILx = 1mA
18, 20,
26, 27
VHxL, VLxL
x = 1, 2
0.3
V
A
ILx = –10µA
(PWM = static)
18, 20
VHxHstat1(7)
VVBAT +
VVG – 1
VVBAT +
VVG
V
A
Designed for
0V < VVBAT < 40V
17, 18,
19, 20
RPDHx
25
140
kΩ
A
Static high-side switch
8.12 output high-voltage pins
H1, H2
8.13
Ohmic sink resistance
between pins Hx and Sx
100
25
100
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on T100; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 4.9.1 “Cross Conduction Time” on page 11
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
11. See Figure 4-5 on page 9 “Definition of Bus Timing Parameters”
20
ATA6824C [DATASHEET]
9212G–AUTO–09/13
9.
Electrical Characteristics (Continued)
All parameters given are valid for VTHUV ≤ VVBAT ≤ VTHOV and for –40°C ≤ ϑambient ≤ 150°C unless stated otherwise.
No.
Parameters
Test Conditions
Pin
Symbol
Propagation delay time,
Figure 4-6 on page 12
8.15 low-side driver from high to
VVBAT = 13.5V
low
26, 27
Propagation delay time,
8.16 low-side driver from low to VVBAT = 13.5V
high
8.17 Fall time low-side driver
Min
Typ
Max
Unit
Type*
tLxHL
0.5
µs
A
26, 27
tLxLH
0.5 + tCC
µs
A
VVBAT = 13.5V
CGx = 5nF
26, 27
tLxf
0.5
µs
A
8.18 Rise time low-side driver
VVBAT = 13.5V
26, 27
tLxr
0.5
µs
A
Propagation delay time,
8.19 high-side driver from high
to low
Figure 4-6 on page 12
VVBAT = 13.5V
18, 20
tHxHL
0.5
µs
A
Propagation delay time,
8.20 high-side driver from low to VVBAT = 13.5V
high
18, 20
tHxLH
0.5 + tCC
µs
A
8.21 Fall time high-side driver
VVBAT = 13.5V,
CGx = 5nF
18, 20
tHxf
0.5
µs
A
8.22 Rise time high-side driver
VVBAT = 13.5V
Dynamic Parameters
18, 20
tHxr
8.24 External resistor
4
RCC
8.25 External capacitor
4
CCC
4
RONCC
4
tCC
3.75
17, 19
VSC
3.5
17, 19
tSC
5
8.26
RON of tCC switching
transistor
8.27 Cross conduction time(8)
8.28
Short circuit detection
voltage
RCC = 10kΩ
CCC = 1nF
(9)
8.29 Short circuit blanking time (10)
9
0.5
µs
A
kΩ
D
5
nF
D
200
Ω
A
4.45
µs
A
4
4.7
V
A
10
15
µs
A
5
Diagnostic Outputs DG1, DG2, DG3
9.1
Low level output current
VDG = 0.4V(6)
14, 15,
16
IL
2
mA
A
9.2
High level output current
VDG = VCC – 0.4V(6)
14, 15,
16
IH
0.8
mA
A
* Type: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes:
1.
DIR, PWM = high
2.
The use of X7R material is recommended
3.
For higher values, stability at zero load is not guaranteed
4.
Tested during qualification only
5.
Value depends on T100; function tested with digital test pattern
6.
Tested during characterization only
7.
Supplied by charge pump
8.
See Section 4.9.1 “Cross Conduction Time” on page 11
9.
Voltage between source-drain of external switching transistors in active case
10. The short-circuit message will never be generated for switch-on time < tsc
11. See Figure 4-5 on page 9 “Definition of Bus Timing Parameters”
ATA6824C [DATASHEET]
9212G–AUTO–09/13
21
10.
Ordering Information
Extended Type Number
ATA6824C-MFHW
11.
Package
Remarks
TPQFP32, 7mm × 7mm
Pb-free
Package Information
D
D1
32
technical drawings
according to DIN
specifications
25
24
8
17
Dimensions in mm
E
E1
e
1
9
16
b
A2
A1
L
A
COMMON DIMENSIONS
(Unit of Measure = mm)
Symbol
MIN
NOM
MAX
A
E2
A1
A2
0.05
0.95
D2
D
9 BSC
7 BSC
D2
3.5 BSC
E
9 BSC
E1
7 BSC
E2
L
3.5 BSC
0.6
b
e
32
0.15
1.05
1
D1
0.45
N
1
NOTE
1.2
0.75
32
0.3
0.37
0.45
0.8 BSC
11/25/08
TITLE
Package Drawing Contact:
[email protected]
22
ATA6824C [DATASHEET]
9212G–AUTO–09/13
Package: epad TPQFP32
(acc. JEDEC OUTLINE)
GPC
DRAWING NO.
REV.
6.543-5157.01-4
1
12.
Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
9212G-AUTO-09/13
9212F-AUTO-04/12
9212E-AUTO-01/12
History
• Section 11 “Package Information” on page 22 updated
• Section 5 “Absolute Maximum Ratings” on page 13 changed
• Section 9 “Electrical Characteristics” number 4.1 on page 16 changed
• QFN32 package variant on all pages removed
• Figure 5-5 “Definition of Bus Timing Parameters” on page 9 changed
9212D-AUTO-11/11
• Section 6 “Absolute Maximum Ratings” on page 13 changed
• Section 10 “Electrical Characteristics” numbers 5.12, 5.14, 5.15, 5.16 and 5.17 on page 18
changed
• Section 5.1.2 “Voltage Supervisor” on page 6 changed
9212C-AUTO-09/11
• Section 5.5.2 “Pin PWM” on page 10 changed
• Section 10 “Electrical Characteristics” numbers 1.4, 1.4.1 and 1.5 on page 15 changed
9212B-AUTO-04/11
• Section 10 “Electrical Characteristics” numbers 8.6 and 8.13 on page 20 changed
ATA6824C [DATASHEET]
9212G–AUTO–09/13
23
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© 2014 Atmel Corporation. / Rev.: Rev.: 9212G–AUTO–09/13
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