Maxim MAX1446 10-bit, 60msps, 3.0v, low-power adc with internal reference Datasheet

19-1729; Rev 4; 11/08
KIT
ATION
EVALU
E
L
B
A
AVAIL
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
The MAX1446 10-bit, 3V analog-to-digital converter
(ADC) features a fully differential input, a pipelined 10stage ADC architecture with digital error correction and
wideband track and hold (T/H) incorporating a fully differential signal path. This ADC is optimized for lowpower, high dynamic performance applications in
imaging and digital communications. The MAX1446
operates from a single 2.7V to 3.6V supply, consuming
only 90mW while delivering a 59.5dB signal-to-noise
ratio (SNR) at a 20MHz input frequency. The fully differential input stage has a 400MHz, -3dB bandwidth and
may be operated with single-ended inputs. In addition
to low operating power, the MAX1446 features a 5µA
power-down mode for idle periods.
An internal 2.048V precision bandgap reference is used
to set the ADC full-scale range. A flexible reference
structure allows the user to supply a buffered, direct or
externally derived reference for applications requiring
increased accuracy or a different input voltage range.
Lower and higher speed, pin-compatible versions of
the MAX1446 are also available. Refer to the MAX1444
data sheet for a 40Msps version, the MAX1448 data
sheet for an 80Msps version, and the MAX1449 data
sheet for a 105Msps version.
The MAX1446 has parallel, offset binary, three-state
outputs that can be operated from 1.7V to 3.3V to allow
flexible interfacing. The device is available in a 5mm x
5mm, 32-pin TQFP package and is specified over the
extended industrial (-40°C to +85°C) and automotive
(-40°C to +105°C) temperature ranges.
Features
o Single 3.0V Operation
o Excellent Dynamic Performance
59.5dB SNR at fIN = 20MHz
73dB SFDR at fIN = 20MHz
o Low Power:
30mA (Normal Operation)
5µA (Shutdown Mode)
o Fully Differential Analog Input
o Wide 2VP-P Differential Input Voltage Range
o 400MHz -3dB Input Bandwidth
o On-Chip 2.048V Precision Bandgap Reference
o CMOS-Compatible Three-State Outputs
o 32-Pin TQFP Package
o Evaluation Kit Available (MAX1448 EV Kit)
Ordering Information
PART
TEMP RANGE
PINPACKAGE
MAX1446EHJ+
-40°C to +85°C
32 TQFP
MAX1446GHJ+
-40°C to +105°C
32 TQFP
+Denotes a lead(Pb)-free/RoHS-compliant package.
________________________Applications
Functional Diagram
Ultrasound Imaging
CCD Imaging
Baseband and IF Digitization
CLK
VDD
MAX1446
Digital Set-Top Boxes
GND
CONTROL
Video Digitizing Applications
IN+
T/H
PIPELINE ADC
IN-
Pin-Compatible,
Lower/Higher Speed Versions
PART
SAMPLING SPEED (Msps)
MAX1444
40
MAX1448
80
MAX1449
105
PD
REF
D
E
C
10
OUTPUT
DRIVERS
OVDD
REF SYSTEM +
BIAS
REFOUT REFIN REFP COM REFN
D9–D0
OGND
OE
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1
MAX1446
General Description
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
ABSOLUTE MAXIMUM RATINGS
VDD, OVDD to GND ...............................................-0.3V to +3.6V
OGND to GND.......................................................-0.3V to +0.3V
IN+, IN- to GND........................................................-0.3V to VDD
REFIN, REFOUT, REFP,
REFN, and COM to GND.........................-0.3V to (VDD + 0.3V)
OE, PD, CLK to GND..................................-0.3V to (VDD + 0.3V)
D9–D0 to GND.........................................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
32-Pin TQFP (derate 18.7mW/°C above +70°C)......1495.3mW
Operating Temperature Ranges:
MAX1446EHJ+ .................................................-40°C to +85°C
MAX1446GHJ+...............................................-40°C to +105°C
Storage Temperature Range ............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DC ACCURACY
Resolution
10
Bits
Integral Nonlinearity
INL
fIN = 7.492MHz, TA ≥ +25°C
±0.6
±1.9
LSB
Differential Nonlinearity
DNL
No missing codes, fIN = 7.492MHz
±0.4
±1.0
LSB
< ±0.1
±1.9
% FS
0
±2.0
% FS
Offset Error
-1.6
TA ≥ +25°C
Gain Error
ANALOG INPUT
Input Differential Range
Common-Mode Voltage Range
VDIFF
Differential or single-ended inputs
VCOM
Input Resistance
RIN
Input Capacitance
CIN
Switched capacitor load
±1.0
V
VDD/2
± 0.5
V
33
kΩ
5
pF
5.5
Cycles
CONVERSION RATE
Maximum Clock Frequency
fCLK
60
Data Latency
MHz
DYNAMIC CHARACTERISTICS
Signal-to-Noise Ratio
SNR
fIN = 7.492MHz
57
59.5
fIN = 19.943MHz
56.5
59.5
fIN = 39.9MHz (Note 1)
Signal-to-Noise + Distortion
(Up to 5th Harmonic)
SINAD
fIN = 7.492MHz
56.6
fIN = 19.943MHz
56.2
fIN = 39.9MHz (Note 1)
Spurious-Free Dynamic
Range
SFDR
2
59.4
59
dB
58.5
fIN = 7.492MHz
65
74
fIN = 19.943MHz
63
73
fIN = 39.9MHz (Note 1)
dB
59
71
_______________________________________________________________________________________
dBc
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
(VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
fIN = 7.492MHz
-74
fIN = 19.943MHz
-73
fIN = 39.9MHz (Note 1)
-71
IMDTT
f1 = 19MHz at -6.5dBFS,
f2 = 21MHz at -6.5dBFS (Note 2)
-75
dBc
Third-Order Intermodulation
Distortion
IM3
f1 = 19MHz at -6.5dBFS
f2 = 21MHz at -6.5dBFS (Note 2)
-75
dBc
Total Harmonic Distortion
(First 5 Harmonics)
THD
Third-Harmonic Distortion
Two-Tone Intermodulation
Distortion
HD3
Small-Signal Bandwidth
Full-Power Bandwidth
FPBW
dBc
fIN = 7.492MHz
-70
-64
fIN = 19.943MHz
-70
-63
dBc
fIN = 39.9MHz (Note 1)
-69
Input at -20dBFS, differential inputs
500
MHz
Input at -0.5dBFS, differential inputs
400
MHz
Aperture Delay
tAD
1
ns
Aperture Jitter
tAJ
2
psrms
For 1.5 × full-scale input
Overdrive Recovery Time
2
ns
±1
%
±0.25
°
0.2
LSBrms
REFOUT
2.048
±1%
V
TCREF
60
ppm/°C
1.25
mV/mA
Differential Gain
Differential Phase
Output Noise
IN+ = IN- = COM
INTERNAL REFERENCE
Reference Output Voltage
Reference Temperature
Coefficient
Load Regulation
BUFFERED EXTERNAL REFERENCE (VREFIN = 2.048V)
REFIN Input Voltage
VREFIN
2.048
Positive Reference Output Voltage
VREFP
2.012
V
Negative Reference Output
Voltage
VREFN
0.988
V
Common-Mode Level
VCOM
VDD/2
V
Differential Reference Output
Voltage Range
ΔVREF
REFIN Resistance
RREFIN
> 50
MΩ
ISOURCE
5
mA
-250
µA
Maximum REFP, COM Source
Current
Maximum REFP, COM Sink
Current
ISINK
ΔVREF = VREFP - VREFN, TA ≥ +25°C
0.98
1.024
1.07
V
_______________________________________________________________________________________
3
MAX1446
ELECTRICAL CHARACTERISTICS (continued)
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at TA = +25°C.)
PARAMETER
Maximum REFN Source Current
Maximum REFN Sink Current
SYMBOL
CONDITIONS
MIN
ISOURCE
ISINK
TYP
MAX
UNITS
250
µA
-5
mA
UNBUFFERED EXTERNAL REFERENCE (VREFIN = AGND, reference voltage applied to REFP, REFN, and COM)
REFP, REFN Input Resistance
REFP, REFN, COM Input
Capacitance
RREFP,
RREFN
Measured between REFP and COM and
REFN and COM
CIN
4
KΩ
15
pF
1.024
±10%
V
Differential Reference Input
Voltage Range
ΔVREF
COM Input Voltage Range
VCOM
VDD/2
±10%
V
REFP Input Voltage
VREFP
VCOM+
ΔVREF/2
V
REFN Input Voltage
VREFN
VCOM ΔVREF/2
V
ΔVREF = VREFP - VREFN
DIGITAL OUTPUTS (CLK, PD, OE)
Input High Threshold
Input Low Threshold
Input Hysteresis
Input Leakage
Input Capacitance
CLK
0.8 x
VDD
PD, OE
0.8 x
OVDD
VIH
V
CLK
0.2 x
VDD
PD, OE
0.2 x
OVDD
VIL
VHYST
0.1
V
IIH
VIH = VDD = OVDD
±5
IIL
VIL = 0
±5
CIN
V
5
µA
pF
DIGITAL OUTPUTS (D9–D0)
Output Voltage Low
VOL
ISINK = 200µA
Output Voltage High
VOH
ISOURCE = 200µA
Three-State Leakage Current
ILEAK
OE = OVDD
Three-State Output Capacitance
COUT
OE = OVDD
4
0.2
OVDD 0.2
V
V
±10
5
_______________________________________________________________________________________
µA
pF
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
(VDD = 3.0V, OVDD = 2.7V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND; VREFIN = 2.048V, REFOUT connected
to REFIN through a 10kΩ resistor, VIN = 2VP-P (differential with respect to COM), CL ≈ 10pF at digital outputs, fCLK = 62.5MHz
(50% duty cycle), TA = TMIN to TMAX, unless otherwise noted. ≥+25°C guaranteed by production test, < +25°C guaranteed by design
and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.7
3.0
3.6
V
1.7
POWER REQUIREMENTS
Analog Supply Voltage
VDD
Output Supply Voltage
OVDD
Analog Supply Current
IVDD
Output Supply Current
IOVDD
Power-Supply Rejection
PSRR
CL = 10pF
3.0
3.6
V
Operating, fIN = 19.943MHz at -0.5dBFS
30
37
mA
Shutdown, clock idle, PD = OE = OVDD
4
15
µA
Operating, CL = 15pF, fIN = 19.943MHz at
-0.5dBFS
7
Shutdown, clock idle, PD = OE = OVDD
1
mA
20
µA
Offset
± 0.1
mV/V
Gain
± 0.1
%/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
tDO
Figure 5 (Notes 3, 6)
2
5
8
ns
OE Fall to Output Enable
tENABLE
Figure 5
10
ns
OE Rise to Output Disable
tDISABLE
Figure 5
1.5
ns
Clock Duty Cycle
Wake-Up Time
Figure 6, clock period 16ns (Notes 5, 6)
tWAKE
(Notes 4, 6)
45
366
55
%
520
µs
Note 1: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 2: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB better, if referenced to the two-tone envelope.
Note 3: Digital outputs settle to VIH, VIL.
Note 4: Wake-up time is defined as the time from complete reference power-down until the ADC performs within 0.3 ENOB of the
final performance for fIN = 10MHz at -0.5dBFS input amplitude. VREFIN = 2.048V, REFP, REFN, and CML decoupled with
2.3µF.
Note 5: Dynamic characteristics guaranteed at fIN = 19.943MHz for the specified duty-cycle range.
Note 6: Guaranteed by design and engineering characterization.
_______________________________________________________________________________________
5
MAX1446
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless
otherwise noted.)
HD2
-70
-50
HD3
HD2
-40
-50
-60
-80
-80
-80
-90
-90
-90
-100
-100
-100
10
15
20
25
30
35
5
10
15
20
25
30
0
35
20
25
30
FFT PLOT
(fIN = 50MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
FFT PLOT
(fIN = 7.5MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
HD3
-60
SFDR = 70dBc
SNR = 59.1dB
THD = -67.1dBc
SINAD = 58.5dB
-20
-30
-40
-50
HD3
-60
0
MAX1446 toc05
0
-10
HD2
-20
-40
-50
-70
-70
-80
-80
-90
-90
-90
-100
-100
-100
15
20
25
30
35
0
5
10
15
20
25
30
HD3
-60
-80
10
HD2
0
35
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
FFT PLOT
(fIN = 20MHz, 8192-POINT FFT,
SINGLE-ENDED INPUT)
TWO-TONE INTERMODULATION
(8192-POINT IMD,
DIFFERENTIAL INPUT)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
(AIN = -0.5dBFS)
-20
AMPLITUDE (dB)
-30
-40
HD3
-60
HD2
-70
f1 = 19MHz AT -6.5dBFS
f2 = 21MHz AT -6.5dBFS
3RD IMD = -76dBc
-10
-50
-60
-80
-90
-90
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
35
65
SINGLE-ENDED
60
55
50
-100
10
35
70
-40
-80
5
DIFFERENTIAL
75
-30
-70
-100
80
SFDR (dBc)
-20
0
MAX1446 toc08
SINAD = 59.2dB
SNR = 59.5dB
THD = -70.7dBc
SFDR = 71.1dBc
MAX1446 toc07
0
-10
35
-30
-70
5
SINAD = 59.5dB
SNR = 59.7dB
THD = -73.0dBc
SFDR = 73.6dBc
-10
AMPLITUDE (dB)
HD2
-50
0
15
FFT PLOT
(fIN = 26.8MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
-40
-50
10
ANALOG INPUT FREQUENCY (MHz)
-30
0
5
HD2
ANALOG INPUT FREQUENCY (MHz)
SINAD = 59.0dB
SNR = 59.4dB
THD = -70.5dBc
SFDR = 72.9dBc
-20
0
HD3
ANALOG INPUT FREQUENCY (MHz)
MAX1446 toc04
0
5
MAX1446 toc03
-30
-70
-10
6
-40
-60
-20
-70
0
AMPLITUDE (dB)
HD3
-30
SINAD = 59.3dB
SNR = 59.6dB
THD = -70.7dBc
SFDR = 72.2dBc
MAX1446 toc06
-50
0
-10
AMPLITUDE (dB)
-40
-60
-20
AMPLITUDE (dB)
-30
SINAD = 59.3dB
SNR = 59.5dB
THD = -72.9dBc
SFDR = 74.3dBc
-10
AMPLITUDE (dB)
AMPLITUDE (dB)
-20
0
MAX1446 toc02
SFDR = 72.2dBc
SNR = 60.1dB
THD = -71.5dBc
SINAD = 59.8dB
MAX1446 toc01
0
-10
FFT PLOT
(fIN = 20MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
FFT PLOT
(fIN = 13.3MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
MAX1446 toc09
FFT PLOT
(fIN = 7.5MHz, 8192-POINT FFT,
DIFFERENTIAL INPUT)
AMPLITUDE (dB)
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
35
0
10
20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
_______________________________________________________________________________________
90
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT FREQUENCY
(AIN = -0.5dBFS)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
(AIN = -0.5dBFS)
DIFFERENTIAL
59
-55
60
MAX1446 toc11
-50
MAX1446 toc10
60
SINGLE-ENDED
DIFFERENTIAL
59
58
57
SINGLE-ENDED
-65
-70
57
56
55
SINGLE-ENDED
54
-75
DIFFERENTIAL
53
52
-80
55
20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
0
90
10
20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
0
90
66
MAX1446 toc13
80
75
60
-55
-60
THD (dBc)
SNR (dB)
65
48
-65
60
42
-70
55
36
-75
-80
30
50
-20
0
SIGNAL-TO-NOISE AND DISTORTION
vs. ANALOG INPUT POWER
(fIN = 19.943MHz)
-16
-12
-8
-4
ANALOG INPUT POWER (dBFS)
-20
0
SPURIOUS-FREE DYNAMIC RANGE
vs. TEMPERATURE
80
MAX1446 toc16
65
60
fIN = 19.943MHz, AIN = -0.5dBFS
76
-16
-12
-8
-4
ANALOG INPUT POWER (dBFS)
0
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
70
MAX1446 toc17
-16
-12
-8
-4
ANALOG INPUT POWER (dBFS)
90
-50
54
70
20 30 40 50 60 70 80
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
(fIN = 19.943MHz)
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
(fIN = 19.943MHz)
SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
(fIN = 19.943MHz)
-20
10
MAX1446 toc15
10
MAX1446 toc14
0
MAX1446 toc18
56
SFDR (dBc)
SINAD (dB)
THD (dBc)
SNR (dB)
-60
58
MAX1446 toc12
SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
(AIN = -0.5dBFS)
fIN = 19.943MHz, AIN = -0.5dBFS
66
50
45
72
SNR (dB)
SFDR (dBc)
SINAD (dB)
55
68
62
58
40
64
35
30
54
60
-20
-16
-12
-8
-4
ANALOG INPUT POWER (dBFS)
0
50
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
TEMPERATURE (°C)
60
85
_______________________________________________________________________________________
7
MAX1446
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless
otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless
otherwise noted.)
SIGNAL-TO-NOISE AND DISTORTION
vs. TEMPERATURE
66
SINAD (dB)
-68
fIN = 19.943MHz, AIN = -0.5dBFS
-72
TA = +105°C
-76
fIN = 7.5MHz
0.4
0.3
62
0.2
INL (LSB)
-64
0.5
MAX1446 toc20
fIN = 19.943MHz, AIN = -0.5dBFS
THD (dBc)
70
MAX1446 toc19
-60
INTEGRAL NONLINEARITY vs. DIGITAL
OUTPUT CODE (BEST STRAIGHT LINE)
MAX1446 toc21
TOTAL HARMONIC DISTORTION
vs. TEMPERATURE
0.1
58
0
-0.1
TA = +105°C
54
-0.2
110
-40
10
35
60
TEMPERATURE (°C)
85
0
110
10
MAX1446 toc22
fIN = 7.5MHz
8
6
GAIN ERROR (%FS)
0.1
0
-0.1
-0.2
-0.3
4
-0.5
200
400
600
800
1000
TA = +105°C
2
0
-2
-4
6
4
0
-4
-8
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
-40
-15
85
MAX1446 toc25
50
46
42
-15
10
35
60
TEMPERATURE (°C)
85
110
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
8
fIN = 7.5MHz
7
6
34
30
26
5
4
22
27
-40
IOVDD (mA)
IVDD (mA)
110
TA = +105°C
38
29
TA = +105°C
-2
-10
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
31
1200
2
-10
10
35
60
TEMPERATURE (°C)
33
1000
-6
DIGITAL OUTPUT CODE
35
800
8
-8
1200
600
10
MAX1446 toc26
0
400
OFFSET ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (VREFIN = 2.048V)
-6
-0.4
200
DIGITAL OUTPUT CODE
GAIN ERROR vs. TEMPERATURE,
EXTERNAL REFERENCE (VREFIN = 2.048V)
0.3
0.2
-15
MAX1446 toc24
85
OFFSET ERROR (%FS)
10
35
60
TEMPERATURE (°C)
MAX1446 toc23
-15
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
DNL (LSB)
-0.3
50
-40
MAX1446 toc27
-80
IVDD (mA)
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
18
3
14
25
2.70
3.00
3.15
VDD (V)
8
2
10
2.85
3.30
3.45
3.60
-40
-15
10
35
60
TEMPERATURE (°C)
85
110
1.2
1.8
2.4
OVDD (V)
_______________________________________________________________________________________
3.0
3.6
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
(VDD = 3.0V, OVDD = 2.7V, internal reference, differential input at -0.5dBFS, fCLK = 62.35MHz, CL ≈ 10pF, TA = +25°C, unless
otherwise noted.)
4.5
4.0
IVDD (μA)
IOVDD (mA)
TA = +105°C
12
8
10
3.5
MAX1446 toc30
16
OE = OVDD,
PD = VDD
PD = VDD,
OE = OVDD
8
IOVDD (μA)
fIN = 7.5MHz
MAX1446 toc29
5.0
MAX1446 toc28
20
DIGITAL POWER-DOWN CURRENT
vs. DIGITAL POWER SUPPLY
ANALOG POWER-DOWN CURRENT
vs. ANALOG POWER SUPPLY
DIGITAL SUPPLY CURRENT
vs. TEMPERATURE
6
4
3.0
2
4
2.5
0
0
-15
10
35
60
TEMPERATURE (°C)
85
2.0
2.70
110
3.15
3.30
3.45
2.08
3.6
SNR
62
56
2.06
2.08
VREFOUT (V)
-THD
2.04
2.02
2.06
2.04
2.02
TA = +105°C
SINAD
50
58
62
66
CLOCK FREQUENCY (MHz)
2.00
2.70
70
2.00
2.85
3.00
3.15 3.30
VDD (V)
3.45
3.60
-40
-15
10
35
60
TEMPERATURE (°C)
85
110
OUTPUT NOISE HISTOGRAM (DC INPUT)
140000
MAX1446 toc34
160000
129421
120000
100000
COUNT
54
3.0
2.10
MAX1446 toc32
74
50
2.4
OVDD (V)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
2.10
VREFOUT (V)
SFDR
fIN = 20MHz, AIN = -0.5dBFS
1.8
3.60
INTERNAL REFERENCE VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
MAX1446 toc31
80
SNR/SINAD, -THD/SFDR (dB, dBc)
3.00
VDD (V)
SNR/SINAD, -THD/SFDR vs. CLOCK FREQUENCY
68
1.2
2.85
MAX1446 toc33
-40
80000
60000
40000
20000
0
926
725
0
N+1
N+2
0
N-2
N-1
N
DIGITAL OUTPUT CODE
_______________________________________________________________________________________
9
MAX1446
Typical Operating Characteristics (continued)
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1446
Pin Description
10
PIN
NAME
FUNCTION
1
REFN
Lower Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF
capacitor.
2
COM
Common-Mode Voltage Output. Bypass to GND with a > 0.1µF capacitor.
3, 9, 10
VDD
Analog Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in parallel
with 0.1µF.
4, 5, 8, 11, 14, 30
GND
Analog Ground
6
IN+
Positive Analog Input. For single-ended operation, connect signal source to IN+.
7
IN-
Negative Analog Input. For single-ended operation, connect IN- to COM.
12
CLK
Conversion Clock Input
13
PD
Power-Down Input
High: power-down mode
Low: normal operation
15
OE
Output Enable Input
High: digital outputs disabled
Low: digital outputs enabled
16–20
D9–D5
Three-State Digital Outputs D9–D5. D9 is the MSB.
21
OVDD
Output Driver Supply Voltage. Bypass to GND with a capacitor combination of 2.2µF in
parallel with 0.1µF.
22
T.P.
23
OGND
Output Driver Ground
24–28
D4–D0
Three-State Digital Outputs D4–D0. D0 is the LSB.
29
REFOUT
31
REFIN
Reference Input. VREFIN = 2 × (VREFP - VREFN). Bypass to GND with a > 0.01µF capacitor.
32
REFP
Upper Reference. Conversion range is ±(VREFP - VREFN). Bypass to GND with a > 0.1µF
capacitor.
Test Point. Do not connect.
Internal Reference Voltage Output. May be connected to REFIN through a resistor or a
resistor-divider.
______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
The MAX1446 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Each sample moves through a pipeline stage
every half-clock cycle. Counting the delay through the
output latch, the clock-cycle latency is 5.5.
A 1.5-bit (2-comparator) flash ADC converts the held
input voltage into a digital code. The following digitalto-analog converter (DAC) converts the digitized result
back into an analog voltage, which is then subtracted
from the original held input signal. The resulting error
signal is then multiplied by two, and the product is
passed along to the next pipeline stage where the
process is repeated until the signal has been processed by all 10 stages. Each stage provides a 1-bit resolution. Digital error correction compensates for ADC
comparator offsets in each pipeline stage and ensures
no missing codes.
Input Track-and-Hold Circuit
Figure 2 displays a simplified functional diagram of the
input T/H circuit in both track and hold mode. In track
mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b
are closed. The fully differential circuit samples the
input signal onto the two capacitors (C2a and C2b).
S2a and S2b set the common mode for the amplifier
input. The resulting differential voltage is held on C2a
and C2b. S4a, S4b, S5a, S5b, S1, S2a, and S2b are
then opened before S3a, S3b and S4c are closed, connecting capacitors C1a and C1b to the amplifier output,
and S4c is closed. This charges C1a and C1b to the
same values originally held on C2a and C2b. This value
is then presented to the first stage quantizer and isolates the pipeline from the fast-changing input. The
wide-input-bandwidth T/H amplifier allows the
MAX1446 to track and sample/hold analog inputs of
high frequencies beyond Nyquist. The analog inputs
(IN+ and IN-) can be driven either differentially or single
ended. It is recommended to match the impedance of
IN+ and IN- and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
Analog Input and Reference Configuration
The MAX1446 full-scale range is determined by the
internally generated voltage difference between REFP
(VDD/2 + VREFIN/4) and REFN (VDD/2 - VREFIN/4). The
ADC’s full-scale range is user adjustable through the
REFIN pin, which provides a high input impedance for
this purpose. REFOUT, REFP, COM (VDD/2), and REFN
are internally buffered, low-impedance outputs.
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
MDAC
VIN
Σ
T/H
x2
VOUT
S4a
IN+
FLASH
ADC
OUT
C2a
DAC
S4c
1.5 bits
S1
OUT
INS4b
C2b
C1b
VIN
STAGE 1
STAGE 2
S3b
STAGE 10
S2b
INTERNAL
BIAS
S5b
COM
DIGITAL CORRECTION LOGIC
10
D9–D0
VIN = INPUT VOLTAGE BETWEEN
IN+ AND IN- (DIFFERENTIAL OR SINGLE ENDED)
Figure 1. Pipelined Architecture—Stage Blocks
TRACK
HOLD
TRACK
CLK
INTERNAL
HOLD NONOVERLAPPING
CLOCK SIGNALS
Figure 2. Internal T/H Circuit
______________________________________________________________________________________
11
MAX1446
Detailed Description
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
The MAX1446 provides three modes of reference operation:
• Internal reference mode
• Buffered external reference mode
• Unbuffered external reference mode
In internal reference mode, the internal reference output (REFOUT) can be tied to the REFIN pin through a
resistor (e.g., 10kΩ) or resistor-divider if an application
requires a reduced full-scale range. For stability purposes, it is recommended to bypass REFIN with a
> 10nF capacitor to GND.
In buffered external reference mode, the reference voltage levels can be adjusted externally by applying a
stable and accurate voltage at REFIN. In this mode,
REFOUT may be left open or connected to REFIN
through a > 10kΩ resistor.
In unbuffered external reference mode, REFIN is connected to GND, thereby deactivating the on-chip
buffers of REFP, COM, and REFN. With their buffers
shut down, these pins become high impedance and
can be driven by external reference sources.
Clock Input (CLK)
The MAX1446 CLK input accepts CMOS-compatible
clock signals. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (< 2ns). In particular,
sampling occurs on the falling edge of the clock signal,
mandating this edge to provide lowest possible jitter.
Any significant aperture jitter would limit the SNR performance of the ADC as follows:
⎛
⎞
1
SNR = 20 × log⎜
⎟
⎝ 2 × π × fIN × t AJ ⎠
Clock jitter is especially critical for undersampling
applications. The clock input should always be considered as an analog input and routed away from any analog input or other digital signal lines.
The MAX1446 clock input operates with a voltage
threshold set to VDD/2. Clock inputs with a duty cycle
other than 50% must meet the specifications for high
and low periods as stated in the Electrical Characteristics. See Figures 3a, 3b, 4a, and 4b for the relationship between spurious-free dynamic range (SFDR),
signal-to-noise ratio (SNR), total harmonic distortion
(THD), or signal-to-noise plus distortion (SINAD) vs.
duty cycle.
Output Enable (OE), Power-Down (PD),
and Output Data (D0–D9)
All data outputs, D0 (LSB) through D9 (MSB), are
TTL/CMOS-logic compatible. There is a 5.5 clock-cycle
latency between any particular sample and its valid
output data. The output coding is straight offset binary
(Table 1). With OE and PD (power-down) high, the digital output enters a high-impedance state. If OE is held
low with PD high, the outputs are latched at the last
value prior to the power-down.
The capacitive load on the digital outputs D0–D9
should be kept as low as possible (< 15pF) to avoid
large digital currents that could feed back into the analog portion of the MAX1446, degrading its dynamic performance. The use of buffers on the ADC’s digital
outputs can further isolate the digital outputs from
heavy capacitive loads.
To further improve the dynamic performance of the
MAX1446 small series resistors (e.g., 100Ω) may be
added to the digital output paths, close to the ADC.
Figure 5 displays the timing relationship between output enable and data output valid, as well as powerdown/wake-up and data output valid.
where fIN represents the analog input frequency, and
tAJ is the time of the aperture jitter.
System Timing Requirements
Figure 6 shows the relationship between the clock
input, analog input, and data output. The MAX1446
Table 1. MAX1446 Output Code for Differential Inputs
DIFFERENTIAL INPUT VOLTAGE*
DIFFERENTIAL INPUT
STRAIGHT OFFSET BINARY
VREF × 511/512
VREF × 510/512
VREF × 1/512
0
- VREF × 1/512
- VREF × 511/512
- VREF × 512/512
+Full Scale -1LSB
+Full Scale -2LSB
+1LSB
Bipolar Zero
-1LSB
Negative Full Scale + 1LSB
Negative Full Scale
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
*VREFIN = VREFP = VREFN
12
______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
fIN = 12.5MHz AT -0.5dBFS
fIN = 12.5MHz AT -0.5dBFS
-50
THD (dBc)
SFDR (dBc)
70
60
-60
-70
50
-80
40
20
30
40
50
60
20
70
30
40
50
60
70
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
Figure 3a. SFDR vs. Clock Duty Cycle (Differential Input)
Figure 4a. THD vs. Clock Duty Cycle (Differential Input)
70
70
fIN = 12.5MHz AT -0.5dBFS
fIN = 12.5MHz AT -0.5dBFS
65
65
60
60
SINAD (dB)
SNR (dB)
MAX1446
-40
80
55
55
50
50
45
45
40
40
20
30
40
50
60
20
70
30
40
50
60
70
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
Figure 3b. SNR vs. Clock Duty Cycle (Differential Input)
Figure 4b. SINAD vs. Clock Duty Cycle (Differential Input)
OE
tDISABLE
tENABLE
OUTPUT
DATA D9–D0
HIGH-Z
VALID DATA
HIGH-Z
Figure 5. Output Enable Timing
______________________________________________________________________________________
13
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
samples at the falling edge of the input clock. Output
data is valid on the rising edge of the input clock. The
output data has an internal latency of 5.5 clock cycles.
Figure 6 also shows the relationship between the input
clock parameters and the valid output data.
Applications Information
Figure 7 shows a typical application circuit containing a
single-ended to differential converter. The internal reference provides a VDD/2 output voltage for level shifting
purposes. The input is buffered and then split to a voltage follower and inverter. A lowpass filter follows the op
amps to suppress some of the wideband noise associated with high-speed op amps. The user may select the
RISO and CIN values to optimize the filter performance
to suit a particular application. For the application in
Figure 7, an RISO of 50Ω is placed before the capacitive load to prevent ringing and oscillation. The 22pF
CIN capacitor acts as a small bypassing capacitor.
Using Transformer Coupling
An RF transformer (Figure 8) provides an excellent
solution for converting a single-ended source signal to
a fully differential signal, required by the MAX1446 for
optimum performance. Connecting the transformer’s
center tap to COM provides a VDD/2 DC level shift to
the input. Although a 1:1 transformer is shown, a stepup transformer may be selected to reduce the drive
requirements. A reduced signal swing from the input
driver, such as an op amp, may also improve the overall distortion.
In general, the MAX1446 provides better SFDR and
THD with fully differential input signals than singleended drive, especially for very high input frequencies.
In differential input mode, even-order harmonics are
lower since both inputs (IN+, IN-) are balanced, and
each of the inputs only requires half the signal swing
compared to single-ended mode.
Single-Ended AC-Coupled
Input Signal
Figure 9 shows an AC-coupled, single-ended application. The MAX4108 op amp provides high speed, high
bandwidth, low noise, and low distortion to maintain the
integrity of the input signal.
Buffered External Reference Drives
Multiple ADCs
Multiple-converter systems based on the MAX1446 are
well suited for use with a common reference voltage.
The REFIN pin of those converters can be connected
directly to an external reference source. A precision
bandgap reference like the MAX6062 generates an
external DC level of 2.048V (Figure 10), and exhibits a
noise voltage density of 150n√Hz. Its output passes
through a 1-pole lowpass filter (with 10Hz cutoff frequency) to the MAX4250, which buffers the reference
before its output is applied to a second 10Hz lowpass
5.5 CLOCK-CYCLE LATENCY
N
N+1
N+2
N+3
N+4
N+5
N+6
ANALOG INPUT
CLOCK INPUT
tDO
DATA OUTPUT
N-6
N-5
N-4
N-3
N-2
N-1
N
Figure 6. System and Output Timing Diagram
14
______________________________________________________________________________________
N+1
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1446
5V
0.1μF
LOWPASS FILTER
IN+
MAX4108
RISO
50Ω
0.1μF
300Ω
CIN
22pF
0.1μF
-5V
MAX1446
600Ω
600Ω
300Ω
COM
0.1μF
5V
5V
0.1μF
600Ω
INPUT
0.1μF
LOWPASS FILTER
MAX4108
300Ω
0.1μF
-5V
IN-
MAX4108
RISO
50Ω
CIN
22pF
300Ω
-5V
0.1μF
300Ω
300Ω
600Ω
Figure 7. Typical Application Circuit for Single-Ended to Differential Conversion
25Ω
IN+
REFP
22pF
MAX1446
0.1μF
VIN
3
T1
1kΩ
VIN
0.1μF
4
RISO
IN+
MAX4108
N.C. 5
1
100Ω
2
6
CIN
1kΩ
MAX1446
COM
2.2μF
0.1μF
COM
REFN
0.1μF
RISO
MINI-CIRCUITS
ADT1–1WT
100Ω
25Ω
IN22pF
Figure 8. Using a Transformer for AC-Coupling
RISO = 50Ω
CIN = 22pF
INCIN
Figure 9. Single-Ended AC-Coupled Input
______________________________________________________________________________________
15
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
3.3V
0.1μF
3.3V
N.C.
0.1μF
2.048V
1
MAX6062
31
0.1μF
2
16.2kΩ
3
32
1
5
162Ω
1μF
4
3
MAX4250
2
10Hz LOWPASS
FILTER
29
2
1
100μF
0.1μF
0.1μF
REFOUT
REFIN
REFP MAX1446
N=1
REFN
COM
0.1μF
10Hz LOWPASS
FILTER
0.1μF
N.C.
29
31
32
1
0.1μF
2
0.1μF
0.1μF
2.2μF
10V
REFOUT
REFIN
REFP MAX1446
N = 1000
REFN
COM
0.1μF
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 1000 ADCs.
Figure 10. Buffered External Reference Drives Up to 1000 ADCs
filter. The MAX4250 provides a low offset voltage (for
high-gain accuracy) and a low noise level. The passive
10Hz filter following the buffer attenuates noise produced in the voltage reference and buffer stages. This
filtered noise density, which decreases for higher frequencies, meets the noise levels specified for precision
ADC operation.
Unbuffered External Reference Drives
Multiple ADCs
Connecting each REFIN to analog ground disables the
internal reference of each device, allowing the internal
reference ladders to be driven directly by a set of external reference sources. Followed by a 10Hz lowpass filter and precision voltage-divider (Figure 11), the
MAX6066 generates a DC level of 2.500V. The buffered
outputs of this divider are set to 2.0V, 1.5V, and 1.0V,
with an accuracy that depends on the tolerance of the
divider resistors. The three voltages are buffered by the
16
MAX4252, which provides low noise and low DC offset.
The individual voltage followers are connected to 10Hz
lowpass filters, which filter both the reference voltage
and amplifier noise to a level of 3n√Hz. The 2.0V and
1.0V reference voltages set the differential full-scale
range of the associated ADCs at 2VP-P. The 2.0V and
1.0V buffers drive the ADC’s internal ladder resistances
between them. Note that the common power supply for
all active components removes any concern regarding
power-supply sequencing when powering up or down.
With the outputs of the MAX4252 matching better than
0.1%, the buffers and subsequent lowpass filters can
be replicated to support as many as 32 ADCs. For
applications that require more than 32 matched ADCs,
a voltage reference and divider string common to all
converters is highly recommended.
______________________________________________________________________________________
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
MAX1446
3.3V
0.1μF
N.C.
29
31
REFOUT
REFIN
1
2.0V
2
32
3.3V
21.5kΩ
3
MAX6066
1
1
47Ω
1/4 MAX4252
2
2
21.5kΩ
3
REFP MAX1446
2.0V AT 8mA
4
11
10μF
6V
330μF
6V
0.1μF
0.1μF
N=1
REFN
COM
0.1μF
1.47kΩ
1μF
1.5V
3.3V
5
3.3V
1.5V AT 0mA
4
7
47Ω
1/4 MAX4252
0.1μF
6
11
21.5kΩ
MAX4254 POWER-SUPPLY BYPASSING.
PLACE CAPACITOR AS CLOSE AS
POSSIBLE TO THE OP AMP.
10μF
6V
330μF
6V
1.47kΩ
1.0V
3.3V
10
1.0V AT -8mA
4
8
47Ω
0.1μF
1/4 MAX4252
21.5kΩ
21.5kΩ
9
11
10μF
6V
N.C.
330μF
6V
29
31
1.47kΩ
32
1
2
0.1μF
0.1μF
2.2μF
10V
REFOUT
REFIN
REFP MAX1446
N = 32
REFN
COM
0.1μF
NOTE: ONE FRONT-END REFERENCE CIRCUIT DESIGN MAY BE USED WITH UP TO 32 ADCs.
Figure 11. Unbuffered External Reference Drives Up to 32 ADCs
Grounding, Bypassing,
__________________and Board Layout
The MAX1446 requires high-speed board layout design
techniques. Locate all bypass capacitors as close to
the device as possible, preferably on the same side as
the ADC, using surface-mount devices for minimum
inductance. Bypass VDD, REFP, REFN, and COM with
two parallel 0.1µF ceramic capacitors and a 2.2µF
bipolar capacitor to GND. Follow the same rules to
bypass the digital supply (OVDD) to OGND. Multilayer
boards with separated ground and power planes pro-
duce the highest level of signal integrity. Consider
using a split ground plane arranged to match the physical location of the analog ground (GND) and the digital
output driver ground (OGND) on the ADC's package.
The two ground planes should be joined at a single
point so that the noisy digital ground currents do not
interfere with the analog ground plane. The ideal location of this connection can be determined experimentally at a point along the gap between the two ground
planes that produces optimum results. Make this connection with a low-value, surface-mount resistor (1Ω to
5Ω), a ferrite bead, or a direct short. Alternatively, all
______________________________________________________________________________________
17
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
ground pins could share the same ground plane if the
ground plane is sufficiently isolated from any noisy, digital systems ground plane (e.g., downstream output
buffer or DSP ground plane). Route high-speed digital
signal traces away from sensitive analog traces. Keep
all signal lines short and free of 90° turns.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at
a specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB
is computed from:
Static Parameter Definitions
ENOB =
(SINAD − 1.76)
6.02
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the endpoints of the transfer function
once offset and gain errors have been nullified. The
MAX1446’s static linearity parameters are measured
using the best-straight-line fit method.
Total Harmonic Distortion (THD)
THD is typically the ratio of the rms sum of the input
signal’s first four harmonics to the fundamental itself.
This is expressed as:
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
where V1 is the fundamental amplitude, and V2 through
V5 are the amplitudes of the 2nd- through 5th-order
harmonics.
Dynamic Parameter Definitions
Aperture Jitter
Figure 12 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
falling edge of the sampling clock and the instant when
an actual sample is taken (Figure 12).
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (rms value) to the rms quantization error (residual error). The ideal, theoretical minimum A/D noise is caused by quantization error only
and results directly from the ADC’s resolution (N bits):
SNR(MAX) = 6.02 x N + 1.76
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the rms signal to the rms noise, which includes all spectral components minus the fundamental, the first five harmonics,
and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the rms signal
to all spectral components minus the fundamental and
the DC offset.
18
⎛ V 2 +V 2 +V 2 +V 2
2
3
4
5
THD = 20 × log ⎜
⎜
V
1
⎝
⎞
⎟
⎟
⎠
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the rms
amplitude of the fundamental (maximum signal component) to the rms value of the next largest spurious component, excluding DC offset.
Intermodulation Distortion (IMD)
The two-tone IMD is the ratio expressed in decibels of
either input tone to the worst 3rd-order (or higher) intermodulation products. The individual input tone levels
are at -6.5dB full scale.
CLK
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
T/H
TRACK
HOLD
Figure 12. T/H Aperture Timing
______________________________________________________________________________________
TRACK
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
REFP
REFIN
GND
REFOUT
D0
D1
D2
D3
TOP VIEW
32
31
30
29
28
27
26
25
REFN
1
24 D4
COM
2
23 OGND
VDD
3
22 T.P.
GND
4
GND
5
IN+
6
19 D6
IN-
7
18 D7
GND
8
17 D8
21 OVDD
MAX1446
9
10
11
12
13
14
15
16
VDD
VDD
GND
CLK
PD
GND
OE
D9
20 D5
TQFP
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
32 TQFP
H32-2F
21-0110
______________________________________________________________________________________
19
MAX1446
Pin Configurations (continued)
MAX1446
10-Bit, 60Msps, 3.0V, Low-Power
ADC with Internal Reference
Revision History
REVISION
NUMBER
REVISION
DATE
3
11/07
Various corrections; updated to extended temperature range for automotive
applications; replaced TOCs 9–20, 23, 24, 26, 30, 31, 33; updated package
outlines.
4
11/08
Updates to the Electrical Characteristics table and notes section.
DESCRIPTION
PAGES
CHANGED
1–9, 15, 18, 20, 21
5, 14
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2008 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.