M48T08 M48T08Y, M48T18 5V, 64 Kbit (8 Kb x8) TIMEKEEPER® SRAM FEATURES SUMMARY ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT, AND BATTERY BYTEWIDE™ RAM-LIKE CLOCK ACCESS BCD CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES, and SECONDS TYPICAL CLOCK ACCURACY OF ±1 MINUTE A MONTH, AT 25°C AUTOMATIC POWER-FAIL CHIP DESELECT AND WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): – M48T08: VCC = 4.75 to 5.5V 4.5V ≤ VPFD ≤ 4.75V – M48T18/T08Y: VCC = 4.5 to 5.5V 4.2V ≤ VPFD ≤ 4.5V SOFTWARE CONTROLLED CLOCK CALIBRATION FOR HIGH ACCURACY APPLICATIONS SELF-CONTAINED BATTERY AND CRYSTAL IN THE CAPHAT™ DIP PACKAGE PACKAGING INCLUDES A 28-LEAD SOIC AND SNAPHAT® TOP (to be ordered separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP WHICH CONTAINS THE BATTERY AND CRYSTAL PIN AND FUNCTION COMPATIBLE WITH DS1643 and JEDEC STANDARD 8K x8 SRAMs RoHS COMPLIANCE Lead-free components are compliant with the RoHS Directive. Figure 1. 28-pin PCDIP, CAPHAT™ Package 28 1 PCDIP28 (PC) Battery/Crystal CAPHAT Figure 2. 28-pin SOIC Package SNAPHAT (SH) Battery/Crystal 28 1 SOH28 (MH) Rev 7.0 December 2005 1/27 M48T08, M48T08Y, M48T18 TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 28-pin PCDIP, CAPHAT™ Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. Table 1. Figure 4. Figure 5. Figure 6. Logic Diagram . . . . . . . . . . . . . . . . . . . . . Signal Names . . . . . . . . . . . . . . . . . . . . . DIP Connections . . . . . . . . . . . . . . . . . . . SOIC Connections . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... .....4 .....4 .....5 .....5 .....5 OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 7. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 8. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 9. Chip Enable Controlled, WRITE AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Power-fail Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Stopping and Starting the Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 10.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11.Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 12.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 7. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . Figure 13.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2/27 ...... ...... ...... ...... ...... . . . . 18 . . . . 18 . . . . 18 . . . . 19 . . . . 20 M48T08, M48T08Y, M48T18 Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 15.PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline . . . . . . . . . . . . . . . . 21 Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data. . . . . . . . . 21 Figure 16.SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline. 22 Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data . . . . . 22 Figure 17.SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline . . . . . . . 23 Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data. . . . 23 Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 24 Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 24 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3/27 M48T08, M48T08Y, M48T18 SUMMARY DESCRIPTION The M48T08/18/08Y TIMEKEEPER® RAM is an 8K x 8 non-volatile static RAM and real time clock which is pin and functional compatible with the DS1643. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. The M48T08/18/08Y is a non-volatile pin and function equivalent to any JEDEC standard 8K x 8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special WRITE timing or limitations on the number of WRITEs that can be performed. The 28-pin, 600mil DIP CAPHAT™ houses the M48T08/18/08Y silicon with a quartz crystal and a long- life lithium button cell in a single package. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT® housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28-BR12SH” or “M4T32-BR12SH” (see Table 17., page 25). Figure 3. Logic Diagram Table 1. Signal Names VCC 13 8 A0-A12 W E1 DQ0-DQ7 M48T08 M48T08Y M48T18 INT A0-A12 Address Inputs DQ0-DQ7 Data Inputs / Outputs INT Power Fail Interrupt (Open Drain) E1 Chip Enable 1 E2 Chip Enable 2 G Output Enable W WRITE Enable VCC Supply Voltage VSS Ground E2 G VSS AI01020 4/27 M48T08, M48T08Y, M48T18 Figure 4. DIP Connections INT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS Figure 5. SOIC Connections 1 28 2 27 3 26 4 25 5 24 6 23 7 M48T08 22 8 M48T18 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 INT A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS VCC W E2 A8 A9 A11 G A10 E1 DQ7 DQ6 DQ5 DQ4 DQ3 28 1 2 27 3 26 4 25 5 24 6 23 7 22 M48T08Y 8 21 9 20 10 19 11 18 12 17 13 16 14 15 AI01182 AI01021B Figure 6. Block Diagram OSCILLATOR AND CLOCK CHAIN 8 x 8 BiPORT SRAM ARRAY 32,768 Hz CRYSTAL A0-A12 POWER 8184 x 8 SRAM ARRAY LITHIUM CELL DQ0-DQ7 E1 VOLTAGE SENSE AND SWITCHING CIRCUITRY VCC INT E2 VPFD W G VSS AI01333 5/27 M48T08, M48T08Y, M48T18 OPERATION MODES As Figure 6., page 5 shows, the static memory array and the quartz-controlled clock oscillator of the M48T08/18/08Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDE™ clock information in the bytes with addresses 1FF8h-1FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting. The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORT™ READ/WRITE memory cells. The M48T08/18/08Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T08/18/08Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below the Battery Back-up Switchover Voltage (VSO), the control circuitry connects the battery which maintains data and clock operation until valid power returns. Table 2. Operating Modes Mode VCC Deselect Deselect WRITE READ 4.75 to 5.5V or 4.5 to 5.5V READ E1 E2 G W DQ0-DQ7 Power VIH X X X High Z Standby X VIL X X High Z Standby VIL VIH X VIL DIN Active VIL VIH VIL VIH DOUT Active VIL VIH VIH VIH High Z Active Deselect VSO to VPFD(min)(1) X X X X High Z CMOS Standby Deselect ≤ VSO(1) X X X X High Z Battery Back-up Mode Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 1. See Table 11., page 20 for details. 6/27 M48T08, M48T08Y, M48T18 READ Mode The M48T08/18/08Y is in the READ Mode whenever W (WRITE Enable) is high, E1 (Chip Enable 1) is low, and E2 (Chip Enable 2) is high. The device architecture allows ripple-through access of data from eight of 65,536 locations in the static storage array. Thus, the unique address specified by the 13 address inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within address access time (tAVQV) after the last address input signal is stable, providing that the E1, E2, and G access times are also satisfied. If the E1, E2 and G access times are not met, valid data will be available after the latter of the Chip Enable Access times (tE1LQV or tE2HQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E1, E2 and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the address inputs are changed while E1, E2 and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next address access. Figure 7. READ Mode AC Waveforms tAVAV A0-A12 VALID tAVQV tAXQX tE1LQV tE1HQZ E1 tE1LQX tE2HQV tE2LQZ E2 tE2HQX tGLQV tGHQZ G tGLQX DQ0-DQ7 VALID AI00962 Note: WRITE Enable (W) = High. 7/27 M48T08, M48T08Y, M48T18 Table 3. READ Mode AC Characteristics M48T08/M48T18/T08Y Symbol (1) Parameter –100/–10 (T08Y) Min Max –150/–15 (T08Y) Min Max tAVAV READ Cycle Time tAVQV Address Valid to Output Valid 100 150 ns tE1LQV Chip Enable 1 Low to Output Valid 100 150 ns tE2HQV Chip Enable 2 High to Output Valid 100 150 ns tGLQV Output Enable Low to Output Valid 50 75 ns tE1LQX Chip Enable 1 Low to Output Transition 10 10 ns tE2HQX Chip Enable 2 High to Output Transition 10 10 ns tGLQX Output Enable Low to Output Transition 5 5 ns tE1HQZ Chip Enable 1 High to Output Hi-Z 50 75 ns tE2LQZ Chip Enable 2 Low to Output Hi-Z 50 75 ns tGHQZ Output Enable High to Output Hi-Z 40 60 ns tAXQX Address Transition to Output Transition 100 5 150 ns 5 Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 8/27 Unit ns M48T08, M48T08Y, M48T18 WRITE Mode The M48T08/18/08Y is in the WRITE Mode whenever W, E1, and E2 are active. The start of a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2. The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low for a minimum of tE1HAX or tE2LAX from Chip Enable or tWHAX from WRITE Enable prior to the initiation of another READ or WRITE Cycle. Data-in must be valid tDVWH prior to the end of WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE Cycles to avoid bus contention; however, if the output bus has been activated by a low on E1 and G and a high on E2, a low on W will disable the outputs tWLQZ after W falls. Figure 8. WRITE Enable Controlled, WRITE AC Waveform tAVAV A0-A12 VALID tAVWH tWHAX tAVE1L E1 tAVE2H E2 tWLWH tAVWL W tWLQZ tWHQX tWHDX DQ0-DQ7 DATA INPUT tDVWH AI00963 9/27 M48T08, M48T08Y, M48T18 Figure 9. Chip Enable Controlled, WRITE AC Waveforms tAVAV A0-A12 VALID tAVE1H tAVE1L tE1LE1H tE1HAX E1 tAVE2L tAVE2H tE2HE2L tE2LAX E2 tAVWL W tE1HDX tE2LDX DQ0-DQ7 DATA INPUT tDVE1H tDVE2L 10/27 AI00964B M48T08, M48T08Y, M48T18 Table 4. WRITE Mode AC Characteristics M48T08/M48T18/T08Y Symbol (1) Parameter –100/–10 (T08Y) Min tAVAV WRITE Cycle Time tAVWL Max –150/–15 (T08Y) Min Unit Max 100 150 ns Address Valid to WRITE Enable Low 0 0 ns tAVE1L Address Valid to Chip Enable 1 Low 0 0 ns tAVE2H Address Valid to Chip Enable 2 High 0 0 ns tWLWH WRITE Enable Pulse Width 80 100 ns tE1LE1H Chip Enable 1 Low to Chip Enable 1 High 80 130 ns tE2HE2L Chip Enable 2 High to Chip Enable 2 Low 80 130 ns tWHAX WRITE Enable High to Address Transition 10 10 ns tE1HAX Chip Enable 1 High to Address Transition 10 10 ns tE2LAX Chip Enable 2 Low to Address Transition 10 10 ns tDVWH Input Valid to WRITE Enable High 50 70 ns tDVE1H Input Valid to Chip Enable 1 High 50 70 ns tDVE2L Input Valid to Chip Enable 2 Low 50 70 ns tWHDX WRITE Enable High to Input Transition 5 5 ns tE1HDX Chip Enable 1 High to Input Transition 5 5 ns tE2LDX Chip Enable 2 Low to Input Transition 5 5 ns tWLQZ WRITE Enable Low to Output Hi-Z tAVWH Address Valid to WRITE Enable High 80 130 ns tAVE1H Address Valid to Chip Enable 1 High 80 130 ns tAVE2L Address Valid to Chip Enable 2 Low 80 130 ns tWHQX WRITE Enable High to Output Transition 10 10 ns 50 70 ns Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 11/27 M48T08, M48T08Y, M48T18 Data Retention Mode With valid VCC applied, the M48T08/18/08Y operates as a conventional BYTEWIDE™ static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD (max), VPFD (min) window. All outputs become high impedance, and all inputs are treated as “Don't care.” Note: A power failure during a WRITE cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD (min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T08/18/08Y may respond to transient noise spikes on VCC that reach into the deselect window during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO , the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T08/18/ 08Y for an accumulated period of at least 10 years when VCC is less than VSO. 12/27 Note: Requires use of M4T32-BR12SH SNAPHAT® top when using the SOH28 package. As system power returns and VCC rises above VSO, the battery is disconnected and the power supply is switched to external VCC. Write protection continues until VCC reaches VPFD (min) plus trec (min). E1 should be kept high or E2 low as VCC rises past VPFD (min) to prevent inadvertent WRITE cycles prior to system stabilization. Normal RAM operation can resume trec after VCC exceeds VPFD (max). For more information on Battery Storage Life refer to the Application Note AN1012. Power-fail Interrupt Pin The M48T08/18/08Y continuously monitors VCC. When VCC falls to the power-fail detect trip point, an interrupt is immediately generated. An internal clock provides a delay of between 10µs and 40µs before automatically deselecting the M48T08/18/ 08Y. The INT pin is an open drain output and requires an external pull up resistor, even if the interrupt output function is not being used. M48T08, M48T08Y, M48T18 CLOCK OPERATIONS Reading the Clock Setting the Clock ® Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are only data registers and not the actual clock counters, so updating the registers can be halted without disturbing the clock itself. Updating is halted when a '1' is written to the READ Bit, the seventh bit in the control register. As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0.' The eighth bit of the control register is the WRITE Bit. Setting the WRITE Bit to a '1,' like the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (on Table 5.). Resetting the WRITE Bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. The FT Bit and the bits marked as '0' in Table 5. must be written to '0' to allow for normal TIMEKEEPER and RAM operation. See the Application Note AN923, “TIMEKEEPER ® Rolling Into the 21 st Century” for information on Century Rollover. Table 5. Register Map Data Address D7 1FFFh D6 D5 D4 D3 D2 10 Years 10 M D0 Function/Range BCD Format Year Year 00-99 Month Month 01-12 Date Date 01-31 Day 01-07 Hours Hours 00-23 1FFEh 0 0 1FFDh 0 0 1FFCh 0 FT 1FFBh 0 0 1FFAh 0 10 Minutes Minutes Minutes 00-59 1FF9h ST 10 Seconds Seconds Seconds 00-59 1FF8h W R 0 D1 10 Date 0 0 0 Day 10 Hours S Calibration Control Keys: S = SIGN Bit FT = FREQUENCY TEST Bit (Set to '0' for normal clock operation) R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to '0' 13/27 M48T08, M48T08Y, M48T18 Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP Bit (ST) is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T08/18/08Y (in the PCDIP28 package) is shipped from STMicroelectronics with the STOP Bit set to a '1.' When reset to a '0,' the M48T08/18/08Y oscillator starts within one second. Note: To guarantee oscillator start-up after initial power-up, first write the STOP Bit (ST) to '1,' then reset to '0.' Calibrating the Clock The M48T08/18/08Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768 Hz. A typical M48T08/18/08Y is accurate within 1 minute per month at 25°C without calibration. The devices are tested not to exceed ± 35 ppm (parts per million) oscillator frequency error at 25°C, which equates to about ±1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T08/18/08Y improves to better than +1/–2 ppm at 25°C. The oscillation rate of any crystal changes with temperature. Figure 10., page 15 shows the frequency error that can be expected at various temperatures. Most clock chips compensate for crystal frequency and temperature shift error with cumbersome “trim” capacitors. The M48T08/18/ 08Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 11., page 15. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five-bit Calibration Byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration Byte occupies the five lower order bits in the Control register. This byte can be set to represent any value between 0 and 31 in binary form. The sixth bit is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or 14/27 lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles; that is +4.068 or –2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768Hz, each of the 31 increments in the Calibration Byte would represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T08/18/08Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration Byte. The second approach is better suited to a manufacturing environment, and involves the use of standard test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit in the Day Register, is set to a '1,' and the oscillator is running at 32,768 Hz, the LSB (DQ0) of the Seconds Register will toggle at 512 Hz. Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a –10 (WR001010) to be loaded into the Calibration Byte for correction. Note: Setting or changing the Calibration Byte does not affect the Frequency Test output frequency. The device must be selected and addresses must be stable at Address 1FF9h when reading the 512 Hz on DQ0. The LSB of the Seconds Register is monitored by holding the M48T08/18/08Y in an extended READ of the Seconds Register, but without having the READ Bit set. The FT Bit MUST be reset to '0' for normal clock operations to resume. For more information on calibration, see the Application Note AN934, “TIMEKEEPER ® Calibration.” M48T08, M48T08Y, M48T18 Figure 10. Crystal Accuracy Across Temperature ppm 20 0 -20 -40 ∆F = -0.038 ppm (T - T )2 ± 10% 0 F C2 -60 T0 = 25 °C -80 -100 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 °C AI02124 Figure 11. Clock Calibration NORMAL POSITIVE CALIBRATION NEGATIVE CALIBRATION AI00594B 15/27 M48T08, M48T08Y, M48T18 VCC Noise And Negative Going Transients ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure 12.) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommended to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. 16/27 Figure 12. Supply Voltage Protection VCC VCC 0.1µF DEVICE VSS AI02169 M48T08, M48T08Y, M48T18 MAXIMUM RATING Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 6. Absolute Maximum Ratings Symbol TA TSTG TSLD(1,2,3) Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Value Unit 0 to 70 °C –40 to 85 °C 260 °C VIO Input or Output Voltages –0.3 to 7 V VCC Supply Voltage –0.3 to 7 V IO Output Current 20 mA PD Power Dissipation 1 W Note: 1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds). 2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for between 90 to 150 seconds). 3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C for greater than 30 seconds). CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets. 17/27 M48T08, M48T08Y, M48T18 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the Measure- ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters. Table 7. Operating and AC Measurement Conditions Parameter M48T08 M48T18/T08Y Unit 4.75 to 5.5 4.5 to 5.5 V 0 to 70 0 to 70 °C Load Capacitance (CL) 100 100 pF Input Rise and Fall Times ≤5 ≤5 ns 0 to 3 0 to 3 V 1.5 1.5 V Supply Voltage (VCC) Ambient Operating Temperature (TA) Input Pulse Voltages Input and Output Timing Ref. Voltages Note: Output Hi-Z is defined as the point where data is no longer driven. Figure 13. AC Testing Load Circuit 5V 1.8kΩ DEVICE UNDER TEST OUT 1kΩ CL = 100pF CL includes JIG capacitance AI01019 Table 8. Capacitance Parameter(1,2) Symbol CIN CIO(3) Min Max Unit Input Capacitance 10 pF Input / Output Capacitance 10 pF Note: 1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested. 2. At 25°C, f = 1MHz. 3. Outputs deselected. 18/27 M48T08, M48T08Y, M48T18 Table 9. DC Characteristics Symbol ILI Parameter Input Leakage Current ILO(2) ICC Output Leakage Current Supply Current Test Condition(1) M48T08/M48T18/T08Y Unit Min Max 0V ≤ VIN ≤ VCC ±1 µA 0V ≤ VOUT ≤ VCC ±1 µA Outputs open 80 mA ICC1(3) Supply Current (Standby) TTL E1 = VIH, E2 = VIL 3 mA ICC2(3) Supply Current (Standby) CMOS E1 = VCC – 0.2V, E2 = VSS + 0.2V 3 mA VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.2 VCC + 0.3 V VOL VOH Note: 1. 2. 3. 4. Output Low Voltage IOL = 2.1mA 0.4 V Output Low Voltage (INT)(4) IOL = 0.5mA 0.4 V Output High Voltage IOH = –1mA 2.4 V Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). Outputs deselected. Measured with Control Bits set as follows: R = '1'; W, ST, FT = '0.' The INT pin is Open Drain. 19/27 M48T08, M48T08Y, M48T18 Figure 14. Power Down/Up Mode AC Waveforms VCC VPFD (max) VPFD (min) VSO tDR tF tPD tR tRB tFB tPFX tPFH INT trec INPUTS DON'T CARE RECOGNIZED NOTE RECOGNIZED HIGH-Z OUTPUTS VALID VALID (PER CONTROL INPUT) (PER CONTROL INPUT) AI00566 Note: Inputs may or may not be recognized at this time. Caution should be taken to keep E1 high or E2 low as VCC rises past VPFD (min). Some systems may perform inadvertent WRITE cycles after VCC rises above VPFD (min) but before normal system operations begin. Even though a power on reset is being applied to the processor, a reset condition may not occur until after the system clock is running. Table 10. Power Down/Up AC Characteristics Symbol Parameter(1) Min tPD E1 or W at VIH or E2 at VIL before Power Down tF(2) tFB(3) Max Unit 0 µs VPFD (max) to VPFD (min) VCC Fall Time 300 µs VPFD (min) to VSS VCC Fall Time 10 µs tR VPFD (min) to VPFD (max) VCC Rise Time 0 µs tRB VSS to VPFD (min) VCC Rise Time 1 µs trec E1 or W at VIH or E2 at VIL before Power Up 1 ms tPFX INT Low to Auto Deselect 10 tPFH VPFD (max) to INT High 40 µs 120 µs Note: 1. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after VCC passes VPFD (min). 3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data. Table 11. Power Down/Up Trip Points DC Characteristics Symbol Parameter(1,2) VPFD Power-fail Deselect Voltage VSO Battery Back-up Switchover Voltage tDR Expected Data Retention Time Min Typ Max Unit M48T08 4.5 4.6 4.75 V M48T18/T08Y 4.2 4.3 4.5 V 3.0 10(3) V YEARS Note: 1. All voltages referenced to VSS. 2. Valid for Ambient Operating Temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where noted). 3. At 55°C, VCC = 0V; tDR = 8.5 years (typ) at 70°C. Requires use of M4T32-BR12SH SNAPHAT® top when using the SOH28 package. 20/27 M48T08, M48T08Y, M48T18 PACKAGE MECHANICAL INFORMATION Figure 15. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Outline A2 A1 B1 B A L C e1 eA e3 D N E 1 PCDIP Note: Drawing is not to scale. Table 12. PCDIP28 – 28-pin Plastic DIP, battery CAPHAT, Package Mechanical Data mm inches Symb Typ Min Max A 8.89 A1 Typ Min Max 9.65 0.350 0.380 0.38 0.76 0.015 0.030 A2 8.38 8.89 0.330 0.350 B 0.38 0.53 0.015 0.021 B1 1.14 1.78 0.045 0.070 C 0.20 0.31 0.008 0.012 D 39.37 39.88 1.550 1.570 E 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 e3 29.72 36.32 1.170 1.430 eA 15.24 16.00 0.600 0.630 L 3.05 3.81 0.120 0.150 N 28 28 21/27 M48T08, M48T08Y, M48T18 Figure 16. SOH28 – 28-lead Plastic Small Outline, 4-socket battery SNAPHAT, Package Outline A2 A C B eB e CP D N E H A1 α L 1 SOH-A Note: Drawing is not to scale. Table 13. SOH28 – 28-lead Plastic SO, 4-socket battery SNAPHAT, Package Mech. Data mm inches Symb Typ Min A Typ Min 3.05 Max 0.120 A1 0.05 0.36 0.002 0.014 A2 2.34 2.69 0.092 0.106 B 0.36 0.51 0.014 0.020 C 0.15 0.32 0.006 0.012 D 17.71 18.49 0.697 0.728 E 8.23 8.89 0.324 0.350 – – – – eB 3.20 3.61 0.126 0.142 H 11.51 12.70 0.453 0.500 L 0.41 1.27 0.016 0.050 α 0° 8° 0° 8° N 28 e CP 22/27 Max 1.27 0.050 28 0.10 0.004 M48T08, M48T08Y, M48T18 Figure 17. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Outline A1 eA A2 A3 A B L eB D E SHTK-A Note: Drawing is not to scale. Table 14. SH – 4-pin SNAPHAT Housing for 48mAh Battery & Crystal, Package Mech. Data mm inches Symb Typ Min A Max Typ Min 9.78 Max 0.385 A1 6.73 7.24 0.265 0.285 A2 6.48 6.99 0.255 0.275 A3 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 14.22 14.99 0.560 0.590 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 23/27 M48T08, M48T08Y, M48T18 Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline A1 eA A2 A3 A B L eB D E SHTK-A Note: Drawing is not to scale. Table 15. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data mm inches Symb Typ Min A Typ Min 10.54 Max 0.415 A1 8.00 8.51 0.315 .0335 A2 7.24 8.00 0.285 0.315 A3 24/27 Max 0.38 0.015 B 0.46 0.56 0.018 0.022 D 21.21 21.84 0.835 0.860 E 17.27 18.03 0.680 .0710 eA 15.55 15.95 0.612 0.628 eB 3.20 3.61 0.126 0.142 L 2.03 2.29 0.080 0.090 M48T08, M48T08Y, M48T18 PART NUMBERING Table 16. Ordering Information Scheme Example: M48T 18 –100 PC 1 E Device Type M48T Supply Voltage and Write Protect Voltage 08(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V 18/08Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V Speed –100 = 100ns –150 = 150ns –10 = 100ns (M48T08Y) Package PC(1) = PCDIP28 MH(2) = SOH28 Temperature Range 1 = 0 to 70°C Shipping Method For SOH28: blank = Tubes (Not for New Design - Use E) E = ECOPACK Package, Tubes F = ECOPACK Package, Tape & Reel TR = Tape & Reel (Not for New Design - Use F) For PCDIP28: blank = ECOPACK Package, Tubes Note: 1. The M48T08/18 part is offered with the PCDIP28 (e.g., CAPHAT™) package only. 2. The SOIC package (SOH28) requires the SNAPHAT ® battery/crystal package which is ordered separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in Tape & Reel form (see Table 17.). The M48T08Y part is offered in the SOH28 (SNAPHAT) package only. Caution: Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will drain the lithium button-cell battery. For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. Table 17. SNAPHAT Battery Table Part Number Description Package M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH M4T32-BR12SH Lithium Battery (120mAh) SNAPHAT SH 25/27 M48T08, M48T08Y, M48T18 REVISION HISTORY Table 18. Document Revision History Date Version December 1999 1.0 First Issue 07-Feb-00 2.0 From Preliminary Data to Data Sheet; Battery Low Flag paragraph changed; 100ns speed class identifier changed (Tables 3, 4) 11-Jul-00 2.1 tFB changed (Table 10); Watchdog Timer paragraph changed 16-Jul-01 3.0 Reformatted; SNAPHAT battery table added (Table 17); added temp./voltage info. to tables (Tables 8, 9, 3, 4, 10, 11) 01-Aug-01 3.1 Reference to App. Note corrected in “Calibrating the Clock” section 21-Dec-01 3.2 Changes to text in document to reflect addition of M48T08Y option 06-Mar-02 3.3 Fix Ordering Information table and add to footnote (Table 16) 20-May-02 3.4 Modify reflow time and temperature footnotes (Table 6) 29-Aug-02 3.5 tDR specification temperature updated (Table 11) 28-Mar-03 4.0 v2.2 template applied; updated test conditions (Table 10) 10-Dec-03 5.0 Reformatted 30-Mar-04 6.0 Reformatted; Lead-free (Pb-free) information package update (Table 6, 16) 13-Dec-05 7.0 Updated template, Lead-free information, removed footnote (Table 9, 16) 26/27 Revision Details M48T08, M48T08Y, M48T18 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 27/27