IRF IRS25401PBF Led buck regulator control ic Datasheet

September 8, 2010
Datasheet No – PD97524
IRS254(01,11)
LED BUCK REGULATOR CONTROL IC
Product Summary
Features
Topology
• 200 V (IRS25401) and 600 V (IRS25411) half
bridge driver
• Micropower startup (<500 μA)
• ±2% voltage reference
• 140 ns deadtime
• 15.6 V zener clamp on VCC
• Frequency up to 500 kHz
• Auto restart, non-latched shutdown
• PWM dimmable
• Small 8-Lead DIP/8-Lead SOIC packages
Buck
VOFFSET
200V,600V
VOUT
VCC
Io+ & I o- (typical)
0.5A/0.7A
tON & tOFF (typical)
50/30nS
Deadtime (typical)
140nS
Packages
Typical Applications
LED drivers for lamp replacement
LED driver back end current regulator
8-Lead PDIP
IRS254(01,11)PbF
8-LeadSOIC
IRS254(01,11)SPbF
Typical Connection Diagram
VBUS
L2
VOUT+
RS1
RS2
DBOOT
IC1
VCC
CVCC1
COM
DCLAMP
CBUS2
CVCC2
2
IFB
3
CBUS1
DOV
ENN
4
8
IRS25401
ROV1
1
ROV2
CEN
7
6
5
VB
HO
VS
RG1
M1
CBOOT
LO
L1
M2
RG2
COUT
VOUT-
RF
RCS
ROUT
CF
COM
EN
DEN1
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© 2010 International Rectifier
IRS254(01,11)(S)
Table of Contents
Page
Description
3
Qualification Information
5
Absolute Maximum Ratings
6
Recommended Operating Conditions
6
lectrical Characteristics
7
Functional Block Diagram
8
Input/Output Pin Equivalent Circuit Diagram
9
Lead Definitions
10
Lead Assignments
10
Application Information and Additional Details
12
Package Details
17
Tape and Reel Details
18
Part Marking Information
19
Ordering Information
20
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© 2010 International Rectifier
2
IRS254(01,11)(S)
Description
The IRS254(01,11) are high voltage, high frequency buck control ICs for constant LED current regulation. They
incorporate a continuous mode time-delayed hysteretic buck regulator to directly control the average load current,
using an accurate on-chip bandgap voltage reference. These parts directly replace the IRS2540 and IRS2541
with improved latch up immunity.
The application is inherently protected against short circuit conditions, with the ability to easily add open-circuit
protection. An external high-side bootstrap circuit drives the buck switching element at high frequencies. A lowside driver is also provided for synchronous rectifier designs. All functions are realized within a simple 8 pin DIP
or SOIC package.
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© 2010 International Rectifier
3
IRS254(01,11)(S)
Alternate application circuit using a single MOSFET
IRS25401
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© 2010 International Rectifier
4
IRS254(01,11)(S)
†
Qualification Information
Qualification Level
Moisture Sensitivity Level
Industrial††
Comments: This family of ICs has passed JEDEC’s Industrial
qualification. IR’s Consumer qualification level is granted by
extension of the higher Industrial level.
MSL2††† 260°C
SOIC8
(per IPC/JEDEC J-STD-020)
PDIP8
Class B
(per JEDEC standard JESD22-A115)
Class 1C
(per EIA/JEDEC standard EIA/JESD22-A114)
Class I, Level A
(per JESD78)
Yes
Machine Model
ESD
Human Body Model
IC Latch-Up Test
RoHS Compliant
†
††
†††
Not applicable
(non-surface mount package style))
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
Higher qualification ratings may be available should the user have such requirements. Please
contact your International Rectifier sales representative for further information.
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
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© 2010 International Rectifier
5
IRS254(01,11)(S)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM, all currents are defined positive into any lead. The
thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.
Symbol
Definition
Min
Max
Units
IRS25401
-0.3
225
VB
High-side floating well supply voltage
IRS25411
-0.3
625
VS
High-side floating well supply return voltage
VB + 0.3
VB + 0.3
VHO
Floating gate drive output voltage
VS – 0.3
VB + 0.3
V
VLO
Low-side output voltage
-0.3
VCC + 0.3
VIFB
Feedback voltage
-0.3
VCC + 0.3
VENN
Enable voltage
-0.3
VCC + 0.3
ICC
Supply current (†)
-20
20
mA
dV/dt
Allowable offset voltage slew rate
-50
50
V/ns
(8-Pin DIP)
--1
Package power dissipation @ TA ≤+25 ºC
W
PD
(8-Pin SOIC)
--0.625
PD = (TJMAX-TA)/RTHJA
(8-Pin DIP)
--125
RΘJA
Thermal resistance, junction to ambient
ºC/W
(8-Pin SOIC)
--200
TJ
Junction temperature
-55
150
TS
Storage temperature
-55
150
ºC
TL
Lead temperature (soldering, 10 seconds)
--300
† : This IC contains a zener clamp structure between the chip VCC and COM, with a nominal breakdown voltage
of 15.6 V. Please note that this supply pin should not be driven by a low impedance DC power source greater
than VCLAMP specified in the electrical characteristics section.
Recommended Operating Conditions
For proper operation the device should be used within recommended conditions.
Symbol
Definition
Min
Max
VBS
High-side floating supply voltage
VCC -0.7
VCLAMPHS
Steady state high-side floating supply offset
IRS25401
-1
200
VS
voltage
IRS25411
-1
600
VCC
Supply voltage
VCCUV+
VCLAMP
ICC
Supply current
-Note 2
10
TJ
Junction temperature
-25
125
†† : Sufficient current should be supplied to VCC to keep the internal 15.6 V zener regulating at VCLAMP.
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Units
V
© 2010 International Rectifier
6
IRS254(01,11)(S)
Electrical Characteristics
VCC = VBS = VBIAS = 14 V +/- 0.25 V, CLO=CHO=1000 pF, CVCC=CVBS=0.1 μF, TA=25 °C unless otherwise
specified.
Symbol
Definition
Supply Characteristics
VCC supply undervoltage positive going
VCCUV+
threshold
VCC supply undervoltage negative going
VCCUVthreshold
VCC supply undervoltage lockout
VUVHYS
hysteresis
IQCCUV
UVLO mode quiescent current
IQCCENN
Diesabled mode quiescent current
IQCC
Quiescent VCC supply current
Min
Typ
Max Units
8.0
9.0
10.0
6.5
7.5
8.5
1.0
1.2
2.0
-------
50
1.0
1.0
150
2.0
2.0
---
2.0
3.0
14.6
15.6
16.6
V
-----
0.05
1.0
1.0
2.0
mA
6.5
7.5
8.5
6.0
7.0
8.0
Offset supply leakage current
---
1
50
µA
VCLAMPHS VBS high side zener clamp voltage
Current Control Operation
VENNTH+
ENN pin positive threshold
VENNTHENN pin negative threshold
V0.5
0.5 V voltage reference (die level test)
VIFBTH
IFB pin threshold
f
Maximum frequency
Gate Driver Output Characteristics
VOL
Low level output voltage (HO or LO)
VOH
High level output voltage (HO or LO)
tr
Turn-on rise time
tf
Turn-off fall time
Output source/sink short circuit pulsed
IO+/current
DT
Deadtime
tLO,ON
Delay between VIFB>VIFBTH and LO turn-on
tLO,OFF
Delay between VIFB<VIFBTH and LO turn-off
Delay between VIFB<VIFBTH and HO turntHO,ON
on
Delay between VIFB>VIFBTH and HO turntHO,OFF
off
Watchdog timer
tWD
Watchdog timer period
PWWD
LO pulse width
24.4
26.0
27.6
V
2.5
1.7
490
455
---
2.7
2.0
500
500
500
3.0
2.3
510
540
---
---------
COM
VCC
50
30
----120
50
---
0.5/0.7
---
-------
140
320
180
-------
---
320
---
---
180
---
-----
20
1.0
-----
ICC50k
VCC supply current, f = 50 kHz
VCLAMP
VCC zener clamp voltage
Floating Supply Characteristics
IQBS0
Quiescent VBS supply current
IQBS1
Quiescent VBS supply current
VBS supply undervoltage positive going
VBSUV+
threshold
VBS supply undervoltage negative going
VBSUVthreshold
ILK
Test Conditions
VCC rising from 0 V
V
VCC falling from 14 V
µA
VCC=6 V
EN>VENTH+
IFB = 1 V
Duty Cycle = 50%
f = 50 kHz
ICC = 10 mA
mA
VHO = VS
IFB = 0 V
V
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IRS25401:VB=VS=200 V
IRS25411:VB=VS=600 V
ICC = 10 mA
V
mV
kHz
V
ns
A
ns
μs
IFB = 50 kHz square
wave, 200 mV pk-pk
DC offset = 400 mV
Duty Cycle = 50%
IFB =1 V
© 2010 International Rectifier
7
IRS254(01,11)(S)
Functional Block Diagram
DELAY
IFB
LEVEL
SHIFT
PULSE
FILTER &
LATCH
3
UVLO
UVN
DELAY
15.6 V
8
VB
7
HO
6
VS
1
VCC
5
LO
2
COM
ENN 4
100 K
2V
BANDGAP
REFERENCE 0. 5 V
Watchdog
Timer 20 ?S
1 ?S Pulse
Generator
Values in block diagram are typical values
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© 2010 International Rectifier
8
IRS254(01,11)(S)
Input/Output Pin Equivalent Circuit Diagrams: IRS25401/IRS25411
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IRS254(01,11)(S)
Lead Definitions
PIN #
1
2
3
4
5
6
7
8
Symbol
VCC
COM
IFB
ENN
LO
VS
HO
VB
Description
Supply voltage
IC power & signal ground
Current feedback
Disable outputs (LO=High, HO=Low)
Low–side gate driver output
High–side floating return
High–side gate driver output
High–side gate driver floating supply
Lead Assignments
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IRS254(01,11)(S)
State Diagram
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11
IRS254(0,1)(S)PbF
Application Information and Additional
Details
determined as follows. When the inductance value
is large enough to maintain a low ripple on IFB, Iout,avg
can be calculated:
Operating Mode
Iout (avg ) = VIFBTH
The IRS254(01,11) operates as a time-delayed
hysteritic buck controller. During normal operating
conditions the output current is regulated via the IFB
pin voltage (nominal value of 500 mV). This feedback
is compared to an internal high precision bandgap
voltage reference. An on-board dV/dt filter has also
been used to ignore erroneous transitioning.
Once the supply to the IC reaches VCCUV+, the LO
output is held high and the HO output low for a
predetermined period of time. This initiates charging of
the bootstrap capacitor, establishing the VBS floating
supply for the high-side output. The IC then begins
toggling HO and LO outputs as needed to regulate the
current.
(A)
(B)
Fig.2 (A) Storing Energy in Inductor
(B) Releasing Inductor Stored Energy
HO
50%
50%
50%
t_HO_off
Iout
t_HO_on
DT1
DT2
50%
50%
LO
HO
RCS
t_LO_on
t_LO_off
IFB
LO
IFBTH
Fig.1 IRS254(01,11) Control Signals, Iavg=1.2 A
Fig.3 IRS254(0,1) Time Delayed Hysterisis
As long as VIFB is below VIFBTH, HO is on, modulated by
the watchdog timer described below, which maintains
charge for the floating high side on the bootstrap
capacitor. The load is receiving current from VBUS,
which simultaneously stores energy in the inductor, as
VIFB increases, unless the load is open circuit. Once
VIFB crosses VIFBTH, the control loop switches HO off
after the delay tHO,OFF. When HO switches off, LO will
turn on after the deadtime (DT), the inductor then
releases its stored energy into the load and VIFB starts
decreasing. When VIFB drops below VIFBTH again, the
control loop switches HO on after the delay tHO,ON and
LO off after the delay tHO,ON + DT. The switching
continues to regulate the current at an average value
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The control method is hysteretic with a free running
frequency, which enables average current regulation
in constrast to a fixed frequency scheme providing
peak current regulation only. This reduces the part
count since there is no need for frequency setting
components and also provides an inherently stable
system, which acts as a dynamic current source.
A deadtime of approximately 140 ns between the two
gate drive signals is incoporated to prevent shootthrough. The deadtime has been adjusted to maintain
precise current regulation, while still preventing
shoot-through.
© 2010 International Rectifier
12
IRS254(0,1)(S)PbF
Watchdog Timer
Disable (ENN) Pin
During an open circuit condition, without the watchdog
timer, the HO output would remain high at all times and
the charge stored in the bootstrap capacitor CBOOT
would gradually discharge the floating power supply for
the high-side driver, which would then be unable to fully
switch on the upper MOSFET causing high losses. To
maintain sufficient charge on the bootstrap capacitor, a
watchdog timer has been implemented.
In the
condition where VIFB remains below VIFBTH, the HO
output is driven low after 20 μs and the LO output
forced high. This toggling of the outputs will last for
approximately 1 μs to maintain and replenish sufficient
charge on CBOOT.
The disable pin can be used for PWM dimming and
open-circuit protection. When the ENN pin is held
low, the chip remains in a fully functional state with no
alterations to the operating environment. To disable
the control feedback and regulation, a voltage greater
than VENTH (approximately 2.5 V) needs to be applied
to the ENN pin. With the chip in a disabled state, HO
output will remain low, whereas the LO output will
remain high to prevent VS from floating, in addition to
maintaining charge on the bootstrap capacitor. The
threshold for disabling the IRS254(01,11) has been
set to 2.5 V to enhance noise immunity. This 2.5 V
threshold also provides compatibility for a drive signal
from a microcontroller.
Dimming Mode
To achieve dimming, a signal with constant frequency
and adjustable duty cycle can be fed into the ENN
pin. There is a direct linear relationship between the
average load current and duty cycle. If the ratio is
50%, 50% of the maximum set light output will be
realized. Likewise if the ratio is 30%, 70% of the
maximum set light output will be realized. A
sufficiently high frequency of the dimming signal must
be chosen to avoid noticeable flashing or “strobe
light” effect. A signal above 120Hz up to 5kHz is
sufficient.
The ENN pin logic is inverted to provide enable low
so that the default state is with the IC running.
HO
LO
Fig.4 Illustration of Watchdog Timer
Bootstrap Capacitor and Diode
The bootstrap capacitor value needs to be selected so
that it maintains sufficient charge for at least the
approximately 20 μs interval until the watchdog timer
allows the capacitor to recharge. If the capacitor value
is too small, it will discharge in less than 20 μs. The
typical bootstrap capacitor is approximately 100 nF.
The bootstrap diode must be a fast recovery or ultrafast
recovery component to maintain good efficiency. Since
the cathode of the bootstrap diode will be switching
between zero and to the high voltage bus, the reverse
recovery time of this diode is critical. For additional
information concerning the bootstrap components, refer
to the Design Tip (DT 98-2), “Bootstrap Component
Selection For Control ICs” at www.irf.com under Design
Support
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The minimum amount of dimming achievable (light
output approaches 0%) will be determined by the “on”
time of the HO output, when in a fully functional
regulating state. To maintain reliable dimming, it is
recommended to keep the “off” time of the enable
signal at least 10 times that of the HO “on” time. For
example, if the application is running at 75 kHz with
an input voltage of 100 V and an output voltage of 20
V, the HO “on” time will be approximately 2.7 µs
according to standard buck topology theory. This will
set the minimum “off” time of the enable signal to 27
µs.
Duty Cycle =
Vout
20V
∗ 100 =
* 100 = 20%
Vin
100V
HOon time = 20% * 1
75kHz
≈ 2.7 μs
© 2010 International Rectifier
13
IRS254(0,1)(S)PbF
to form the voltage clamp. The repetition of the
spikes can be reduced by simply increasing the
capacitor size.
Enable Duty Cycle Relationship to Light Output
100
90
Enable Pin Duty Cycle
80
The two resistors form a voltage divider for the
output, which is then fed into the cathode of the zener
diode. The diode will only conduct, flooding the
enable pin, when its nominal voltage is exceeded.
The chip will enter a disabled state once the divider
network produces a voltage at least 2.5 V greater
than the zener rating. The capacitor serves only to
filter and slow the transients/switching at the positive
output terminal. The clamped output voltage can be
determined by the following analysis. The choice of
capacitor is at the designer’s discretion.
This scheme will not be adequate in all applications.
An improved method is described in IRPLLED1 Rev
D reference design documentation.
70
60
50
40
30
20
10
0
0
10
20
30
40
50
60
70
80
90
100
Percentage of Light Output
Fig.5 Light Output vs Enable Pin Duty Cycle
EN
Vout =
(2.5V + DZ )(R1 + R2 )
R2
DZ = Zener Diode Nominal Rated Voltage
HO
LO
Fig.6 IRS254(01,11) Dimming Signals
Open Circuit Protection Mode
IRS2540/1
There
are
several
Vout
methods of providing
R1
over voltage protection
at the output if needed.
IFB
The
following
very
3
simple method uses a
EN
voltage
divider,
4
capacitor, and zener
R2
diode,
the
output
Fig.7 Open Circuit
voltage can be clamped
Protection Scheme
at any desired value. In opencircuit condition without any
output clamp, the positive output terminal may reach a
high DC voltage. Switching will still occur between the
HO and LO outputs, whether due to the output voltage
clamp or the watchdog timer. Transients and switching
will be observed at the positive output terminal as seen
in Fig. 8. The difference in signal shape, between the
output voltage and the IFB, is due to the capacitor used
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Fig.8 Open Circuit Fault Signals, with Clamp
Under-voltage Lock-out Mode
The under-voltage lock-out mode (UVLO) is defined
as the state IRS254(01,11) is in when VCC is below
the turn-on threshold of the IC. During startup
conditions, if the IC supply remains below VCCUV+, the
IRS254(01,11) will enter the UVLO mode. This state
is very similar to when the IC has been disabled via
control signals, except that LO is also held low.
When the supply is increased to VCCUV+, the IC enters
© 2010 International Rectifier
14
IRS254(0,1)(S)PbF
the normal operation mode. If already in normal
operation, the IC does not enter UVLO unless the
supply voltage falls below VCCUV--.
has a significant effect on the operating frequency or
current regulation, as can be seen in Figs. 13 and 14.
Inductance Selection
400
390
380
Iout (mA)
To maintain tight hysteretic current regulation the
inductor and output capacitor COUT (in parallel with the
LEDs) need to be large enough to maintain the supply to
the load during tHO,ON and avoid significant
undershooting of the load current, which in turn causes
the average current to fall below the desired value.
470uH
370
680uH
360
1mH
1.5mH
350
First, consider the effect of the inductor when there is no
output capacitor to clearly demonstrate the impact of the
inductor. In this case, the load current is identical to the
inductor current. Fig. 9 shows how the inductor value
impacts the frequency over a range of input voltages. As
can be seen, the input voltage has a great impact on the
frequency and the inductor value has the greatest impact
at reducing the frequency for smaller input voltages.
340
330
30
80
130
180
Vin (V)
Fig.10 Current Regulation for Chosen Inductances
Iout = 350 mA, Vout = 16.8 V
400
380
360
Frequency (kHz)
425
Frequency (kHz)
375
470uH
325
680uH
1mH
275
340
470uH
320
680uH
300
1mH
280
1.5mH
260
240
1.5mH
220
200
225
13
18
23
28
33
Vout (V)
175
30
80
130
180
Fig.11 Frequency Response for Chosen Inductances
Iout = 350 mA, Vin = 50 V
Vin (V)
Fig.9 Frequency Response for Chosen Inductances
Iout = 350 mA, Vout = 16.8 V
345
343
341
339
Iout (mA)
Fig. 10 shows how the variation in load current increases
over a span of input voltages, as the inductance is
decreased. Fig. 11 shows the variation of frequency over
different output voltages and different inductance values.
Finally Fig. 12 shows how the load current variation
increases with lower inductance over a range of output
voltages.
470uH
337
680uH
335
1mH
333
1.5mH
331
329
327
325
The output capacitor can be used simultaneously to
achieve the target frequency and current control
accuracy. Fig. 11 shows how the capacitance reduces
the frequency over a range of input voltage. A small
capacitance of 4.7 μF has a large effect on reducing the
frequency. Fig. 12 shows how the current regulation is
also improved with the output capacitance. There is a
point at which continuing to add capacitance no longer
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13
18
23
28
33
Vout (V)
Fig.12 Current Regulation for Chosen Inductances
Iout = 350 mA, Vin = 50 V
© 2010 International Rectifier
15
IRS254(0,1)(S)PbF
0uF
1000
4.7uF
10uF
Frequency (kHz)
22uF
33uF
47uF
100
10
30
50
70
90
110
130
150
170
Vin (V)
Fig. 13 Iout = 350 mA, Vout = 16.8 V, L = 470 μH
Fig. 15 Iout = 350 mA, Vin = 100 V, Vout = 16.85 V, L = 470 μH,
C out = 33 μF
400
350
Frequency (kHz)
300
250
40V
200
100V
160V
150
100
50
0
0
10
20
30
40
50
Capacitance (uF)
Fig. 14 I out = 350 mA, Vout = 16.8 V, L = 470 μH
The addition of the COUT increases the amount of
energy that can be stored in the output stage, which
also means it can supply current for an increased
period of time. Therefore by slowing down the di/dt
transients in the load, the frequency is effectively
decreased.
With the COUT capacitor, the inductor current is no
longer identical to that seen in the load. The inductor
current will still have a perfectly triangular shape, where
as the load will see the same basic trend in the current,
but all sharp corners will be rounded with all peaks
significantly reduced, as can be seen in Fig. 15
The resistance between VBUS and VCC supply should
be large enough to minimize the current sourced
directly from the input voltage line; value should be on
the order of hundreds of kΩ. Through the supply
resistor, a current will flow to charge the VCC
capacitor. Once the capacitor is charged up to the
VCCUV+ threshold, the IRS254(01,11) enters the micro
start-up regime and begins to operate, activating the
LO and HO outputs. After the first few cycles of
switching, the resistor connected between the output
and VCC will take over and source all necessary
current for the IC. The resistor connecting the output
to the supply should be carefully designed according
to its power rating.
RS 2 =
Vout − 15.6V
10mA
PRS 2 = (10mA) 2 RS 2 ≤
PRS 2 _ Rated
2
Icc ≈ 10mA
VCC Supply
Since the IRS254(01,11) is rated for 200 V (or 600 V),
VBUS can reach values of this magnitude. If a supply
resistor to VBUS is used, it can experience high power
losses. For higher voltage applications if the output
voltage is above VCCUV+ plus one diode drop an
alternate VCC supply scheme utilizing the micro-power
start-up and a resistor feed-back from the output can to
be implemented, as seen in Fig. 16.
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Fig. 16 Alternate Supply Diagram
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16
IRS254(0,1)(S)PbF
Package Details
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© 2010 International Rectifier
17
IRS254(0,1)(S)PbF
Tape and Reel Details
LOADED TAPE FEED DIRECTION
A
B
H
D
F
C
NOTE : CONTROLLING
DIM ENSION IN M M
E
G
CARRIER TAPE DIMENSION FOR
Metric
Code
Min
Max
A
7.90
8.10
B
3.90
4.10
C
11.70
12.30
D
5.45
5.55
E
6.30
6.50
F
5.10
5.30
G
1.50
n/a
H
1.50
1.60
8SOICN
Imperial
Min
Max
0.311
0.318
0.153
0.161
0.46
0.484
0.214
0.218
0.248
0.255
0.200
0.208
0.059
n/a
0.059
0.062
F
D
C
B
A
E
G
H
REEL DIMENSIONS FOR 8SOICN
Metric
Code
Min
Max
A
329.60
330.25
B
20.95
21.45
C
12.80
13.20
D
1.95
2.45
E
98.00
102.00
F
n/a
18.40
G
14.50
17.10
H
12.40
14.40
www.irf.com
Imperial
Min
Max
12.976
13.001
0.824
0.844
0.503
0.519
0.767
0.096
3.858
4.015
n/a
0.724
0.570
0.673
0.488
0.566
© 2010 International Rectifier
18
IRS254(0,1)(S)PbF
Part Marking Information
SOIC
PDIP
www.irf.com
© 2010 International Rectifier
19
IRS254(0,1)(S)PbF
Ordering Information
Base Part Number
Package Type
PDIP8
IRS25401
SOIC8
PDIP8
IRS25411
SOIC8
Standard Pack
Complete Part Number
Form
Quantity
Tube/Bulk
50
IRS25401PBF
Tube/Bulk
95
IRS25401SPBF
Tape and Reel
2500
IRS25401STRPBF
Tube/Bulk
50
IRS25411PBF
Tube/Bulk
95
IRS25411SPBF
Tape and Reel
2500
IRS25411STRPBF
The information provided in this document is believed to be accurate and reliable. However, International Rectifier assumes no responsibility
for the consequences of the use of this information. International Rectifier assumes no responsibility for any infringement of patents or of
other rights of third parties which may result from the use of this information. No license is granted by implication or otherwise under any
patent or patent rights of International Rectifier. The specifications mentioned in this document are subject to change without notice. This
document supersedes and replaces all information previously supplied.
For technical support, please contact IR’s Technical Assistance Center
http://www.irf.com/technical-info/
WORLD HEADQUARTERS:
233 Kansas St., El Segundo, California 90245
Tel: (310) 252-7105
www.irf.com
© 2010 International Rectifier
20