49 CY7C148 CY7C149 1Kx4 Static RAM Features • • • • sion is provided by an active LOW chip select (CS) input and three-state outputs. The CY7C148 remains in a low-power mode as long as the device remains unselected; i.e., (CS) is HIGH, thus reducing the average power requirements of the device. The chip select (CS) of the CY7C149 does not affect the power dissipation of the device. Automatic power-down when deselected (7C148) CMOS for optimum speed/power 25-ns access time Low active power — 440 mW (commercial) Writing to the device is accomplished when the chip select (CS) and write enable (WE) inputs are both LOW. Data on the I/O pins (I/O0 through I/O3) is written into the memory locations specified on the address pins (A0 through A9). — 605 mW (military) • Low standby power (7C148) — 82.5 mW (25-ns version) Reading the device is accomplished by taking chip select (CS) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the location specified on the address pins will appear on the four data I/O pins. — 55 mW (all others) • 5-volt power supply ± 10% tolerance, both commercial and military • TTL-compatible inputs and outputs The I/O pins remain in a high-impedance state when chip select (CS) is HIGH or write enable (WE) is LOW. Functional Description The CY7C148 and CY7C149 are high-performance CMOS static RAMs organized as 1024 by 4 bits. Easy memory expan- Logic Block Diagram Pin Configurations DIP Top View A6 A5 A4 A3 A0 A1 A2 64 x 64 ARRAY I/O0 SENSE AMP CS GND I/O1 I/O 3 WE LCC Top View CS A4 A13 A10 A11 A12 WE A3 A2 A1 A0 VCC A7 A8 A9 I/O 0 I/O 1 I/O 2 C148–2 I/O2 POWER DOWN (7C148) 14 13 12 11 10 7 8 9 I/O3 COLUMN DECODER 18 17 16 15 A5 A6 VCC A7 A9 A8 A7 A6 A5 A4 ROW DECODER INPUTBUFFER 1 2 3 4 5 6 CS GND WE I/03 C148–1 2 1 1817 3 16 4 15 5 14 6 13 7 12 8 9 1011 A8 A9 I/O 0 I/O 1 I/O2 C148–3 Selection Guide 7C148−25 7C148−35 7C148−45 7C149−25 7C149−35 7C149−45 Maximum Access Time (ns) 25 35 45 25 35 45 Maximum Operating Current (mA) Commercial 90 90 Maximum Standby Current (mA) Commercial Military 15 Military Cypress Semiconductor Corporation Document #: 38-05059 Rev. ** • 80 80 110 110 10 10 10 10 3901 North First Street • San Jose • 80 80 110 110 CA 95134 • 408-943-2600 Revised September 18, 2001 [+] Feedback CY7C148 CY7C149 Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ......................................−65°C to+150°C Latch-Up Current..................................................... >200 mA Operating Range Ambient Temperature with Power Applied................................................... −55°C to+125°C Ambient Temperature VCC Commercial 0°C to +70°C 5V ± 10% Military[1] −55°C to +125°C 5V ± 10% Range Supply Voltage to Ground Potential (Pin 18 to Pin 9)....................................................−0.5V to+7.0V DC Voltage Applied to Outputs in High Z State ......................................................−0.5V to+7.0V Note: 1. TA is the “instant on” case temperature. DC Input Voltage .................................................−3.0V to +7.0V Electrical Characteristics Over the Operating Range[2] 7C148−25 7C149−25 Parameter Description Test Conditions Min. 7C148−35, 45 7C149−35, 45 Max. VOH Output HIGH Voltage VCC = Min., IOH = −4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.0 6.0 VIL Input LOW Voltage −3.0 0.8 IIX Input Load Current GND < VI < VCC −10 10 IOZ Output Leakage Current GND < VO < VCC Output Disabled −50 50 ICC VCC Operating Supply Current Max. VCC, CS < VIL, Output Open Automatic CS Power-Down Current Max. VCC, CS > VIH Peak Power-On Current[3] Max. VCC, CS > VIH Output Short Circuit Current[4] GND < VO < VCC ISB IPO IOS 2.4 Min. 2.4 0.4 Com’l 90 Mil 7C148 Only Com’l 7C148 Only Com’l Unit V 0.4 V 2.0 6.0 V −3.0 0.8 V −10 10 µA −50 50 µA 80 mA 110 15 10 Mil mA 10 15 10 Mil Com’l Max. mA 10 ±275 ±275 mA ±350 Mil Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = 5.0V Max. Unit 8 pF 8 pF Notes: 2. See the last page of this specification for Group A subgroup testing information. 3. A pull-up resistor to VCC on the CS input is required to keep the device deselected during VCC power-up. Otherwise current will exceed values given (CY7C148 only). 4. For test purposes, not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05059 Rev. ** Page 2 of 9 [+] Feedback CY7C148 CY7C149 AC Test Loads and Waveforms R1481 Ω 5V R1481 Ω 5V OUTPUT ALL INPUT PULSES OUTPUT R2 255Ω 30 pF INCLUDING JIG AND SCOPE R2 255Ω 5 pF INCLUDING JIG AND SCOPE (a) Equivalent to: 3.0V 90% 90% 10% 10% GND < 10 ns < 10 ns C148–5 C148–4 (b) THÉVENIN EQUIVALENT OUTPUT 167Ω 1.73V Switching Characteristics Over the Operating Range[2] 7C148−25 7C149−25 Parameter Description Min. Max. 7C148−35 7C149−35 Min. Max. 7C148−45 7C149−45 Min. Max. Unit READ CYCLE tRC Address Valid to Address Do Not Care Time (Read Cycle Time) tAA Address Valid to Data Out Valid Delay (Address Access Time) tACS1 tACS2 Chip Select LOW to Data Out Valid (7C148 only) tACS Chip Select LOW to Data Out Valid (7C149 only) tLZ[8] Chip Select LOW to Data Out On tHZ[8] Chip Select HIGH to Data Out Off tOH Address Unknown to Data Out Unknown Time tPD Chip Select HIGH to Power-Down Delay 7C148 tPU Chip Select LOW to Power-Up Delay 7C148 25 35 8 7C149 5 0 ns 25 35 45 ns 25[6] 35 45 ns 30[7] 35 45 ns 20 ns 15 7C148 45 15 10 10 5 15 0 0 5 20 0 20 ns 0 20 5 30 ns ns 30 ns 0 0 0 ns WRITE CYCLE tWC Address Valid to Address Do Not Care (Write Cycle Time) 25 35 45 ns tWP[9] Write Enable LOW to Write Enable HIGH 20 30 35 ns tWR Address Hold from Write End 5 5 5 ns tWZ [8] Write Enable to Output in High Z 0 tDW Data in Valid to Write Enable HIGH 12 20 20 ns tDH Data Hold Time 0 0 0 ns tAS Address Valid to Write Enable LOW 0 0 0 ns tCW [9] 8 0 8 0 8 ns Chip Select LOW to Write Enable HIGH 20 30 40 ns tOW[8] Write Enable HIGH to Output in Low Z 0 0 0 ns tAW Address Valid to End of Write 20 30 35 ns Notes: 6. Chip deselected greater than 25 ns prior to selection. 7. Chip deselected less than 25 ns prior to selection. 8. At any given temperature and voltage condition, tHZ is less than tLZ for all devices. Transition is measured ±500 mV from steady-state voltage with specified loading in part (b) of AC Test Loads. 9. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going high. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. Document #: 38-05059 Rev. ** Page 3 of 9 [+] Feedback CY7C148 CY7C149 Switching Waveforms Read Cycle No. 1 [10,11] tRC ADDRESS tOH DATA OUT tAA DATA VALID PREVIOUS DATA VALID C148–6 Read Cycle No. 2 [10,12] tRC CS tACS tLZ DATA OUT tHZ HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tPU tPD ICC VCC SUPPLY CURRENT 50% 50% ISB C148–7 Write Cycle No.1 (WE Controlled) tWC ADDRESS tCW CS tAS tAW tWA tWP WE tDW DATA–IN VALID DATA IN tWZ DATA OUT tDH tOW HIGH IMPEDANCE DATA UNDEFINED C148–8 Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CS = VIL. 12. Address valid prior to or coincident with CS transition LOW. Document #: 38-05059 Rev. ** Page 4 of 9 [+] Feedback CY7C148 CY7C149 Switching Waveforms (continued) Write Cycle No. 2 (CSControlled) [13] tWC ADDRESS tCW CS tWR tAW tWP WE tDH tDW DATA IN DATAIN VALID tWZ DATA OUT HIGH IMPEDANCE DATA UNDEFINED C148–9 Notes: 13. If CS goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. NORMALIZED SUPPLY CURRENT vs.AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs.SUPPLY VOLTAGE 1.2 1.2 NORMALIZED CC I, I SB ICC 1.0 0.8 VIN =5.0V TA =25°C 0.6 0.4 ICC 1.0 0.8 0.6 0.4 VCC =5.0V VIN =5.0V 0.2 0.2 0.0 4.0 ISB ISB 4.5 5.0 5.5 0.0 −55 6.0 NORMALIZED ACCESS TIME vs.AMBIENT TEMPERATURE NORMALIZED ACCESS TIME vs.SUPPLY VOLTAGE 1.4 1.6 1.3 1.4 NORMALIZED t AA NORMALIZED t AA 125 1.2 1.1 TA =25°C 1.0 1.2 1.0 VCC =5.0V 0.8 0.9 4.5 5.0 5.5 SUPPLY VOLTAGE(V) Document #: 38-05059 Rev. ** OUTPUT SOURCE CURRENT vs.OUTPUT VOLTAGE 120 100 80 VCC =5.0V TA =25°C 60 40 20 0 0.0 AMBIENT TEMPERATURE(°C) SUPPLY VOLTAGE(V) 0.8 4.0 25 6.0 0.6 −55 25 125 AMBIENT TEMPERATURE(°C) 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) OUTPUT SINK CURRENT (mA) NORMALIZED CC I, I SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE 140 120 100 80 60 VCC =5.0V TA =25°C 40 20 0 0.0 1.0 2.0 3.0 4.0 OUTPUT VOLTAGE(V) Page 5 of 9 [+] Feedback CY7C148 CY7C149 Typical DC and AC Characteristics TYPICAL POWER–ON CURRENT vs.SUPPLY VOLTAGE(7C148) TYPICAL ACCESS TIME CHANGE vs.OUTPUT LOADING TA =25°C 1K Ω CSPULL–UP RESISTORTOV CC 2.0 1.5 ISB 1.0 0.0 0.0 1.4 25.0 1.3 20.0 15.0 10.0 VCC =4.5V TA =25°C 5.0 0.5 1.0 2.0 3.0 4.0 0.0 5.0 NORMALIZED I CC vs.ACCESS TIME 30.0 SUPPLY VOLTAGE(V) 0 200 400 600 800 1000 NORMALIZED I CC 2.5 DELTA tAA (ns) NORMALIZED I PO 3.0 1.2 1.1 1.0 0.9 0.8 10 CAPACITANCE (pF) 20 30 40 50 60 CYCLE FREQUENCY (MHz) Ordering Information Speed (ns) Ordering Code 25 CY7C148−25PC 35 45 Speed (ns) Package Type Operating Range P3 18-Lead (300-Mil) Molded DIP Commercial CY7C148−35PC P3 18-Lead (300-Mil) Molded DIP Commercial CY7C148−35DMB D4 18-Lead (300-Mil) CerDIP Military CY7C148−45PC P3 18-Lead (300-Mil) Molded DIP Commercial CY7C148−45DMB D4 18-Lead (300-Mil) CerDIP Military Ordering Code 25 CY7C149−25PC 35 45 Package Name Package Name Package Type Operating Range P3 18-Lead (300-Mil) Molded DIP Commercial CY7C149−35PC P3 18-Lead (300-Mil) Molded DIP Commercial CY7C149−35DMB D4 18-Lead (300-Mil) CerDIP Military CY7C149−35LMB L50 18-Pin Rectangular Leadless Chip Carrier CY7C149−45PC P3 18-Lead (300-Mil) Molded DIP Commercial CY7C149−45DMB D4 18-Lead (300-Mil) CerDIP Military CY7C149−45LMB L50 18-Pin Rectangular Leadless Chip Carrier Document #: 38-05059 Rev. ** Page 6 of 9 [+] Feedback CY7C148 CY7C149 MILITARY SPECIFICATIONS Group A Subgroup Testing Switching Characteristics Parameters DC Characteristics Subgroups READ CYCLE Subgroups tRC IOH 1, 2, 3 tAA IOL 1, 2, 3 tACS1 [14] 7, 8, 9, 10, 11 VIH 1, 2, 3 tACS2[14] 7, 8, 9, 10, 11 VIL Max. 1, 2, 3 tACS[15] 7, 8, 9, 10, 11 IIX 1, 2, 3 1, 2, 3 tOH 7, 8, 9, 10, 11 IOZ ICC 1, 2, 3 ISB[14] 1, 2, 3 Parameters 7, 8, 9, 10, 11 7, 8, 9, 10, 11 WRITE CYCLE tWC 7, 8, 9, 10, 11 tWP 7, 8, 9, 10, 11 tWR 7, 8, 9, 10, 11 tDW 7, 8, 9, 10, 11 tDH 7, 8, 9, 10, 11 tAS 7, 8, 9, 10, 11 tAW 7, 8, 9, 10, 11 Notes: 14. 7C148 only. 15. 7C149 only. Document #: 38-05059 Rev. ** Page 7 of 9 [+] Feedback CY7C148 CY7C149 18–Lead(300–Mil) CerDIP D4 MIL−STD−1835 D− 8Config.A 18–Pin Rectangular Leadless ChipCarrier L50 MIL−STD−1835 C−10A 18–Lead(300–Mil) Molded DIP P3 Document #: 38-05059 Rev. ** Page 8 of 9 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. [+] Feedback CY7C148 CY7C149 Document Title: CY7C148 / CY7C149 1K x 4 Static RAM Document Number: 38-05059 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110170 09/29/01 SZV Change from Spec number: 38-00031 to 38-05059 Document #: 38-05059 Rev. ** Page 9 of 9 [+] Feedback