Energy Metering IC with Pulse Output
ADE7755
FEATURES
GENERAL DESCRIPTION
High accuracy, surpasses 50 Hz/60 Hz IEC 687/IEC 1036
Less than 0.1% error over a dynamic range of 500 to 1
Supplies active power on the frequency outputs, F1 and F2
High frequency output CF is intended for calibration and
supplies instantaneous active power
Synchronous CF and F1/F2 outputs
Logic output REVP provides information regarding the sign
of the active power
Direct drive for electromechanical counters and 2-phase
stepper motors (F1 and F2)
Programmable gain amplifier (PGA) in the current channel
facilitates usage of small shunts and burden resistors
Proprietary ADCs and DSPs provide high accuracy over large
variations in environmental conditions and time
On-chip power supply monitoring
On-chip creep protection (no load threshold)
On-chip reference 2.5 V ± 8% (30 ppm/°C typical) with
external overdrive capability
Single 5 V supply, low power (15 mW typical)
Low cost CMOS process
The ADE7755 is a high accuracy electrical energy measurement
IC. The part specifications surpass the accuracy requirements as
quoted in the IEC 1036 standard.
The only analog circuitry used in the ADE7755 is in the ADCs
and reference circuit. All other signal processing (for example,
multiplication and filtering) is carried out in the digital domain.
This approach provides superior stability and accuracy over
extremes in environmental conditions and over time.
The ADE7755 supplies average active power information on the
low frequency outputs, F1 and F2. These logic outputs can be
used to directly drive an electromechanical counter or interface to
an MCU. The CF logic output gives instantaneous active power
information. This output is intended to be used for calibration
purposes or for interfacing to an MCU.
The ADE7755 includes a power supply monitoring circuit on the
AVDD supply pin. The ADE7755 remains in a reset condition until
the supply voltage on AVDD reaches 4 V. If the supply falls below
4 V, the ADE7755 resets and no pulse is issued on F1, F2, and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched whether the HPF in Channel 1
is on or off. An internal no load threshold ensures that the
ADE7755 does not exhibit any creep when there is no load.
The ADE7755 is available in a 24-lead SSOP package.
FUNCTIONAL BLOCK DIAGRAM
G0 G1
AVDD
AGND
AC/ DC
DVDD
DGND
16 15
3
11
2
1
21
ADE7755
POWER
SUPPLY MONITOR
V1P 5
V1N 6
SIGNAL
PROCESSING
BLOCK
PHASE
CORRECTION
...110101...
ADC
PGA
×1, ×2, ×8, ×16
HPF
LPF
MULTIPLIER
ADC
...11011001...
DIGITAL-TO-FREQUENCY
CONVERTER
4kΩ
2.5V
REFERENCE
10
REFIN/OUT
17
18
12
14
CLKIN CLKOUT SCF S0
13
20
9
22
24
23
S1 REVP CF
F1
F2
RESET
02896-001
V2P 8
V2N 7
Figure 1.
1
U.S. Patents 5,745,323; 5,760,617; 5,862,069; and 5,872,469.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2009 Analog Devices, Inc. All rights reserved.
ADE7755
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Inputs ............................................................................. 13
General Description ......................................................................... 1
Typical Connection Diagrams .................................................. 14
Functional Block Diagram .............................................................. 1
Power Supply Monitor ............................................................... 14
Revision History ............................................................................... 2
Digital-to-Frequency Conversion ............................................ 15
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 4
Interfacing the ADE7755 to a Microcontroller for Energy
Measurement ............................................................................... 16
Absolute Maximum Ratings............................................................ 5
Power Measurement Considerations ....................................... 16
ESD Caution .................................................................................. 5
Transfer Function ....................................................................... 17
Pin Configuration and Function Descriptions ............................. 6
Selecting a Frequency for an Energy Meter Application ...... 18
Typical Performance Characteristics ............................................. 8
Frequency Outputs ..................................................................... 18
Terminology .................................................................................... 11
No Load Threshold .................................................................... 19
Theory of Operation ...................................................................... 12
Outline Dimensions ....................................................................... 20
Power Factor Considerations .................................................... 12
Ordering Guide .......................................................................... 20
Nonsinusoidal Voltage and Current ........................................ 13
REVISION HISTORY
8/09—Rev. 0 to Rev. A
Changes to Format ............................................................. Universal
Changes to Features Section and General Description Section . 1
Moved Figure 2 ................................................................................. 4
Changes to Pin 22, Pin 23, and Pin 24 Descriptions, Table 4 ..... 7
Changes to Terminology Section.................................................. 11
Changes to Theory of Operation Section, Figure 22, Power
Factor Considerations Section, and Figure 23 ............................ 12
Changes to Nonsinusoidal Voltage and Current Section and
Analog Inputs Section .................................................................... 13
Changes to Figure 27 ...................................................................... 14
Changes to HPF and Offset Effects Section, Figure 29, and
Digital-to-Frequency Conversion Section .................................. 15
Changes to Figure 32 ...................................................................... 16
Changes to Transfer Function Section......................................... 17
Changes to Selecting a Frequency for an Energy Meter
Application Section ........................................................................ 18
Changes to No Load Threshold Section ...................................... 19
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
5/02—Revision 0: Initial Version
Rev. A | Page 2 of 20
ADE7755
SPECIFICATIONS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C.
Table 1.
Parameter
ACCURACY 1, 2
Measurement Error1 on Channel 1
Gain = 1
Gain = 2
Gain = 8
Gain = 16
Phase Error1 Between Channels
V1 Phase Lead 37° (PF = 0.8 Capacitive)
V1 Phase Lag 60° (PF = 0.5 Inductive)
AC Power Supply Rejection1
Output Frequency Variation (CF)
Min
Degrees
Degrees
0.2
% reading
±0.3
% reading
±1
±7
V
kΩ
kHz
mV
% ideal
±0.2
% ideal
390
14
±25
2.7
2.3
3.2
10
V
V
kΩ
pF
Test Conditions/Comments
Channel 2 with full-scale signal (±660 mV), 25°C
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
Over a dynamic range of 500 to 1
Line frequency = 45 Hz to 65 Hz
AC/DC = 0 and AC/DC = 1
AC/DC = 0 and AC/DC = 1
AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
V1 = 100 mV rms, V2 = 100 mV rms @ 50 Hz,
ripple on AVDD of 200 mV rms @ 100 Hz
AC/DC = 1, S0 = S1 = 1, G0 = G1 = 0
V1 = 100 mV rms, V2 = 100 mV rms,
AVDD = DVDD = 5 V ± 250 mV
See the Analog Inputs section
V1P, V1N, V2N, and V2P to AGND
CLKIN = 3.58 MHz
CLKIN/256, CLKIN = 3.58 MHz
Gain = 11, 2
External 2.5 V reference, gain = 1
V1 = 470 mV dc, V2 = 660 mV dc
External 2.5 V reference
2.5 V + 8%
2.5 V − 8%
Nominal 2.5 V
±200
mV
ppm/°C
4
MHz
MHz
±30
Note all specifications for CLKIN of 3.58 MHz
1
LOGIC INPUTS 3
SCF, S0, S1, AC/DC, RESET, G0, and G1
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS3
F1 and F2
Output High Voltage, VOH
Output Low Voltage, VOL
CF and REVP
Output High Voltage, VOH
Output Low Voltage, VOL
Unit
% reading
% reading
% reading
% reading
±0.1
±0.1
Gain Error Match1
REFERENCE INPUT
REFIN/OUT Input Voltage Range
Input Impedance
Input Capacitance
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
CLKIN
Input Clock Frequency
Max
0.1
0.1
0.1
0.1
DC Power Supply Rejection1
Output Frequency Variation (CF)
ANALOG INPUTS
Maximum Signal Levels
Input Impedance (DC)
−3 dB Bandwidth
ADC Offset Error1, 2
Gain Error1
Typ
2.4
0.8
±3
10
V
V
μA
pF
DVDD = 5 V ± 5%
DVDD = 5 V ± 5%
Typically 10 nA, VIN = 0 V to DVDD
0.5
V
V
ISOURCE = 10 mA, DVDD = 5 V
ISINK = 10 mA, DVDD = 5 V
0.5
V
V
ISOURCE = 5 mA, DVDD = 5 V
ISINK = 5 mA, DVDD = 5 V
4.5
4
Rev. A | Page 3 of 20
ADE7755
Parameter
POWER SUPPLY
AVDD
Min
Typ
Max
4.75
5.25
DVDD
4.75
5.25
3
2.5
AIDD
DIDD
1
2
3
Unit
V
V
V
V
mA
mA
Test Conditions/Comments
For specified performance
5 V − 5%
5 V + 5%
5 V − 5%
5 V + 5%
Typically 2 mA
Typically 1.5 mA
See the Terminology section.
See the Typical Performance Characteristics section for the plots.
Sample tested during initial release and after any redesign or process change that may affect this parameter.
TIMING CHARACTERISTICS
AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.58 MHz, TMIN to TMAX = −40°C to +85°C.
Table 2.
Parameter 1, 2
t1 3
t2
t3
t43, 4
t5
t6
Specification
275
See Table 7
1/2 t2
90
See Table 8
CLKIN/4
Unit
ms
sec
sec
ms
sec
sec
Test Conditions/Comments
F1 and F2 pulse width (logic low)
Output pulse period; see the Transfer Function section
Time between F1 falling edge and F2 falling edge
CF pulse width (logic high)
CF pulse period; see the Transfer Function section
Minimum time between F1 and F2 pulse
1
Sample tested during initial release and after any redesign or process change that may affect this parameter.
See Figure 2.
3
The pulse widths of F1, F2, and CF are not fixed for higher output frequencies. See the Frequency Outputs section.
4
The CF pulse is always 18 μs in the high frequency mode. See the Frequency Outputs section and Table 8.
2
t1
F1
t6
F2
t2
t3
t5
02896-002
t4
CF
Figure 2. Timing Diagram for Frequency Outputs
Rev. A | Page 4 of 20
ADE7755
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
AVDD to AGND
DVDD to DGND
DVDD to AVDD
Analog Input Voltage to AGND
V1P, V1N, V2P, and V2N
Reference Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature
24-Lead SSOP, Power Dissipation
θJA Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−6 V to +6 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
450 mW
112°C/W
215°C
220°C
Rev. A | Page 5 of 20
ADE7755
DVDD 1
24
F1
AC/DC 2
23
F2
AVDD 3
22
CF
NC 4
21
DGND
ADE7755
20
REVP
TOP VIEW
(Not to Scale)
19
NC
18
CLKOUT
V2P 8
17
CLKIN
RESET 9
16
G0
REFIN/OUT 10
15
G1
AGND 11
14
S0
SCF 12
13
S1
V1P 5
V1N 6
V2N 7
NC = NO CONNECT
02896-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
DVDD
2
AC/DC
3
AVDD
4, 19
5, 6
NC
V1P, V1N
7, 8
V2N, V2P
9
RESET
10
REFIN/OUT
11
AGND
12
SCF
13, 14
S1, S0
15, 16
G1, G0
Description
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7755. The supply
voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled with a 10 μF
capacitor in parallel with a ceramic 100 nF capacitor.
High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (current channel). A Logic 1 on
this pin enables the HPF. The associated phase response of this filter is internally compensated over a
frequency range of 45 Hz to 1 kHz. The HPF should be enabled in power metering applications.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the ADE7755. The supply
should be maintained at 5 V ± 5% for specified operation. Every effort should be made to minimize power
supply ripple and noise at this pin by the use of proper decoupling. This pin should be decoupled to AGND
with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
No Connect.
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with a
maximum differential signal level of ±470 mV for specified operation. Channel 1 also has a PGA, and the gain
selections are outlined in Table 5. The maximum signal level at these pins is ±1 V with respect to AGND. Both
inputs have internal ESD protection circuitry. An overvoltage of ±6 V can be sustained on these inputs without
risk of permanent damage.
Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential input pair
with a maximum differential input voltage of ±660 mV for specified operation. The maximum signal level at
these pins is ±1 V with respect to AGND. Both inputs have internal ESD protection circuitry, and an overvoltage
of ±6 V can be sustained on these inputs without risk of permanent damage.
Reset Pin. A logic low on this pin holds the ADCs and digital circuitry in a reset condition.
Bringing this pin logic low clears the ADE7755 internal registers.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may also be
connected at this pin. In either case, this pin should be decoupled to AGND with a 1 μF ceramic capacitor and
a 100 nF ceramic capacitor.
This pin provides the ground reference for the analog circuitry in the ADE7755, that is, the ADCs and reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground reference
for all analog circuitry, for example, antialiasing filters and current and voltage transducers. For good noise
suppression, the analog ground plane should be connected to the digital ground plane at one point only. A
star ground configuration helps to keep noisy digital currents away from the analog circuits.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output, CF.
Table 8 shows how the calibration frequencies are selected.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion.
This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for
an Energy Meter Application section.
These logic inputs are used to select one of four possible gains for Channel 1, that is, V1. The possible gains
are 1, 2, 8, and 16. See the Analog Inputs section.
Rev. A | Page 6 of 20
ADE7755
Pin No.
17
Mnemonic
CLKIN
18
CLKOUT
20
REVP
21
DGND
22
CF
23, 24
F2, F1
Description
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be
connected across CLKIN and CLKOUT to provide a clock source for the ADE7755. The clock frequency for
specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and 33 pF (ceramic) should
be used with the gate oscillator circuit.
A crystal can be connected across this pin and CLKIN to provide a clock source for the ADE7755. The CLKOUT
pin can drive one CMOS load when an external clock is supplied at CLKIN or by the gate oscillator circuit.
This logic output goes logic high when negative power is detected, that is, when the phase angle between
the voltage and current signals is greater than 90°. This output is not latched and is reset when positive power
is detected again. The output goes high or low at the same time that a pulse is issued on CF.
This pin provides the ground reference for digital circuitry in the ADE7755, that is, the multiplier, filters, and
digital-to-frequency converter. This pin should be tied to the digital ground plane of the PCB. The digital ground
plane is the ground reference for all digital circuitry, for example, counters (mechanical and digital), MCUs, and
indicator LEDs. For good noise suppression, the analog ground plane should be connected to the digital ground
plane at one point only, for example, a star ground.
Calibration Frequency Logic Output. The CF logic output gives instantaneous active power information.
This output is intended to be used for calibration purposes. Also, see the SCF pin description.
Low Frequency Logic Outputs. F1 and F2 supply average active power information. The logic outputs can
be used to directly drive electromechanical counters and 2-phase stepper motors. See the Transfer Function
section.
Rev. A | Page 7 of 20
ADE7755
TYPICAL PERFORMANCE CHARACTERISTICS
0.5
0.5
–40°C
0.4
0.3
0.2
0.2
0.1
0.1
ERROR (%)
0.3
+25°C
0
+85°C
–0.2
–0.3
0.1
–0.4
1
10
FULL-SCALE CURRENT (%)
100
–0.5
0.01
Figure 4. Error as a % of Reading (Gain = 1)
0.6
–40°C PF = 0.5
0.2
0.1
ERROR (%)
+25°C
0
–0.1
+25°C PF = 0.5
–0.2
+85°C
–0.2
+25°C PF = 1
0
+85°C PF = 0.5
–0.3
–0.4
PF = 1
GAIN = 2
ON-CHIP REFERENCE
1
10
FULL-SCALE CURRENT (%)
100
–0.6
0.01
02896-005
0.1
Figure 5. Error as a % of Reading (Gain = 2)
0.1
1
10
FULL-SCALE CURRENT (%)
Figure 8. Error as a % of Reading (Gain = 1)
0.6
0.6
0.5
PF = 0.5
GAIN = 2
ON-CHIP REFERENCE
–40°C
0.4
0.4
0.3
–40°C PF = 0.5
0.2
ERROR (%)
PF = 1
GAIN = 8
ON-CHIP REFERENCE
0.1
+25°C
0
+25°C PF = 1
0
+25°C PF = 0.5
–0.2
–0.1
100
+85°C
–0.2
+85°C PF = 0.5
–0.4
–0.4
0.01
0.1
1
10
FULL-SCALE CURRENT (%)
100
02896-006
–0.3
Figure 6. Error as a % of Reading (Gain = 8)
–0.6
0.01
0.1
1
10
FULL-SCALE CURRENT (%)
Figure 9. Error as a % of Reading (Gain = 2)
Rev. A | Page 8 of 20
100
02896-009
ERROR (%)
0.2
ERROR (%)
100
PF = 0.5
GAIN = 1
ON-CHIP REFERENCE
0.4
0.3
0.2
1
10
FULL-SCALE CURRENT (%)
–40°C
0.4
–0.5
0.01
0.1
Figure 7. Error as a % of Reading (Gain = 16)
0.5
–0.4
+85°C
02896-008
–0.5
0.01
+25°C
–0.1
–0.3
PF = 1
GAIN = 1
ON-CHIP REFERENCE
PF = 1
GAIN = 16
ON-CHIP REFERENCE
0
–0.2
–0.4
–40°C
02896-007
–0.1
02896-004
ERROR (%)
0.4
ADE7755
0.4
0.8
0.6
–40°C PF = 0.5
PF = 0.5
GAIN = 8
ON-CHIP REFERENCE
–40°C
0.2
0.4
0.2
ERROR (%)
ERROR (%)
PF = 1
GAIN = 16
EXTERNAL REFERENCE
0.3
+25°C PF = 1
0
+25°C PF = 0.5
–0.2
0.1
+25°C
0
–0.1
+85°C
–0.2
+85°C PF = 0.5
–0.3
–0.6
0.1
1
10
FULL-SCALE CURRENT (%)
100
–0.4
0.01
02896-010
–0.8
0.01
Figure 10. Error as a % of Reading (Gain = 8)
0.1
100
1
10
FULL-SCALE CURRENT (%)
02896-013
–0.4
Figure 13. Error as a % of Reading over Temperature with an External
Reference (Gain = 16)
0.8
0.4
–40°C PF = 0.5
0.2
0.6
PF = 1
0.4
0
ERROR (%)
+25°C PF = 0.5
–0.4
+85°C PF = 0.5
–1.0
0.01
0
–0.2
PF = 0.5
GAIN = 16
ON-CHIP REFERENCE
0.1
PF = 0.5
–0.4
1
10
FULL-SCALE CURRENT (%)
100
–0.6
45
Figure 11. Error as a % of Reading (Gain = 16)
50
55
60
65
FREQUENCY (Hz)
Figure 14. Error as a % of Reading over Frequency
0.4
0.3
VDD
PF = 1
GAIN = 2
EXTERNAL REFERENCE
ERROR (%)
10µF
100nF
–40°C
1kΩ
0.1
500µΩ
1.5mΩ
10mΩ
+25°C
0
100nF
3
40A TO
40mA
0.2
2
AVDD AC/DC DVDD
NC
F1 24
5
V1P
33nF
U1
–0.1
1kΩ
+85°C
NC 19
CLKOUT 18
33nF
–0.2
1MΩ
–0.3
220V
1
10
FULL-SCALE CURRENT (%)
100
Figure 12. Error as a % of Reading over Temperature with an External
Reference (Gain = 2)
CLKIN 17
10µF
G0 16
V2P
8
33nF
G1 15
10
02896-012
0.1
1kΩ
100nF
CF 22
V2N
7
REFIN/OUT
2
3
11
33pF
K8
Y1
3.58MHz 33pF
VDD
GAIN
SELECT
10kΩ
S1 13
10nF
10nF
10nF
21
NC = NO CONNECT
VDD
Figure 15. Test Circuit for Performance Curves
Rev. A | Page 9 of 20
PS2501-1
S0 14
SCF 12
RESET AGND DGND
9
4
REVP 20
V1N
6
K7
U3
1
F2 23
ADE7755
1kΩ
10µF
1
4
33nF
–0.4
0.01
75
70
02896-015
–0.8
0.2
02896-014
–0.6
02896-011
ERROR (%)
+25°C PF = 1
–0.2
ADE7755
16
14
12
30
DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –9.78871
GAIN = 1
MAXIMUM: 7.2939
TEMPERATURE = 25°C
MEAN: –1.73203
STD. DEV: 3.61157
25
20
HITS
10
HITS
DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –2.48959
MAXIMUM: 5.81126
MEAN: –1.26847
GAIN = 8
TEMPERATURE = 25°C
STD. DEV: 1.57404
8
6
15
10
4
–9
–3
3
CH1 OFFSET (mV)
9
15
0
–15
Figure 16. Channel 1 Offset Distribution (Gain = 1)
18
16
14
35
30
25
10
HITS
HITS
12
–3
3
CH1 OFFSET (mV)
9
15
15
Figure 19. Channel 1 Offset Distribution (Gain = 8)
GAIN = 2
TEMPERATURE = 25°C
DISTRIBUTION
CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –5.61779
MAXIMUM: 6.40821
MEAN: –0.01746
STD. DEV: 2.35129
–9
02896-019
–15
02896-016
0
02896-020
5
2
8
DISTRIBUTION CHARACTERISTICS
NUMBER POINTS: 101
MINIMUM: –1.96823
MAXIMUM: 5.71177
GAIN = 16
MEAN: –1.48279
TEMPERATURE = 25°C
STD. DEV: 1.47802
20
15
6
10
4
5
–15
–9
–3
3
CH1 OFFSET (mV)
9
15
0
Figure 17. Channel 1 Offset Distribution (Gain = 2)
–3
3
CH1 OFFSET (mV)
9
0.5
0.4
0.4
5.25V
0.3
0.3
0.2
0.2
0.1
ERROR (%)
–0.1
–0.2
4.75V
–0.3
–0.1
–0.2
4.75V
–0.3
–0.4
–0.5
–0.5
1
10
FULL-SCALE CURRENT (%)
5V
0
–0.4
0.1
5.25V
0.1
5V
0
100
02896-018
ERROR (%)
–9
Figure 20. Channel 1 Offset Distribution (Gain = 16)
0.5
–0.6
0.01
–15
Figure 18. PSR with Internal Reference (Gain = 16)
–0.6
0.01
0.1
1
10
FULL-SCALE CURRENT (%)
Figure 21. PSR with External Reference (Gain = 16)
Rev. A | Page 10 of 20
100
02896-021
0
02896-017
2
ADE7755
TERMINOLOGY
Measurement Error
The error associated with the energy measurement made by the
ADE7755 is defined by the following formula:
Percentage Error =
Energy Registered by the ADE7755 − True Energy
True Energy
×100%
Phase Error Between Channels
The high-pass filter (HPF) in Channel 1 has a phase lead response.
To offset this phase response and equalize the phase response
between channels, a phase compensation network is also placed
in Channel 1. The phase compensation network matches the
phase to within ±0.1° over a range of 45 Hz to 65 Hz and ±0.2°
over a range of 40 Hz to 1 kHz. See Figure 30 and Figure 31.
Power Supply Rejection (PSR)
The PSR quantifies the ADE7755 measurement error as a
percentage of the reading when the power supplies are varied.
For the ac PSR measurement, a reading at nominal supplies
(5 V) is taken. A 200 mV rms/100 Hz signal is then introduced
onto the supplies and a second reading is obtained under the
same input signal levels. Any error introduced is expressed as a
percentage of the reading (see the Measurement Error definition).
ADC Offset Error
The ADC offset error refers to the dc offset associated with the
analog inputs to the ADCs. It means that with the analog inputs
connected to AGND, the ADCs still see a small dc signal
(offset). The offset decreases with increasing gain in Channel 1.
This specification is measured at a gain of 1. At a gain of 16, the
dc offset is typically less than 1 mV. However, when the HPF is
switched on, the offset is removed from the current channel,
and the power calculation is not affected by this offset.
Gain Error
The gain error of the ADE7755 is defined as the difference between
the measured output frequency (minus the offset) and the ideal
output frequency. It is measured with a gain of 1 in Channel 1.
The difference is expressed as a percentage of the ideal frequency.
The ideal frequency is obtained from the ADE7755 transfer
function (see the Transfer Function section).
Gain Error Match
The gain error match is defined as the gain error (minus the
offset) obtained when switching between a gain of 1 and a gain
of 2, 8, or 16. It is expressed as a percentage of the output frequency
obtained under a gain of 1. This gives the gain error observed
when the gain selection is changed from 1 to 2, 8, or 16.
For the dc PSR measurement, a reading at nominal supplies
(5 V) is taken. The supplies are then varied ±5% and a second
reading is obtained with the same input signal levels. Any error
introduced is again expressed as a percentage of the reading.
Rev. A | Page 11 of 20
ADE7755
THEORY OF OPERATION
The two ADCs of the ADE7755 digitize the voltage signals from
the current and voltage transducers. These ADCs are 16-bit,
second-order Σ-Δ with an oversampling rate of 900 kHz. This
analog input structure greatly simplifies transducer interfacing
by providing a wide dynamic range for direct connection to the
transducer and also by simplifying the antialiasing filter design.
A programmable gain stage in the current channel further
facilitates easy transducer interfacing. A high-pass filter in the
current channel removes any dc components from the current
signal. This removal eliminates any inaccuracies in the active
power calculation due to offsets in the voltage or current signals
(see the HPF and Offset Effects section).
POWER FACTOR CONSIDERATIONS
The active power calculation is derived from the instantaneous
power signal. The instantaneous power signal is generated by a
direct multiplication of the current and voltage signals. To
extract the active power component (that is, the dc component),
the instantaneous power signal is low-pass filtered. Figure 22
illustrates the instantaneous active power signal and shows how
the active power information can be extracted by low-pass filtering
the instantaneous power signal. This scheme correctly calculates
active power for nonsinusoidal current and voltage waveforms
at all power factors. All signal processing is carried out in the
digital domain for superior stability over temperature and time.
This is the correct active power calculation.
The method used to extract the active power information from
the instantaneous power signal (that is, by low-pass filtering) is
valid even when the voltage and current signals are not in phase.
Figure 23 displays the unity power factor condition and a
displacement power factor (DPF) = 0.5, that is, current signal
lagging the voltage by 60°. Assuming that the voltage and current
waveforms are sinusoidal, the active power component of the
instantaneous power signal (that is, the dc term) is given by
⎛V × I ⎞
⎜
⎟ × cos (60°)
⎝ 2 ⎠
V×I
2
0V
CURRENT
VOLTAGE
INSTANTANEOUS
POWER SIGNAL
DIGITAL-TOFREQUENCY
F1
PGA
ADC
F2
HPF
MULTIPLIER
V×I
cos(60°)
2
DIGITAL-TOFREQUENCY
LPF
ADC
CH2
0V
CF
INSTANTANEOUS
POWER SIGNAL {p(t)}
INSTANTANEOUS ACTIVE
POWER SIGNAL
VOLTAGE
Figure 23. DC Component of Instantaneous Power Signal Conveys
Active Power Information PF < 1
V×I
2
02896-022
TIME
p(t) = i(t) × v(t)
WHERE:
v(t) = V × cos(ωt)
i(t) = I × cos(ωt)
V×I
p(t) =
{1+cos (2ωt)}
2
CURRENT
60°
V×I
V×I
2
INSTANTANEOUS ACTIVE
POWER SIGNAL
Figure 22. Signal Processing Block Diagram
The low frequency output of the ADE7755 is generated by
accumulating this active power information. This low frequency
inherently means a long accumulation time between output
pulses. The output frequency is therefore proportional to the
average active power. This average active power information
can, in turn, be accumulated (for example, by a counter) to
generate active energy information. Because of its high output
frequency and shorter integration time, the calibration frequency
(CF) output is proportional to the instantaneous active power.
This is useful for system calibration purposes that take place
under steady load conditions.
Rev. A | Page 12 of 20
02896-023
CH1
INSTANTANEOUS ACTIVE
POWER SIGNAL
INSTANTANEOUS
POWER SIGNAL
ADE7755
NONSINUSOIDAL VOLTAGE AND CURRENT
The active power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current
waveforms in practical applications have some harmonic content.
Using the Fourier Transform operation, instantaneous voltage
and current waveforms can be expressed in terms of their
harmonic content.
∞
(1)
h≠0
ANALOG INPUTS
where:
v(t) is the instantaneous voltage.
VO is the average voltage value.
Vh is the rms value of the voltage harmonic, h.
ah is the phase angle of the voltage harmonic.
i(t ) = IO + 2 ×
Channel 1 (Current Channel)
The voltage output from the current transducer is connected
to the ADE7755 at Channel 1. Channel 1 is a fully differential
voltage input. V1P is the positive input with respect to V1N.
∞
∑ Ih × sin(hωt + βh )
Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 3.5795 MHz.
(2)
h≠0
where:
i(t) is the instantaneous current.
IO is the current dc component.
Ih is the rms value of the current harmonic, h.
βh is the phase angle of the current harmonic.
The maximum peak differential signal on Channel 1 should be
less than ±470 mV (330 mV rms for a pure sinusoidal signal)
for specified operation. Note that Channel 1 has a programmable
gain amplifier (PGA) with user-selectable gain of 1, 2, 8, or 16
(see Table 5). These gains facilitate easy transducer interfacing.
V1
+470mV
V1P
Using Equation 1 and Equation 2, the active power (P) can be
expressed in terms of its fundamental active power (P1) and
harmonic active power (PH).
P = P 1 + PH
VCM
COMMON-MODE
±100mV MAX
(3)
and
PH is the active power of all harmonic components:
∞
PH = ∑ Vh × I h cos Φ h
h ≠1
Φh = αh – βh
V1
V1N
VCM
AGND
–470mV
where:
P1 is the active power of the fundamental component:
P1 = V1 × I1 cosΦ1
Φ1 = α1 – β1
DIFFERENTIAL INPUT
±470mV MAX PEAK
02896-024
v(t ) = VO + 2 × ∑ Vh × sin(hωt + ah )
A harmonic active power component is generated for every
harmonic, provided that the harmonic is present in both the
voltage and current waveforms. The power factor calculation
previously shown is accurate in the case of a pure sinusoid;
therefore, the harmonic active power must also correctly
account for the power factor because it is made up of a series of
pure sinusoids.
Figure 24. Maximum Signal Levels, Channel 1, Gain = 1
Figure 24 illustrates the maximum signal levels on V1P and
V1N. The maximum differential voltage is ±470 mV divided by
the gain selection. The differential voltage signal on the inputs
must be referenced to a common mode, for example, AGND.
The maximum common-mode signal is ±100 mV, as shown in
Figure 24.
Table 5. Gain Selection for Channel 1
G1
0
0
1
1
Rev. A | Page 13 of 20
G0
0
1
0
1
Gain
1
2
8
16
Maximum Differential Signal (mV)
±470
±235
±60
±30
ADE7755
Channel 2 (Voltage Channel)
Cf
Rf
Cf
AGND
PHASE NEUTRAL
V2
Cf
Ra1
+660mV
Rb1
V2P
VCM
PHASE NEUTRAL
AGND
–660mV
TYPICAL CONNECTION DIAGRAMS
Figure 26 shows a typical connection diagram for Channel 1. A
current transformer (CT) is the current transducer selected for
this example. Note that the common-mode voltage for Channel 1
is AGND and is derived by center-tapping the burden resistor to
AGND. This provides the complementary analog input signals for
V1P and V1N. The CT turns ratio and burden resistor Rb are
selected to give a peak differential voltage of ±470 mV/gain at
maximum load.
AGND
±470mV
GAIN
Rf
The ADE7755 contains an on-chip power supply monitor. The
analog supply (AVDD) is continuously monitored by the ADE7755.
If the supply is less than 4 V ± 5%, the ADE7755 resets. This is
useful to ensure correct device startup at power-up and powerdown. The power supply monitor has built-in hysteresis and
filtering. These features give a high degree of immunity to false
triggering due to noisy supplies.
In Figure 28, the trigger level is nominally set at 4 V. The
tolerance on this trigger level is about ±5%. The power supply
and decoupling for the part should be such that the ripple at
AVDD does not exceed 5 V ± 5%, as specified for normal
operation.
AVDD
5V
4V
V1P
Cf
V1N
0V
TIME
Cf
PHASE NEUTRAL
02896-026
Rb
Cf
Rb + VR = Rf
POWER SUPPLY MONITOR
Channel 2 must be driven from a common-mode voltage, that
is, the differential voltage signal on the input must be referenced
to a common mode (usually AGND). The analog inputs of the
ADE7755 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However, best results are achieved
using a common mode equal to AGND.
Rf
1Ra >> Rb + VR
Figure 27. Typical Connections for Channel 2
Figure 25. Maximum Signal Levels, Channel 2
CT
V2N
Rf
V2N
Figure 26. Typical Connection for Channel 1
Figure 27 shows two typical connections for Channel 2. The first
option uses a potential transformer (PT) to provide complete
isolation from the power line. In the second option, the ADE7755
is biased around the neutral wire, and a resistor divider provides
a voltage signal that is proportional to the line voltage. Adjusting
the ratio of Ra, Rb, and VR is also a convenient way of carrying
out a gain calibration on the meter.
Rev. A | Page 14 of 20
INTERNAL
RESET
RESET
ACTIVE
RESET
Figure 28. On-Chip Power Supply Monitor
02896-028
COMMON-MODE
±100mV MAX
V2
V2P
±660mV
VR1
02896-025
DIFFERENTIAL INPUT
±660mV MAX PEAK
VCM
IP
V2N
±660mV
02896-027
The output of the line voltage transducer is connected to the
ADE7755 at this analog input. Channel 2 is a fully differential
voltage input. The maximum peak differential signal on Channel 2
is ±660 mV. Figure 25 illustrates the maximum signal levels that
can be connected to Channel 2 of the ADE7755.
V2P
Rf
PT
ADE7755
HPF and Offset Effects
0.30
Figure 29 shows the effect of offsets on the active power calculation.
An offset on Channel 1 and Channel 2 contributes a dc component
after multiplication. Because the dc component is extracted by
the LPF, it accumulates as active power. If not properly filtered, dc
offsets introduce error to the energy accumulation. This problem is
easily avoided by enabling the HPF (that is, the AC/DC pin is
set to logic high) in Channel 1. By removing the offset from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at cos(ωt) are removed by the
LPF and the digital-to-frequency conversion (see the Digital-toFrequency Conversion section).
0.25
PHASE (Degrees)
0.20
2
V ×I
–0.10
40
V×I
2
55
60
FREQUENCY (Hz)
65
70
The magnitude response of the filter is given by
H( f ) =
IOS × V
ω
02896-029
VOS × I
0
2ω
FREQUENCY (RAD/s)
Figure 29. Effect of Channel Offset on the Active Power Calculation
The HPF in Channel 1 has an associated phase response that is
compensated for on chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figure 30 and Figure 31 show the phase error between
channels with the compensation network activated. The ADE7755
is phase compensated up to 1 kHz, as shown. This ensures correct
active harmonic power calculation even at low power factors.
0.30
0.25
0.20
PHASE (Degrees)
50
The digital output of the low-pass filter after multiplication
contains the active power information. However, because this
LPF is not an ideal brick-wall filter implementation, the output
signal also contains attenuated components at the line frequency
and its harmonics, that is, cos(hωt) where h = 1, 2, 3, and so on.
× cos(2ωt )
VOS × IOS
0.15
0
300
400 500 600 700
FREQUENCY (Hz)
800
900
1000
02896-030
–0.05
200
(4)
Figure 32 shows the instantaneous active power signal at the
output of the LPF, which still contains a significant amount of
instantaneous power information, that is, cos(2 ωt). This signal
is then passed to the digital-to-frequency converter where it is
integrated (accumulated) over time to produce an output frequency.
This accumulation of the signal suppresses or averages out any
non-dc components in the instantaneous active power signal. The
average value of a sinusoidal signal is 0. Therefore, the frequency
generated by the ADE7755 is proportional to the average active
power. Figure 32 shows the digital-to-frequency conversion for
steady load conditions, that is, constant voltage and current.
0.05
100
1
1 + ( f / 8.9 Hz)
For a line frequency of 50 Hz, the filter gives an attenuation
of the 2ω (100 Hz) component of approximately −22 dB. The
dominating harmonic is at twice the line frequency, that is,
cos(2 ωt), which is due to the instantaneous power signal.
0.10
0
45
02896-031
–0.05
DIGITAL-TO-FREQUENCY CONVERSION
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR ACTIVE
POWER CALCULATION
–0.10
0.05
Figure 31. Phase Error Between Channels (40 Hz to 70 Hz)
+ VOS × IOS + VOS × I cos(ωt ) + IOS × V cos(ωt ) +
2
0.10
0
{V cos(ωt) + VOS} × {I cos(ωt) + IOS} =
V ×I
0.15
Figure 30. Phase Error Between Channels (0 Hz to 1 kHz)
Rev. A | Page 15 of 20
MULTIPLIER
F2
LPF
DIGITAL-TOFREQUENCY
I
CF
LPF TO EXTRACT
REAL POWER
(DC TERM)
V×I
2
F1
CF
FREQUENCY
RIPPLE
AVERAGE
FREQUENCY
TIME
±10%
fOUT
TIME
COUNTER
cos(2ωt)
ATTENUATED BY LPF
CF
REVP1
ω
2ω
FREQUENCY (RAD/s)
UP/DOWN
TIMER
02896-032
0
MCU
ADE7755
TIME
INSTANTANEOUS ACTIVE POWER SIGNAL
(FREQUENCY DOMAIN)
1REVP MUST BE USED IF THE METER IS BIDIRECTIONAL OR
DIRECTION OF ENERGY FLOW IS NEEDED
02896-033
V
FREQUENCY
DIGITAL-TOFREQUENCY
F1
FREQUENCY
ADE7755
Figure 32. Active Power-to-Frequency Conversion
Figure 33. Interfacing the ADE7755 to an MCU
As can be seen in Figure 32, the frequency output CF varies over
time, even under steady load conditions. This frequency variation
is primarily due to the cos(2 ωt) component in the instantaneous
active power signal. The output frequency on CF can be up to
2048 times higher than the frequency on F1 and F2. This higher
output frequency is generated by accumulating the instantaneous
active power signal over a much shorter time while converting
it to a frequency. This shorter accumulation period means less
averaging of the cos(2 ωt) component. Consequently, some of
this instantaneous power signal passes through the digital-tofrequency conversion, which is not a problem in the
application. When CF is used for calibration purposes, the
frequency should be averaged by the frequency counter. This
averaging operation removes any ripple. If CF is measuring
energy, for example, in a microprocessor-based application, the
CF output should also be averaged to calculate power. Because
the outputs, F1 and F2, operate at a much lower frequency,
more averaging of the instantaneous active power signal is
carried out. The result is a greatly attenuated sinusoidal content
and a virtually ripple-free frequency output.
As shown in Figure 33, the frequency output CF is connected to
an MCU counter or port, which counts the number of pulses in
a given integration time that is determined by an MCU internal
timer. The average power proportional to the average frequency
is given by
INTERFACING THE ADE7755 TO A
MICROCONTROLLER FOR ENERGY MEASUREMENT
The easiest way to interface the ADE7755 to a microcontroller
is to use the CF high frequency output with the output frequency
scaling set to 2048 × F1, F2. This is done by setting SCF = 0 and
S0 = S1 = 1 (see Table 8). With full-scale ac signals on the analog
inputs, the output frequency on CF is approximately 5.5 kHz.
Figure 33 illustrates one scheme that can be used to digitize the
output frequency and carry out the necessary averaging described
in the Digital-to-Frequency Conversion section.
Average Frequency = Average Active Power =
Counter
Timer
The energy consumed during an integration period is given by
Energy = Average Power × Time =
Counter
× Time = Counter
Time
For the purpose of calibration, this integration time can be
10 seconds to 20 seconds to accumulate enough pulses to ensure
correct averaging of the frequency. In normal operation, the
integration time can be reduced to 1 second or 2 seconds
depending, for example, on the required update rate of a display.
With shorter integration times on the MCU, the amount of
energy in each update may still have some small amount of
ripple, even under steady load conditions. However, over a
minute or more, the measured energy has no ripple.
POWER MEASUREMENT CONSIDERATIONS
Calculating and displaying power information always has some
associated ripple that depends on the integration period used in
the MCU to determine average power and also the load. For
example, at light loads, the output frequency can be 10 Hz. With
an integration period of 2 seconds, only about 20 pulses are
counted. The possibility of missing one pulse always exists because
the ADE7755 output frequency is running asynchronously to the
MCU timer. This possibility results in a 1-in-20 (or 5%) error in
the power measurement.
Rev. A | Page 16 of 20
ADE7755
If the on-chip reference is used, actual output frequencies may
vary from device to device due to a reference tolerance of ±8%.
TRANSFER FUNCTION
Frequency Outputs F1 and F2
The ADE7755 calculates the product of two voltage signals (on
Channel 1 and Channel 2) and then low-pass filters this product
to extract active power information. This active power information
is then converted to a frequency. The frequency information is
output on F1 and F2 in the form of active low pulses. The pulse
rate at these outputs is relatively low, for example, 0.34 Hz
maximum for ac signals with S0 = S1 = 0 (see Table 7). This
means that the frequency at these outputs is generated from
active power information accumulated over a relatively long
time. The result is an output frequency that is proportional to
the average active power. The averaging of the active power
signal is implicit to the digital-to-frequency conversion. The
output frequency or pulse rate is related to the input voltage
signals by the following equation:
Freq =
8.06 × V1 × V2 × Gain × fi
VREF 2
where:
Freq = output frequency on F1 and F2 (Hz).
V1 = differential rms voltage signal on Channel 1 (volts).
V2 = differential rms voltage signal on Channel 2 (volts).
Gain = 1, 2, 8, or 16, depending on the PGA gain selection
made using logic inputs G0 and G1.
VREF = the reference voltage (2.5 V ± 8%) (volts).
fi = one of the four possible frequencies (f1, f2, f3, or f4) selected
by using the logic inputs S0 and S1, see Table 6.
Table 6. f1, f2, f3, and f4 Frequency Selection
S1
0
0
1
1
1
S0
0
1
0
1
f1, f2, f3, and f4 (Hz)
f1 = 1.7
f2 = 3.4
f3 = 6.8
f4 = 13.6
XTAL/CLKIN1
3.579 MHz/221
3.579 MHz/220
3.579 MHz/219
3.579 MHz/218
Example 1
If full-scale differential dc voltages of +470 mV and −660 mV
are applied to V1 and V2, respectively (470 mV is the maximum
differential voltage that can be connected to Channel 1, and
660 mV is the maximum differential voltage that can be
connected to Channel 2), the expected output frequency
is calculated as follows:
8.06 × V1 × V2 × Gain × f i
VREF 2
In this example, with ac voltages of ±470 mV peak applied to
V1 and ±660 mV peak applied to V2, the expected output
frequency is calculated as follows:
Freq =
8.06 × 0.47 × 0.66 × 1 × 1.7
2 × 2 × 2.5 2
= 0.34
where:
Gain = 1, G0 = G1 = 0.
fi = f1 = 1.7 Hz, S0 = S1 = 0.
V1 = rms of 470 mV peak ac = 0.47/√2 V.
V2 = rms of 660 mV peak ac = 0.66/√2 V.
VREF = 2.5 V (nominal reference value).
If the on-chip reference is used, actual output frequencies may
vary from device to device due to a reference tolerance of ±8%.
As can be seen from these two example calculations, the maximum
output frequency for ac inputs is always half that for dc input
signals. Table 7 shows a complete listing of all the maximum
output frequencies.
Table 7. Maximum Output Frequency on F1 and F2
S1
0
0
1
1
S0
0
1
0
1
Maximum Frequency
for DC Inputs (Hz)
0.68
1.36
2.72
5.44
Maximum Frequency
for AC Inputs (Hz)
0.34
0.68
1.36
2.72
Frequency Output CF
f1, f2, f3, or f4 is a binary fraction of the master clock and, therefore, varies if
the specified CLKIN frequency is altered.
Freq =
Example 2
The pulse output CF is intended for use during calibration. The
output pulse rate on CF can be up to 2048 times the pulse rate
on F1 and F2. The lower the fi frequency selected (i = 1, 2, 3, or 4),
the higher the CF scaling (except for the high frequency mode
SCF = 0, S1 = S0 = 1). Table 8 shows how the two frequencies
are related, depending on the state of the logic inputs, S0, S1,
and SCF. Because of its relatively high pulse rate, the frequency
at CF is proportional to the instantaneous active power. As is
the case with F1 and F2, the frequency is derived from the
output of the low-pass filter after multiplication. However, because
the output frequency is high, this active power information is
accumulated over a much shorter time. Therefore, less averaging is
carried out in the digital-to-frequency conversion. With much
less averaging of the active power signal, the CF output is much
more responsive to power fluctuations (see the signal processing
block diagram in Figure 22).
where:
Gain = 1, G0 = G1 = 0.
fi = f1 = 1.7 Hz, S0 = S1 = 0.
V1 = +470 mV dc = 0.47 V (rms of dc = dc).
V2 = −660 mV dc = 0.66 V (rms of dc = |dc|).
VREF = 2.5 V (nominal reference value).
Rev. A | Page 17 of 20
ADE7755
Table 8. Maximum Output Frequency on CF
SCF
1
0
1
0
1
0
1
0
S1
0
0
0
0
1
1
1
1
S0
0
0
1
1
0
0
1
1
f1, f2, f3, and f4 (Hz)
f1 = 1.7
f1 = 1.7
f2 = 3.4
f2 = 3.4
f3 = 6.8
f3 = 6.8
f4 = 13.6
f4 = 13.6
CF Maximum for AC Signals
128 × F1, F2 = 43.52 Hz
64 × F1, F2 = 21.76 Hz
64 × F1, F2 = 43.52 Hz
32 × F1, F2 = 21.76 Hz
32 × F1, F2 = 43.52 Hz
16 × F1, F2 = 21.76 Hz
16 × F1, F2 = 43.52 Hz
2048 × F1, F2 = 5.57 kHz
SELECTING A FREQUENCY FOR AN ENERGY
METER APPLICATION
As shown in Table 6, the user can select one of four frequencies.
This frequency selection determines the maximum frequency
on F1 and F2. These outputs are intended to be used to drive
the energy register (electromechanical or other). Because only
four different output frequencies can be selected, the available
frequency selection has been optimized for a meter constant of
100 imp/kWh with a maximum current between 10 A and 120 A.
Table 9 shows the output frequency for several maximum currents
(IMAX) with a line voltage of 220 V. In all cases, the meter
constant is 100 imp/kWh.
Table 9. F1 and F2 Frequency at 100 imp/kWh
IMAX (A)
12.5
25
40
60
80
120
F1 and F2 (Hz)
0.076
0.153
0.244
0.367
0.489
0.733
The fi frequencies (i = 1, 2, 3, or 4) allow complete coverage of
this range of output frequencies on F1 and F2. When designing
an energy meter, the nominal design voltage on Channel 2 (voltage)
should be set to half scale to allow for calibration of the meter
constant. The current channel should also be no more than half
scale when the meter sees maximum load. This allows overcurrent
signals and signals with high crest factors to be accommodated.
Table 10 shows the output frequency on F1 and F2 when both
analog inputs are half scale. The frequencies listed in Table 10
align well with those listed in Table 9 for maximum load.
When selecting a suitable fi frequency (i = 1, 2, 3, or 4) for a
meter design, the frequency output at IMAX (maximum load)
with a meter constant of 100 imp/kWh should be compared with
Column 4 of Table 10. The frequency that is closest in Table 10
determines the best choice of fi frequency (i = 1, 2, 3, or 4). For
example, if a meter with a maximum current of 25 A is being
designed, the output frequency on F1 and F2 with a meter constant
of 100 imp/kWh is 0.153 Hz at 25 A and 220 V (from Table 9).
Table 10, the closest frequency to 0.153 Hz in Column 4, is 0.17 Hz.
Therefore, f2 (3.4 Hz, see Table 6) is selected for this design.
FREQUENCY OUTPUTS
Figure 2 shows a timing diagram for the various frequency
outputs. The F1 and F2 outputs are the low frequency outputs
that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide
two alternating low going pulses. The pulse width (t1) is set at
275 ms, and the time between the falling edges of F1 and F2 (t3)
is approximately half the period of F1 (t2). If, however, the period of
F1 and F2 falls below 550 ms (1.81 Hz), the pulse width of F1 and
F2 is set to half of their period. The maximum output frequencies
for F1 and F2 are shown in Table 7.
The high frequency CF output is intended to be used for
communications and calibration purposes. CF produces a
90 ms wide active high pulse (t4) at a frequency proportional
to active power. The CF output frequencies are listed in Table 8.
As in the case of F1 and F2, if the period of CF (t5) falls below
180 ms, the CF pulse width is set to half the period. For example,
if the CF frequency is 20 Hz, the CF pulse width is 25 ms.
When the high frequency mode is selected (that is, SCF = 0,
S1 = S0 = 1), the CF pulse width is fixed at 18 μs. Therefore, t4
is always 18 μs, regardless of the output frequency on CF.
Table 10. F1 and F2 Frequency with Half-Scale AC Inputs
S1
0
0
1
1
S0
0
1
0
1
f1, f2, f3, and f4 (Hz)
f1 = 1.7
f2 = 3.4
f3 = 6.8
f4 = 13.6
F1 and F2 Frequency on CH1 and
CH2 Half-Scale AC Inputs (Hz)
0.085
0.17
0.34
0.68
Rev. A | Page 18 of 20
ADE7755
NO LOAD THRESHOLD
The ADE7755 also includes a no load threshold and start-up
current feature that eliminates any creep effects in the meter. The
ADE7755 is designed to issue a minimum output frequency in all
modes except when SCF = 0 and S1 = S0 = 1. The no load detection
threshold is disabled in this output mode to accommodate
specialized application of the ADE7755. Any load generating a
frequency lower than this minimum frequency will not cause a
pulse to be issued on F1, F2, or CF. The minimum output
frequency is given as 0.0014% of the full-scale output frequency
for each of the fi frequencies (i = 1, 2, 3, or 4), see Table 6.
For example, in an energy meter with a meter constant of
100 imp/kWh on F1 and F2 using f2 (3.4 Hz), the maximum
output frequency at F1 or F2 is 0.0014% of 3.4 Hz or 4.76 × 10−5 Hz.
This is 3.05 × 10−3 Hz at CF (64 × F1 Hz). In this example, the no
load threshold is equivalent to 1.7 W of the load or a start-up
current of 8 mA at 220 V. IEC 1036 states that the meter must
start up with a load current equal to or less than 0.4% Ib. For a
5 A (Ib) meter, 0.4% Ib is equivalent to 20 mA. The start-up
current of this design therefore satisfies the IEC requirement.
As illustrated in this example, the choice of fi frequency
(i = 1, 2, 3, or 4) and the ratio of the stepper motor display
determine the start-up current.
Rev. A | Page 19 of 20
ADE7755
OUTLINE DIMENSIONS
8.50
8.20
7.90
13
24
5.60
5.30
5.00
1
8.20
7.80
7.40
12
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
COMPLIANT TO JEDEC STANDARDS MO-150-AG
0.95
0.75
0.55
060106-A
0.05 MIN
COPLANARITY
0.10
0.25
0.09
1.85
1.75
1.65
2.00 MAX
Figure 34. 24-Lead Shrink Small Outline Package [SSOP]
(RS-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADE7755ARSZ 1
ADE7755ARSRLZ1
EVAL-ADE7755EBZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP], 13” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
©2002–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02896-0-8/09(A)
Rev. A | Page 20 of 20
Package Option
RS-24
RS-24