Intersil EL5185CS 4ns high-speed comparator Datasheet

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8
1-88
®
4ns High-Speed Comparator
Features
The EL5185 comparator is designed
for operation in single supply and dual
supply applications with 5V to 12V
between VS+ and V S-. For single supplies, the inputs can
operate from 0.1V below ground for use in ground-sensing
applications.
• 4ns typ. propagation delay
EL5185
FN7179
• 5V to 12V input supply
• +2.7V to +5V output supply
• True-to-ground input
• Rail-to-rail outputs
The output side of the comparator can be supplied from a
single supply of 2.7V to 5V. The rail-to-rail output swing
enables direct connection of the comparator to both CMOS
and TTL logic circuits.
The latch input of the EL5185 can be used to hold the
comparator output value by applying a low logic level to the
pin.
The EL5185 is available in the 8-pin SO package and is
specified for operation over the -40°C to +85°C temperature
range. Also available are dual (EL5285), window comparator
(EL5287), and quad (EL5485 and EL5486) versions.
• Active low latch
• Dual available (EL5285)
• Window comparator (EL5287)
• Quad available (EL5485 & EL5486)
• Pin-compatible 8ns family available (EL5x81, EL5283 &
EL5482)
Applications
• Threshold detection
• High speed sampling circuits
Pinout
• High speed triggers
• Line receivers
EL5185
(8-PIN SO)
TOP VIEW
VS+
1
• PWM circuits
• High speed V/F converters
8
VSD
Ordering Information
IN+
L
A
T
C
H
2
+
-
IN-
VS-
3
7
6
4
5
1
OUT
GND
LATCH
PART
NUMBER
PACKAGE
TAPE & REEL
PKG. NO.
EL5185CS
8-Pin SO
-
MDP0027
EL5185CS-T7
8-Pin SO
7”
MDP0027
EL5185CS-T13
8-Pin SO
13”
MDP0027
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc.
All other trademarks mentioned are the property of their respective owners.
EL5185
Absolute Maximum Ratings (TA = 25°C)
Analog Supply Voltage (V S+ to VS-) . . . . . . . . . . . . . . . . . . . +12.6V
Digital Supply Voltage (VSD to GND) . . . . . . . . . . . . . . . . . . . . .+7V
Differential Input Voltage . . . . . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V]
Common-mode Input Voltage . . . . . . .[(VS-) -0.2V] to [(VS+) +0.2V]
Latch Input Voltage . . . . . . . . . . . . . . . . . . . . -0.2V to [(V SD) +0.2V]
Storage Temperature Range . . . . . . . . . . . . . . . . . . -65°C to +150°C
Ambient Operating Temperature . . . . . . . . . . . . . . . . -40°C to +85°C
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 125°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS = ±5V, VSD = 5V, RL = 2.3kΩ, TA = 25°C, unless otherwise specified.
DESCRIPTION
CONDITION
MIN
TYP
MAX
UNIT
1
4
mV
INPUT
VOS
Input Offset Voltage
VCM = 0V, VO = 2.5V
IB
Input Bias Current
CIN
Input Capacitance
IOS
Input Offset Current
VCM
Input Voltage Range
CMRR
Common-mode Rejection Ratio
-5.1V < VCM < +2.75V
VOH
Output High Voltage
VIN > 250mV
VOL
Output Low Voltage
VIN > 250mV
-10
VCM = 0V, VO = 2.5V
-2.5
-5
µA
5
pF
0.5
(VS-) - 0.1
2.5
µA
(VS+) - 2.25
V
65
90
dB
VSD - 0.6
VSD - 0.4
V
OUTPUT
GND + 0.25
GND + 0.5
V
DYNAMIC PERFORMANCE
tPD+
Positive Going Delay Time
VIN = 1V P-P, VOD = 50mV
4
6
ns
tPD-
Negative Going Delay Time
VIN = 1V P-P, VOD = 50mV
4
6
ns
IS+
Positive Analog Supply Current
Per comparator
12
13.5
mA
IS-
Negative Analog Supply Current
Per comparator
7.5
8.5
mA
ISD
Digital Supply Current at No Load
Per comparator, output high
5.5
6.5
mA
Per comparator, output low
0.9
1.2
mA
SUPPLY
PSRR
Power Supply Rejection Ratio
55
80
dB
LATCH
VLH
Latch Input Voltage High
VLL
Latch Input Voltage Low
ILH
Latch Input Current High
VLH = 3.0V
-30
-18
µA
ILL
Latch Input Current Low
VLL = 0.3V
-30
-24
µA
tD+
Latch Disable to High Delay
4
ns
tD-
Latch Disable to Low Delay
4
ns
tS
Minimum Setup Time
2
ns
tH
Minimum Hold Time
1
ns
tPW(D)
Minimum Latch Disable Pulse Width
5
ns
2
2.0
0.8
V
V
EL5185
Typical Performance Curves
Supply Current vs Supply Voltage
Output High Voltage vs Temperature
14
5
VIN =-50mV
RL=2.3kΩ
12
4.8
IS (mA)
VOH (V)
IS +
10
8
IS -
6
4.6
4.4
4
4.2
2
0
0
1
2
3
4
5
4
-50
6
-30
-10
10
30
50
70
90
50
70
90
Temperature (°C)
±VS (V)
Offset Voltage vs Temperature
Input Bias Current vs Temperature
2.5
9
8
2
7
6
IB (µA)
VOS (mV)
1.5
1
5
4
0.5
3
0
2
-0.5
-50
-30
-10
10
30
50
70
1
-50
90
-30
-10
Temperature (°C)
10
30
Temperature (°C)
Output Low Voltage vs Temperature
Supply Current vs Temperature (per comparator)
0.4
14
Supply Current (mA)
12
VOL (V)
0.3
0.2
IS +
10
8
IS -
6
4
2
0.1
-50
-30
-10
10
30
Temperature (°C)
3
50
70
90
0
-50
-30
-10
10
30
Temperature (°C)
50
70
90
EL5185
Typical Performance Curves
4.2
(Continued)
Propagation Delay vs Overdrive
VIN = 1VSTEP
VS = ±5V
VSD = 5V
RL = 2.3kΩ
4
4.3
TPD +
3.9
3.8
TPD-
3.7
VSD = VS+
VOD = 50mV
RL = 2.2kΩ
4.4
Delay Time (ns)
4.1
Delay Time (ns)
Propagation Delay vs Supply Voltage
4.5
4.2
TPD+
4.1
4
TPD-
3.9
3.8
3.7
3.6
3.6
3.5
3.5
50 100 150 200 250 300 350 400 450 500 550 600
4
4.2
4.4
4.6
4.8
6.8
5.2
5.4
5.6
5.8
6
Digital Supply Current vs Switching Frequency
(per comparator)
Propagation Delay vs Overdrive
VIN = 3VSTEP
25
VS = ±5V
VSD = 5V
RL = 2.3kΩ
6.6
6.4
VS = ±5V
TA = 25°C
RL = 2.3kΩ
20
6.2
ISD (mA)
Delay Time (ns)
5
±VS (V)
VOD (mV)
TPD+
6
5.8
TPD -
5.6
5.4
15
VSD=5V
10
VSD=3V
5
5.2
5
0.2
0
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
2
20
10
7.2
Propagation Delay vs Overdrive
VIN = 5VSTEP
16
VS = ±5V
VSD = 5V
RL = 2.3kΩ
TPD+
6.8
TPD-
6.6
50
6.4
6.2
Propagation Delay vs Source Resistance
VIN = 1VSTEP
VS = ±5V
VSD = 5mV
VOD = 50mV
RL = 2.3kΩ
14
Delay Time (ns)
Delay Time (ns)
7
40
30
Frequency (MHz)
VOD (V)
12
TPD+
10
TPD-
8
6
6
5.8
0.2 0.4 0.6 0.8
4
1
1.2 1.4 1.6 1.8
VOD (V)
4
2
2.2 2.4 2.6
0
0.2
0.4
0.6
0.8
1
1.2
1.4
Source Resistance (kΩ)
1.6
1.8
2
EL5185
Typical Performance Curves
Propagation Delay vs Load Capacitance
VIN=1VSTEP
0.7
VS = ±5V
VSD = 5V
VOD = 50mV
RL = 2.3kΩ
Delay Time (ns)
7
6.5
TPD +
6
TPD-
5.5
5
4.5
625mW
0.5
16
0.4
SO
8
0°
C
/W
0.3
0.2
0.1
4
0
0
20
10
30
40
50
60
70
80
90
100
0
Package Power Dissipation vs Ambient Temperature
JEDEC JESD51-7 High Effective Thermal Conductivity Test
Board
1.2
1 909mW
SO
8
11
0°
C/
W
0.6
Output
(5ns/div,
2V/div)
0.4
Input
(5ns/div,
0.5V/div)
0.2
0
0
25
50
75 85 100
Ambient Temperature (°C)
Output with 50MHz Input
VIN = 3VP-P
Output
(5ns/div,
2V/div)
Input
(5ns/div,
2V/div)
5
50
75 85
Output with 50MHz Input
VIN = 1VP-P
1.4
0.8
25
100
Ambient Temperature (°C)
CLOAD (pF)
Power Dissipation (W)
Package Power Dissipation vs Ambient Temp.
JEDEC JESD51-3 Low Effective Thermal Conductivity
Test Board
0.6
Power Dissipation (W)
7.5
(Continued)
125
150
125
150
EL5185
Timing Diagram
Compare
Compare
Latch
Enable
Input
1.4V
Latch
Latch
Differenti
al Input
Voltage
Latch
tPW(D)
tS
tH
VIN
VOS
VOD
tPD -
tD+
Comparator
Output
2.4V
Definition of Terms
TERM
DEFINITION
VOS
Input Offset Voltage - Voltage applied between the two input terminals to obtain CMOS logic threshold at the output
VIN
Input Voltage Pulse Amplitude - Usually set to 1V for comparator specifications
VOD
Input Voltage Overdrive - Usually set to 50mV and in opposite polarity to VIN for comparator specifications
tPD+
Input to Output High Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to
the CMOS logic threshold of an output low to high transition
tPD-
Input to Output Low Delay - The propagation delay measured from the time the input signal crosses the input offset voltage to
the CMOS logic threshold of an output high to low transition
tD+
Latch Disable to Output High Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a
low to high transition to the point of the output crossing CMOS threshold in a low to high transition
tD-
Latch Disable to Output Low Delay - The propagation delay measured from the latch signal crossing the CMOS threshold in a
low to high transition to the point of the output crossing CMOS threshold in a high to low transition
tS
Minimum Setup Time - The minimum time before the negative transition of the latch signal that an input signal change must be
present in order to be acquired and held at the outputs
tH
Minimum Hold Time - The minimum time after the negative transition of the latch signal that an input signal must remain
unchanged in order to be acquired and held at the output
tPW (D)
Minimum Latch Disable Pulse Width - The minimum time that the latch signal must remain high in order to acquire and hold an
input signal change
6
EL5185
Pin Descriptions
PIN NUMBER
PIN NAME
FUNCTION
1
VS+
Positive supply voltage
2
IN+
Positive input
EQUIVALENT CIRCUIT
VS+
IN-
IN+
VS-
Circuit 1
3
IN-
Negative input
4
VS-
Negative supply voltage
5
LATCH
(Reference Circuit 1)
Latch input
VS+
VSD
VSD
LATCH
VS-
Circuit 2
6
GND
Digital ground
7
OUT
Output
VSD
VS+
OUT
VS-
Circuit 3
8
VSD
Digital Supply
Applications Information
Power Supplies and Circuit Layout
The EL5185 comparator operates with single and dual
supply with 5V to 12V between V S+ and VS-. The output
side of the comparator is supplied by a single supply from
2.7V to 5V. The rail to rail output swing enables direct
connection of the comparator to both CMOS and TTL logic
circuits. As with many high speed devices, the supplies must
be well bypassed. Elantec recommends a 4.7µF tantalum in
parallel with a 0.1µF ceramic. These should be placed as
close as possible to the supply pins. Keep all leads short to
reduce stray capacitance and lead inductance. This will also
minimize unwanted parasitic feedback around the
comparator. The device should be soldered directly to the
PC board instead of using a socket. Use a PC board with a
good, unbroken low inductance ground plane. Good ground
plane construction techniques enhance stability of the
comparators.
7
Input Voltage Considerations
The EL5185 input range is specified from 0.1V below V S- to
2.25V below V S+. The criterion for the input limit is that the
output still responds correctly to a small differential input
signal. The differential input stage is a pair of PNP
transistors, therefore, the input bias current flows out of the
device. When either input signal falls below the negative
input voltage limit, the parasitic PN junction formed by the
substrate and the base of the PNP will turn on, resulting in a
significant increase of input bias current. If one of the inputs
goes above the positive input voltage limit, the output will still
maintain the correct logic level as long as the other input
stays within the input range. However, the propagation delay
will increase. When both inputs are outside the input voltage
range, the output becomes unpredictable. Large differential
voltages greater than the supply voltage should be avoided
to prevent damages to the input stage.
EL5185
Let the hysteresis be VH, and calculate R3:
Input Slew Rate
Most high speed comparators oscillate when the voltage of
one of the inputs is close to or equal to the voltage on the
other input due to noise or undesirable feedback. For clean
output waveform, the input must meet certain minimum slew
rate requirements. In some applications, it may be helpful to
apply some positive feedback (hysteresis) between the
output and the positive input. The hysteresis effectively
causes one comparator's input voltage to move quickly past
the other, thus taking the input out of the region where
oscillation occurs. For the EL5185, the propagation delay
increases when the input slew rate increases for low
overdrive voltages. With high overdrive voltages, the
propagation delay does not change much with the input slew
rate.
VO
R 3 = -------× ( R 1 || R 2 )
VH
where:
VO = VSD-0.8V (swing of the output)
Recalculate R2 to maintain the same value of VTH:

 V TH  V TH -0.5VSD 
R 2 1 = ( ( VREF )-  V TH ) ÷  ---------- + ----------------------------------- 
R3

 R1 

Non inverting comparator with hysteresis:
R3
Latch Pin Dynamics
R1
The EL5185 contains a transparent latch for each channel.
The latch pin is designed to be driven with either a TTL or
CMOS output. When the latch is connected to a logic high
level or left floating, the comparator is transparent and
immediately responds to the changes at the input terminals.
When the latch is switched to a logic low level, the
comparator output remains latched to its value just before
the latch’s high-to-low transition. To guarantee data
retention, the input signal must remain the same state at
least 1ns (hold time) after the latch goes low and at least 2ns
(setup time) before the latch goes low. When the latch goes
high, the new data will appear at the output in approximately
4ns (latch propagation delay).
Hysteresis
+
VIN
VREF
-
R3 adds a portion of the output to the positive input. Note
that the current through R 3 should be much greater than the
input bias current in order to minimize errors. The calculation
of the resistor values as follows:
Pick the value of R 1. R1 should be small (less than 1kΩ) in
order to minimize the propagation delay time.
Choose the hysteresis VH and calculate R 3:
R1
R 3 = ( V SD -0.8 ) × ------V
H
Hysteresis can be added externally. The following two
methods can be used to add hysteresis.
Inverting comparator with hysteresis:
VREF
R3
Check the current through R 3 and make sure that it is much
greater than the input bias current as follows:
0.5VSD -V REF
I = --------------------------------------R3
R2
+
R1
VIN
-
R3 adds a portion of the output to the threshold set by R 1
and R2. The calculation of the resistor values are as follows:
Select the threshold voltage V TH and calculate R1 and R2.
The current through R1/R2 bias string must be many times
greater than the input bias current of the comparator:
R1
V TH = V REF × --------------------R +R
1
The above two methods will generate hysteresis of up to a
few hundred millivolts. Beyond that, the impedance of R 3 is
low enough to affect the bias string and adjustment of R 1
may be required.
Power Dissipation
When switching at high speeds, the comparator's drive
capability is limited by the rise in junction temperature
caused by the internal power dissipation. For reliable
operation, the junction temperature must be kept below
TJMAX (125°C).
An approximate equation for the device power dissipation is
as follows. Assume the power dissipation in the load is very
small:
2
P DISS = ( VS × IS + V SD × I SD )
8
EL5185
where:
Crystal Oscillator
VS is the analog supply voltage from V S+ to VSIS is the analog quiescent supply current per comparator
VSD is the digital supply voltage from VSD to ground
ISD is the digital supply current per comparator
ISD strongly depends on the input switching frequency.
Please refer to the performance curve to choose the input
driving frequency. Having obtained the power dissipation,
the maximum junction temperature can be determined as
follows:
TJMAX = T MAX + Θ JA × PDISS
where:
TMAX is the maximum ambient temperature
A simple crystal oscillator using one comparator of an
EL5185 is shown below. The resistors R1 and R 2 set the
bias point at the comparator's non-inverting input. Resistors
R3, R4, and C 1 set the inverting input node at an appropriate
DC average voltage based on the output. The crystal's path
provides resonant positive feedback and stable oscillation
occurs. Although the EL5185 will give the correct logic
output when an input is outside the common mode range,
additional delays may occur when it is so operated.
Therefore, the DC bias voltages at the inputs are set about
500mV below the center of the common mode range and the
200Ω resistor attenuates the feedback to the non-inverting
input. The circuit will operate with most AT-cut crystal from
1MHz to 8MHz over a 2V to 7V supply range. The output
duty cycle for this circuit is roughly 50% at 5V VCC, but it is
affected by the tolerances of the resistors. The duty cycle
can be adjusted by changing VCC value.
θJA is the thermal resistance of the package
Threshold Detector
5V
200Ω
1MHz to
8MHz
R1
The inverting input is connected to a reference voltage and
the non-inverting input is connected to the input. As the input
passes the VREF threshold, the comparator's output
changes state. The non-inverting and inverting inputs may
be reversed.
VIN
+
VREF
-
5kΩ
+
R2
-
VOUT
1.5kΩ
R3
C1
R4
0.01µF
2kΩ
2kΩ
VOUT
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9
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