ON MC74VHCT74AD Dual d-type flip-flop with set and reset Datasheet

SEMICONDUCTOR TECHNICAL DATA
The MC74VHCT74A is an advanced high speed CMOS D–type flip–flop
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The signal level applied to the D input is transferred to Q output during the
positive going transition of the Clock pulse.
Reset (RD) and Set (SD) are independent of the Clock (CP) and are
accomplished by setting the appropriate input Low.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
The VHCT74A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when VCC=0V. These input and output
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.
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D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
High Speed: fmax = 60MHz (Typ) at VCC = 5V
Low Power Dissipation: ICC = 2µA (Max) at TA = 25°C
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 4.5V to 5.5V Operating Range
Low Noise: VOLP = 0.8V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 128 FETs or 32 Equivalent Gates
ORDERING INFORMATION
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
PIN ASSIGNMENT
LOGIC DIAGRAM
RD1
D1
CP1
SD1
1
13
RD2
2
5
3
6
Q1
D2
Q1
CP2
4
12
9
11
8
Q2
Q2
10
SD2
FUNCTION TABLE
Inputs
Outputs
SD
RD
CP
D
L
H
L
H
H
H
H
H
H
L
L
H
H
H
H
H
X
X
X
X
X
X
H
L
X
X
X
L
H
Q
Q
H
L
L
H
H*
H*
H
L
L
H
No Change
No Change
No Change
* Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
3/98
 Motorola, Inc. 1998
1
SOIC
TSSOP
SOIC EIAJ
REV 0
RD1
1
14
VCC
D1
2
13
RD2
CP1
3
12
D2
SD1
4
11
CP2
Q1
5
10
SD2
Q1
6
9
Q2
GND
7
8
Q2
MC74VHCT74A
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MAXIMUM RATINGS*
Symbol
Value
Unit
DC Supply Voltage
– 0.5 to + 7.0
V
Vin
DC Input Voltage
– 0.5 to + 7.0
V
Vout
DC Output Voltage
– 0.5 to + 7.0
– 0.5 to VCC + 0.5
V
IIK
Input Diode Current
– 20
mA
IOK
Output Diode Current (VOUT < GND; VOUT > VCC)
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air,
500
450
mW
Tstg
Storage Temperature
– 65 to + 150
_C
VCC
Parameter
VCC = 0
High or Low State
SOIC Packages†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high–impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND (Vin or Vout) VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V CC ).
Unused outputs must be left open.
v
v
* Absolute maximum continuous ratings are those values beyond which damage to the device
may occur. Exposure to these conditions or conditions beyond those indicated may adversely
affect device reliability. Functional operation under absolute–maximum–rated conditions is not
implied.
†Derating — SOIC Packages: – 7 mW/_C from 65_ to 125_C
TSSOP Package: – 6.1 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Max
Unit
4.5
5.5
V
0
5.5
V
0
0
5.5
VCC
V
– 40
+ 85
_C
0
20
ns/V
DC Supply Voltage
Vin
DC Input Voltage
Vout
DC Output Voltage
TA
Operating Temperature
tr, tf
Input Rise and Fall Time
VCC = 0
High or Low State
VCC =5.0V ±0.5V
DC ELECTRICAL CHARACTERISTICS
S b l
Symbol
P
Parameter
T
Test
C
Conditions
di i
VCC
V
TA = 25°C
Min
VIH
Minimum High–Level
Input Voltage
4.5 to
5.5
VIL
Maximum Low–Level
Input Voltage
4.5 to
5.5
VOH
Minimum High–Level
Output Voltage
Vin = VIH or VIL
IOH = – 50µA
4.5
4.4
IOH = – 8mA
4.5
3.94
Maximum Low–Level
Output Voltage
Vin = VIH or VIL
IOL = 50µA
4.5
IOL = 8mA
VOL
Typ
TA = – 40 to 85°C
Max
2.0
Min
Max
2.0
0.8
4.5
U i
Unit
V
0.8
4.4
V
V
3.80
0.0
0.1
0.1
4.5
0.36
0.44
V
Maximum Input
Leakage Current
Vin = 5.5 V or GND
0 to 5.5
± 0.1
± 1.0
µA
Maximum Quiescent
Supply Current
Vin = VCC or GND
5.5
2.0
20.0
µA
ICCT
Quiescent Supply
Current
Per Input: VIN = 3.4V
Other Input: VCC or GND
5.5
1.35
1.50
mA
IOPD
Output Leakage
Current
VOUT = 5.5V
0
0.5
5.0
µA
Iin
ICC
MOTOROLA
2
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
MC74VHCT74A
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AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)
TA = 25°C
S b l
Symbol
P
Parameter
T
Test
C
Conditions
di i
Min
TA = – 40 to 85°C
Typ
Max
Min
Max
U i
Unit
tPLH,
tPHL
Maximum Propagation Delay,
CP to Q or Q
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
5.8
6.3
7.8
8.8
1.0
1.0
9.0
10.0
ns
tPLH,
tPHL
Maximum Propagation Delay,
SD or RD to Q or Q
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
7.6
8.1
10.4
11.4
1.0
1.0
12.0
13.0
ns
fmax
Maximum Clock Frequency
(50% Duty Cycle)
VCC = 5.0 ± 0.5V
CL = 15pF
CL = 50pF
Cin
Maximum Input Capacitance
100
80
160
140
80
65
4
MHz
10
10
pF
Typical @ 25°C, VCC = 5.0V
CPD
P
Power
Dissipation
Di i i Capacitance
C
i
(N
(Note NO TAG)
pF
F
24
1. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.
Average operating current can be obtained by the equation: ICC(OPR) = CPD VCC fin + ICC / 2 (per flip–flop). CPD is used to determine the
no–load dynamic power consumption; PD = CPD VCC2 fin + ICC VCC.
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TIMING REQUIREMENTS (Input tr = tf = 3.0ns)
Guaranteed Limit
VCC
V
TA = – 40 to
85_C
U i
Unit
5.0
ns
tw
tw
Minimum Pulse Width, CP
5.0 ± 0.5
TA = 25_C
5.0
Minimum Pulse Width, RD or SD
5.0 ± 0.5
5.0
5.0
ns
tsu
th
Minimum Setup Time, D to CP
5.0 ± 0.5
5.0
5.0
ns
Minimum Hold Time, D to CP
5.0 ± 0.5
0.0
0.0
ns
trec
Minimum Recovery Time, SD or RD to CP
5.0 ± 0.5
3.5
3.5
ns
S b l
Symbol
P
Parameter
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
3
MOTOROLA
MC74VHCT74A
SWITCHING WAVEFORMS
tw
3V
1.5V
SD or RD
GND
tPHL
3V
CP
1.5V
1.5V VCC
Q or Q
GND
tw
tPLH
1/fmax
tPLH
tPHL
Q or Q
VOH
1.5V
Q or Q
3V
1.5V VCC
GND
trec
3V
VOL
1.5V
CP
GND
Figure 1.
Figure 2.
TEST POINT
OUTPUT
VALID
DEVICE
UNDER
TEST
3V
D
1.5V
GND
tsu
CL*
th
3V
1.5V
CP
GND
* Includes all probe and jig capacitance
Figure 3.
Figure 4.
INPUT
Figure 5. Input Equivalent Circuit
MOTOROLA
4
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
MC74VHCT74A
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
14
8
P 7 PL
–B–
1
0.25 (0.010)
7
G
D
0.25 (0.010)
T
M
F
J
M
K
14 PL
M
R X 45°
C
SEATING
PLANE
B
M
B
S
A
S
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
8.75
8.55
4.00
3.80
1.75
1.35
0.49
0.35
1.25
0.40
1.27 BSC
0.25
0.19
0.25
0.10
7°
0°
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.337 0.344
0.150 0.157
0.054 0.068
0.014 0.019
0.016 0.049
0.050 BSC
0.008 0.009
0.004 0.009
7°
0°
0.228 0.244
0.010 0.019
DT SUFFIX
PLASTIC TSSOP PACKAGE
CASE 948G–01
ISSUE O
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS. MOLD FLASH
OR GATE BURRS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION. INTERLEAD FLASH OR
PROTRUSION SHALL NOT EXCEED
0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE DETERMINED
AT DATUM PLANE –W–.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
–U–
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
–V–
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
K1
J J1
SECTION N–N
–W–
C
0.10 (0.004)
–T– SEATING
PLANE
D
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
G
H
DETAIL E
5
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
–––
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.193
0.200
0.169
0.177
–––
0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.020
0.024
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
MOTOROLA
MC74VHCT74A
OUTLINE DIMENSIONS
M SUFFIX
PLASTIC SOIC EIAJ PACKAGE
CASE 965–01
ISSUE O
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
LE
8
Q1
E HE
L
7
1
M_
DETAIL P
Z
D
VIEW P
A
e
c
A1
b
0.13 (0.005)
M
0.10 (0.004)
DIM
A
A1
b
c
D
E
e
HE
0.50
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
1.42
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.056
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MOTOROLA
◊
6
MC74VHCT74A/D
VHC Data – Advanced CMOS Logic
DL203 — Rev 2
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