SiC462 www.vishay.com Vishay Siliconix 4.5 V to 60 V Input, 6 A Synchronous Buck Regulator FEATURES • • • • • • Single supply operation from 4.5 V to 60 V input voltage Adjustable output voltage down to 0.8 V 6 A continuous output current Adjustable switching frequency from 100 kHz to 2 MHz Adjustable current limit and soft start 98 % peak efficiency DESCRIPTION • Ultra-fast transient response • ± 1 % output voltage accuracy • Normal, ultrasonic or pulse skipping operation The SiC462 is a wide input voltage high efficiency synchronous buck regulator with integrated high-side and low-side power MOSFETs. Its power stage is capable of supplying 6 A continuous current at up to 2 MHz switching frequency. This regulator produces an adjustable output voltage down to 0.8 V from 4.5 V to 60 V input rail to accommodate a variety of applications, including computing, consumer electronics, telecom, and industrial. • • • • • • • SiC462’s architecture delivers ultra-fast transient response with minimum output capacitance and tight ripple regulation at very light load. The device is stable with any capacitor and no external ESR network is required for loop stability. The device also incorporates a power saving scheme that significantly increases light load efficiency. 5 μA shutdown current 250 μA operating current Cycle-by-cycle current limit Output overvoltage protection Output undervoltage / short circuit protection Output voltage tracking and sequencing Scalable family of output current: 3 A (SiC463), 6 A (SiC462), 10 A (SiC461) APPLICATIONS • • • • The regulators integrates a full protection feature set, including over current protection (OCP), output overvoltage protection (OVP), short circuit protection (SCP), output undervoltage protection (UVP) and thermal shutdown (OTP). It also has UVLO for input rail and a user programmable soft start. POLs for telecom Industrial and automation Industrial computing Consumer electronics The SiC462 is available in lead (Pb)-free power enhanced MLP55-27L package. TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS PGOOD ENABLE BOOT PGOOD EN VCIN INPUT VIN 4.5 VDC to 60 VDC Phase VOUT SW SiC462 VDD V SNS SS ULTRASONIC MODE ILIMIT VFB fSW COMP PGND VDRV AGND Fig. 1 - Typical Application Circuit for SiC462 S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 1 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix 6 15 GL GL 1 5 14 SW SW 1 4 13 SW SW 1 3 12 SW SW 1 2 27 MODE 26 VDD 25 ILIM 24 fSW 22 VFB 23 AGND 3 EN 4 BOOT 30 PGND 29 VIN 5 PHASE 6 PGND 11 PGND 10 PGND 9 VIN 8 VIN 7 PHASE 6 VDRV 1 6 2 PGOOD 6 PHASE VIN 7 29 PGND 16 VDRV 28 AGND VIN 8 30 VIN PGND 1 7 PGND 9 BOOT 4 ULTRASONIC 1 8 17 PGND PGND 11 EN 3 PHASE 5 20 VSNS 18 ULTRASONIC 28 AGND PGOOD 2 1 VCIN SS 19 19 SS PGND 10 1 VCIN 1 21 COMP 20 VSNS 22 VFB 21 COMP 23 AGND 24 fSW 26 VDD 25 ILIM 27 MODE PIN CONFIGURATION Fig. 2 - SiC462 Pin Configuration PIN DESCRIPTION PIN NUMBER SYMBOL DESCRIPTION 1 VCIN Supply voltage for internal regulators VDD and VDRV. This pin should be tied to VIN, but can also be connected to a lower supply voltage (> 5 V) to reduce losses in the internal linear regulators 2 PGOOD 3 EN Open-drain power good indicator - high impedance indicates power is good. An external pull-up resistor is required Enable pin 4 BOOT High-side driver bootstrap voltage 5, 6 PHASE Return path of high-side gate driver 7, 8, 29 VIN 9, 10, 11, 17, 30 PGND 12, 13, 14 SW 15 GL Power stage input voltage. Drain of high-side MOSFET Power ground Power stage switch node Low-side MOSFET gate signal 16 VDRV Supply voltage for internal gate driver. When using the internal LDO as a bias power supply, VDRV is the LDO output. Connect a 4.7 μF decoupling capacitor to PGND 18 ULTRASONIC Float to disable ultrasonic mode, connect to VDD to enable. Depending on the operation mode set by the MODE pin, power save mode or forced continuous mode will be enabled when the ultrasonic mode is disabled 19 SS Set the soft start ramp by connecting a capacitor to AGND. An internal current source will charge the capacitor 20 VSNS 21 COMP Output of the internal error amplifier. The feedback loop compensation network is connected from this pin to the VFB pin 22 VFB Feedback input for switching regulator used to program the output voltage - connect to an external resistor divider from VOUT to AGND 23, 28 AGND 24 fSW 25 ILIMIT 26 VDD 27 MODE S17-0360-Rev. D, 13-Mar-17 Power inductor signal feedback pin for system stability compensation Analog ground Set the on-time by connecting a resistor to AGND Set the current limit by connecting a resistor to AGND Bias supply for the IC. VDD is an LDO output, connect a 1 μF decoupling capacitor to AGND Set various operation modes by connecting a resistor to AGND. See specification table for details Document Number: 65124 2 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix ORDERING INFORMATION PART NUMBER PACKAGE MARKING CODE PowerPAK® MLP55-27L SiC462ED-T1-GE3 SiC462EVB SiC462 Reference board PART MARKING INFORMATION = pin 1 indicator P/N P/N = = Siliconix logo LL = ESD symbol F = assembly factory code Y = year code WW = week code LL = lot code FYWW part number code ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) ELECTRICAL PARAMETER EN, VCIN, VIN SW / PHASE VDRV VDD SW / PHASE (AC) BOOT AGND to PGND All other pins Temperature Junction temperature Storage temperature Power Dissipation Thermal resistance from junction to ambient Thermal resistance from junction to case ESD Protection Electrostatic discharge protection CONDITIONS LIMITS UNIT Reference to PGND Reference to PGND Reference to PGND Reference to AGND 100 ns V Reference to AGND -0.3 to +63 -0.3 to +66 -0.3 to +6 -0.3 to +6 -4 to +72 -0.3 to VPHASE + VDRV -0.3 to +0.3 -0.3 to VDD + 0.3 TJ TSTG -40 to +150 -65 to +150 °C 12 2 °C/W 2000 750 V Human body model, JESD22-A114 Charged device model, JESD22-A101 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (all voltages referenced to GND = 0 V) PARAMETER MIN. TYP. MAX. UNIT Input voltage (VIN) Control input voltage (VCIN) (1) Enable (EN) Bias supply (VDD) Drive supply voltage (VDRV) Output voltage (VOUT) Temperature Recommended ambient temperature Operating junction temperature 4.5 4.5 0 4.75 4.75 0.8 5 5.3 - 60 60 60 5.25 5.5 0.8 x VIN V -40 to +105 -40 to +125 °C Note (1) For input voltages below 5 V, provide a separate supply to V CIN of at least 5 V to prevent the internal VDD rail UVLO from triggering. S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 3 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, TJ = -40 °C to +125 °C, unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. VIN = VCIN = 6 V to 60 V, VEN = 5 V, not switching - 5 - VIN = VCIN = 5 V, VEN = 5 V, not switching - 4.96 - UNIT Power Supplies VDD supply VDD dropout VDD VDD_DROPOUT VDD UVLO threshold VDD_UVLO VDD UVLO hysteresis VDD_UVLO_HYST Maximum VDD current IDD VDRV supply VDRV dropout Maximum VDRV current VDRV VIN = VCIN = 5 V, IVDD = 1 mA V - 60 - mV - 4.25 - V - 250 - mV VIN = VCIN = 6 V to 60 V 3 - - mA VIN = VCIN = 6 V to 60 V, VEN = 5 V, not switching - 5.3 - VIN = VCIN = 5 V, VEN = 5 V, not switching - 5 - V VDRV_DROPOUT VIN = VCIN = 5 V, IVDD = 10 mA - 160 - mV IDRV VIN = VCIN = 6 V to 60 V 50 - - mA VDRV UVLO threshold VDRV_UVLO - 4.25 - V VDRV UVLO hysteresis VDRV_UVLO_HYST - 275 - mV Input current Shutdown current IVCIN Non-switching, VFB > 0.8 V - 245 - IVCIN_SHDN VEN = 0 V - 5 10 796 800 804 792 800 808 μA Controller and Timing TJ = 25 °C Feedback voltage VFB VFB input bias current IFB - 2 - nA mS Transconductance COMP source current COMP sink current Minimum on-time tON accuracy On-time range TJ = -40 °C to +125 °C (1) m/V gm - 0.3 - ICOMP_SOURCE - 20 - ICOMP_SINK - 20 - tON_MIN. - 100 - tON_ACCURACY - 10 - % tON_RANGE 100 - 8000 ns Ultrasonic mode enabled 20 - 2000 Ultrasonic mode disabled - - 2000 - 250 - ns - 5 - μA - 1.5 - V - 25 - - 11 - -20 - 20 - 20 - Frequency range fkHz Minimum off-time tOFF_MIN. Soft start current ISS Soft start voltage VSS When VOUT reaches regulation μA ns kHz Power MOSFETs High-side on resistance RON_HS Low-side on resistance RON_LS VGS = 5.3 V m Fault Protections Current limit accuracy ILIM_ACCURACY Output OVP threshold OVP Output UVP threshold Over temperature protection S17-0360-Rev. D, 13-Mar-17 UVP 1 % resistor used for RLIM VFB with respect to 0.8 V reference - -80 - OTPR Rising temperature - 150 - OTPHYST Hysteresis - 35 - % °C Document Number: 65124 4 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix ELECTRICAL SPECIFICATIONS (VIN = VCIN = 48 V, TJ = -40 °C to +125 °C, unless otherwise stated) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. VFB_RISING_VTH_OV VFB rising above 0.8 V reference - 20 - VFB_FALLING_VTH_UV VFB falling below 0.8 V reference - -10 - 55 - UNIT Power Good Power good output threshold % Power good hysteresis PGOOD_HYST - Power good on resistance RON_PGOOD - 8 - Power good delay time tDLY_PGOOD - 25 - μs EN logic high level VEN_H 1.4 - - EN logic low level VEN_L - - 0.4 mV EN / MODE / Ultrasonic Threshold REN - 5 - Ultrasonic mode high Level EN pull down resistance UHIGH 2 - - Ultrasonic mode low level ULOW - - 0.8 Mode pull up current IMODE - 5 - MODE1 Power save mode enabled, VDD, VDRV Pre-reg on 0 - 0.7 MODE2 Power save mode disabled, VDD, VDRV Pre-reg on 1.3 - 1.7 MODE3 Power save mode disabled, VDRV Pre-reg off, VDD Pre-reg on, provide external VDRV 2.3 - 2.7 MODE4 Power save mode enabled, VDRV Pre-reg off, VDD Pre-reg on, provide external VDRV 3.3 - VDD V M V μA V Note (1) Guaranteed by design S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 5 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VCIN VDD VDRV VCIN 5 μA Current source 5 μA Internal LDO Ref Driver LDO 5 μA Sync. rectifier VDD BOOT VDRV EN UVLO fsw VIN On timer MODE Ultrasonic Off timer MODE Ref Bandgap Ref Ref Control logic and driver SW Over temp PHASE 25 kHz 0.8 V SS PGND Comp Error Amp VFB Ramp COMP GL PWM Comp Zero current DET Over voltage VSNS DC Restore VFB Under voltage Current sense SW PGOOD SW AGND ILIMIT Fig. 3 - SiC462 Functional Block Diagram S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 6 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix OPERATIONAL DESCRIPTION Device Overview SiC462 is a high-efficiency synchronous buck regulator capable of delivering up to 6 A continuous current. The device has programmable switching frequency of 100 kHz to 2 MHz. The control scheme is based on voltage mode constant on time. It delivers fast transient response and minimizes external components. It also enables loop stability regardless of the type of output capacitor used, including low-ESR ceramic capacitors. This device also incorporates a power saving feature by enabling diode emulation mode and frequency fold back as the load decreases. • The reference of a basic voltage mode COT regulator is replaced with a high gain error amplifier loop. This loop ensures the DC component of the output voltage follows the internal accurate reference voltage provides excellent regulation • A second voltage feedback path via the VSNS with a ripple injection scheme ensures rapid correction of the transient perturbation • This establishes two parallel voltage regulating feedback paths, a ripple injection path, and a steady accurate dc reference path SiC462 has a full set of protection and monitoring features: • Over current protection in pulse-by-pulse mode 48 V1 Q1 • Output overvoltage protection LOUT • Output undervoltage protection with device latch • Over temperature protection with hysteresis • Dedicated enable pin for easy power sequencing RX Q2 CY 1 nF Erroramp Ripple based controller RCOMP • Power good open drain output + X1 R1 CX R2 COUT Load Ref. CCOMP • This device is available in MLP55-27L package to deliver high power density and minimize PCB area. Fig. 4 - SiC462 Control Block Diagram Power Stage SiC462 integrates a high-performance power stage with a 25 m n-channel high side MOSFET and a 11 m n-channel low side MOSFET. The MOSFETs are optimized to achieve up to 98 % efficiency. The power input voltage (VIN) can go up to 60 V and down as low as 4.5 V for power conversion. Control Scheme SiC462 employs a voltage - mode COT control mechanism in conjunction with adaptive zero current detection which allows precise power saving feature. The switching frequency, fSW, is set by an external resistor to AGND, Rfsw. V OUT R fsw = -------------------------------------------– 12 f sw 190 10 Note, that there is no VIN dependency on fSW as the on time adjusts as VIN is varied. During steady-state operation, VCOMP is generated from the feedback voltage and internal 0.8 V reference inputs to the error amplifier. An internally generated ramp signal and VCOMP are fed into a comparator. Once VRAMP crosses VCOMP, a single shot ON-time pulse is generated for a fixed time, programmed by the external RFSW. During the On-time pulse, the high side MOSFET will be turned ON. Once the ON-time pulse expires, the high side MOSFET is turned off and the low side MOSFET will be turned ON after a break-before-make period. The low side MOSFET will be on for duration of minimum OFF-time pulse until VRAMP crosses VCOMP. The cycle is then repeated. Fig. 4 illustrates the basic block diagram for voltage mode constant on time architecture with external ripple injection. S17-0360-Rev. D, 13-Mar-17 For stability purposes the SiC462 requires 200 mV of ripple injection. CX, CY, and RX are selected to achieve the desired ripple injection. Typically Cy is chosen to be 2 nF to meet the internal impedance of the VSNS pin. CX is chosen to be 10 times greater than CY, CX = 10 x CY. R X = V IN - V OUT x V OUT / V IN f SW x C X x V RIPPLE Fig. 5 demonstrates the basic operational waveforms: VRAMP VCOMP PWM Fixed on-time Fig. 5 - SiC462 Operational Principle Typically, the frequency of RCOMP and CCOMP is chosen to be around the resonance frequency of LOUT and COUT. In this case, set R COMP x C COMP = L OUT x C OUT For good slew rate / transient load response, pick CCOMP 1 nF, RCOMP can be calculated according the formula above. Document Number: 65124 7 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix Power-Save Mode, MODE Pin, and Ultrasonic Pin Operation To improve efficiency at light-loads, SiC462 provides a set of innovative implementations to eliminate LS re-circulating current and switching losses. The internal zero crossing detector (ZCD) monitors SW node voltage to determine when inductor current starts to flow negatively. In power saving mode, as soon as inductor valley current crosses zero, the device first deploys diode emulation mode by turning off the LS FET. If load further decreases, switching frequency is reduced proportional to the load condition to save switching losses while keeping output ripple within tolerance. If the ultrasonic pin is tied to VDD, the minimum switching frequency in the discontinuous mode is 25 kHz to avoid switching frequencies in the audible range. If this feature is not required this ultrasonic mode can be disabled by floating the ultrasonic pin. When the ultrasonic mode is disabled, the regulator will either operate in forced continuous mode or in a power save mode where there is no limit to the lower frequency limit. In this state, at zero load switching frequency can go as low as hundreds of Hz. To improve the converter efficiency, the user can choose to disable the internal VDRV regulator by picking either Mode 3 or Mode 4 and connecting a 5 V supply to the VDRV pin. This reduces power dissipation in the SiC462 by eliminating the VDRV linear regulator losses. The MODE pin supports several modes of operation as shown in table 1. An internal current source is used to set the voltage on this pin using an external resistor: TABLE 1 - OPERATION MODES MODE RANGE (V) POWER SAVE MODE INTERNAL VDRV REGULATOR OCP is enabled immediately after VCC passes UVLO level. OCP is set by an external resistor to AGND, RLIM. R LIM = 480k / I OUT max. OCPthreshold Iload Iinductor GH Fig. 6 - Over-Current Protection Illustration Output Undervoltage Protection (UVP) UVP is implemented by monitoring output through VFB pin. If the voltage level at VFB goes below 0.16 V (VOUT is 20 % of VOUT set point) for more than 25 μs a UVP event is recognized and both HS and LS MOSFETs are turned off. After a time-out period equal to 20 soft start cycles, the IC attempts to re-start by going through a soft start cycle. If the fault condition still exists, the above cycle will be repeated. UVP is only active after the completion of soft-start sequence. Output Over-Voltage Protection (OVP) For OVP implementation, output is monitored through FB pin. After soft start, if the voltage level at FB is above 0.96 V (typ.) (VOUT is 120 % of VOUT set point), OVP is triggered with both the HS and LS MOSFETs turned off. Normal operation is resumed once FB voltage drops back to 0.96 V. 1 0 to 0.7 Enabled ON 2 1.3 to 1.7 Disabled ON 3 2.3 to 2.7 Disabled OFF (1) OVP is active immediately after VCC passes UVLO level. 4 3.3 to VDD Enabled OFF (1) Over-Temperature Protection (OTP) Note (1) Connect a 5 V (± 5 %) supply to the V DRV pin The mode pin is not latched to any state and can be changed on the fly. OUTPUT MONITORING FEATURES AND PROTECTION Output Over-Current Protection (OCP) SiC462 has cycle by cycle current limiting. The inductor valley current is monitored during LS FET turn-on period through RDS(on) sensing. After a pre-defined blanking time, the valley current is compared with an internal threshold. If monitored current is higher than threshold, HS turn-on pulse is skipped and LS FET is kept on until the valley current returns below OCP limit. In a short circuit or a severe over-current condition, output undervoltage protection (UVP) will result in both the HS and LS FET turning off. See output undervoltage protection (UVP) section for more details. S17-0360-Rev. D, 13-Mar-17 SiC462 has internal thermal monitor block that turns off both HS and LS FETs when junction temperature is above 150 °C (typ). A hysteresis of 35 °C is implemented, so when junction temperature drops below 115 °C, the device restarts by initiating soft-start sequence again. Sequencing of Input / Output Supplies SiC462 has no sequencing requirements on any of its input / output (VIN, VDRV, VDD, VCIN, EN) supplies or enables. Enable The SiC462 has an enable pin to turn the part on and off. Driving this pin high enables the device, while grounding it turns it off. The SiC462 enable has a weak pull down to prevent unwanted turn on due to a floating GPIO. There are no sequencing input / output supplies. requirements w.r.t other Document Number: 65124 8 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix Soft-Start SiC462 soft-start time is adjustable by selecting a capacitor value from the following equation. Once VCC is above UVLO level (2.55 V typ.), VOUT will ramp up slowly, rising monotonically to the programmed output voltage. There is an internal 5 μA current source tied to the soft start pin which charges the external soft start cap. C ext x 0.8 V SS time = -------------------------------5 μA VFB_Rising_Vth_OV (typ. = 0.96 V) VFB_Falling_Vth_OV (typ. = 0.91 V) Vref (0.8 V) VFB_Falling_Vth_UV VFB_Rising_Vth_UV (typ. = 0.72 V) (typ. = 0.77 V) VFB Pull-high PG During soft-start period, OCP is activated. Short-circuit protection is not active until soft-start is complete. Pull-low Pre-Bias Start-Up In case of pre-bias startup, output is monitored through FB pin. If the sensed voltage on FB is higher than the internal reference ramp value, control logic prevents HS and LS FET from switching to avoid negative output voltage spike and excessive current sinking through LS FET. Fig. 8 - PGOOD Window and Timing Diagram Power Good SiC462’s power good is an open-drain output. Pull PGOOD pin high up to 5 V through a 10K resistor to use this signal. Power good window is shown in the diagram above. If voltage level on FB pin is out of this window, PG signal is de-asserted by pulling down to GND. To prevent false triggering during transient events, PGOOD has a 25 μs blanking time. Fig. 7 - Pre-Bias Start-Up S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 9 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 J5 CON4 1 2 3 4 VO VIN VO_GND J7 J8 J10 J11 TP1 C6 C7 C8 C9 Open R12 2.2uF 2.2uF 2.2uF 0.1uF PGD Vdrv EN R6 0 PGND1 PGND2 PGND3 VIN1 VIN2 IC1 7 8 9 10 11 GL 4k R14 R16 C16 DNP C1 100n SiC462 C14 L1 22nF 2.2n C15 C13 4.7u 15uH Mode C2 0.1uF 1u C3 679 R10 40k R11 DNP R7 R8 DNP 82k VDD1 27 26 Ilim COMP R15 100 1 1 TP4 R13 9.50kTP3 25 24 23 22 21 20 C12 4.7nF MODE VDD ILIM FSW AGND VFB COMP VSNS Ultra J9 JUMPER VDD1 22uF 22uF 22uF R9 126k C10 1n 22uF C11 VO 22uF 22uF J1 750K R4 J2 C25 1 J4 JUMPER POSCAP J3 JUMPER JUMPER JUMPER TP5 Vout C24 22uF 1 2 R3 2 500K 1 300K R2 2 R1 10k 2 1 R5 100k Vin 1 VCIN PGD PGOOD EN Ultrasonic Vin 56u C4 C5 56u TP2 GND PGD 1 1 VDRV 1 EN GND 1 DNP VDRV 2 EN 28 PGND GND-PAD 17 4 BOOT 16 SS C17 C18 C19 C20 C21 C22 C23 0.1u 1 TP6 GND Document Number: 65124 10 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 S17-0360-Rev. D, 13-Mar-17 14 GL 15 5 Phase1 6 Phase2 13 SW1 SW2 SW3 12 1 1 3 18 2 1 19 VO_GND 1 Vishay Siliconix www.vishay.com REFERENCE BOARD SCHEMATIC SiC462 www.vishay.com Vishay Siliconix BILL OF MATERIAL QTY REFERENCE DESIGNATOR DESCRIPTION PART NUMBER MANUFACTURER 1 C1 Capacitor ceramic 0.1 μF 100 V X5R 0402 GRM155R62A104ME14D Murata Electronics 1 C3 Capacitor ceramic 1 μF 35 V X5R 0402 C1005X5R1V105M050BC TDK Corporation 1 C10 DNP - - 1 C11 Capacitor ceramic 1000 pF 100 V X7R 0402 GRM155R72A102KA01D Murata Electronics 1 C12 Capacitor ceramic 10000 pF 100 V X7S 0402 C1005X7S2A103K050BB TDK Corporation 2 C2, C9 Capacitor ceramic 0.1 μF 100 V X7R 0603 GRM188R72A104KA35D Murata Electronics 1 C15 Capacitor ceramic 0.022 μF 100 V X7R 0603 C0603C223K1RACTU Kemet 1 C14 Capacitor ceramic 2200 pF 100 V X7R 0603 C0603C222K1RACTU Kemet 1 C16 DNP - - 1 C17 Capacitor ceramic 0.1 μF 35 V X5R 0603 GMK107BJ104KAHT Taiyo Yuden 1 C13 Capacitor ceramic 4.7 μF 35 V X5R 0805 GRM219R6YA475KA73D Murata Electronics 3 C6, C7, C8 Capacitor ceramic 2.2 μF 100 V X7R 1210 HMK325B7225KN-T Taiyo Yuden 7 C18, C19, C20, C21, C22, C23, C24 Capacitor ceramic 22 μF 25 V X5R 1210 GRM32ER61E226KE15L Murata Electronics 1 J5 Terminal block 5.08 mm VERT 4POS ED120/4DS On Shore Technology Inc. 2 C4, C5 (1) Capacitor aluminum 56 μF 20 % 100 V radial UHE2A560MPD Nichicon 1 L1 Inductor 10 μH IHLP4040DZER100M11 Vishay 5 J1, J2, J3, J4, J9 B/S II HDR. SR 68000-402 Amphenol FCI 1 C25 DNP - - 1 R1 Resistor 10K 1 % 1/16 W 0402 RC0402FR-0710KL Yageo 1 R2 Resistor 300K 1 % 1/16 W 0402 RC0402FR-07300KL Yageo 1 R3 Resistor 499K 1 % 1/16 W 0402 RC0402FR-07499KL Yageo 1 R4 Resistor 750K 1 % 1/16 W 0402 RC0402FR-07750KL Yageo 2 R5, R7 Resistor 100K 1 % 1/16 W 0402 RC0402FR-07100KL Yageo 1 R6 Resistor 0.0 Jumper 1/16 W 0402 RC0402JR-070RL Yageo 1 R8 Resistor 48.7K 1 % 1/16 W 0402 RC0402FR-0748K7L Yageo 1 R9 Resistor 210K 1 % 1/16 W 0402 RC0402FR-07210KL Yageo 1 R10 Resistor 56K 5 % 1/16 W 0402 RC0402JR-0756KL Yageo 1 R11 Resistor 10K 5 % 1/10 W 0603 RC0603FR-0710KL Yageo 1 R12 - - - 1 R14 Resistor 6.8K 5 % 1/10 W 0603 RC0603JR-076K8L Yageo 1 R13 Resistor 140K 1 % 1/10 W 0603 RC0603FR-07140KL Yageo 1 R15 Resistor 100 1 % 1/10 W 0603 RC0603FR-07100RL Yageo 1 R16 DNP - - 1 IC1 IC SiC462 SiC462 Vishay 10 J7, J8, J10, J11, TP, TP2, TP3, TP4, TP5, TP6 BERGSTIK II 0.100" SNGL ST 68002-401HLF Amphenol FCI Note (1) These two large Aluminium Electrolytic caps are included in case the customers evaluation set up has long leads. They are not needed for SiC462 operation. S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 11 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix EXTERNAL COMPONENT SELECTION FOR THE SiC462 A reference design has been developed to illustrate how to choose component values for proper operation of the SiC462. The schematic for the demo board is shown in Fig. 9 and Table 2. Demo Board Connection and Signal / Test Points Power Sockets VIN, GND (P1): input voltage source with VIN to be positive. Connect to a voltage source: VOUT, GND (P3): output voltage with VOUT to be positive. Connect to a load that draws no more than: 5 V, GND (P10): external 5 V MOSFET gate voltage source with 5 V to be the positive input. Apply 5 V when Mode 3 or Mode 4 is selected. Selection Jumpers Mode Select P7: this is an 8 way header which allows the user to select one of four modes of operation. MODE1 - SHORT PIN 1 to 2 Power save, VDRV and Pre-reg on MODE2 - SHORT PIN 3 to 4 Forced PWM, VDRV and Pre-reg on MODE3 - SHORT PIN 5 to 6 Forced PWM, VDRV and Pre-reg off - external 5 V supply MODE4 - SHORT PIN 7 to 8 Power save, VDRV and Pre-reg off - external 5 V supply VDRV External Supply P10: this is a 2 way header that will enable the user to supply an external MOSFET gate driver supply if an external 5 V supply is available. This should only be used in MODES 3 and 4. ENABLE P9: this is a 2 way header that will enable the part if left open. When shorted the part is disabled. Output Voltage Sense VOUT_SENSE, GNDOUT_SENSE (P4): this allows the user to measure the voltage at the output of the regulator and remove any losses generated due to the connections, from the measurement. This can also be used by an active load with sense capability. POWER GOOD INDICATOR PGOOD (P11): is an open drain output and is pulled up with a 10 k resistor to VIN. When FB or VOUT are within -10 % to +20 % of the set voltage this pin will go HI to indicate the output is okay. POWER UP PROCEDURE To turn-on the reference board, apply 12 V to VIN with the P7 jumper is in position 1. If the P7 jumper is in place 1 the board will come up in power save mode, if in place 2 then constant PWM will be observed. When applying higher than 12 V to the input it is reasonable to install a RC snubber from SW to GND if needed however this will affect efficiency. There are place holders on the reference board, R11 and C12 for the snubber. Values of 4 and 1 nF are a reasonable starting point. ADJUSTMENTS TO THE REFERENCE BOARD OUTPUT VOLTAGE ADJUSTMENT If a different output voltage is needed, simply change the value of VOUT and solve for R12 based on the following formula: R 13 V OUT - VFB R 12 = --------------------------------------------V FB OPEN Pin 1-2 - automatic enable on power up SHORT Pin 1-2 - IC disabled. Where VFB is 0.8 V for the SiC46X. RBOTTOM (R13) should be a maximum of 10 k to prevent VOUT from drifting at no load. Ultrasonic CHANGING SWITCHING FREQUENCY P8: this is a 2 way header that will enable the user to select the ultrasonic mode of operation. In ultrasonic mode the minimum frequency of operation is 20 kHz, above the audible range. When not in ultrasonic mode the frequency can drop below 20 kHz. The following equation illustrates the relationship between on-time, VIN, VOUT, and Rfsw value: OPEN Pin 1-2 - ultrasonic disabled SHORT Pin 1-2 - ultrasonic enabled SIGNALS AND TEST LEADS Input Voltage Sense VIN_SENSE, GNDIN_SENSE (P2): this allows the user to measure the voltage at the input of the regulator and remove any losses generated due to the, connections from the measurement. This can also be used by a power source with sense capability. S17-0360-Rev. D, 13-Mar-17 V OUT R fsw = R 7 = -------------------------------------------– 12 f sw 190 10 OUTPUT RIPPLE VOLTAGE There is no requirement for this converter to see output capacitor ripple voltage in the control loop as a voltage injection circuit is employed; the voltage injection ramp is used to alert the converter to the next switch event. Output ripple voltage is measured with a tip and barrel measurement across COUT; the barrel of the probe is the GND / 0 V connection and this removes the effect of the long GND / 0 V leads of the probe. Typically output ripple voltage Document Number: 65124 12 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix is set to 3 % to 5 % of the output voltage, but an all ceramic output solution can bring output ripple voltage to a much lower level since the ESR of ceramics can be in the range of m’s. VOLTAGE INJECTION NETWORK This is the network seen placed across the output inductor in the schematic consisting of R10, C10 and C11. A quick method to add or remove injection is to reduce or increase R10. The time constant of the voltage injection network is as follows: INJECTION = R X x C X In order to set a correct magnitude, the SiC46x requires around 200 mV, the following equation is used: V OUT R X = V IN - VOUT x ---------------------------------------------------------------------------- V IN x f sw x C X x V INJECTION Where VINJECTION = 200 mV is the midpoint of the ripple injection RC circuit. L Compensation The COT loop uses a transconductance amplifier to convert a proportional current from the output voltage, VFB. This has the effect of offering a high impedance at the VFB node, however this circuitry is left with a wide bandwidth to accommodate the different switching frequencies. This will require rolling off with an RC circuit, use the following equation: L x C OUT R COMP = ----------------------------C COMP CCOMP will be set to 1 nF. This provides a frequency breakpoint around the LC filter peak. It may be necessary to reduce the roll off further, this can be a choice of the designer but an example might be to start at 1/2 the LC filter peak frequency. This will affect the transient response time, something to note is the minimal phase delay in the COT topology and its fast response compared to PWM converters. INDUCTOR SELECTION The choice of inductor is specific to each application and quickly determined with the following equations: VOUT RX VINJ CY CX a and b Fig. 9 - Voltage Injection Circuit In fig. 9 the recommended value of CX = C10 (a or b) 22 nF and CY = C11 2.2 nF. The reference design allows placement of CX in two positions as shown in fig. 9, “a” and “b”. The “b” option removes the output ripple and transient response voltage from the injection signal. The effect of connecting the CX capacitor to GND / 0 V is the same as removing the output information from the fast loop. The output will be very stable in this setup when large transient loads are experienced at the output; in any case you will notice that the effective impedance of the output node is very small and the FB loop will react quickly enough for all loads. Another key aspect of using the GND / 0 V connection for the injection circuit is the ability to use a smaller output capacitance. Be aware that the b) option is should only be used with forced PWM operation. V INJECTION = V IN_min. 1 - V OUT x 1 - ---------- t --------- INJ e Where t is the ON period. The required magnitude is ~ 100 mVpp for stable operation. S17-0360-Rev. D, 13-Mar-17 V OUT t ON = ------------------------------------V IN_max. x f sw V IN - VOUT x t ON L = -------------------------------------------------I OUT_MAX. x K Where K is a percentage of maximum output current ripple required. The designer can quickly make a choice of inductor if the ripple percentage is decided, usually no more than 30 % however higher or lower percentages of IOUT can be acceptable depending on application. This device allows choices larger than 30 %. Other than the inductance the DCR and saturation current parameters are key values. The DCR causes an I2R loss which will decrease the system efficiency and generate heat. The saturation current has to be higher than the maximum output current plus ½ of the ripple current. In an over current condition the inductor current may be very high. All this needs to be considered when selecting the inductor. On this board Vishay IHLP series inductors are used to meet cost requirement and high efficiency, a part that utilizes a material that has incredible saturation behaviour compared to competing products. Document Number: 65124 13 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix OUTPUT CAPACITOR SELECTION CURRENT LIMIT RESISTOR Voltage rating, ESR, transient response, overall PCB area and cost are requirements for selecting output capacitors. The types of capacitors and there general advantages and disadvantages are covered next. The current limit is set by placing a resistor between ILIM and AGND. The values can be found using the following equation: Electrolytic have high ESR, dry out over time so ripple current rating must be examined and have slower transient response, but are fairly inexpensive for the amount of overall capacitance. Tantalums can come in low ESR varieties and high capacitance value for its overall size, but they fail short when damaged and also have slower transient response. Ceramics have very low ESR, fast transient response and overall small size, but come in low capacitance values compared to the others types. A combination of technology is sensible, however these converters suit an ceramic solution also. The output capacitance will be determined by the ripple voltage requirement. Voltage mode COT topology can work with very small values of capacitor ESR. 480 000 R LIM = ------------------------I OUT_max. INPUT CAPACITANCE In order to keep the design compact and minimize parasitic elements, ceramic capacitors will be chosen. The initial requirement for the input capacitance is decided by the maximum input voltage, 60 V in this case however a 100 V rated capacitor will be chosen of the X7R variety. The footprint will be a compact 1206. In order to determine the minimum capacitance the input voltage ripple needs to be specified; VCINPP 500 mV is a suitable starting point. This magnitude is determined by the final application specification. The input current needs to be determined for the lowest operating input voltage, I CIN RMS = The following equations are used to calculate the size needed to meet a transient load response: IO x I LPK = I max. + 0.5 x I RIPPLE_max. 2 V OUT 2 1 D x 1 – D + ------ ------------------------------------- 1 – D D L ƒ sw I OUT 12 The minimum input capacitance can then be found, and 2 C OUT_min. = I LPK 2 I LPK I max x dt L x -------------- - --------------------------dl LOAD V OUT x ---------------------------------------------------------2 x V PK - VOUT Where ILPK is the peak inductor current, IMAX. is the maximum output current, dILOAD is the current step in μs and VPK is the peak voltage, the output voltage summed with the specified over and under shoot. The evaluation PCB is fitter with 66 μF. ENABLE PIN VOLTAGE The EN pin has an internal pull down resistor and only requires an enable voltage. This needs to be greater than 1.4 V. An input voltage or a resistor connected across VIN and EN can be used. The internal pull down resistance is 5 M. D - 1 - D C IN_min. = I OUT x ----------------------------------------V CINPKPK x f sw For output voltage greater than 5 V the input capacitance should be increased accordingly. As the output power increases so does the input voltage ripple, the evaluation PCB has 4.4 μF. Note • If the input voltage becomes very small then extra capacitance needs adding to the input as the ripple will affect the duty cycle calculation when larger current is required. SOFT START SETTING Soft start is a useful function helping to limit the current magnitude from the source at switch on. This is simply set with a ceramic capacitor using the following equation: C SS x 0.8 t SS = ------------------------–6 5 x 10 A 100 nF capacitor will provide ~ 16 ms soft start time. VDD pin will need to be decoupled in order to provide a stable voltage internally and externally. The value for this capacitor is recommended as 1 μF. S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 14 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz unless noted otherwise) 100 100 VIN = 24 V, L = 10 μH VIN = 24 V, L = 10 μH 95 VIN = 36 V, L = 15 μH 90 Efficiency (%) Efficiency (%) 95 VIN = 48 V, L = 15 μH 85 90 VIN = 36 V, L = 15 μH 85 VIN = 48 V, L = 15 μH 80 80 Complete converter efficiency PIN = [(VIN x IIN) + (VCIN x ICIN)] POUT = VOUT x IOUT, measured at output capacitor Complete converter efficiency PIN = [(VIN x IIN) + (VCIN x ICIN)] POUT = VOUT x IOUT, measured at output capacitor 75 75 0 0.6 1.2 1.8 2.4 3 3.6 4.2 Output Current, IOUT (A) 4.8 5.4 0.01 6 0.1 Output Current, IOUT (A) 1 Fig. 13 - Efficiency vs. Output Current (VOUT = 12 V, fsw = 500 kHz) Fig. 10 - Efficiency vs. Output Current (VOUT = 12 V, fsw = 500 kHz) 100 100 VIN = 12 V, L = 8.2 μH VIN = 12 V, L = 8.2 μH 95 95 90 90 Efficiency (%) Efficiency (%) VIN = 24 V, L = 10 μH VIN = 36 V, L = 15 μH VIN = 48 V, L = 8.2 μH 85 85 VIN = 24 V, L = 10 μH 80 75 VIN = 48 V, L = 8.2 μH 70 80 Complete converter efficiency PIN = [(VIN x IIN) + 5 (VCIN V xx (IICIN )] + IVCIN)] VDRV POUT = VOUT x IOUT, measured at output capacitor Complete converter efficiency PIN = [(VIN x IIN) + (VCIN x ICIN)] POUT = VOUT x IOUT, measured at output capacitor 65 60 75 0 0.6 1.2 1.8 2.4 3 3.6 4.2 Output Current, IOUT (A) 4.8 5.4 6 0.01 Fig. 11 - Efficiency vs. Output Current (VOUT = 5 V, fsw = 300 kHz) 48 300 42 280 36 High side 30 24 18 12 Low side 1 260 240 220 200 180 160 6 0 -60 -40 -20 0.1 Output Current, IOUT (A) Fig. 14 - Efficiency vs. Output Current (VOUT = 5 V, fsw = 300 kHz) Input Current, IVCIN + IVIN (μA) On-State Resistance, RDSON (mΩ) VIN = 36 V, L = 15 μH 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 12 - On Resistance vs. Junction Temperature S17-0360-Rev. D, 13-Mar-17 140 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 15 - Input Current vs. Junction Temperature Document Number: 65124 15 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz unless noted otherwise) 8.0 Shutdown Current, IVCIN_SHDN + IVIN_SHDN (μA) Shutdown Current, IVCIN_SHDN + IVIN_SHDN (μA) 8.0 7.0 6.0 5.0 4.0 3.0 2.0 1.0 0.0 0 6 12 18 24 30 36 42 Input Voltage, VCIN / VIN (V) 48 54 6.0 5.0 4.0 3.0 2.0 1.0 0.0 -60 -40 -20 60 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 19 - Shutdown Current vs. Junction Temperature Fig. 16 - Shutdown Current vs. Input Voltage 1.0 1.0 0.8 0.8 0.6 0.6 0.4 0.4 Line Regulation (%) Load Regulation (%) 7.0 0.2 0.0 -0.2 -0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.6 -0.8 -0.8 -1.0 -1.0 0 0.6 1.2 1.8 2.4 3 3.6 4.2 Output Current (A) 4.8 5.4 20 6 25 30 35 40 45 Input Voltage (V) 50 55 60 Fig. 20 - Line Regulation, VOUT = 12 V Fig. 17 - Load Regulation, VOUT = 12 V 1.2 1.4 1.1 1.3 1.0 1.2 EN Current, IEN (μA) EN Logic Threshold, VEN (V) VEN = 5 V 0.9 VIH_EN 0.8 0.7 VIL_EN 1.1 1.0 0.9 0.6 0.8 0.5 0.7 0.6 0.4 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 18 - EN Logic Threshold vs. Junction Temperature S17-0360-Rev. D, 13-Mar-17 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 21 - EN Current vs. Junction Temperature Document Number: 65124 16 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz unless noted otherwise) 808 Voltage Reference, VFB (mV) 806 804 802 800 798 796 794 792 -60 -40 -20 0 20 40 60 80 Temperature (°C) 100 120 140 Fig. 22 - Voltage Reference vs. Junction Temperature Fig. 25 - Load Transient (3 A to 6 A), (6 A to 3 A), Time = 100 μs/div Fig. 23 - Start-Up with EN, Time = 1 ms/div Fig. 26 - Line Transient (8 V to 48 V), Time = 10 ms/div Fig. 24 - Start-Up with VIN, Time = 5 ms/div Fig. 27 - Output Ripple 2 A, Time = 5 μs/div S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 17 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix ELECTRICAL CHARACTERISTICS (VIN = 48 V, VOUT = 5 V, fsw = 300 kHz unless noted otherwise) Fig. 28 - Output Ripple 300 mA, Time = 5 μs/div S17-0360-Rev. D, 13-Mar-17 Fig. 29 - Output Ripple PSM, Time = 10 ms/div Document Number: 65124 18 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix PCB LAYOUT RECOMMENDATIONS Step 3: VSWH Plane Step 1: VIN/GND Planes and Decoupling Snubber VIN Plane PGND Plane VIN VSWH PGND Plane VSWH Fig. 32 Fig. 30 1. Layout VIN and PGND planes as shown above. 2. Ceramic capacitors should be placed between VIN and PGND, and very close to the device for best decoupling effect. 1. Connect output inductor to SiC462 with large plane to lower the resistance. 2. If any snubber network is required, place the components on the bottom side as shown above. Step 4: VDD/VDRV Input Filter 3. Different values / packages of ceramic capacitors should be used to cover entire decoupling spectrum e.g. 1210 and 0603. CVDD 4. Smaller capacitance values, placed closer to device’s VIN pin(s), is better for high frequency noise absorbing. Step 2: VCIN Pin AGND P G N D Vcin decouple cap Cvdrv AGND Plane Fig. 31 Fig. 33 1. VCIN (pin 1) is the input pin for both internal LDO and tON block. TON time varies based on input voltage. It’s necessary to put a decoupling capacitor close to this pin. 1. CVDD cap should be placed between pin 26 and pin 23 (the AGND of driver IC) to achieve best noise filtering. 2. The connection can be made through a via and the cap can be placed at bottom layer. S17-0360-Rev. D, 13-Mar-17 2. CVDRV cap should be placed close to VDRV (pin 16) and PGND (pin 17) to reduce effects of trace impedance and provide maximum instantaneous driver current for low side MOSFET during switching cycle. Document Number: 65124 19 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Step 5: BOOT Resistor and Capacitor Placement Rboot Vishay Siliconix Step 6: Signal Routing Cboot AGND plane PGND F B Fig. 34 s i g n Ripple injection a l circuit 1. These components need to be placed very close to SiC462, right between PHASE (pin 5, 6) and BOOT (pin 4). 2. In order to reduce parasitic inductance, it is recommended to use 0402 chip size for the resistor and the capacitor. Fig. 35 1. Separate the small analog signal from high current path. As shown above, the high current paths with high dv/dt, di/dt are placed on the left side of the IC, while the small control signals are placed on the right side of the IC. All the components for small analog signal should be placed closer to IC with minimum trace length. 2. Pin 23 is the IC analog ground, which should have a single connection to power ground. The AGND ground plane connected with pin 23 helps keep AGND quiet and improve noise immunity. 3. Feedback signal can be routed through inner layer. Make sure this signal is far away from VSWH node and shielded by inner ground layer. 4. Ripple injection circuit can be placed next to inductor. Kelvin connection as shown above is recommended. S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 20 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Step 7: Adding Thermal Relief Vias and Duplicate Power Path Plane Vishay Siliconix Step 8: Ground Layer VIN Plane AGND Plane PGND Plane PGND Plane VSWH Fig. 36 1. Thermal relief vias can be added on the VIN and PGND pads to utilize inner layers for high-current and thermal dissipation. 2. To achieve better thermal performance, additional vias can be put on VIN and PGND plane. Also, it is necessary to duplicate the VIN and ground planes at bottom layer to maximize the power dissipation capability from PCB. 1. It is recommended to make the entire inner layer (next to top layer) ground plane. 3. VSWH pad is a noise source and not recommended to put vias on this pad. 2. This ground plane provides shielding between noise source on top layer and signal trace within inner layer. 4. 8 mil drill for pads and 10 mils drill for plane are optional via sizes. The vias on pads may drain solder during assembly and cause assembly issues. Please consult with the assembly house for guidelines. 3. The ground plane can be broken into two sections as PGND and AGND. S17-0360-Rev. D, 13-Mar-17 Fig. 37 Document Number: 65124 21 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiC462 www.vishay.com Vishay Siliconix PACKAGE OUTLINE DRAWING PowerPAK® MLP55-27 2x A 0.08 C 27 e1 K x3 E2-1 K1 D2-3 12 1.000 e E2-2 E2-4 E2-3 K2 D2-2 7 6 F2 Side view Top view K3 11 7 11 B C 1 D2-4 ex2 12 D2-1 e x4 4 b E MLP55-27L (5 mm x 5 mm) 6 19 0.10 19 1 20 C A B 20 27 e x7 A1 A2 e1 0.10 C A D A F1 ex2 1.225 e1 Bottom view DIM. MILLIMETERS INCHES MIN. NOM. MAX. MIN. NOM. A (8) 0.70 0.75 0.80 0.027 0.029 0.031 A1 0.00 - 0.05 0.000 - 0.002 0.30 0.078 A2 b (4) 0.20 ref. 0.20 D 0.25 0.008 ref. 5.00 BSC 0.098 e 0.50 BSC 0.019 BSC 0.65 BSC 0.0256 BSC E 5.00 BSC 0.196 BSC L 0.35 0.40 0.011 0.196 BSC e1 N (3) MAX. 0.45 0.014 28 0.016 0.018 28 D2-1 3.25 3.30 3.35 0.128 0.130 0.132 D2-2 0.95 1.00 1.05 0.037 0.039 0.041 D2-3 1.95 2.00 2.05 0.077 0.079 0.081 D2-4 1.37 1.42 1.47 0.054 0.056 0.058 E2-1 0.95 1.00 1.05 0.037 0.039 0.041 E2-2 2.55 2.60 2.65 0.100 0.102 0.104 E2-3 2.55 2.60 2.65 0.100 0.102 0.104 E2-4 1.58 1.63 1.68 0.062 0.064 0.066 F1 0.20 - 0.25 0.008 - 0.010 F2 0.20 min. 0.008 min. K 0.40 BSC 0.016 BSC K1 0.70 BSC 0.028 BSC K2 0.70 BSC 0.028 BSC K3 0.30 BSC 0.012 BSC Notes 1. Use millimeters as primary measurement 2. Dimensioning and tolerances conform to ASME Y14.5M - 1994 3. N is the number of terminals, Nd is the number of terminals in x-direction, and Ne is the number of terminals in y-direction 4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip 5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body 6. Exact shape and size of this feature is optional 7. Package warpage max. 0.08 mm 8. Applied only for terminals Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package / tape drawings, part marking, and reliability data, see www.vishay.com/ppg?65124. S17-0360-Rev. D, 13-Mar-17 Document Number: 65124 22 For technical questions, contact: [email protected] THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Revision: 13-Jun-16 1 Document Number: 91000