TI ADS5463 12-bit, 500-msps analog-to-digital converter Datasheet

AD
S5
46
3
ADS5463
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12-Bit, 500-MSPS Analog-to-Digital Converter
•
FEATURES
1
•
•
•
•
•
•
•
•
•
•
23
•
500-MSPS Sample Rate
12-Bit Resolution, 10.4 Bits ENOB
2.3-GHz Input Bandwidth
SFDR = 75 dBc at 450 MHz and 500 MSPS
SNR = 64.6 dBFS at 450 MHz and 500 MSPS
2.2-VPP Differential Input Voltage
LVDS-Compatible Outputs
Total Power Dissipation: 2.2 W
Offset Binary Output Format
Output Data Transitions on the Rising and
Falling Edges of a Half-Rate Output Clock
On-Chip Analog Buffer, Track and Hold, and
Reference Circuit
•
•
80-Pin TQFP PowerPAD™ Package
(14-mm × 14-mm)
Industrial Temperature Range = –40°C to 85°C
Pin-Similar/Compatible to 12-, 13-, and 14-Bit
Family: ADS5440/ADS5444/ADS5474
APPLICATIONS
•
•
•
•
•
•
Test and Measurement Instrumentation
Software-Defined Radio
Data Acquisition
Power Amplifier Linearization
Communication Instrumentation
Radar
DESCRIPTION
The ADS5463 is a 12-bit, 500-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and
3.3-V supply, while providing LVDS-compatible digital outputs. This ADC is one of a family of 12-, 13-, and 14-bit
ADCs that operate from 210 MSPS to 500 MSPS. The ADS5463 input buffer isolates the internal switching of the
onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An
internal reference generator is also provided to simplify the system design.
Designed with a 2.3-GHz input bandwidth for the conversion of signals that exceed 500MHz of input center
frequency at 500 MSPS, the ADS5463 has outstanding low noise performance and spurious-free dynamic range
over a large input frequency range.
The ADS5463 is available in a TQFP-80 PowerPAD™ package. The ADS5463 is built on Texas Instrument's
complementary bipolar process (BiCom3) and is specified over the full industrial temperature range (–40°C to
85°C).
VIN
VIN
A1
TH1
+
TH2
S
+
TH3
A2
–
ADC1
VREF
S
A3
ADC3
–
DAC1
ADC2
DAC2
Reference
5
5
4
Digital Error Correction
CLK
CLK
Timing
OVR
OVR
DRY
DRY
D[11:0]
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2008, Texas Instruments Incorporated
ADS5463
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT
PACKAGE-LEAD
PACKAGE
DESIGNATOR (1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ADS5463
HTQFP-80 (2)
PowerPAD
PFP
–40°C to 85°C
ADS5463I
(1)
(2)
ORDERING
NUMBER
TRANSPORT
MEDIA, QUANTITY
ADS5463IPFP
Tray, 96
ADS5463IPFPR
Tape and reel, 1000
For the most current product and ordering information, see the Package Option Addendum located at the end of this data sheet.
Thermal pad size: 6.15 mm × 6.15 mm (min), 7.5 mm × 7.5 mm (maximum), see Thermal Pad Addendum located at the end of the data
sheet.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
ADS5463
UNIT
AVDD5 to GND
6
V
AVDD3 to GND
5
V
DVDD3 to GND
5
V
–0.3 to (AVDD5 + 0.3)
V
–0.3 to (AVDD5 + 0.3)
V
Analog input to
GND
Valid when supplies are on and within normal ranges. See additional
information in the Power Supplies portion of the applications information
in the back of the datasheet regarding Clock and Analog Inputs when the
Clock input to GND
supplies are off.
CLK to CLK
Digital data output
to GND
±2.5
V
–0.3 to (DVDD3 + 0.3)
V
–40 to 85
°C
150
°C
Operating temperature range
Maximum junction temperature
Storage temperature range
ESD, human-body model (HBM)
(1)
–65 to 150
°C
2
kV
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime is available upon
request.
THERMAL CHARACTERISTICS (1)
PARAMETER
(2)
RθJA
(3)
RθJP
(1)
(2)
(3)
2
TEST CONDITIONS
TYP
Soldered thermal pad, no airflow
23.7
Soldered thermal pad, 150-LFM airflow
17.8
Soldered thermal pad, 250-LFM airflow
16.4
Bottom of package (thermal pad)
2.99
UNIT
°C/W
°C/W
Using 36 thermal vias (6 × 6 array). See PowerPAD Package in the Application Information section.
RθJA is the thermal resistance from the junction to ambient.
RθJP is the thermal resistance from the junction to the thermal pad.
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RECOMMENDED OPERATING CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLIES
AVDD5
Analog supply voltage
4.75
5
5.25
V
AVDD3
Analog supply voltage
3
3.3
3.6
V
DVDD3
Output driver supply voltage
3
3.3
3.6
V
ANALOG INPUT
VCM
Differential input range
2.2
Vpp
Input common mode
2.4
V
10
pF
DIGITAL OUTPUT (DRY, DATA, OVR)
Maximum differential output load
CLOCK INPUT (CLK)
TA
CLK input sample rate (sine wave)
20
500
Clock amplitude, differential sine wave
0.5
5
Vpp
Clock duty cycle
40
60
%
85
°C
Open free-air temperature
50
–40
MSPS
ELECTRICAL CHARACTERISTICS
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input,
and 3-VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Resolution
TYP
MAX
UNIT
12
Bits
ANALOG INPUTS
Differential input range
VCM
2.2
VPP
Analog Input common-mode voltage
Self-biased
2.4
V
Input resistance (dc)
Each input to VCM
500
Ω
Input capacitance
Each input to GND (including package)
4.8
pF
2.3
GHz
90
dB
2.4
V
Analog input bandwidth (–3 dB)
CMRR
Common-mode rejection ratio
Common mode signal = 10 MHz
INTERNAL REFERENCE VOLTAGE
VREF
Reference voltage
DYNAMIC ACCURACY
No missing codes
Specified
DNL
Differential linearity error
fIN = 10 MHz
INL
Integral linearity error
fIN = 10 MHz
Offset error
–0.95
±0.25
0.95
LSB
–2.5 +0.8/–0.3
2.5
LSB
–11
11
Offset temperature coefficient
mV
0.0005
Gain error
–5
Gain temperature coefficient
mV/°C
5
–0.02
%FS
%FS/°C
POWER SUPPLY
IAVDD5
5-V analog supply current
IAVDD3
3.3-V analog supply current
IDVDD3
3.3-V digital supply current (includes
LVDS)
VIN = full scale, fIN = 10 MHz,
fS = 500 MSPS
Total power dissipation
Power-up time
PSRR
Power-supply rejection ratio
Without 0.1-µF board supply capacitors,
with 100-kHz supply noise
300
330
mA
125
138
mA
82
88
mA
2.18
2.4
W
200
µs
85
dB
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input,
and 3-VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS
fIN = 10 MHz
65.4
fIN = 70 MHz
65.4
fIN = 100 MHz
63.5
fIN = 230 MHz
SNR
Signal-to-noise ratio
fIN = 300 MHz
65.1
63
64.6
fIN = 650 MHz
63.9
fIN = 900 MHz
62.6
fIN = 1.3 GHz
59.3
fIN = 10 MHz
85
fIN = 100 MHz
fIN = 300 MHz
78
64
fIN = 650 MHz
65
fIN = 900 MHz
56
fIN = 1.3 GHz
45
fIN = 10 MHz
87
fIN = 300 MHz
81
64
fIN = 650 MHz
77
fIN = 900 MHz
66
fIN = 1.3 GHz
50
fIN = 10 MHz
85
4
fIN = 300 MHz
87
90
64
80
fIN = 450 MHz
75
fIN = 650 MHz
65
fIN = 900 MHz
56
fIN = 1.3 GHz
45
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dBc
90
70
fIN = 230 MHz
Third harmonic
77
80
fIN = 70 MHz
HD3
80
fIN = 450 MHz
fIN = 100 MHz
dBc
82
70
fIN = 230 MHz
Second harmonic
77
75
fIN = 70 MHz
HD2
82
fIN = 450 MHz
fIN = 100 MHz
dBFS
82
70
fIN = 230 MHz
Spurious-free dynamic range
65
fIN = 450 MHz
fIN = 70 MHz
SFDR
65.3
dBc
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ELECTRICAL CHARACTERISTICS (continued)
Typical values at TA = 25°C, minimum and maximum values over full temperature range TMIN = –40°C to TMAX = 85°C,
sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, –1-dBFS differential input,
and 3-VPP differential clock (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS (continued)
Worst harmonic/spur (other than HD2
and HD3)
THD
Total Harmonic Distortion
fIN = 10 MHz
86
fIN = 70 MHz
86
fIN = 100 MHz
86
fIN = 230 MHz
77
fIN = 300 MHz
81
fIN = 450 MHz
86
fIN = 650 MHz
85
fIN = 900 MHz
78
fIN = 1.3 GHz
67
fIN = 10 MHz
80
fIN = 70 MHz
79
fIN = 100 MHz
77
fIN = 230 MHz
75
fIN = 300 MHz
73
fIN = 450 MHz
73
fIN = 650 MHz
64
fIN = 900 MHz
55
fIN = 1.3 GHz
44
fIN = 10 MHz
64.2
fIN = 70 MHz
fIN = 100 MHz
SINAD
Signal-to-noise and distortion
Two-tone SFDR
ENOB
Effective number of bits
RMS idle-channel noise
dBc
64.2
62
64.1
fIN = 230 MHz
63.7
fIN = 300 MHz
63.5
fIN = 450 MHz
63.1
fIN = 650 MHz
60.5
fIN = 900 MHz
54.4
fIN = 1.3 GHz
44.1
fIN1 = 65 MHz, fIN2 = 70 MHz, each tone at
–7 dBFS
90
fIN1 = 65 MHz, fIN2 = 70 MHz, each tone at
–16 dBFS
89
fIN1 = 350 MHz, fIN2 = 355 MHz, each tone
at –7 dBFS
82
fIN1 = 350 MHz, fIN2 = 355 MHz, each tone
at –16 dBFS
89
fIN = 100 MHz
dBc
10
fIN = 300 MHz
dBc
dBFS
10.4
Bits
10.4
Inputs tied to common-mode
0.7
LSB
LVDS DIGITAL OUTPUTS
VOD
Differential output voltage (±)
VOC
Common mode output voltage
247
1.125
350
454
1.375
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mV
V
5
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Sample
N–1
N+4
N+2
ta
N
N+1
N+3
tCLKH
N+5
tCLKL
CLK
CLK
Latency = 3.5 Clock Cycles
tDRY
DRY
DRY
(1)
tDATA
D[11:0], OVR
N
N–1
N+1
D[11:0], OVR
(1)
Polarity of DRY is undetermined. For further information, see the Digital Outputs section.
Figure 1. Timing Diagram
TIMING CHARACTERISTICS (1)
Typical values at TA = 25°C, Min and Max values over full temperature range TMIN = –40°C to TMAX = 85°C, sampling rate =
500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V, and 3-VPP differential clock (unless
otherwise noted)
PARAMETER
ta
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Aperture delay
200
ps
Aperture jitter, rms
150
fs
Latency
3.5
cycles
tCLK
Clock period
2
tCLKH
Clock pulse duration, high
1
ns
tCLKL
Clock pulse duration, low
1
ns
tDRY
CLK to DRY delay (2)
Zero crossing, 10-pF parasitic loading to GND on each
output pin
950
1600
ps
tDATA
CLK to DATA/OVR delay (2)
Zero crossing, 10-pF parasitic loading to GND on each
output pin
750
2100
ps
tSKEW
DATA to DRY skew
tDATA – tDRY, 10-pF parasitic loading to GND on each output
pin
650
ps
tRISE
DRY/DATA/OVR rise time
10-pF parasitic loading to GND on each output pin
500
ps
tFALL
DRY/DATA/OVR fall time
10-pF parasitic loading to GND on each output pin
500
ps
(1)
(2)
6
–350
50
0
ns
Timing parameters are specified by design or characterization, but not production tested.
DRY, DATA, and OVR are updated on the falling edge of CLK. The latency must be added to tDATA to determine the overall propagation
delay.
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PIN CONFIGURATION
D4
D5
D4
D5
GND
D6
DVDD3
D7
D6
D8
D7
D9
D8
D10
D9
D11 (MSB)
D10
DRY
D11 (MSB)
DRY
PFP PACKAGE
(TOP VIEW)
DVDD3
1
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
60
D3
GND
2
59
D3
AVDD5
3
4
58
57
D2
NC
NC
5
56
D1
VREF
6
55
D1
GND
54
D0
AVDD5
7
8
53
D0
GND
9
52
GND
CLK
10
51
DVDD3
CLK
11
50
NC
ADS5463
D2
GND
12
49
NC
AVDD5
13
48
NC
AVDD5
14
47
NC
GND
15
46
NC
AIN
16
45
NC
AIN
17
44
NC
GND
18
43
NC
AVDD5
19
42
OVR
GND
20
41
OVR
GND
AVDD3
GND
AVDD3
GND
GND
AVDD3
GND
RESERVED
GND
AVDD5
GND
RESERVED
GND
AVDD5
GND
AVDD5
AVDD5
GND
AVDD5
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P0027-02
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Table 1. TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
DESCRIPTION
AIN
16
Differential input signal (positive)
AIN
17
Differential input signal (negative)
AVDD5
3, 8, 13, 14, 19, 21,
23, 25, 27, 31
AVDD3
35, 37, 39
Analog power supply (3.3 V) (Suggestion for ≤250 MSPS: leave option to connect to 5 V for
ADS5440/4 13-bit compatibility)
1, 51, 66
Output driver power supply (3.3 V)
DVDD3
Analog power supply (5 V)
GND
2, 7, 9, 12, 15, 18,
20, 22, 24, 26, 28,
30, 32, 34, 36, 38,
40, 52, 65
CLK
10
Differential input clock (positive). Conversion is initiated on rising edge.
CLK
11
Differential input clock (negative)
Ground
D0, D0
54, 53
LVDS digital output pair, least-significant bit (LSB)
D1–D10,
D1–D10
55–64,
67–76
LVDS digital output pairs
D11, D11
78, 77
LVDS digital output pair, most-significant bit (MSB)
DRY, DRY
80, 79
Data ready LVDS output pair
4, 5, 43–50
No connect (4 and 5 should be left floating, 43–50 are possible future bit additions for this pinout
and therefore can be connected to a digital bus or left floating)
OVR, OVR
42, 41
Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale
range.
RESERVED
29, 33
Pin 29 is reserved for possible future Vcm output for this pinout, like ADS5474; pin 33 is reserved for
possible future power-down control pin for this pinout, like ADS5474.
NC
VREF
8
6
Reference voltage input/output (2.4V nominal)
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TYPICAL CHARACTERISTICS
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
FFT FOR 30-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 100-MHz INPUT SIGNAL
0
0
SFDR = 82.4 dBc
SINAD = 65.3 dBFS
SNR = 65.4 dBFS
THD = 79 dBc
−40
−20
Amplitude − dB
Amplitude − dB
−20
−60
−80
SFDR = 80.6 dBc
SINAD = 65.1 dBFS
SNR = 65.3 dBFS
THD = 77.1 dBc
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
Frequency − MHz
Frequency − MHz
Figure 2.
Figure 3.
SPECTRAL PERFORMANCE
FFT FOR 230-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 300-MHz INPUT SIGNAL
0
0
SFDR = 77.5 dBc
SINAD = 64.7 dBFS
SNR = 65.2 dBFS
THD = 73.7 dBc
−20
SFDR = 77.1 dBc
SINAD = 64.5 dBFS
SNR = 65 dBFS
THD = 73.1 dBc
−20
−40
Amplitude − dB
Amplitude − dB
75 100 125 150 175 200 225 250
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
Frequency − MHz
25
50
75 100 125 150 175 200 225 250
Frequency − MHz
Figure 4.
Figure 5.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SPECTRAL PERFORMANCE
FFT FOR 450-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 650-MHz INPUT SIGNAL
0
0
SFDR = 74.3 dBc
SINAD = 64.3 dBFS
SNR = 64.8 dBFS
THD = 73 dBc
−40
−20
Amplitude − dB
Amplitude − dB
−20
−60
−80
SFDR = 65.5 dBc
SINAD = 61.8 dBFS
SNR = 64 dBFS
THD = 64.9 dBc
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
Frequency − MHz
Frequency − MHz
Figure 6.
Figure 7.
SPECTRAL PERFORMANCE
FFT FOR 900-MHz INPUT SIGNAL
SPECTRAL PERFORMANCE
FFT FOR 1,300-MHz INPUT SIGNAL
0
0
SFDR = 55.5 dBc
SINAD = 55.3 dBFS
SNR = 62.8 dBFS
THD = 55.1 dBc
−40
−60
−80
−100
SFDR = 45.6 dBc
SINAD = 45.1 dBFS
SNR = 59.3 dBFS
THD = 44.3 dBc
−20
Amplitude − dB
Amplitude − dB
−20
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
Frequency − MHz
25
50
75 100 125 150 175 200 225 250
Frequency − MHz
Figure 8.
10
75 100 125 150 175 200 225 250
Figure 9.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 65.1 MHz AND 70.1 MHz AT –7 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 65.1 MHz AND 70.1 MHz AT –16 dBFS)
0
0
fIN1 = 65.1 MHz, −7 dBFS
fIN2 = 70.1 MHz, −7 dBFS
IMD3 = 90.5 dBFS
SFDR = 90.3 dBFS
−40
−20
Amplitude − dB
Amplitude − dB
−20
−60
−80
fIN1 = 65.1 MHz, −16 dBFS
fIN2 = 70.1 MHz, −16 dBFS
IMD3 = 96.1 dBFS
SFDR = 88.8 dBFS
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
25
50
Frequency − MHz
Frequency − MHz
Figure 10.
Figure 11.
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 350 MHz AND 355 MHz AT –7 dBFS)
TWO-TONE INTERMODULATION DISTORTION
(FFT FOR 350 MHz AND 355 MHz AT –16 dBFS)
0
0
fIN1 = 350 MHz, −7 dBFS
fIN2 = 355 MHz, −7 dBFS
IMD3 = 81.6 dBFS
SFDR = 81.6 dBFS
−20
fIN1 = 350 MHz, −16 dBFS
fIN2 = 355 MHz, −16 dBFS
IMD3 = 101.1 dBFS
SFDR = 88.9 dBFS
−20
−40
Amplitude − dB
Amplitude − dB
75 100 125 150 175 200 225 250
−60
−80
−100
−40
−60
−80
−100
−120
−120
0
25
50
75 100 125 150 175 200 225 250
0
Frequency − MHz
25
50
75 100 125 150 175 200 225 250
Frequency − MHz
Figure 12.
Figure 13.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
NORMALIZED GAIN RESPONSE
vs
INPUT FREQUENCY
DIFFERENTIAL NONLINEARITY
3
0.3
fS = 500 MSPS
fIN = 10 MHz
0
Differential Nonlinearity − LSB
Normalized Gain - dB
0.2
-3
-6
-9
-12
-15
0.1
0.0
−0.1
−0.2
-18
fS = 500 MSPS
AIN = ±0.4 VPP
-21
10 M
−0.3
100 M
1G
50
5G
Code
Figure 14.
Figure 15.
G014
INTEGRAL NONLINEARITY
NOISE HISTOGRAM WITH INPUTS SHORTED
60
fS = 500 MSPS
fIN = 10 MHz
0.8
55
fS = 500 MSPS
50
0.6
45
Percentage − %
0.4
0.2
0.0
−0.2
−0.4
40
35
30
25
20
15
−0.6
10
−0.8
5
−1.0
0
50
550
1050 1550 2050 2550 3050 3550 4050
2050
Code
G015
Figure 16.
12
1050 1550 2050 2550 3050 3550 4050
Input Frequency - Hz
1.0
INL − Integral Nonlinearity − LSB
550
2049
2048
2047
2046
Code Number
G016
Figure 17.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
AC PERFORMANCE
vs
INPUT AMPLITUDE (100-MHz INPUT SIGNAL)
AC PERFORMANCE
vs
INPUT AMPLITUDE (300-MHz INPUT SIGNAL)
120
AC Performance − dB
80
100
80
SNR (dBFS)
AC Performance − dB
100
120
SFDR (dBFS)
60
40
SFDR (dBc)
20
0
SNR (dBc)
−20
SNR (dBFS)
60
40
SFDR (dBc)
20
0
SNR (dBc)
−20
−40
−60
−120
SFDR (dBFS)
−40
fS = 500 MSPS
fIN = 100.3 MHz
−100
−80
−60
−40
−20
−60
−120
0
Input Amplitude − dBFS
fS = 500 MSPS
fIN = 301.1 MHz
−100
−80
−60
−40
−20
G017
G018
Figure 18.
Figure 19.
AC PERFORMANCE
vs
INPUT AMPLITUDE (350-MHz AND 355-MHz TWO-TONE
INPUT SIGNAL)
100
Worst Spur (dBFS)
AC Performance − dB
SNR (dBFS)
60
Worst Spur (dBc)
40
20
SNR (dBc)
0
−20
−80
fS = 500 MSPS
fIN1 = 350 MHz
fIN2 = 355 MHz
−70
−60
−50
−40
−30
−20
−10
SFDR
vs
AVDD5 ACROSS TEMPERATURE
80
SFDR − Spurious-Free Dynamic Range − dBc
80
0
Input Amplitude − dBFS
75
70
TA = 05C
TA = 405C
65
TA = 655C
TA = 255C
TA = −405C
60
TA = 855C
fS = 500 MSPS
fIN= 100 MHz
TA = 1005C
55
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
0
AVDD − Supply Voltage − V
Input Amplitude − dBFS
G020
Figure 20.
G026
Figure 21.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SNR
vs
AVDD5 ACROSS TEMPERATURE
SFDR
vs
AVDD3 ACROSS TEMPERATURE
80
66.5
fS = 500 MSPS
fIN= 100 MHz
SFDR − Spurious-Free Dynamic Range − dBc
SNR − Signal-to-Noise Ratio − dBFS
67.0
TA = −405C
66.0
TA = 05C
65.5
TA = 255C
TA = 405C
65.0
64.5
TA = 655C
64.0
TA = 855C
TA = 1005C
63.5
63.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
AVDD − Supply Voltage − V
TA = 05C
76
TA = 655C
74
72
TA = 855C
TA = 1005C
70
TA = −405C
fS = 500 MSPS
fIN= 100 MHz
2.9
3.1
3.3
3.5
AVDD − Supply Voltage − V
G027
3.7
G028
Figure 22.
Figure 23.
SNR
vs
AVDD3 ACROSS TEMPERATURE
SFDR
vs
DVDD3 ACROSS TEMPERATURE
66.0
SFDR − Spurious-Free Dynamic Range − dBc
80
TA = −405C
TA = 05C
65.5
TA = 255C
TA = 405C
65.0
TA = 655C
64.5
TA = 855C
64.0
fS = 500 MSPS
fIN= 100 MHz
63.5
2.7
2.9
TA = 1005C
3.1
3.3
AVDD − Supply Voltage − V
3.5
3.7
TA = 255C
78
TA = 405C
TA = 05C
76
TA = 655C
74
TA = 855C
72
TA = −405C
70
TA = 1005C
fS = 500 MSPS
fIN= 100 MHz
68
2.7
G029
Figure 24.
14
TA = 255C
78
68
2.7
66.5
SNR − Signal-to-Noise Ratio − dBFS
TA = 405C
2.9
3.1
3.3
DVDD − Supply Voltage − V
3.5
3.7
G030
Figure 25.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SNR
vs
DVDD3 ACROSS TEMPERATURE
0
fS = 500 MSPS
fIN= 100 MHz
66.0
CMMR - Common-Mode Rejection Ratio - dB
SNR − Signal-to-Noise Ratio − dBFS
66.5
CMRR
vs
COMMON-MODE INPUT FREQUENCY
TA = −405C
TA = 05C
65.5
TA = 255C
TA = 405C
65.0
TA = 655C
64.5
TA = 855C
64.0
TA = 1005C
63.5
2.7
2.9
3.1
3.3
3.5
fS = 500 MSPS
-20
-30
-40
-50
-60
-70
-80
-90
-100
0.1
3.7
DVDD − Supply Voltage − V
-10
1
10
100
10k
1000
Input Frequency - MHz
G031
Figure 26.
Figure 27.
SNR vs INPUT FREQUENCY AND SAMPLING FREQUENCY
550
63
64
64
65
61
62
63
fS - Sampling Frequency - MHz
500
65
450
64
400
63
62
350
300
65
64
63
62
250
61
200
170
10
58
59
65
100
200
300
400
500
600
700
800
900
1000
64
65
66
67
fIN - Input Frequency - MHz
57
58
59
60
61
62
63
SNR - dBFS
M0048-09
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
Typical plots at TA = 25°C, sampling rate = 500 MSPS, 50% clock duty cycle, AVDD5 = 5 V, AVDD3 = 3.3 V, DVDD3 = 3.3 V,
and 3-VPP differential clock, (unless otherwise noted)
SFDR vs INPUT FREQUENCY AND SAMPLING FREQUENCY
550
70
75
80
500
fS - Sampling Frequency - MHz
60
75
55
65
80
80
450
400
70
75
65
80
350
55
60
80
300
85
250
60
200
170
10
70
75
85
80
100
300
200
55
65
400
500
600
700
800
900
1000
fIN - Input Frequency - MHz
45
50
55
60
65
70
75
SFDR - dBc
80
85
90
M0049-09
Figure 29.
APPLICATION INFORMATION
Theory of Operation
The ADS5463 is a 12-bit, 500-MSPS, monolithic pipeline ADC. Its bipolar analog core operates from 5-V and
3.3-V supplies, while the output uses a 3.3-V supply to provide LVDS-compatible outputs. The conversion
process is initiated by the rising edge of the external input clock. At that instant, the differential input signal is
captured by the input track-and-hold (T&H), and the input sample is sequentially converted by a series of lower
resolution stages, with the outputs combined in a digital correction logic block. Both the rising and the falling
clock edges are used to propagate the sample through the pipeline every half clock cycle. This process results in
a data latency of 3.5 clock cycles, after which the output data is available as a 12-bit parallel word, coded in
offset binary format.
Input Configuration
The analog input for the ADS5463 consists of an analog pseudo-differential buffer followed by a bipolar transistor
track-and-hold (see Figure 30). The analog buffer isolates the source driving the input of the ADC from any
internal switching and presents a high impedance that is easy to drive at high input frequencies, compared to an
ADC without a buffered input. The input common mode is set internally through a 500-Ω resistor connected from
2.4 V to each of the inputs. This results in a differential input impedance of 1 kΩ.
16
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ADS5474/5463/5444/5440
AVDD5
~ 2.5 nH Bond Wire
Buffer
AIN
~ 0.5 pF
package
~ 200 fF
bondpad
1.6 pF
500 W
GND
VCM
GND
AVDD5
1.6 pF
500 W
~ 2.5 nH Bond Wire
AIN
~ 0.5 pF
package
Buffer
~ 200 fF
bondpad
GND
Figure 30. Analog Input Equivalent Circuit
For a full-scale differential input, each of the differential lines of the input signal (pins 16 and 17) swing
symmetrically between 2.4 V + 0.55 V and 2.4 V – 0.55 V. This means that each input has a maximum signal
swing of 1.1 VPP for a total differential input signal swing of 2.2 VPP. Operation below 2.2 VPP is allowable, with
the characteristics of performance versus input amplitude demonstrated in Figure 18 and Figure 19. For
instance, for performance at 1.1 VPP rather than 2.2 VPP, see the SNR and SFDR at -6 dBFS (0 dBFS = 2.2 VPP).
The maximum swing is determined by the internal reference voltage generator, eliminating the need for any
external circuitry for this purpose.
The ADS5463 obtains optimum performance when the analog inputs are driven differentially. The circuit in
Figure 31 shows one possible configuration using an RF transformer with termination either on the primary or on
the secondary of the transformer. In addition, the evaluation module is configured with two back-to-back
transformers, which also demonstrates good performance. If voltage gain is required, a step-up transformer can
be used.
R0
50 W
Z0
50 W
AIN
R
200 W
AC Signal
Source
Mini-Circuits
JTX-4-10T
ADS5463
AIN
S0176-03
Figure 31. Converting a Single-Ended Input to a Differential Signal Using an RF Transformer
In addition to the transformer configurations, Texas Instruments offers a wide selection of single-ended
operational amplifiers that can be selected depending on the application. An RF gain-block amplifier, such as the
Texas Instruments THS9001, can also be used for high-input-frequency applications. For large voltage gains at
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intermediate-frequencies in the 50-MHz–350-MHz range, the configuration shown in Figure 32 can be used. The
component values can be tuned for different intermediate frequencies. The example shown is located on the
evaluation module and is tuned for an IF of 170 MHz. More information regarding this configuration can be found
in the ADS5463 EVM User Guide (SLAU194) and the THS9001 50 MHz to 350 MHz Cascadeable Amplifier data
sheet (SLOS426).
1000 pF
VIN
1000 pF
AIN
THS9001
50 W
18 mH
39 pF
ADS5463
50 W
VIN
0.1 mF
AIN
THS9001
1000 pF
1000 pF
S0177-03
Figure 32. Using the THS9001 IF Amplifier With the ADS5463
From
50 W
Source
VIN
100 W
78.9 W
348 W
+5V
49.9 W
0.22 mF
100 W
AIN
THS4509
ADS5463
49.9 W 18 pF
AIN
VREF
CM
49.9 W
0.22 mF
78.9 W
49.9 W
0.22 mF
0.1 mF
0.1 mF
348 W
S0193-02
Figure 33. Using the THS4509 With the ADS5463
For applications requiring dc-coupling with the signal source, a differential input/differential output amplifier like
the THS4509 (see Figure 33) provides good harmonic performance and low noise over a wide range of
frequencies. Notice that VREF is used for the common mode with the ADS5463 and ADS5444/5440, whereas
VCM must be used with the ADS5474.
In this configuration, the THS4509 amplifier circuit provides 10 dB of gain, converts the single-ended input to
differential, and sets the proper input common-mode voltage to the ADS5463 by using the VREF pin from the
ADC. The 50-Ω resistors and 18-pF capacitor between the THS4509 outputs and ADS5463 inputs (along with
the input capacitance of the ADC) limit the bandwidth of the signal to about 70 MHz (–3 dB). Input termination is
accomplished via the 78.9-Ω resistor and 0.22-µF capacitor to ground, in conjunction with the input impedance of
the amplifier circuit. A 0.22-µF capacitor and 49.9-Ω resistor are inserted to ground across the 78.9-Ω resistor
and 0.22-µF capacitor on the alternate input to balance the circuit. Gain is a function of the source impedance,
termination, and 348-Ω feedback resistor. See the THS4509 data sheet for further component values to set
proper 50-Ω termination for other common gains. Because the ADS5463 recommended input common-mode
voltage is 2.4 V, the THS4509 is operated from a single power supply input with V S+ = 5 V and V S– = 0 V
(ground). This maintains maximum headroom on the internal transistors of the THS4509.
18
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External Voltage Reference
For systems that require the analog signal gain to be adjusted or calibrated, this can be performed by using an
external reference. The dependency on the signal amplitude to the value of the external reference voltage is
characterized typically by Figure 34 (VREF = 2.4 V is normalized to 0 dB as this is the internal reference voltage.
This figure is the average gain adjustment from the data collected from -1dBFS to -6dBFS in 1 dB steps.) As can
be seen in the linear fit, this equates to approximately –0.3 dB of signal adjustment per 100 mV of reference
adjustment. The range of allowable variation depends on the analog input amplitude that is applied to the inputs
and the desired spectral performance, as can be seen in the performance versus external reference graphs in
Figure 35 and Figure 36. As the applied analog signal amplitude is reduced, more variation in the reference
voltage is allowed in the positive direction (which equates to a reduction in signal amplitude), whereas an
adjustment in reference voltage below the nominal 2.4 V (which equates to an increase in signal amplitude) is
not recommended below approximately 2.35 V. The power consumption versus reference voltage and operating
temperature should also be considered, especially at high ambient temperatures, because the lifetime of the
device is affected by internal junction temperature, see Figure 49.
The ADS5463 does not have a VCM output pin and primarily uses the VREF pin to provide the common-mode
voltage in dc-coupled applications. The ADS5463 (VCM = 2.4 V) and ADS5474 (VCM = 3.1 V) do not have the
same common-mode voltage, but they do share the same approximate VREF (2.4 V). To create a board layout
that may accommodate both devices in dc-coupled applications, route the VCM of the ADS5474 and the VREF
of the ADS5463 both to a common point that can be selected via a switch, jumper, or a 0 Ω resistor to be used
as the common-mode voltage of the driving circuit.
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1.0
90
SFDR - Spurious-Free Dynamic Range - dBc
0.5
Normalized Gain Adjustment - dB
AIN = -5 dBFS
fS = 500 MSPS
fIN = 230 MHz
AIN = < -1 dBFS
0
Best Fit:
y = -3.06x + 7.33
-0.5
-1.0
Normalized
Amplitude
-1.5
-2.0
Linear
(Normalized Amplitude)
-2.5
AIN = -6 dBFS
80
70
AIN = -4 dBFS
AIN = -3 dBFS
60
AIN = -2 dBFS
AIN = -1 dBFS
50
fS = 500 MSPS
fIN = 230 MHz
Normalized to 0dB at Nominal VREF = 2.4 V
-3.0
2.2
70
40
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15
3.1
External VREF Applied - V
External VREF Applied - V
Figure 34. Signal Gain Adjustment versus External
Reference (VREF)
Figure 35. SFDR versus External VREF and AIN
3.0
fS = 500 MSPS
fIN = 230 MHz
AIN = -6 dBFS
2.9
2.8
2.7
60
AIN = -2 dBFS
55
Power - W
SNR - Signal-to-Noise Ratio - V
65
fS = 500 MSPS
fIN = 230 MHz
AIN = -3 dBFS
2.6
2.5
2.4
AIN = -4 dBFS
50
2.3
AIN = -1 dBFS
AIN = -5 dBFS
45
2.2
2.1
40
20
2.0
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15
2.05 2.15 2.25 2.35 2.45 2.55 2.65 2.75 2.85 2.95 3.05 3.15
External VREF Applied - V
External VREF Applied - V
Figure 36. SNR versus External VREF and AIN
Figure 37. Total Power Consumption versus External
VREF
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Clock Inputs
The ADS5463 clock input can be driven with either
equivalent clock input circuit can be seen in Figure
be a big concern, the use of a single-ended clock
without much performance tradeoff. When clocked
with a 0.01-µF capacitor, while CLK is ac-coupled
Figure 39.
ADS5463/5444/5440
a differential clock signal or a single-ended clock input. The
38. In low-input-frequency applications, where jitter may not
(as shown in Figure 39) could save cost and board space
with this configuration, it is best to connect CLK to ground
with a 0.01-µF capacitor to the clock source, as shown in
AVDD5
Parasitic
~ 0.8 pF
~ 2.5 nH Bond Wire
CLK
~ 0.5 pF
package
~ 200 fF
bondpad
1000 W
Internal
Clock
Buffer
~ 2.4 V
GND
AVDD5
GND
1000 W
~ 2.5 nH Bond Wire
CLK
~ 0.5 pF
package
Parasitic
~ 0.8 pF
~ 200 fF
bondpad
GND
Figure 38. Clock Input Circuit
Square Wave or
Sine Wave
CLK
0.01 mF
ADS5463
CLK
0.01 mF
S0168-05
Figure 39. Single-Ended Clock
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66.0
79
fIN = 100 MHz
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
80
78
77
fIN = 300 MHz
76
75
74
73
72
fIN = 100 MHz
65.5
65.0
fIN = 300 MHz
64.5
64.0
63.5
63.0
fS = 500 MSPS
fS = 500 MSPS
62.5
71
0
1
2
3
4
0
5
Clock Amplitude − VP−P
1
3
4
Clock Amplitude − VP−P
G022
Figure 40. SFDR versus Differential Clock Level
2
5
G023
Figure 41. SNR versus Differential Clock Level
The characterization of the ADS5463 is typically performed with a 3-VPP differential clock, but the ADC performs
well with a differential clock amplitude down to ~0.5 VPP (250mV swing on both CLK and CLK), as shown in
Figure 40 and Figure 41. For jitter-sensitive applications, the use of a differential clock has some advantages at
the system level. The differential clock allows for common-mode noise rejection at the printed circuit board (PCB)
level. With a differential clock, the signal-to-noise ratio of the ADC is better for jitter-sensitive, high-frequency
applications because the board level clock jitter is superior.
Larger clock amplitude levels are recommended for high analog input frequencies or slow clock frequencies. At
high analog input frequencies, the sampling process is sensitive to jitter. At slow clock frequencies, a small
amplitude sinusoidal clock has a lower slew rate and can create jitter-related SNR degradation due to the
uncertainty in the sampling point associated with a slow slew rate. Figure 42 demonstrates a recommended
method for converting a single-ended clock source into a differential clock; it is similar to the configuration found
on the evaluation board and was used for much of the characterization. See also Clocking High Speed Data
Converters (SLYT075) for more details.
0.1 mF
Clock
Source
CLK
ADS5463
CLK
S0194-02
Figure 42. Differential Clock
The common-mode voltage of the clock inputs is set internally to 2.4 V using internal 1-kΩ resistors (see
Figure 38). It is recommended to use ac coupling, but if this scheme is not possible, the ADS5474 features good
tolerance to clock common-mode variation, as shown in Figure 43 and Figure 44. The internal ADC core uses
both edges of the clock for the conversion process. Ideally, a 50% duty-cycle clock signal should be provided,
though even 40/60 is good enough for many applications. Performance degradation as a result of duty cycle can
be seen in Figure 45.
22
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66
fIN = 100 MHz
SNR − Signal-to-Noise Ratio − dBFS
SFDR − Spurious-Free Dynamic Range − dBc
85
fIN = 100 MHz
80
fIN = 300 MHz
75
70
65
65
fIN = 300 MHz
64
63
62
61
fS = 500 MSPS
fS = 500 MSPS
60
60
0
1
2
3
4
5
0
1
Clock Common Mode − V
2
3
4
5
Clock Common Mode − V
G025
G024
Figure 43. SFDR versus Clock Common Mode
Figure 44. SNR versus Clock Common Mode
SFDR − Spurious-Free Dynamic Range − dBc
85
fIN = 100 MHz
80
75
fIN = 300 MHz
70
65
60
55
fS = 500 MSPS
50
20
30
40
50
60
70
80
Duty Cycle − %
G021
Figure 45. SFDR vs Clock Duty Cycle
To understand how to determine the required clock jitter, an example is useful. The ADS5463 is capable of
achieving 63.6 dBFS SNR at 450 MHz of analog input frequency. In order to achieve this SNR at 450 MHz the
clock source rms jitter must be at least 181 fsec when combined with the 150 fsec of internal aperture jitter in
order for the total rms jitter to be 234 fsec. A summary of maximum recommended rms clock jitter as a function
of analog input frequency is provided in Table 2 (using 150 fsec of internal aperture jitter). The equations used to
create the table are also presented.
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Table 2. Recommended RMS Clock Jitter
INPUT FREQUENCY
(MHz)
MEASURED SNR
(dBc)
TOTAL JITTER
(fsec rms)
MAXIMUM CLOCK JITTER
(fsec rms)
10
64.4
9590
9589
70
64.4
1370
1362
100
64.3
970
959
230
64.1
432
405
300
64
335
300
450
63.6
234
181
650
62.9
175
94
1300
58.3
149
16
Equation 1 and Equation 2 are used to estimate the required clock source jitter.
SNR (dBc) = -20 x LOG10 (2 x p x fIN x jTOTAL)
2
(1)
2 1/2
jTOTAL = (jADC + jCLOCK )
(2)
where:
jTOTAL = the rms summation of the clock and ADC aperture jitter;
jADC = the ADC internal aperture jitter which is located in the data sheet;
jCLOCK = the rms jitter of the clock at the clock input pins to the ADC; and
fIN = the analog input frequency.
Notice that the SNR is a strong function of the analog input frequency, not the clock frequency. The slope of the
clock source edges can have a mild impact on SNR as well and is not taken into account for these estimates.
For this reason, maximizing clock source amplitudes at the ADC clock inputs is recommended, though not
required (faster slope is desirable for jitter-related SNR). For more information on clocking high-speed ADCs, see
Application Note SLWA034, Implementing a CDC7005 Low Jitter Clock Solution For High-Speed, High-IF ADC
Devices. Recommended clock distribution chips (CDCs) are the TI CDC7005 and CDCM7005. Depending on the
jitter requirements, a band pass filter (BPF) is sometimes required between the CDC and the ADC. If the
insertion loss of the BPF causes the clock amplitude to be too low for the ADC, or the clock source amplitude is
too low to begin with, an inexpensive amplifier can be placed between the CDC and the BPF.
Figure 46 represents a scenario where an LVCMOS single-ended clock output is used from a TI CDCM7005 with
the clock signal path optimized for maximum amplitude and minimum jitter. This type of conditioning might
generally be well-suited for use with greater than 250 MHz of input frequency. The jitter of this setup is difficult to
estimate and requires a careful phase noise analysis of the clock path. The BPF (and possibly a low-cost
amplifier because of insertion loss in the BPF) can improve the jitter between the CDC and ADC when the jitter
provided by the CDC is still not adequate. The total jitter at the CDCM7005 output depends largely on the phase
noise of the VCXO selected, as well as the CDCM7005, and typically has 50–100 fs of rms jitter. If it is
determined that the jitter from the CDCM7005 with a VCXO is sufficient without further conditioning, it is possible
to clock the ADS5463 directly from the CDCM7005 using differential LVPECL outputs, as illustrated in Figure 47
(see the CDCM7005 data sheet for the exact schematic). This scenario may be more suitable for less than 150
MHz of input frequency where jitter is not as critical. A careful analysis of the required jitter and of the
components involved is recommended before determining the proper approach.
24
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Low-Jitter Clock Distribution
AMP and/or BPF are Optional
Board Master
Reference Clock
(high or low jitter)
10 MHz
LVCMOS
REF
BPF
AMP
CLKIN
XFMR
CLKIN
500 MHz
ADC
1000 MHz (to transmit DAC)
ADS5463
125 MHz (to DSP)
LVPECL
or
LVCMOS
Low-Jitter Oscillator
1000 MHz
VCO
.
.
.
250 MHz (to FPGA)
To Other
CDC
(Clock Distribution Chip)
CDCM7005
This is an example block diagram.
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 46. Optimum Jitter Clock Circuit
Low-Jitter Clock Distribution
Board Master
Reference Clock
(high or low jitter)
10 MHz
500 MHz
CLKIN
LVPECL
REF
CLKIN
ADC
1000 MHz (to transmit DAC)
ADS5463
125 MHz (to DSP)
LVPECL
or
LVCMOS
Low-Jitter Oscillator
1000 MHz
VCO
.
.
.
250 MHz (to FPGA)
To Other
CDC
(Clock Distribution Chip)
CDCM7005
This is an example block diagram.
Consult the CDCM7005 data sheet for proper schematic and specifications regarding allowable input and output
frequency and amplitude ranges.
Figure 47. Acceptable Jitter Clock Circuit
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Digital Outputs
The ADC provides 12 LVDS-compatible, offset binary data outputs (D11 to D0; D11 is the MSB and D0 is the
LSB), a data-ready signal (DRY), and an over-range indicator (OVR). It is recommended to use the DRY signal
to capture the output data of the ADS5463. DRY is source-synchronous to the DATA/OVR outputs and operates
at the same frequency, creating a half-rate DDR interface that updates data on both the rising and falling edges
of DRY. It is recommended that the capacitive loading on the digital outputs be minimized. Higher capacitance
shortens the data-valid timing window. The values given for timing (see Figure 1) were obtained with a measured
10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic capacitance). When
setting the time relationship between DRY and DATA at the receiving device, it is generally recommended that
setup time be maximized, but this partially depends on the setup and hold times of the device receiving the
digital data (like an FPGA, Field Programmable Field Array). Since DRY and DATA are coincident, it will likely be
necessary to delay either DRY or DATA such that setup time is maximized.
Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined
because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a
frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and
the polarity of DRY could invert when power is cycled off/on. Data capture from the transition and not the polarity
of DRY is recommended, but not required. If the synchronization of multiple ADS5463 devices is required, it
might be necessary to use a form of the CLKIN signal rather than DRY to capture the data.
The DRY frequency is identical on the ADS5463 to the ADS5474 (where DRY equals 1/2 CLK frequency), but
different than it is on the pin-similar ADS5444/ADS5440 (where DRY equals the CLK frequency). The LVDS
outputs all require an external 100-Ω load between each output pair in order to meet the expected LVDS voltage
levels. For long trace lengths, it may be necessary to place a 100-Ω load on each digital output as close to the
ADS5474 as possible and another 100-Ω differential load at the end of the LVDS transmission line to provide
matched impedance and avoid signal reflections. The effective load in this case reduces the LVDS voltage levels
by half.
The OVR output equals a logic high when the 12-bit output word attempts to exceed either all 0s or all 1s. This
flag is provided as an indicator that the analog input signal exceeded the full-scale input limit of approximately
2.2 VPP (± gain error). The OVR indicator is provided for systems that use gain control to keep the analog input
signal within acceptable limits.
26
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Power Supplies
The ADS5463 uses three power supplies. For the analog portion of the design, a 5-V and 3.3-V supply (AVDD5
and AVDD3) are used, while the digital portion uses a 3.3-V supply (DVDD3). All of the ground pins are marked
as GND, although analog and digital grounds are not tied together inside the package. The use of low-noise
power supplies with adequate decoupling is recommended. Linear supplies are preferred to switched supplies;
switched supplies tend to generate more noise components that can be coupled to the ADS5463. However, the
PSRR value and the plot shown in Figure 48 were obtained without bulk supply decoupling capacitors. When
bulk (0.1 µF) decoupling capacitors are used, the board-level PSRR is much higher than the stated value for the
ADC. The user may be able to supply power to the device with a less-than-ideal supply and still achieve good
performance. It is not possible to make a single recommendation for every type of supply and level of decoupling
for all systems. If the noise characteristics of the available supplies are understood, a study of the PSRR data for
the ADS5463 may provide the user with enough information to select noisy supplies if the performance is still
acceptable within the frequency range of interest. The power consumption of the ADS5463 does not change
substantially over clock rate or input frequency as a result of the architecture and process. The DVDD3 PSRR is
superior to both the AVDD5 and AVDD3 so was not graphed.
Because there are two diodes connected in reverse between AVDD3 and DVDD3 internally, a power-up
sequence is recommended. When there is a delay in power up between these two supplies, the one that lags
could have current sinking through an internal diode before it powers up. The sink current can be large or small
depending on the impedance of the external supply and could damage the device or affect the supply source.
The best power up sequence is one of the following options (regardless of when AVDD5 powers up):
1) Power up both AVDD3 and DVDD3 at the same time (best scenario), OR
2) Keep the voltage difference less than 0.8V between AVDD3 and DVDD3 during the power up (0.8V is not a
hard specification - a smaller delta between supplies is safer).
If the above sequences are not practical then the sink current from the supply needs to be controlled or
protection added externally. The max transient current (on the order of µsec) for DVDD3 or AVDD3 pin is 500mA
to avoid potential damage to the device or reduce its lifetime.
Values for analog and clock input given in the Absolute Maximum Ratings are valid when the supplies are on.
When the power supplies are off and the clock or analog inputs are still alive, the input voltage and current needs
to be limited to avoid device damage. If the ADC supplies are off, the max/min continuous DC voltage is +/- 0.95
V and max DC current is 20 mA for each input pin (clock or analog), relative to ground.
PSRR − Power Supply Rejection Ratio − dB
100
AVDD3
90
80
AVDD5
70
60
50
fS = 500 MSPS
fIN= None
40
0.01
0.1
1
10
100
Frequency − MHz
G032
Figure 48. PSRR versus Supply Injected Frequency
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Operational Lifetime
It is important for applications that anticipate running continuously for long periods of time near the
maximum-rated ambient temperature of +85°C to consider the data shown in Figure 49 and Figure 50. Referring
to the Thermal Characteristics table, the worst-case operating condition with no airflow has a thermal rise of
23.7°C/W. At approximately 2.2 W of normal power dissipation, at a maximum ambient of +85°C with no airflow,
the junction temperature of the ADS5463 reaches approximately +85°C + 23.7°C/W × 2.2 W = +137°C and
therefore the expected lifetime is approximately 8 years due to an electro migration failure and 18 years due to a
wirebonding failure. Being even more conservative and accounting for the maximum possible power dissipation
that is ensured (2.4 W), the junction temperature becomes nearly +142°C. As Figure 49 and Figure 50 show, this
operating condition limits the expected lifetime of the ADS5463 even more. Operation at +85°C continuously may
require airflow or an additional heatsink in order to decrease the internal junction temperature and increase the
expected lifetime. An airflow of 250 LFM (linear feet per minute) reduces the thermal resistance to 16.4°C/W, the
maximum junction temperature to +124°C and the expected lifetime to over 10 years, assuming a worst-case of
2.4 W and +85°C ambient. Of course, operation at lower ambient temperatures greatly increases the expected
lifetime.
The ADS5463 performance over temperature is quite good and can be seen starting in Figure 21. Though the
typical plots show good performance at +100°C, the device is only rated from –40°C to +85°C. For continuous
operation at temperatures near or above the maximum, aside from performance degradation, the expected
primary negative effect is a shorter device lifetime.
100
Estimated Life - Years
Estimated Life - Years
1000
100
10
1
80
90
100
110
120
130
140
150
160
170
180
10
1
0.1
130
TJ - Continuous Junction Temperature - oC
Figure 49. Operating Life Derating Chart, Electro
Migration Fail Mode
28
140
150
160
170
180
190
200
TJ - Continuous Junction Temperature - oC
Figure 50. Operating Life Derating Chart, Wirebound
Voiding Fail Mode
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Layout Information
The evaluation board represents a good guideline of how to lay out the board to obtain the maximum
performance from the ADS5463. General design rules, such as the use of multilayer boards, single ground plane
for ADC ground connections, and local decoupling ceramic chip capacitors, should be applied. The input traces
should be isolated from any external source of interference or noise, including the digital outputs as well as the
clock traces. The clock signal traces should also be isolated from other signals, especially in applications where
low jitter is required like high IF sampling. Besides performance-oriented rules, care must be taken when
considering the heat dissipation of the device. The thermal heat sink should be soldered to the board as
described in the PowerPad Package section. See ADS5463 EVM User Guide (SLAU194) on the TI Web site for
the evaluation board schematic.
PowerPAD Package
The PowerPAD package is a thermally enhanced standard-size IC package designed to eliminate the use of
bulky heatsinks and slugs traditionally used in thermal packages. This package can be easily mounted using
standard printed circuit board (PCB) assembly techniques, and can be removed and replaced using standard
repair procedures.
The PowerPAD package is designed so that the leadframe die pad (or thermal pad) is exposed on the bottom of
the IC. This provides an extremely low thermal resistance path between the die and the exterior of the package.
The thermal pad on the bottom of the IC can then be soldered directly to the printed circuit board (PCB), using
the PCB as a heatsink.
Assembly Process
1. Prepare the PCB top-side etch pattern including etch for the leads as well as the thermal pad as illustrated in
the Mechanical Data section.
2. Place a 6-by-6 array of thermal vias in the thermal pad area. These holes should be 13 mils in diameter. The
small size prevents wicking of the solder through the holes.
3. It is recommended to place a small number of 25-mil-diameter holes under the package, but outside the
thermal pad area, to provide an additional heat path.
4. Connect all holes (both those inside and outside the thermal pad area) to an internal copper plane (such as a
ground plane).
5. Do not use the typical web or spoke via-connection pattern when connecting the thermal vias to the ground
plane. The spoke pattern increases the thermal resistance to the ground plane.
6. The top-side solder mask should leave exposed the terminals of the package and the thermal pad area.
7. Cover the entire bottom side of the PowerPAD vias to prevent solder wicking.
8. Apply solder paste to the exposed thermal pad area and all of the package terminals.
For more detailed information regarding the PowerPAD package and its thermal properties, see either the
PowerPAD Made Easy application brief (SLMA004) or the PowerPAD Thermally Enhanced Package application
report (SLMA002).
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DEFINITION OF SPECIFICATIONS
Analog Bandwidth
The analog input frequency at which the power of the
fundamental is reduced by 3 dB with respect to the
low-frequency value
Aperture Delay
The delay in time between the rising edge of the input
sampling clock and the actual time at which the
sampling occurs
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay
Clock Pulse Duration/Duty Cycle
The duty cycle of a clock signal is the ratio of the time
the clock signal remains at a logic high (clock pulse
duration) to the period of the clock signal, expressed
as a percentage.
Differential Nonlinearity (DNL)
An ideal ADC exhibits code transitions at analog input
values spaced exactly 1 LSB apart. DNL is the
deviation of any single step from this ideal value,
measured in units of LSB.
Common-Mode Rejection Ratio (CMRR)
CMRR measures the ability to reject signals that are
presented to both analog inputs simultaneously. The
injected common-mode frequency level is translated
into dBFS, the spur in the output FFT is measured in
dBFS, and the difference is the CMRR in dB.
Effective Number of Bits (ENOB)
ENOB is a measure in units of bits of a converter's
performance as compared to the theoretical limit
based on quantization noise
ENOB = (SINAD – 1.76)/6.02
Gain Error
Gain error is the deviation of the ADC actual input
full-scale range from its ideal value, given as a
percentage of the ideal input full-scale range.
PSRR is a measure of the ability to reject frequencies
present on the power supply. The injected frequency
level is translated into dBFS, the spur in the output
FFT is measured in dBFS, and the difference is the
PSRR in dB. The measurement calibrates out the
benefit of the board supply decoupling capacitors.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), excluding the power at
dc and in the first five harmonics.
P
SNR + 10log 10 S
PN
(4)
SNR is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Signal-to-Noise and Distortion (SINAD)
SINAD is the ratio of the power of the fundamental
(PS) to the power of all the other spectral components
including noise (PN) and distortion (PD), but excluding
dc.
PS
SINAD + 10log 10
PN ) PD
(5)
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Temperature Drift
Temperature drift (with respect to gain error and
offset error) specifies the change from the value at
the nominal temperature to the value at TMIN or TMAX.
It is computed as the maximum variation the
parameters over the whole temperature range divided
by TMIN – TMAX.
Integral Nonlinearity (INL)
INL is the deviation of the ADC transfer function from
a best-fit line determined by a least-squares curve fit
of that transfer function. The INL at each analog input
value is the difference between the actual transfer
function and this best-fit line, measured in units of
LSB.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS)
to the power of the first five harmonics (PD).
P
THD + 10log 10 S
PD
(6)
Offset Error
Offset error is the deviation of output code from
mid-code when
both
inputs are tied
to
common-mode.
Two-Tone Intermodulation Distortion (IMD3)
IMD3 is the ratio of the power of the fundamental (at
frequencies f1, f2) to the power of the worst spectral
component at either frequency 2f1 – f2 or 2f2 – f1).
IMD3 is given in units of either dBc (dB to carrier)
when the absolute power of the fundamental is used
as the reference, or dBFS (dB to full scale) when the
power of the fundamental is extrapolated to the
converter’s full-scale range.
Power-Supply Rejection Ratio (PSRR)
30
THD is typically given in units of dBc (dB to carrier).
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
ADS5463IPFP
ACTIVE
HTQFP
PFP
80
96
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
ADS5463IPFPG4
ACTIVE
HTQFP
PFP
80
96
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
ADS5463IPFPR
ACTIVE
HTQFP
PFP
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
ADS5463IPFPRG4
ACTIVE
HTQFP
PFP
80
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-4-260C-72 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
ADS5463IPFPR
Package Package Pins
Type Drawing
HTQFP
PFP
80
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
15.0
15.0
1.5
20.0
24.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Jun-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
ADS5463IPFPR
HTQFP
PFP
80
1000
333.2
345.9
31.8
Pack Materials-Page 2
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