CY8CLED02 EZ-Color™ HB LED Controller Features ■ HB LED Controller ❐ Configurable Dimmers Support up to 2 Independent LED Channels ❐ 8-32 Bits of Resolution per Channel ❐ Dynamic Reconfiguration Enables LED Controller plus other Features; Battery Charging, Motor Control ■ Visual Embedded Design ❐ LED-Based Drivers • Binning Compensation • Temperature Feedback • Optical Feedback • DMX512 ■ PrISM Modulation Technology ❐ Reduces Radiated EMI ❐ Reduces Low Frequency Blinking ■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ 3.0 to 5.25V Operating Voltage ❐ Operating Voltages down to 1.0V using On-Chip Switch Mode Pump (SMP) ❐ Industrial Temperature Range: -40°C to +85°C ■ ■ ■ Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Source on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to 12 Analog Inputs on GPIO ❐ Four 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO ■ Complete Development Tools ❐ Free Development Software • PSoC Designer™ ❐ Full featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128 KBytes Trace Memory Logic Block Diagram Port 1 Port 0 PSoC CORE System Bus Flexible On-Chip Memory ❐ 4K Flash Program Storage 50,000 Erase/Write Cycles ❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash Global Digital Interconnect Global Analog Interconnect SROM SRAM Flash CPU Core (M8C) Interrupt Controller Sleep and Watchdog Clock Sources (Includes IMO and ILO) Advanced Peripherals (PSoC Blocks) ❐ 4 Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • Full-Duplex UART • Multiple SPI Masters or Slaves • Connectable to all GPIO Pins ❐ 4 Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators ❐ Complex Peripherals by Combining Blocks DIGITAL SYSTEM Digital PSoC Block Array Digital Clocks ANALOG SYSTEM Analog PSoC Block Array POR and LVD I2C System Resets Switch Mode Pump Analog Ref. Internal Voltage Ref. SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-13704 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 15, 2010 [+] Feedback CY8CLED02 Contents EZ-Color™ Functional Overview........................................ 3 Target Applications......................................................... 3 The PSoC Core .............................................................. 3 The Digital System ......................................................... 3 The Analog System ........................................................ 4 Additional System Resources ........................................ 4 EZ-Color Device Characteristics .................................... 5 Getting Started..................................................................... 5 Development Kits ........................................................... 5 Technical Training Modules ........................................... 5 Consultants .................................................................... 5 Technical Support .......................................................... 5 Application Notes ........................................................... 5 Development Tools ............................................................. 6 PSoC Designer Software Subsystems........................... 6 In-Circuit Emulator.......................................................... 6 Document Conventions ...................................................... 7 Acronyms Used .............................................................. 7 Units of Measure ............................................................ 7 Numeric Naming............................................................. 7 Pin Information .................................................................... 8 Pinouts ........................................................................... 8 Register Reference............................................................ 10 Register Conventions ................................................... 10 Register Mapping Tables ............................................. 10 Register Map Bank 1.................................................... 11 Document Number: 001-13704 Rev. *C Electrical Specifications ................................................... Absolute Maximum Ratings.......................................... Operating Temperature ................................................ DC Electrical Characteristics........................................ AC Electrical Characteristics ........................................ Packaging Information...................................................... Packaging Dimensions................................................. Thermal Impedances.................................................... Solder Reflow Peak Temperature ................................ Development Tool Selection ............................................ Software Tools ............................................................. Hardware Tools ............................................................ Evaluation Tools........................................................... Device Programmers.................................................... Accessories (Emulation and Programming) ................. Third Party Tools .......................................................... Build a PSoC Emulator into Your Board....................... Ordering Information......................................................... Key Device Features .................................................... Ordering Code Definitions ............................................ Document History Page .................................................... Sales, Solutions, and Legal Information ......................... Worldwide Sales and Design Support.......................... Products ....................................................................... 13 14 14 15 22 31 31 33 33 34 34 34 34 35 36 36 36 37 37 37 38 39 39 39 Page 2 of 39 [+] Feedback CY8CLED02 EZ-Color™ Functional Overview Cypress's EZ-Color family of devices offers the ideal control solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and flexibility of PSoC (Programmable System-on-Chip™); with Cypress' PrISM (precise illumination signal modulation) drive technology providing lighting designers a fully customizable and integrated lighting solution platform. The EZ-Color family supports a range of independent LED channels from 4 channels at 32 bits of resolution each, up to 16 channels at 8 bits of resolution each. This enables lighting designers the flexibility to choose the LED array size and color quality. PSoC Designer software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature, optical, and LED binning compensation. EZ-Color's virtually limitless analog and digital customization enables the simple integration of features in addition to intelligent lighting, such as Battery Charging, Image Stabilization, and Motor Control during the development process. These features, along with Cypress's best-in-class quality and design support, make EZ-Color the ideal choice for intelligent HB LED control applications. Target Applications The Analog System consists of four analog blocks, supporting comparators, and analog-to-digital conversion up to 10 bits of precision. The Digital System The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below. ■ PrISM (8 to 32 bit) ■ PWMs (8 to 32 bit) ■ PWMs with dead band (8 to 32 bit) ■ Counters (8 to 32 bit) ■ Timers (8 to 32 bit) ■ UART 8 bit with selectable parity ■ SPI master and slave ■ I2C slave, master, multi-master (1 available as a System Resource) ■ Cyclical redundancy checker/generator (8 to 32 bit) ■ LCD Backlight ■ IrDA (up to 4) ■ Large Signs ■ Generators (8 to 32 bit) ■ General Lighting ■ Architectural Lighting ■ Camera/Cell Phone Flash ■ Flashlights Connect the digital blocks to any GPIO through a series of global busses that can route any signal to any pin. The busses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. The PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and an IMO (internal main oscillator) and an ILO (internal low speed oscillator). The CPU core, called the M8C, is a powerful, four MIPS, 8-bit Harvard architecture microprocessor with speeds up to 24 MHz. Digital blocks are provided in rows of four, where the number of blocks varies by device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled EZ-Color Device Characteristics. Figure 1. Digital System Block Diagram Port 1 Port 0 System Resources provide additional capability, such as digital clocks to increase the flexibility of the PSoC; I2C functionality for implementing an I2C master, slave, or multi-master; an internal voltage reference that provides an absolute value of 1.3V to a number of PSoC subsystems; a switch mode pump (SMP) that generates normal operating voltages off a single battery cell; and various system resets supported by the M8C. DIGITAL SYSTEM Row Input Configuration Digital PSoC Block Array Row 0 DBB00 DBB01 DCB02 4 DCB03 4 8 8 8 8 GIE[7:0] GIO[7:0] Document Number: 001-13704 Rev. *C To Analog System Row Output Configuration The Digital System is composed of an array of digital blocks, which can be configured into any number of digital peripherals. The digital blocks can be connected to the GPIO through a series of global busses that can route any signal to any pin, freeing designers from the constraints of a fixed peripheral controller. To System Bus Digital Clocks From Core Global Digital Interconnect GOE[7:0] GOO[7:0] Page 3 of 39 [+] Feedback CY8CLED02 The Analog System Additional System Resources The analog system is composed of four configurable blocks that enable creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common EZ-Color analog functions (most available as user modules) are listed below. System resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include: ■ Analog-to-digital converters (single or dual, with 10-bit resolution) ■ Pin-to-pin comparators (1) ■ Single-ended comparators (up to 2) with absolute (1.3V) reference or 8-bit DAC reference ■ ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital blocks as clock dividers. ■ The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. ■ Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. ■ An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. ■ An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. 1.3V reference (as a System Resource) In most PSoC based devices, analog blocks are provided in columns of three, which includes one CT (continuous time) and two SC (switched capacitor) blocks. This particular EZ-Color device provides limited functionality Type “E” analog blocks. Each column contains one CT block and one SC block. Figure 2. Analog System Block Diagram Array Input Configuration ACI0[1:0] ACI1[1:0] ACOL1MUX Array ACE00 ACE01 ASE10 ASE11 Document Number: 001-13704 Rev. *C Page 4 of 39 [+] Feedback CY8CLED02 EZ-Color Device Characteristics Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data sheet is shown in the highlighted row of the table Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks SRAM Size Flash Size CapSense CY8CLED02 CY8CLED04 CY8CLED08 CY8CLED16 Digital I/O Part Number LED Channels Table 1. EZ-Color Device Characteristics 2 4 8 16 16 56 44 44 1 1 2 4 4 4 8 16 8 48 12 12 0 2 4 4 2 2 4 4 4 6 12 12 256 Bytes 1K 256 Bytes 2K 4K 16K 16K 32K No Yes No No Getting Started The quickest path to understanding the EZ-Color silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the EZ-Color integrated circuit and presents specific pin, register, and electrical specifications. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest device data sheets on the web at http://www.cypress.com/ez-color. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com/store, click Lighting & Power Control to view a current list of available items. Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located at the center of the web page, and select CYPros Consultants. Technical Support Application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support. Application Notes A long list of application notes will assist you in every aspect of your design effort. To view the application notes, go to the http://www.cypress.com web site and select Application Notes under the Documentation tab. Technical Training Modules Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http://www.cypress.com/techtrain. Document Number: 001-13704 Rev. *C Page 5 of 39 [+] Feedback CY8CLED02 Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. PSoC Designer Software Subsystems System-Level View A drag-and-drop visual embedded system design environment based on PSoC Designer. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional Integrated Development Environment (IDE) based on PSoC Designer. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. Document Number: 001-13704 Rev. *C Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Page 6 of 39 [+] Feedback CY8CLED02 Document Conventions Units of Measure Acronyms Used A units of measure table is located in the Electrical Specifications section. Table 9 on page 13 lists all the abbreviations used to measure the devices. The following table lists the acronyms that are used in this document. Table 2. Acronyms Acronym AC ADC API CPU CT DAC DC EEPROM FSR GPIO I/O IPOR LSb LVD MSb PC POR PPOR PSoC® PWM ROM SC SMP SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose I/O input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter power on reset precision power on reset Programmable System-on-Chip pulse width modulator read only memory switched capacitor switch mode pump static random access memory Document Number: 001-13704 Rev. *C Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Page 7 of 39 [+] Feedback CY8CLED02 Pin Information Pinouts This section describes, lists, and illustrates the CY8CLED02 EZ-Color device pins and pinout configurations. The CY8CLED02 device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O. 8-Pin Part Pinout Table 3. 8-Pin Part Pinout (SOIC) Type Pin Pin Description No. Digital Analog Name 1 I/O I P0[5] Analog column mux input. 2 I/O I P0[3] Analog column mux input. 3 I/O P1[1] I2C Serial Clock (SCL), ISSP-SCLK. 4 Power Vss Ground connection. 5 I/O P1[0] I2C Serial Data (SDA), ISSP-SDATA. 6 I/O I P0[2] Analog column mux input. 7 I/O I P0[4] Analog column mux input. 8 Power Vdd Supply voltage. Figure 3. 8-Pin EZ-Color Device A, I, P0[5] A, I, P0[3] I2C SCL, P1[1] Vss 1 8 2 7 SOIC 3 6 4 5 Vdd P0[4], A, I P0[2], A, I P1[0], I2C SDA LEGEND: A = Analog, I = Input, and O = Output. 16-Pin Part Pinout Table 4. 16-Pin Part Pinout (SOIC) Type Pin No. Digital Analog 1 I/O I 2 I/O I 3 I/O I 4 I/O I 5 Power 6 7 8 9 10 11 Power I/O Power I/O I/O I/O 12 13 14 15 16 I/O I/O I/O I/O Power I I I I Name P0[7] P0[5] P0[3] P0[1] SMP Description Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Switch Mode Pump (SMP) connection to required external components. Vss Ground connection. P1[1] I2C Serial Clock (SCL), ISSP-SCLK. Vss Ground connection. P1[0] I2C Serial Data (SDA), ISSP-SDATA. P1[2] P1[4] Optional External Clock Input (EXTCLK). P0[0] Analog column mux input. P0[2] Analog column mux input. P0[4] Analog column mux input. P0[6] Analog column mux input. Vdd Supply voltage. Figure 4. 16-Pin EZ-Color Device A, I, P0[7] A, I, P0[5] A, I, P0[3] A, I, P0[1] SMP Vss I2C SCL, P1[1] Vss 1 2 3 4 5 6 7 8 SOIC 16 15 14 13 12 11 10 9 Vdd P0[6], A, I P0[4], A, I P0[2], A, I P0[0], A, I P1[4], EXTCLK P1[2] P1[0], I2C SDA LEGEND A = Analog, I = Input, and O = Output. Document Number: 001-13704 Rev. *C Page 8 of 39 [+] Feedback CY8CLED02 24-Pin Part Pinout Table 5. 24-Pin Part Pinout (QFN)[2] 13 14 15 16 17 18 19 20 21 22 23 24 Power I/O I/O I/O I/O P1[6] XRES Input I/O I/O I/O I/O I I I I Power Power I/O I/O I/O I I I NC P0[0] P0[2] P0[4] P0[6] Vdd Vss P0[7] P0[5] P0[3] Optional External Clock Input (EXTCLK). Vdd P0[6], A, I 19 20 21 22 P0[3], A, I P0[5], A, I P0[7], A, I Vss 23 1 18 17 2 QFN 3 16 14 6 13 12 5 11 (Top View ) 15 9 4 10 I2C Serial Clock (SCL), ISSP-SCLK[1]. No connection. Ground connection. I2C Serial Data (SDA), ISSP-SDATA[1]. A, I, P0[1] SMP Vss I2C SCL, P1[7] I2C SDA, P1[5] P1[3] 24 Vss P1[7] P1[5] P1[3] P1[1] NC Vss P1[0] P1[2] P1[4] 8 Power I/O I/O I/O I/O Analog column mux input. Switch Mode Pump (SMP) connection to required external components. Ground connection. I2C Serial Clock (SCL). I2C Serial Data (SDA). Figure 5. 24-Pin EZ-Color Device 7 3 4 5 6 7 8 9 10 11 12 Description P0[4], A, I P0[2], A, I P0[0], A, I NC XRES P1[6] I2C SCL, P1[1] NC Vss I2C SDA, P1[0] P1[2] EXTCLK,P1[4] Type Pin No. Digital Analog Name 1 I/O I P0[1] 2 Power SMP Active high external reset with internal pull down. No connection. Analog column mux input. Analog column mux input. Analog column mux input. Analog column mux input. Supply voltage. Ground connection. Analog column mux input. Analog column mux input. Analog column mux input. LEGEND A = Analog, I = Input, and O = Output. Notes 1. These are the ISSP pins, which are not High Z at POR (Power On Reset). 2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 001-13704 Rev. *C Page 9 of 39 [+] Feedback CY8CLED02 Register Reference Register Conventions Register Mapping Tables This section lists the registers of the CY8CLED02 EZ-Color device. The device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. The register conventions specific to this section are listed in the following table. Note In the following register mapping tables, blank fields are Reserved and should not be accessed. Table 6. Register Conventions Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Table 7. Register Map Bank 0: User Space C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 I2C_CFG D6 I2C_SCR D7 I2C_DR D8 I2C_MSCR D9 INT_CLR0 DA INT_CLR1 DB DC INT_CLR3 DD INT_MSK3 DE DF INT_MSK0 E0 INT_MSK1 E1 Access RW Addr (0,Hex) RW Name Document Number: 001-13704 Rev. *C ASE11CR0 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 Access Blank fields are Reserved and should not be accessed. ASE10CR0 RW Addr (0,Hex) AMX_IN Name # W 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 Access RW RW RW RW RW RW RW RW Addr (0,Hex) Name 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00DR0 20 DBB00DR1 21 Access Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 RW # RW # RW RW RW RW RW RW # Access is bit specific. Page 10 of 39 [+] Feedback CY8CLED02 Table 7. Register Map Bank 0: User Space (continued) RW # # RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 INT_VC RES_WDT RW RW RW RW RW RW RW E2 E3 E4 E5 DEC_CR0 E6 DEC_CR1 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 CPU_F F7 F8 F9 FA FB FC FD CPU_SCR1 FE CPU_SCR0 FF Access ACE01CR1 ACE01CR2 # Addr (0,Hex) ACE00CR1 ACE00CR2 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Name TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 RW Access ADC0_CR ADC1_CR Addr (0,Hex) CMP_CR1 Name CMP_CR0 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access PWM_CR Addr (0,Hex) RW # # W RW # # W RW # # W RW # Name 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access Addr (0,Hex) Name DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 RC W RW RW RL # # # Access is bit specific. Register Map Bank 1 Table 8. Register Map Bank 1: Configuration Space PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 RW RW RW RW RW RW RW 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D Blank fields are Reserved and should not be accessed. Document Number: 001-13704 Rev. *C 80 RW RW Access ASE10CR 0 Addr (1,Hex) 40 Name RW Access Addr (1,Hex) Name Access Addr (1,Hex) Name Access Addr (1,Hex) Name PRT0DM0 00 C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD # Access is bit specific. Page 11 of 39 [+] Feedback CY8CLED02 Table 8. Register Map Bank 1: Configuration Space (continued) Blank fields are Reserved and should not be accessed. Document Number: 001-13704 Rev. *C RW RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IMO_TR ILO_TR BDG_TR ECO_TR RW RW RW RW RW RW RW CPU_F FLS_PR1 CPU_SCR1 CPU_SCR0 CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access ACE01CR1 ACE01CR2 RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Addr (1,Hex) ACE00CR1 ACE00CR2 RW RW RW RW RW Name CLK_CR3 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 RW RW 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access RW RW RW RW RW RW RW RW Addr (1,Hex) RW RW RW Name AMD_CR1 ALT_CR0 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN Addr (1,Hex) DCB03FN DCB03IN DCB03OU RW RW RW Name DCB02FN DCB02IN DCB02OU Access DBB01FN DBB01IN DBB01OU Addr (1,Hex) Name DBB00FN DBB00IN DBB00OU 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW R RW RW W W RW W RL RW # # # Access is bit specific. Page 12 of 39 [+] Feedback CY8CLED02 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CLED02 EZ-Color device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/ez-color. Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Refer to Table 22 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 6. Voltage versus CPU Frequency, and Voltage versus IMO Frequency 5.25 SLIMO Mode = 0 5.25 SLIMO Mode=1 4.75 Vdd Voltage Vdd Voltage lid g Va ratin n pe io O Reg 4.75 3.60 3.00 3.00 2.40 2.40 93 kHz 12 MHz 3 MHz 24 MHz SLIMO Mode=0 SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1 93 kHz 6 MHz 12 MHz 24 MHz IMOFrequency CPU Frequency The following table lists the units of measure that are used in this data sheet. Table 9. Units of Measure Symbol oC dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Document Number: 001-13704 Rev. *C Symbol μW mA ms mV nA ns nV Ω pA pF pp ppm ps sps σ V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Page 13 of 39 [+] Feedback CY8CLED02 Absolute Maximum Ratings Table 10. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature TA Vdd VIO VIOZ IMIO ESD LU Min -55 Ambient Temperature with Power Applied -40 Supply Voltage on Vdd Relative to Vss -0.5 DC Input Voltage Vss - 0.5 DC Voltage Applied to Tri-state Vss - 0.5 Maximum Current into any Port Pin -25 Electro Static Discharge Voltage 2000 Latch up Current – Typ 25 Max +100 Units oC – – – – – – – +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 – 200 oC V V V mA V mA Typ – – Max +85 +100 Units oC oC Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC will degrade reliability. Human Body Model ESD. Operating Temperature Table 11. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Document Number: 001-13704 Rev. *C Min -40 -40 Notes The temperature rise from ambient to junction is package specific. See “Thermal Impedances” on page 33. The user must limit the power consumption to comply with this requirement. Page 14 of 39 [+] Feedback CY8CLED02 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 12. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage Min 2.40 Typ – Max 5.25 Units Notes V See DC POR and LVD specifications, Table 20 on page 20. mA Conditions are Vdd = 5.0V, 25oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. mA Conditions are Vdd = 3.3V, 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. mA Conditions are Vdd = 2.55V, 25oC, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz. μA Vdd = 2.55V, 0oC to 40oC. IDD Supply Current, IMO = 24 MHz – 3 4 IDD3 Supply Current, IMO = 6 MHz – 1.2 2 IDD27 Supply Current, IMO = 6 MHz – 1.1 1.5 ISB27 – 2.6 4 – 2.8 5 μA Vdd = 3.3V, -40oC ≤ TA ≤ 85oC. VREF Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference Voltage (Bandgap) 1.28 1.30 1.32 V VREF27 Reference Voltage (Bandgap) 1.16 1.30 1.330 V Trimmed for appropriate Vdd. Vdd = 3.0V to 5.25V. Trimmed for appropriate Vdd. Vdd = 2.4V to 3.0V. AGND Analog Ground VREF - 0.003 VREF VREF + 0.003 V ISB Document Number: 001-13704 Rev. *C Page 15 of 39 [+] Feedback CY8CLED02 DC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 13. 5V and 3.3V DC GPIO Specifications Symbol Description RPU Pull up Resistor Pull down Resistor RPD High Output Level VOH Min 4 4 Vdd - 1.0 Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V VOL Low Output Level – – 0.75 V IOH High Level Source Current 10 – – mA IOL Low Level Sink Current 25 – – mA VIL VIH VH IIL CIN Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input – 2.1 – – – – – 60 1 3.5 0.8 – – 10 V V mV nA pF COUT Capacitive Load on Pins as Output – 3.5 10 pF Document Number: 001-13704 Rev. *C Notes IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. VOH = Vdd-1.0V. See the limitations of the total current in the Note for VOH. VOL = 0.75V. See the limitations of the total current in the Note for VOL. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Page 16 of 39 [+] Feedback CY8CLED02 The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 2.7V at 25°C and are for design guidance only. Table 14. 2.7V DC GPIO Specifications Symbol RPU RPD VOH Description Pull up Resistor Pull down Resistor High Output Level Min 4 4 Vdd - 0.4 Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V VOL Low Output Level – – 0.75 V IOH High Level Source Current 2.5 – – mA IOL Low Level Sink Current 10 – – mA VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output – 2.0 – – – – – – 60 1 3.5 3.5 0.75 – – – 10 10 V V mV nA pF pF Notes IOH = 2.5 mA (6.25 typical), Vdd = 2.4 to 3.0V (16 mA maximum, 50 mA typical combined IOH budget). IOL = 10 mA, Vdd = 2.4 to 3.0V (90 mA maximum combined IOL budget). VOH = Vdd-0.4V. See the limitations of the total current in the Note for VOH. VOL = 0.75V. See the limitations of the total current in the Note for VOL. Vdd = 2.4 to 3.0. Vdd = 2.4 to 3.0. Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. DC Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 15. 5V DC Amplifier Specifications Symbol Description VOSOA Input Offset Voltage (absolute value) TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog IEBOA Pins) CINOA Input Capacitance (Port 0 Analog Pins) VCMOA Common Mode Voltage Range Open Loop Gain GOLOA Amplifier Supply Current ISOA Min – – – Typ 2.5 10 200 Max 15 – – Units mV μV/oC pA – 4.5 9.5 pF 0.0 80 – – – 10 Vdd - 1 – 30 V dB μA Description Min Typ Max Units Input Offset Voltage (absolute value) Notes Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. Table 16. 3.3V DC Amplifier Specifications Symbol VOSOA Notes – 2.5 15 mV TCVOSOA Average Input Offset Voltage Drift – 10 – μV/oC IEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA. CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC. Document Number: 001-13704 Rev. *C Page 17 of 39 [+] Feedback CY8CLED02 Table 16. 3.3V DC Amplifier Specifications (continued) VCMOA Common Mode Voltage Range 0 – Vdd - 1 V GOLOA Open Loop Gain 80 – – dB ISOA Amplifier Supply Current – 10 30 μA Table 17. 2.7V DC Amplifier Specifications Symbol Min Typ Max Units – 2.5 15 mV TCVOSOA Average Input Offset Voltage Drift – 10 – μV/oC IEBOA Input Leakage Current (Port 0 Analog Pins) – 200 – pA Gross tested to 1 μA. CINOA Input Capacitance (Port 0 Analog Pins) – 4.5 9.5 pF Package and pin dependent. Temp = 25oC. VCMOA Common Mode Voltage Range 0 – Vdd - 1 V GOLOA Open Loop Gain 80 – – dB ISOA Amplifier Supply Current – 10 30 μA VOSOA Description Input Offset Voltage (absolute value) Notes DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 18. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Document Number: 001-13704 Rev. *C Min 0.2 Typ – Max Vdd - 1 Units V – – 10 2.5 40 30 μA mV Notes Page 18 of 39 [+] Feedback CY8CLED02 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 19. DC Switch Mode Pump (SMP) Specifications Symbol Description Min Typ Max Units Notes VPUMP5V 5V Output Voltage from Pump 4.75 5.0 5.25 V Configuration of footnote.[3] Average, neglecting ripple. SMP trip voltage is set to 5.0V. VPUMP3V 3.3V Output Voltage from Pump 3.00 3.25 3.60 V Configuration of footnote.[3] Average, neglecting ripple. SMP trip voltage is set to 3.25V. VPUMP2V 2.6V Output Voltage from Pump 2.45 2.55 2.80 V Configuration of footnote.[3] Average, neglecting ripple. SMP trip voltage is set to 2.55V. IPUMP Available Output Current VBAT = 1.8V, VPUMP = 5.0V VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.3V, VPUMP = 2.55V VBAT5V Configuration of footnote.[3] SMP trip voltage is set to 5.0V. SMP trip voltage is set to 3.25V. SMP trip voltage is set to 2.55V. 5 8 8 – – – – – – mA mA mA Input Voltage Range from Battery 1.8 – 5.0 V Configuration of footnote.[3] SMP trip voltage is set to 5.0V. VBAT3V Input Voltage Range from Battery 1.0 – 3.3 V Configuration of footnote.[3] SMP trip voltage is set to 3.25V. VBAT2V Input Voltage Range from Battery 1.0 – 2.8 V Configuration of footnote.[3] SMP trip voltage is set to 2.55V. VBATSTART Minimum Input Voltage from Battery to Start Pump 1.2 – – V Configuration of footnote.[3] 0oC ≤ TA ≤ 100. 1.25V at TA = -40oC. ΔVPUMP_Line Line Regulation (over Vi range) – 5 – %VO Configuration of footnote.[3] VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 20 on page 20. ΔVPUMP_Load Load Regulation – 5 – %VO Configuration of footnote.[3] VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 20 on page 20. ΔVPUMP_Ripple Output Voltage Ripple (depends on cap/load) – 100 – mVpp Configuration of footnote.[3] Load is 5 mA. E3 Efficiency 35 50 – % Configuration of footnote.[3] Load is 5 mA. SMP trip voltage is set to 3.25V. E2 Efficiency 35 80 – % For I load = 1mA, VPUMP = 2.55V, VBAT = 1.3V, 10 µH inductor, 1 µF capacitor, and Schottky diode. FPUMP Switching Frequency – 1.3 – MHz DCPUMP Switching Duty Cycle – 50 – % Note 3. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 7 on page 20. Document Number: 001-13704 Rev. *C Page 19 of 39 [+] Feedback CY8CLED02 Figure 7. Basic Switch Mode Pump Circuit D1 Vdd L1 VBAT + VPUMP C1 SMP Battery EZ-Color Vss DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 20. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ Max Units – 2.36 2.82 4.55 2.40 2.95 4.70 V V V 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.51[4] 2.99[5] 3.09 3.20 4.55 4.75 4.83 4.95 V V V V V V V V 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.62[6] 3.09 3.16 3.32[7] 4.74 4.83 4.92 5.12 V V V V V V V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. Notes 4. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 5. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. 6. Always greater than 50 mV above VLVD0. 7. Always greater than 50 mV above VLVD3. Document Number: 001-13704 Rev. *C Page 20 of 39 [+] Feedback CY8CLED02 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 21. DC Programming Specifications Symbol VddIWRITE IDDP VILP FlashENPB Description Supply Voltage for Flash Write Operations Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) FlashENT Flash Endurance (total)[9] FlashDR Flash Data Retention VIHP IILP IIHP VOLV VOHV Min 2.70 – – Typ – 5 – Max – 25 0.8 Units V mA V 2.2 – – V – – 0.2 mA – – 1.5 mA – – Vss + 0.75 V Vdd - 1.0 – Vdd V 50,000[8] – – – 1,800,000 –0 –0 –0 10 – – Years 0 Notes Driving internal pull down resistor. Driving internal pull down resistor. Erase/write cycles per block. Erase/write cycles.0 Notes 8. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 2.4V to 3.0V, 3.0V to 3.6V, and 4.75V to 5.25V. 9. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-13704 Rev. *C Page 21 of 39 [+] Feedback CY8CLED02 AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 22. 5V and 3.3V AC Chip-Level Specifications Symbol FIMO24 Description Internal Main Oscillator Frequency for 24 MHz Min 23.4 Typ 24 Max 24.610,11,12 Units MHz FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.5 6 6.510,11,12 MHz FCPU1 FCPU2 FBLK5 CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency0(5V Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency Internal Low Speed Oscillator Untrimmed Frequency 0.093 0.093 0 24 12 48 24.610,11 12.311,12 49.210,11,13 MHz MHz MHz 0 24 24.611,13 MHz 15 5 32 – 64 – kHz kHz DCILO Jitter32k Jitter32k TXRST DC24M Step24M Fout48M Internal Low Speed Oscillator Duty Cycle 32 kHz RMS Period Jitter 32 kHz Peak-to-Peak Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 20 – – 10 40 – 46.8 50 100 1400 – 50 50 48.0 80 200 – – 60 – 49.29,11 % ns ns μs % kHz MHz Jitter24M1 FMAX 24 MHz Peak-to-Peak Period Jitter (IMO) Maximum frequency of signal on row input or row output. Power Supply Slew Rate – – 300 – 12.3 ps MHz – – 250 V/ms Time from End of POR to CPU Executing Code – 16 100 ms FBLK33 F32K1 F32K_U SRPOWER_ Notes Trimmed for 5V or 3.3V operation using factory trim values. See Figure 6 on page 13. SLIMO mode = 0. Trimmed for 3.3V operation using factory trim values. See Figure 6 on page 13. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC Digital Block Specifications below. After a reset and before the m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this. Trimmed. Utilizing factory trim values. Vdd slew rate during power up. UP TPOWERUP Document Number: 001-13704 Rev. *C Power up from 0V. See the System Resets section of the PSoC Technical Reference Manual. Page 22 of 39 [+] Feedback CY8CLED02 Table 23. 2.7V AC Chip-Level Specifications Symbol FIMO12 Description Internal Main Oscillator Frequency for 12 MHz Min 11.5 Typ 120 Max 12.710,11,12 Units MHz FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.5 6 6.510,11,12 MHz FCPU1 FBLK27 CPU Frequency (2.7V Nominal) Digital PSoC Block Frequency (2.7V Nominal) Internal Low Speed Oscillator Frequency Internal Low Speed Oscillator Untrimmed Frequency 0.093 0 3 12 3.1510,11 12.510,11,12 MHz MHz 8 5 32 – 96 – kHz kHz Internal Low Speed Oscillator Duty Cycle 32 kHz RMS Period Jitter 32 kHz Peak-to-Peak Period Jitter External Reset Pulse Width Maximum frequency of signal on row input or row output. Power Supply Slew Rate 20 – – 10 – 50 150 1400 – – 80 200 – – 12.3 % ns ns μs MHz – – 250 V/ms Time from End of POR to CPU Executing Code – 16 100 ms F32K1 F32K_U DCILO Jitter32k Jitter32k TXRST FMAX SRPOWER_ Notes Trimmed for 2.7V operation using factory trim values. See Figure 6 on page 13. SLIMO mode = 1. Trimmed for 2.7V operation using factory trim values. See Figure 6 on page 13. SLIMO mode = 1. 24 MHz only for SLIMO mode = 0. Refer to the AC Digital Block Specifications below. After a reset and before the m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this. Vdd slew rate during power up. UP TPOWERUP Power up from 0V. See the System Resets section of the PSoC Technical Reference Manual. Figure 8. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F24M Figure 9. 32 kHz Period Jitter (ILO) Timing Diagram Jitter32k F32K1 Notes 10. 4.75V < Vdd < 5.25V. 11. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 12. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. 13. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-13704 Rev. *C Page 23 of 39 [+] Feedback CY8CLED02 AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 24. 5V and 3.3V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12 18 18 – – Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Min 0 6 6 18 18 Typ – – – 40 40 Max 3 50 50 120 120 Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Table 25. 2.7V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Figure 10. GPIO Timing Diagram 90% GPIO Pin 10% TRiseF TRiseS TFallF TFallS AC Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only.Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 26. 5V and 3.3V AC Amplifier Specifications Symbol TCOMP1 TCOMP2 Description Comparator Mode Response Time, 50 mVpp Signal Centered on Reference Comparator Mode Response Time, 2.5V Input, 0.5V Overdrive Document Number: 001-13704 Rev. *C Min Typ Max 100 Units ns 300 ns Notes Page 24 of 39 [+] Feedback CY8CLED02 Table 27. 2.7V AC Amplifier Specifications Symbol TCOMP1 TCOMP2 Description Comparator Mode Response Time, 50 mVpp Signal Centered on Ref Comparator Mode Response Time, 1.5V Input, 0.5V Overdrive Min Typ Max 600 Units ns 300 ns Notes AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 28. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Document Number: 001-13704 Rev. *C Min – Typ – Max 50 Units μs Notes ≥ 50 mV overdrive comparator reference set within VREFLPC. Page 25 of 39 [+] Feedback CY8CLED02 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 29. 5V and 3.3V AC Digital Block Specifications Function All Functions Timer Counter Dead Band CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Transmitter Receiver Description Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With or Without Capture Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency Maximum Input Clock Frequency Min Typ Max 49.2 Units MHz Notes 4.75V < Vdd < 5.25V. 24.6 MHz 3.0V < Vdd < 4.75V. 50[14] – – – – – – 49.2 24.6 ns MHz MHz 4.75V < Vdd < 5.25V. 50 – – – – – – 49.2 24.6 ns MHz MHz 4.75V < Vdd < 5.25V. 20 50 50 – – – – – – – – – – 49.2 49.2 ns ns ns MHz MHz Maximum Input Clock Frequency – – 24.6 MHz Maximum Input Clock Frequency – – 8.2 MHz Maximum Input Clock Frequency – Width of SS_ Negated Between Trans- 50 missions Maximum Input Clock Frequency – – – 4.1 – MHz ns – 24.6 MHz Maximum Input Clock Frequency with – Vdd ≥ 4.75V, 2 Stop Bits – 49.2 MHz Maximum Input Clock Frequency – – 24.6 MHz Maximum Input Clock Frequency with – Vdd ≥ 4.75V, 2 Stop Bits – 49.2 MHz 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Maximum data rate at 4.1 MHz due to 2 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Note 14. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-13704 Rev. *C Page 26 of 39 [+] Feedback CY8CLED02 Table 30. 2.7V AC Digital Block Specifications Function Description All Functions Maximum Block Clocking Frequency Timer Capture Pulse Width Counter Dead Band Min Typ Max Units 12.7 MHz 100[15] – – ns Maximum Frequency, With or Without Capture – – 12.7 MHz Enable Pulse Width 100 – – ns Maximum Frequency, No Enable Input – – 12.7 MHz Maximum Frequency, Enable Input – – 12.7 MHz Asynchronous Restart Mode 20 – – ns Synchronous Restart Mode 100 – – ns Disable Mode 100 – – ns Notes 2.4V < Vdd < 3.0V. Kill Pulse Width: Maximum Frequency – – 12.7 MHz CRCPRS (PRS Mode) Maximum Input Clock Frequency – – 12.7 MHz CRCPRS (CRC Mode) Maximum Input Clock Frequency – – 12.7 MHz SPIM Maximum Input Clock Frequency – – 6.35 MHz SPIS Maximum Input Clock Frequency – – 4.1 MHz Width of SS_ Negated Between Transmissions Maximum data rate at 3.17 MHz due to 2 x over clocking. 100 – – ns Transmitter Maximum Input Clock Frequency – – 12.7 MHz Maximum data rate at 1.59 MHz due to 8 x over clocking. Receiver – – 12.7 MHz Maximum data rate at 1.59 MHz due to 8 x over clocking. Maximum Input Clock Frequency AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 31. 5V AC External Clock SpecificationsC Symbol Description Min Typ Max Units FOSCEXT Frequency 0.093 – 24.6 MHz – High Period 20.6 – 5300 ns – Low Period 20.6 – – ns – Power Up IMO to Switch 150 – – μs Notes Note 15. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document Number: 001-13704 Rev. *C Page 27 of 39 [+] Feedback CY8CLED02 Table 32. 3.3V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT Frequency with CPU Clock divide by 1 0.093 – 12.3 MHz Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 – 24.6 MHz If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. – High Period with CPU Clock divide by 1 41.7 – 5300 ns – Low Period with CPU Clock divide by 1 41.7 – – ns – Power Up IMO to Switch 150 – – μs Table 33. 2.7V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT Frequency with CPU Clock divide by 1 0.093 – 6.060 MHz Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.186 – 12.12 MHz If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. – High Period with CPU Clock divide by 1 83.4 – 5300 ns – Low Period with CPU Clock divide by 1 83.4 – – ns – Power Up IMO to Switch 150 – – μs Document Number: 001-13704 Rev. *C Page 28 of 39 [+] Feedback CY8CLED02 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 34. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK3 TDSCLK2 TERASEA Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Flash Erase Time (Bulk) Min 1 1 40 40 0 – – – – – Typ – – – – – 10 80 – – 20 Max 20 20 – – 8 – – 50 70 – Units ns ns ns ns MHz ms ms ns ns ms – – 180[16] ms 3.0 ≤ Vdd ≤ 3.6 2.4 ≤ Vdd ≤ 3.0 Erase all blocks and protection fields at once. 0°C ≤ TJ ≤ 100°C – – 360[16] ms -40°C ≤ TJ ≤ 0°C LL TPROGRA Flash Block Erase + Flash Block Write Time Notes M_HOT TPROGRA Flash Block Erase + Flash Block Write Time M_COLD AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C and are for design guidance only. Table 35. AC Characteristics of the I2C SDA and SCL Pins for Vcc . 3.0V Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Standard-Mode Fast-Mode Min Max Min Max SCL Clock Frequency 0 100 0 400 Hold Time (repeated) START Condition. After 4.0 – 0.6 – this period, the first clock pulse is generated. LOW Period of the SCL Clock 4.7 – 1.3 – HIGH Period of the SCL Clock 4.0 – 0.6 – Set-up Time for a Repeated START Condition 4.7 – 0.6 – Data Hold Time 0 – 0 – Data Set-up Time0 2500 –0 100[17] –0 Set-up Time for STOP Condition 4.0 – 0.6 – Bus Free Time Between a STOP and START 4.7 – 1.3 – Condition Pulse Width of spikes are suppressed by the – – 0 50 input filter. Description Units Notes kHz μs μs μs μs μs ns0 μs μs ns Note 16. For the full industrial range, the user must employ a Temperature Sensor User Module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-13704 Rev. *C Page 29 of 39 [+] Feedback CY8CLED02 Table 36. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast-Mode not Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Standard-Mode Fast-Mode Min Max Min Max SCL Clock Frequency 0 100 – – Hold Time (repeated) START Condition. After 4.0 – – – this period, the first clock pulse is generated. LOW Period of the SCL Clock 4.7 – – – HIGH Period of the SCL Clock 4.0 – – – Set-up Time for a Repeated START Condition 4.7 – – – Data Hold Time 0 – – – Data Set-up Time 250 – – – Set-up Time for STOP Condition 4.0 – – – Bus Free Time Between a STOP and START 4.7 – – – Condition Pulse Width of spikes are suppressed by the – – – – input filter. Description Units Notes kHz μs μs μs μs μs ns μs μs ns Figure 11. Definition for Timing for Fast-/Standard-Mode on the I2C Bus SDA TLOWI2C TSPI2C TSUDATI2C THDSTAI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Note 17. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-13704 Rev. *C Page 30 of 39 [+] Feedback CY8CLED02 Packaging Information Packaging Dimensions This section illustrates the packaging specifications for the CY8CLED02 EZ-Color device, along with the thermal impedances for each package and minimum solder reflow peak temperature. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 12. 8-Pin (150-Mil) SOIC PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] Document Number: 001-13704 Rev. *C 0°~8° 0.0075[0.190] 0.0098[0.249] 0.016[0.406] 0.035[0.889] 51-85066 *C Page 31 of 39 [+] Feedback CY8CLED02 Figure 13. 16-Pin (150-Mil) SOIC 51-85068 *B 51-85068 *C Document Number: 001-13704 Rev. *C Page 32 of 39 [+] Feedback CY8CLED02 Figure 14. 24-Pin (4x4) QFN 51-85203 *B Important Note For information about the preferred dimensions for mounting the QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Important Note Pinned vias for thermal conduction are not required for the low-power 24-, 32-, and 48-pin QFN EZ-Color devices. Thermal Impedances Solder Reflow Peak Temperature Table 37. Thermal Impedances per Package Following is the minimum solder reflow peak temperature to achieve good solderability. Package Typical θJA[18] 8 SOIC 186 oC/W 16 SOIC 125 oC/W Package Minimum Peak Temperature[20] Maximum Peak Temperature 24 QFN[19] 40 oC/W 8 SOIC 240oC 260oC 16 SOIC 240oC 260oC 24 QFN 240oC 260oC Table 38. Solder Reflow Peak Temperature Notes 18. TJ = TA + POWER x θJA 19. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. 20. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications Document Number: 001-13704 Rev. *C Page 33 of 39 [+] Feedback CY8CLED02 Development Tool Selection This section presents the development tools available for all current PSoC based devices including the CY8CLED02 EZ-Color family. Software Tools PSoC Designer At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free C compiler. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. CY3261A-RGB EZ-Color RGB Kit The CY3261A-RGB board is a preprogrammed HB LED color mix board with seven pre-set colors using the CY8CLED16 EZ-Color HB LED Controller. The board is accompanied by a CD containing the color selector software application, PSoC Designer, PSoC Programmer, and a suite of documents, schematics, and firmware examples. The color selector software application can be installed on a host PC and is used to control the EZ-Color HB LED controller using the included USB cable. The application enables you to select colors via a CIE 1931 chart or by entering coordinates. The kit includes: ■ Training Board (CY8CLED16) ■ One mini-A to mini-B USB Cable ■ ■ PSoC Designer CD-ROM Design Files and Application Installation CD-ROM To program and tune this kit via PSoC Designer you must use a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit. CY3263-ColorLock Evaluation Kit Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC based devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the device on the target board and performs full speed (24 MHz) operation. The CY3263-ColorLock evaluation board demonstrates the ability of the EZ-Color device to use real-time optical feedback to control three primary, high brightness LEDs and create accurate, mixed-color output. The kit includes: ■ CY3263-ColorLock Evaluation Board ■ Tools CD, which includes: ❐ PSoC Programmer ❐ .NET Framework 2.0 (for Windows 2000 and Windows XP) ❐ PSoC Designer ❐ ColorLock Express Pack ❐ CY3263-ColorLock EZ-Color Kit CD ❐ ColorLock Monitor Application ❐ Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) ❐ Firmware ■ Retractable USB Cable (A to Mini-B) ■ PSoC MiniProg Programmer ■ Power Supply Adapter I2C to USB Bridge The I2C to USB Bridge is a quick and easy link from any design or application’s I2C bus to a PC via USB for design testing, debugging and communication. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. Document Number: 001-13704 Rev. *C Page 34 of 39 [+] Feedback CY8CLED02 CY3265-RGB EZ-Color Evaluation Kit CY3210-PSoCEval1 The CY3265-RGB evaluation board demonstrates the ability of the EZ-Color device to use real-time temperature feedback to control three primary, high brightness LEDs and create accurate, mixed-color output. There are three variations of the kit available, depending on the LED manufacturer of the LEDs on the board: CY3265C-RGB (Cree LEDs), CY3265N-RGB (Nichia LEDs), or CY3265O-RGB (OSRAM LEDs). The kit includes: The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ CY3265C-RGB Evaluation Board ■ Tools CD, which includes: ❐ PSoC Programmer ❐ PSoC Designer ❐ .NET Framework 2.0 (Windows XP 32 bit) ■ Evaluation Board with LCD Module ■ MiniProg Programming Unit ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable ■ Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) Firmware ■ Blue PCA Enclosure/Case Device Programmers ■ 12V 1A Power Supply All device programmers can be purchased from the Cypress Online Store. ■ Retractable USB Cable (A to Mini-B) ■ PSoC MiniProg Programmer ■ Quick Start Guide CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC based devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ Modular Programmer Base ■ 3 Programming Module Cards ■ MiniProg Programming Unit ■ MiniProg Programming Unit ■ PSoC Designer Software CD ■ MiniEval Socket Programming and Evaluation Board ■ Getting Started Guide ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample ■ USB 2.0 Cable ■ 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample CY3207ISSP In-System Serial Programmer (ISSP) ■ PSoC Designer Software CD ■ Getting Started Guide ■ USB 2.0 Cable The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: Document Number: 001-13704 Rev. *C ■ CY3207 Programmer Unit ■ PSoC ISSP Software CD ■ 110 ~ 240V Power Supply, Euro-Plug Adapter ■ USB 2.0 Cable Page 35 of 39 [+] Feedback CY8CLED02 Accessories (Emulation and Programming) Table 39. Emulation and Programming Accessories Part # Pin Package Flex-Pod Kit[21] Foot Kit[22] CY8CLED02-8SXI 8 SOIC CY3250-LED02 CY3250-8SOIC-FK CY8CLED02-16SXI 16 SOIC CY3250-LED02 CY3250-16SOIC-FK CY8CLED02-24LFXI 24 QFN CY3250-LED02QFN CY3250-24QFN-FK Adapter[23] Adapters can be found at http://www.emulation.com. Third Party Tools Build a PSoC Emulator into Your Board Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Design Support >> Development Kits/Boards. For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323”. Table 40 on page 37 lists the CY8CLED08 EZ-Color devices’ key package features and ordering codes. Notes 21. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 22. Foot kit includes surface mount feet that can be soldered to the target PCB. 23. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-13704 Rev. *C Page 36 of 39 [+] Feedback CY8CLED02 Ordering Information Key Device Features The following table lists the CY8CLED02 EZ-Color devices’ key package features and ordering codes. RAM (Bytes) Switch Mode Pump Temperature Range Digital Blocks Analog Blocks Digital I/O Pins Analog Inputs Analog Outputs XRES Pin 8 Pin (150-Mil) SOIC CY8CLED02-8SXI 4K 256 No -40°C to +85°C 4 4 6 4 0 No 8 Pin (150-Mil) SOIC (Tape and Reel) CY8CLED02-8SXIT 4K 256 No -40°C to +85°C 4 4 6 4 0 No 16 Pin (150-Mil) SOIC CY8CLED02-16SXI 4K 256 Yes -40°C to +85°C 4 4 12 8 0 No 16 Pin (150-Mil) SOIC (Tape and Reel) CY8CLED02-16SXIT 4K 256 Yes -40°C to +85°C 4 4 12 8 0 No 24 Pin (4x4) QFN CY8CLED02-24LFXI 4K 256 Yes -40°C to +85°C 4 4 16 8 0 Yes 24 Pin (4x4) QFN (Tape and Reel) CY8CLED02-24LFXIT 4K 256 Yes -40°C to +85°C 4 4 16 8 0 Yes Package Ordering Code Flash (Bytes) Table 40. Device Key Features and Ordering Information Ordering Code Definitions CY 8 C LED xx - xx xxxx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Pin Count Part Number LED Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-13704 Rev. *C Page 37 of 39 [+] Feedback CY8CLED02 Document History Page Document Title: CY8CLED02 EZ-ColorTM HB LED Controller Document Number: 001-13704 Revision ECN # Submission Date ** 1383443 See ECN *A 2732564 07/09/2009 CGX Converted from Preliminary to Final *B 2794355 10/28/2009 XBM Added “Contents” on page 2 Updated “Development Tools” on page 6. Corrected FCPU1 and FCPU2 parameters in Table 22, “5V and 3.3V AC Chip-Level Specifications,” on page 22 and Table 23, “2.7V AC Chip-Level Specifications,” on page 23 *C 2850593 01/14/2010 FRE Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Modified FIMO6 and TWRITE specifications. Replaced TRAMP (time) specification with SRPOWER_UP (slew rate) specification. Added note to Flash Endurance specification. Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and TPROGRAM_COLD specifications. Corrected the Pod Kit part numbers. Updated Development Tool Selection. Updated copyright and Sales, Solutions, and Legal Information URLs. Updated 24-Pin QFN package diagram. Document Number: 001-13704 Rev. *C Origin of Change Description of Change SFVTMP3/AESA New document Page 38 of 39 [+] Feedback CY8CLED02 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2007-2009, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-13704 Rev. *C Revised January 15, 2010 Page 39 of 39 PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback