Maxim DS26303GN-75 3.3v, e1/t1/j1, short-haul, octal line interface unit Datasheet

DS26303
3.3V, E1/T1/J1, Short-Haul,
Octal Line Interface Unit
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS26303 is an 8-channel short-haul line
interface unit (LIU) that supports E1/T1/J1 from a
single 3.3V power supply. A wide variety of
applications are supported through internal
termination or external termination. A single bill of
material can support E1/T1/J1 with minimum external
components. Redundancy is supported through
nonintrusive monitoring, optimal high-impedance
modes, and configurable 1:1 or 1+1 backup
enhancements. An on-chip synthesizer generates the
E1/T1/J1 clock rates by a single master clock input of
various frequencies. Two clock output references are
also offered.
§
APPLICATIONS
T1 Digital Cross-Connects
ATM and Frame Relay Equipment
Wireless Base Stations
ISDN Primary Rate Interface
E1/T1/J1 Multiplexer and Channel Banks
E1/T1/J1 LAN/WAN Routers
Software Control,
Hardware Control
and JTAG
§
MODESEL
Receiver
RPOS
RNEG
RCLK
Transmitter
TPOS
TNEG
TCLK
RRING
TTTIP
§
§
§
§
§
§
RLOS
RTIP
§
§
§
§
FUNCTIONAL DIAGRAM
Jtag
§
§
TRING
§
§
§
8 Complete E1, T1, or J1 Short Haul Line
Interface Units
Independent E1, T1, or J1 Selections
Internal Software-Selectable Transmit and
Receive-Side Termination
Crystal-Less Jitter Attenuator
Selectable Single-Rail and Dual-Rail Mode and
AMI or HDB3/ B8ZS Line Encoding and
Decoding
Detection and Generation of AIS
Digital/Analog Loss-of-Signal Detection as per
T1.231, G.775, and ETSI 300233
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock will be Internally Adapted
for T1 or E1 Use
Built-In BERT Tester for Diagnostics
8-Bit Parallel Interface Support for Intel or
Motorola Mode or a 4-Wire Serial Interface
Hardware Mode Interface Support
Transmit Short-Circuit Protection
G.772 Nonintrusive Monitoring
Specification Compliance to the Latest T1 and
E1 Standards—ANSI T1.102, AT&T Pub 62411,
T1.231, T1.403, ITU G.703, G.742, G.775,
G.823, ETSI 300 166, and ETSI 300 233
Single 3.3V Supply with 5V Tolerant I/O
JTAG Boundary Scan as per IEEE 1149.1
160-Pin PBGA/144-Pin eLQFP Package
ORDERING INFORMATION
PART
DS26303G-XXX*
1
DS26303
PIN-PACKAGE
0°C to +70°C
160 PBGA
-40°C to +85°C
160 PBGA
DS26303L-XXX
0°C to +70°C
144 eLQFP
DS26303L-XXX+
0°C to +70°C
144 eLQFP
DS26303LN-XXX
-40°C to +85°C
144 eLQFP
DS26303LN-XXX+
-40°C to +85°C
144 eLQFP
DS26303GN-XXX*
8
TEMP RANGE
Note: When XXX is 075, the part defaults to 75W impedance in E1
mode; when XXX is 120, the part defaults to 120W impedance.
+ Denotes a lead-free/ROHS-compliant device.
* Future product—contact factory for availability.
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata.
1 of 97
REV 072205
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
TABLE OF CONTENTS
1
DETAILED DESCRIPTION ............................................................................................................ 6
2
TELECOM SPECIFICATIONS COMPLIANCE............................................................................... 7
3
BLOCK DIAGRAMS ...................................................................................................................... 9
4
PIN DESCRIPTION ...................................................................................................................... 11
4.1 HARDWARE AND HOST PORT OPERATION .................................................................................... 21
4.1.1
4.1.2
4.1.3
4.1.4
5
REGISTERS................................................................................................................................. 25
5.1 REGISTER DESCRIPTION ............................................................................................................. 30
5.1.1
5.1.2
5.1.3
5.1.4
6
Hardware Mode................................................................................................................................... 21
Serial Port Operation .......................................................................................................................... 22
Parallel Port Operation........................................................................................................................ 23
Interrupt Handling................................................................................................................................ 23
Primary Registers................................................................................................................................ 30
Secondary Registers........................................................................................................................... 38
Individual LIU Registers ...................................................................................................................... 39
BERT Registers .................................................................................................................................. 46
FUNCTIONAL DESCRIPTION ..................................................................................................... 53
6.1 POWER-UP AND RESET .............................................................................................................. 53
6.2 MASTER CLOCK ......................................................................................................................... 53
6.3 TRANSMITTER ............................................................................................................................ 54
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
6.3.6
6.3.7
6.3.8
6.4
RECEIVER .................................................................................................................................. 58
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
6.5
6.6
6.7
6.8
Peak Detector and Slicer .................................................................................................................... 58
Clock and Data Recovery ................................................................................................................... 59
Loss of Signal...................................................................................................................................... 59
AIS ...................................................................................................................................................... 60
Bipolar Violation and Excessive Zero Detector................................................................................... 61
LIU Receiver Front End ...................................................................................................................... 61
HITLESS-PROTECTION SWITCHING (HPS).................................................................................... 61
JITTER ATTENUATOR .................................................................................................................. 63
G.772 MONITOR ........................................................................................................................ 64
LOOPBACKS ............................................................................................................................... 64
6.8.1
6.8.2
6.8.3
6.9
Transmit Line Templates .................................................................................................................... 55
LIU Transmit Front End....................................................................................................................... 57
Dual-Rail Mode ................................................................................................................................... 58
Single-Rail Mode................................................................................................................................. 58
Zero Suppression—B8ZS or HDB3 .................................................................................................... 58
Transmit Power-Down ........................................................................................................................ 58
Transmit All Ones................................................................................................................................ 58
Drive Failure Monitor........................................................................................................................... 58
Analog Loopback ................................................................................................................................ 64
Digital Loopback.................................................................................................................................. 64
Remote Loopback ............................................................................................................................... 65
BERT........................................................................................................................................ 66
6.9.1
6.9.2
6.9.3
Configuration and Monitoring.............................................................................................................. 66
Receive Pattern Detection .................................................................................................................. 67
Transmit Pattern Generation............................................................................................................... 68
6.10 SPECIAL TEST FUNCTIONS .......................................................................................................... 69
6.10.1 Metal Options ...................................................................................................................................... 69
7
JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT.................................. 70
7.1 TAP CONTROLLER STATE MACHINE ............................................................................................ 71
7.2 INSTRUCTION REGISTER ............................................................................................................. 74
7.3 TEST REGISTERS ....................................................................................................................... 75
7.3.1
Boundary Scan Register ..................................................................................................................... 75
2 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
7.3.2
7.3.3
8
Bypass Register .................................................................................................................................. 75
Identification Register ......................................................................................................................... 75
OPERATING PARAMETERS....................................................................................................... 76
9
THERMAL CHARACTERISTICS ................................................................................................. 77
10 AC CHARACTERISTICS ............................................................................................................. 78
10.1 LINE INTERFACE CHARACTERISTICS ............................................................................................ 78
10.2 PARALLEL HOST INTERFACE TIMING CHARACTERISTICS ............................................................... 79
10.3 SERIAL PORT ............................................................................................................................. 91
10.4 SYSTEM TIMING ......................................................................................................................... 92
10.5 JTAG TIMING ............................................................................................................................ 94
11 PACKAGE INFORMATION.......................................................................................................... 95
11.1 ELQFP PACKAGE OUTLINE (1 OF 2)............................................................................................ 95
11.2 ELQFP PACKAGE OUTLINE (2 OF 2)............................................................................................ 96
12 DOCUMENT REVISION HISTORY .............................................................................................. 97
3 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
LIST OF FIGURES
Figure 3-1. Block Diagram ........................................................................................................................................... 9
Figure 3-2. Receive Logic Detail................................................................................................................................ 10
Figure 3-3. Transmit Logic Detail............................................................................................................................... 10
Figure 4-1. 160-Pin PBGA Pin Assignment............................................................................................................... 19
Figure 4-2. 144-Pin eLQFP Pin Assignment ............................................................................................................. 20
Figure 4-3. Serial Port Operation for Write Access ................................................................................................... 22
Figure 4-4. Serial Port Operation for Read Access with CLKE = 0 ........................................................................... 22
Figure 4-5. Serial Port Operation for Read Access with CLKE = 1 ........................................................................... 23
Figure 4-6. Interrupt Handling Flow Diagram ............................................................................................................ 24
Figure 6-1. Pre-Scaler PLL and Clock Generator...................................................................................................... 53
Figure 6-2. T1 Transmit Pulse Templates ................................................................................................................. 55
Figure 6-3 E1 Transmit Pulse Templates .................................................................................................................. 56
Figure 6-4. LIU Front End .......................................................................................................................................... 57
Figure 6-5. HPS Logic ............................................................................................................................................... 62
Figure 6-6. HPS Block Diagram................................................................................................................................. 62
Figure 6-7. Jitter Attenuation ..................................................................................................................................... 63
Figure 6-8. Analog Loopback..................................................................................................................................... 64
Figure 6-9. Digital Loopback...................................................................................................................................... 65
Figure 6-10. Remote Loopback ................................................................................................................................. 65
Figure 6-11. PRBS Synchronization State Diagram.................................................................................................. 67
Figure 6-12. Repetitive Pattern Synchronization State Diagram ............................................................................... 68
Figure 7-1. JTAG Functional Block Diagram ............................................................................................................. 70
Figure 7-2. TAP Controller State Diagram................................................................................................................. 73
Figure 10-1. Intel Nonmuxed Read Cycle ................................................................................................................. 80
Figure 10-2. Intel Mux Read Cycle ............................................................................................................................ 81
Figure 10-3. Intel Nonmux Write Cycle...................................................................................................................... 83
Figure 10-4. Intel Mux Write Cycle ............................................................................................................................ 84
Figure 10-5. Motorola Nonmux Read Cycle .............................................................................................................. 86
Figure 10-6. Motorola Mux Read Cycle ..................................................................................................................... 87
Figure 10-7. Motorola Nonmux Write Cycle .............................................................................................................. 89
Figure 10-8. Motorola Mux Write Cycle ..................................................................................................................... 90
Figure 10-9. Serial Bus Timing Write Operation........................................................................................................ 91
Figure 10-10. Serial Bus Timing Read Operation with CLKE = 0.............................................................................. 91
Figure 10-11. Serial Bus Timing Read Operation with CLKE = 1.............................................................................. 91
Figure 10-12. Transmitter Systems Timing ............................................................................................................... 92
Figure 10-13. Receiver Systems Timing ................................................................................................................... 93
Figure 10-14. JTAG Timing ....................................................................................................................................... 94
4 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
LIST OF TABLES
Table 2-1. T1-Related Telecommunications Specifications ........................................................................................ 7
Table 2-2. E1-Related Telecommunications Specifications ........................................................................................ 8
Table 4-1. Pin Descriptions........................................................................................................................................ 11
Table 4-2. Hardware Mode Configuration Examples................................................................................................. 21
Table 4-3. Parallel Port Mode Selection and Pin Functions ...................................................................................... 23
Table 5-1. Primary Register Set ................................................................................................................................ 25
Table 5-2. Secondary Register Set............................................................................................................................ 26
Table 5-3. Individual LIU Register Set ....................................................................................................................... 26
Table 5-4. BERT Register Set ................................................................................................................................... 27
Table 5-5. Primary Register Set Bit Map ................................................................................................................... 28
Table 5-6. Secondary Register Set Bit Map .............................................................................................................. 28
Table 5-7. Individual LIU Register Set Bit Map.......................................................................................................... 28
Table 5-8. BERT Register Bit Map ............................................................................................................................ 29
Table 5-9. G.772 Monitoring Control ......................................................................................................................... 33
Table 5-10. TST Template Select Transmitter Register ............................................................................................ 35
Table 5-11. Template Selection................................................................................................................................. 36
Table 5-12. Address Pointer Bank Selection............................................................................................................. 37
Table 5-13. MCLK Selections .................................................................................................................................... 41
Table 5-14. PLL Clock Select .................................................................................................................................... 44
Table 5-15. Clock A Select ........................................................................................................................................ 44
Table 6-1. Telecommunications Specification Compliance for DS26303 Transmitters ............................................ 54
Table 6-2. Registers Related to Control of DS26303 Transmitters ........................................................................... 54
Table 6-3. DS26303 Template Selections ................................................................................................................. 55
Table 6-4. LIU Front-End Values ............................................................................................................................... 57
Table 6-5. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications............................................................... 59
Table 6-6. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications................................................................. 60
Table 6-7. AIS Detection and Reset Criteria ............................................................................................................. 60
Table 6-8. Registers Related to AIS Detection.......................................................................................................... 60
Table 6-9. BPV, Code Violation, and Excessive Zero Error Reporting ..................................................................... 61
Table 6-10. Pseudorandom Pattern Generation........................................................................................................ 66
Table 6-11. Repetitive Pattern Generation ................................................................................................................ 66
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture....................................................................................... 74
Table 7-2. ID Code Structure..................................................................................................................................... 75
Table 7-3 Device ID Codes........................................................................................................................................ 75
Table 8-1. Recommended DC Operating Conditions ................................................................................................ 76
Table 8-2. Capacitance.............................................................................................................................................. 76
Table 8-3. DC Characteristics.................................................................................................................................... 76
Table 9-1. Thermal Characteristics............................................................................................................................ 77
Table 10-1. Transmitter Characteristics .................................................................................................................... 78
Table 10-2. Receiver Characteristics......................................................................................................................... 78
Table 10-3. Intel Read Mode Characteristics ............................................................................................................ 79
Table 10-4. Intel Write Cycle Characteristics ............................................................................................................ 82
Table 10-5. Motorola Read Cycle Characteristics ..................................................................................................... 85
Table 10-6. Motorola Write Cycle Characteristics ..................................................................................................... 88
Table 10-7. Serial Port Timing Characteristics .......................................................................................................... 91
Table 10-8. Transmitter System Timing .................................................................................................................... 92
Table 10-9. Receiver System Timing......................................................................................................................... 93
Table 10-10. JTAG Timing Characteristics................................................................................................................ 94
5 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
1 DETAILED DESCRIPTION
The DS26303 is a single-chip, 8-channel, short-haul line interface unit (LIU) for T1 (1.544Mbps) and E1
(2.048Mbps) applications. Eight independent receivers and transmitters are provided in a single PBGA package or
an eLQFP package. The LIUs can be individually selected for T1, J1, or E1 operation. The LIU requires a single
reference clock called MCLK. MCLK can be either 1.544MHz or 2.048MHz or a multiple thereof, and either
frequency can be internally adapted for T1, J1, or E1 mode. Internal impedance match provided for both transmit
and receive paths reduces external component count. The transmit waveforms are compliant to G.703 and T1.102
specification. The DS26303 provides software-selectable internal transmit termination for 100W T1 twisted pair,
110W J1 twisted pair, 120W E1 twisted pair, and 75W E1 coaxial applications. The transmitters have fast highimpedance capability and can be individually powered down.
The receivers can function with up to 15dB of receive signal attenuation for T1 mode and E1 mode. The DS26303
can be configured as a 7-channel LIU with channel 1 used for nonintrusive monitoring in accordance with G.772.
The receivers and transmitters can be programmed into single-rail or dual-rail mode. AMI or HDB/B8ZS encoding
and decoding is selectable in single-rail mode. A 128-bit crystal-less on-board jitter attenuator for each LIU can be
placed in the receive or transmit directions. The jitter attenuator meets the ETSI CTR12/13 ITU G.736, G.742,
G.823, and AT&T PUB6411 specifications.
The DS26303 detects and generates AIS in accordance with T1.231, G.775, and ETSI 300233. Loss of signal is
detected in accordance with T1.231, G.775, and ETSI 300233. The DS26303 can perform digital, analog, remote,
and dual loopbacks on individual LIUs. JTAG boundary scan is provided for the digital pins.
The DS26303 can be configured using an 8-bit multiplexed or nonmultiplexed Intel or Motorola port, a 4-pin serial
port, or in limited modes of operation using hardware mode.
The analog AMI/HDB3 waveform of the E1 line or the AMI/B8ZS waveform of the T1 line is transformer coupled
into the RTIP and RRING pins of the DS26303. The user has the option to select internal termination of 75W,
100W, 110W, or 120W applications. The device recovers clock and data from the analog signal and passes it
through a selectable jitter attenuator, outputting the received line clock at RCLK and data at RPOS and RNEG.
The DS26303 receivers can recover data and clock for up 15dB of attenuation of the transmitted signals in T1 and
E1 mode. Receiver 1 can monitor the performance of receivers 2 to 8 or transmitters 2 to 8.
The DS26303 contains eight identical transmitters. Digital transmit data is input at TPOS/TNEG with reference to
TCLK. The data at these pins can be single rail or dual rail. This data is processed by waveshaping circuitry and
line driver to output at TTIP and TRING in accordance with ANSI T1.102 for T1/J1 or G.703 for E1 mask.
The DS26303 drives the E1 or T1 line from the TTIP and TRING pins through a coupling transformer. The
DS26303 functions with a 1:2 and 2:1 transformer for the Tx and Rx paths for operation, respectively.
6 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
2 TELECOM SPECIFICATIONS COMPLIANCE
The DS26303 LIU meets all the relevant latest telecommunications specifications. The following table provides the
T1 specifications and relevant sections that are applicable to the DS26303.
Table 2-1. T1-Related Telecommunications Specifications
ANSI T1.102–Digital Hierarchy Electrical Interface
AMI Coding
B8ZS Substitution Definition
DS1 Electrical Interface. Line rate ±32ppm; Pulse Amplitude between 2.4V to 3.6 V peak; Power level between
12.6dBm to 17.9dBm. The T1 pulse mask is provided that we comply. DSX-1 for cross connects the return loss is
greater than 26dB. The DSX-1 cable is restricted up to 655 feet.
This specification also provides cable characteristics of DSX-Cross Connect cable—22 AVG cable of 1000 feet.
ANSI T1.231–Digital Hierarchy–Layer 1 in Service Performance Monitoring
BPV Error Definition, Excessive Zero Definition, LOS description, AIS definition
ANSI T1.403–Network and Customer Installation Interface–DS1 Electrical Interface
Description of the Measurement of the T1 Characteristics—100W, pulse shape and template according to T1.102;
power level 12.4dBm to 19.7dBm when all ones are transmitted.
LBO for the Customer Interface (CI) is specified as 0dB, 7.5dB, and 15dB. Line rate is ±32ppm.
Pulse Amplitude is 2.4V to 3.6 V.
AIS generation as unframed all ones is defined.
The total cable attenuation is defined as 22dB. The DS26303 functions up to 36dB cable loss.
Note that the pulse mask defined by T1.403 and T1.102 are different—specifically at Times 0.61, -0.27, -34,
and 0.77. The DS26303 is compliant to both templates.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer
characteristics are tighter than G.736 and jitter tolerance is tighter the G.823.
7 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 2-2. E1-Related Telecommunications Specifications
ITUT G.703 Physical/Electrical Characteristics of G.703 Hierarchical Digital Interfaces
Defines the 2048kbps bit rate: 2048 ±50ppm. The transmission media are 75W coax or 120W twisted pair; peak-topeak space voltage is ±0.237V; nominal pulse width is 244ns.
Return loss: 51Hz to 102Hz is 6dB, 102Hz to 3072Hz is 8dB, 2048Hz to 3072Hz is 14dB
Nominal peak voltage is 2.37V for coax and 3V for twisted pair.
The pulse mask for E1 is defined in G.703.
ITUT G.736 Characteristics of Synchronous Digital Multiplex Equipment Operating at 2048kbps
The peak-to-peak jitter at 2048kbps must be less than 0.05UI at 20Hz to 100Hz.
Jitter transfer between 2.048 synchronization signal and 2.048 transmission signal is provided.
ITUT G.742 Second-Order Digital Multiplex Equipment Operating at 8448kbps
The DS26303 jitter attenuator is compliant with jitter transfer curve for sinusoidal jitter input.
ITUT G.772
This specification provides the method for using receiver for transceiver 0 as a monitor for the rest of the seven
transmitter/receiver combinations.
ITUT G.775
An LOS detection criterion is defined.
ITUT G.823–The control of jitter and wander within digital networks that are based on 2.048kbps Hierarchy
G.823 provides the jitter amplitude tolerance at different frequencies, specifically 20Hz, 2.4kHz, 18kHz, and
100kHz.
ETSI 300 166
This specification provides transmit return loss of 6dB for a range of 0.25fb to 0.05fb, and 8dB for a range of 0.05fb
to 1.5fb where fb equals 2.048kHz for 2.048kbps interface.
ETSI 300 233
This specification provides LOS and AIS signal criteria for E1 mode.
Pub 62411
This specification has tighter jitter tolerance and transfer characteristics than other specifications. The jitter transfer
characteristics are tighter than G.736 and jitter tolerance is tighter then G.823.
8 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
3 BLOCK DIAGRAMS
Figure 3-1. Block Diagram
TYPICAL OF ALL 8 CHANNELS
T1CLK E1CLK
MUX
Jitter Attenuator
MUX
2.048MHz to
1.544MHz PLL
VCO/PLL
RLOS
TTIP
RNEG/CV
Remote Loopback
Jitter Attenuator
Local Loopback
Clock/Data
Recovery
Line Drivers
TRING
RCLK
Receive Logic
DS26303
TPOS/TDAT
Wave Shaping
Unframed All
Ones Insertion
Remote Loopback (Dual Mode)
RPOS/RDAT
Peak Detector
Analog Loopback
RTIP
Filter
Optional
Termination
RRING
TCLK
Transmit Logic
TNEG
OE
Reset
Control
and
Interrupt
Port Interface
E1CLK
8
8
Master Clock
Adapter
JTAG PORT
9 of 97
MCLK
JTDI
JTDO
JTCLK
JTMS
JTRSTB
INTB
MODESEL
8
CSB
A0 to A4
ASB/ALE/SCLK
MOTEL
RDY/ACKB/SDO
RDB/RWB
CLKE
WRB/DSB/SDI
MUX
5
D7/AD7/
BSWB
D0 to D6/
AD0 to AD6
Reset
T1CLK
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
LOS
EZDE
Figure 3-2. Receive Logic Detail
RCLK
RCLK
Excessive
Zero
Detect
T1.231
IAISEL
POS
AISEL
NEG
EN
RPOS
RNEG/CV
ENCV
BPV/CV/EXZ
MCLK
LASCS
SRMS
AIS
Detector
G.775, ETSI 300233,
T1.231
CVDEB
ENCODE
LCS
CODE
ENCODE
B8ZS/HDB3/AMI
Decoder (G.703, T1.102)
BPVs, Code Violatiions
(T1.231, O.161)
MUX
NRZ Data
All Ones
Insert
(AIS)
BEIR
ENCODE
SRMS
LCS
CODE
Figure 3-3. Transmit Logic Detail
B8ZS/HDB3/AMI
Coder (G.703,
T1.102)
To Remote
Loopback
BPV
Insert
MUX
TPOS/
TDATA
TNEG/
BPV
TCLK
10 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
4 PIN DESCRIPTION
Table 4-1. Pin Descriptions
NAME
PIN
eLQFP
PBGA
TYPE
FUNCTION
ANALOG TRANSMIT AND RECEIVE
TTIP1
TTIP2
TTIP3
TTIP4
TTIP5
TTIP6
TTIP7
TTIP8
TRING1
TRING2
TRING3
TRING4
TRING5
TRING6
TRING7
TRING8
RTIP1
RTIP2
RTIP3
RTIP4
RTIP5
RTIP6
RTIP7
RTIP8
RRING1
RRING2
RRING3
RRING4
RRING5
RRING6
RRING7
RRING8
45
52
57
64
117
124
129
136
46
51
58
63
118
123
130
135
48
55
60
67
120
127
132
139
49
54
61
66
121
126
133
138
N5
L5
L10
N10
B10
D10
D5
B5
P5
M5
M10
P10
A10
C10
C5
A5
P7
M7
M8
P8
A8
C8
C7
A7
N7
L7
L8
N8
B8
D8
D7
B7
Analog
Output
Transmit Bipolar Tip for Channel 1 to 8. These pins are
differential line-driver tip outputs. These pins can be high
impedance if pin OE is low. If the corresponding clock TCLKn is
low for 64 MCLKs, where n is 1 to 8 for the eight transmitters. This
puts the corresponding transmitter in a power-down mode. When
1 is set in the OEB.OEB bit, the associated pin is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal
matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W.
Analog
Output
Transmit Bipolar Ring for Channel 1 to 8. These pins are
differential line-driver ring outputs. These pins can be high
impedance if pin OE is low. If the corresponding clock TCLKn is
low for 64 MCLKs, where n is 1 to 8 for the eight transmitters. This
puts the corresponding transmitter in a power-down mode. When
1 is set in the OEB.OEB bit, the associated pin is high impedance.
The differential outputs of TTIPn and TRINGn can provide internal
matched impedance for E1 75W, E1 120W, T1 100W, or J1 110W.
Analog
Input
Receive Bipolar Tip for Channel 1 to 8. Receive analog input for
differential receiver. Data and clock are recovered and output at
RPOS/RNEG and RCLK pins, respectively. The differential inputs
of RTIPn and RRINGn can provide internal matched impedance
for E1 75W, E1 120W, T1 100W, or J1 110W.
Analog
Input
Receive Bipolar Ring for Channel 1 to 8. Receive analog input
for differential receiver. Data and clock are recovered and output
at RPOS/RNEG and RCLK pins, respectively. The differential
inputs of RTIPn and RRINGn can provide internal matched
impedance for E1 75W, E1 120W, T1 100W, or J1 110W.
11 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
NAME
PIN
eLQFP
PBGA
TYPE
FUNCTION
DIGITAL Tx/Rx
TPOS1/TDATA1
TPOS2/TDATA2
TPOS3/TDATA3
TPOS4/TDATA4
TPOS5/TDATA5
TPOS6/TDATA6
TPOS7/TDATA7
TPOS8/TDATA8
37
30
80
73
108
101
8
1
N2
L2
L13
N13
B13
D13
D2
B2
TNEG1
38
N3
TNEG2
31
L3
TNEG3
79
L12
TNEG4
72
N12
TNEG5
109
B12
TNEG6
102
D12
TNEG7
7
D3
TNEG8
144
B3
TCLK1
36
N1
TCLK2
29
L1
TCLK3
81
L14
TCLK4
74
N14
TCLK5
107
B14
TCLK6
100
D14
TCLK7
9
D1
TCLK8
2
B1
RPOS1/RDATA1
RPOS2/RDATA2
RPOS3/RDATA3
RPOS4/RDATA4
RPOS5/RDATA5
RPOS6/RDATA6
RPOS7/RDATA7
RPOS8/RDATA8
40
33
77
70
111
104
5
142
P2
M2
M13
P13
A13
C13
C2
A2
O,
tri-state
RNEG1/CV1
41
P3
RNEG2/CV2
34
M3
O,
tri-state
RNEG3/CV3
76
M12
RNEG4/CV4
69
P12
RNEG5/CV5
112
A12
Transmit Positive-Data Input for Channel 1 to 8/Transmit Data
Input for Channel 1 to 8
I
TPOS[1:8]: When the DS26303 is configured in dual-rail mode, the
data input to TPOSn is output as a positive pulse on the line (TIP
and RING).
TDATA[1:8]: When the device is configured in single-rail mode,
NRZ data is input to TDATAn. The data is encoded HDB3/B8ZS or
AMI before being output to the line.
Transmit Negative Data for Channel 1 to 8. When the DS26303
is configured in dual-rail mode, the data input to TNEGn is output
as a negative mark on the line as follows:
I
TPOSn TNEGn
Output Pulse
0
0
Space
0
1
Negative Mark
1
0
Positive Mark
1
1
Space
When TNEGn is pulled High for more than 16 consecutive TCLK
clock cycles, single-rail I/O is selected.
Transmit Clock for Channel 1 to 8. The transmit clock must be
1.544MHz for T1 or 2.048MHz for E1 mode. TCLKn is the clock
used to sample the data TPOS/TNEG or TDAT on the falling edge.
The expected TCLK can be inverted.
I
If TCLKn is high for 16 or more MCLKs, then transmit all-ones
(TAO) signals to the line side of the corresponding transmit
channel. When TCLKn starts clocking again, normal operation will
begin again for the corresponding transmit channel.
If TCLKn is low for 64 or more MCLKs, the corresponding transmit
channel on the line side powers down and must be put into high
impedance. When TCLKn starts clocking again the corresponding
transmit channel powers up and comes out of high impedance.
Receive Positive-Data Output for Channel 1 to 8/Receive Data
Output for Channel 1 to 8
RPOS[1:8]: In dual-rail mode, the NRZ data output indicates a
positive pulse on RTIP/RRING. If a given receiver is in powerdown mode, the associated RPOS pin is high impedance.
RDATA[1:8]: In single-rail mode, NRZ data is output to the pin.
Note: During an RLOS condition, the RPOS/RDATA outputs
remain active.
Receive Negative-Data Output for Channel 1 to 8/Code
Violation for Channel 1 to 8
RNEG[1:8]: In dual-rail mode, the NRZ data output indicates a
negative pulse on RTIP/RRING. If a given receiver is in powerdown mode, the associated RNEG pin is high impedance.
CV[1:8]: In single-rail mode, bipolar violation, code violation, and
excessive zeros are reported by driving CVn high for one clock
12 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
NAME
PIN
TYPE
FUNCTION
eLQFP
PBGA
RNEG6/CV6
105
C12
RNEG7/CV7
4
C3
excessive zeros are reported by driving CVn high for one clock
cycle. If HDB3 or B8ZS is not selected, this pin indicates only
BPVs.
RNEG8/CV8
141
A3
Note: During an RLOS condition the output remains active.
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
39
32
78
71
110
103
6
143
P1
M1
M14
P14
A14
C14
C1
A1
MCLK
10
E1
O,
tri-state
Receive Clock for Channel 1 to 8. The receive data
RPOS/RNEG or RDAT is clocked out on the rising edge of RCLK.
RCLK output can be inverted. If a given receiver is in power-down
mode, the RCLK is high impedance.
I
Master Clock. This is an independent free-running clock that can
be a multiple of 2.048MHz ±50ppm for E1 mode or 1.544MHz
±50ppm for T1 mode. The clock selection is available by MC bits
MPS0, MPS1, FREQS, and PLLE. A multiple of 2.048MHz can be
internally adapted to 1.544MHz and a multiple of 1.544MHz can
be internally adapted to 2.048MHz. In hardware mode, internal
adaptation is not available so the user must provide 2.048MHz
±50ppm for E1 mode or 1.544MHz ±50ppm for T1 mode.
Loss-of-Signal Output/T1-E1 Clock
RLOS1/TECLK
42
K4
O
RLOS1: This output goes high when there is no transition on the
received signal over a specified interval. The output goes low
when there is sufficient ones density in the received signal. The
RLOS criteria for assertion and desertion criteria are described in
the Functional Description section. The RLOS outputs can be
configured to comply with T1.231, ITU G.775, or ETSI 300 233. In
hardware mode, ETSI 300 233 “RLOS Criteria” is not available.
TECLK: When enabled by register MC, this output becomes a T1or E1-programmable clock output. For T1 or E1 frequency
selection, see register CCR. This option is not available in
hardware mode.
RLOS2/
RXPROBEA1
RLOS3/
RXPROBEB1
RLOS4/
RXPROBEC1
35
K3
75
K12
68
K11
Loss-of-Signal Output/Receive Probe
I/O
RLOS[2:4]: See RLOS1 pin description.
RXPROBE A1, B1, C1: Used in test only.
Loss-of-Signal Output/Scan Data Output
RLOS5/
scan_do
113
E11
O
RLOS5: See RLOS1 pin description.
scan_do: Data output during scan.
Loss-of-Signal Output/Scan Data Input
RLOS6/
scan_di
106
E12
I/O
RLOS6: See RLOS1 pin description.
scan_di: Data input during scan.
Loss-of-Signal Output/Scan Clock
RLOS7/
scan_clk
3
E3
I/O
RLOS7: See RLOS1 pin description.
scan_clk: Clock input during scan.
13 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
NAME
PIN
eLQFP
PBGA
TYPE
FUNCTION
Loss-of-Signal Output/Scan Enable
RLOS8/
scan_en
140
E4
I/O
RLOS8: See RLOS1 pin description.
scan_en: Enables scan during test when pin scan_mode is high.
CLKA
93
G13
O,
tri-state
scan_mode
94
H13
I
(pulled
to VSS)
Clock A. This output becomes a programmable clock output when
enabled by register MC. For frequency options see register CCR.
This option is not available in hardware mode. If this option is not
used, the pin should be left unconnected.
Scan Mode. Selects scan mode when high. If not used, this pin
should be left unconnected or grounded.
HARDWARE AND PORT OPERATION
Mode Selection. This pin is used to select the control mode of the
DS26303.
MODESEL
11
E2
I
(pulled
to
VDD/2)
Low → Hardware Mode
VDD/2 → Serial Host Mode
High → Parallel Host Mode
Note: When left unconnected, do not route signals with fast
transitions near MODESEL. This practice minimizes capacitive
coupling.
Multiplexed/Nonmultiplexed Select Pin/
Transmit Impedance/Receive Impedance Match
MUX: In host mode with a parallel port, this pin is used to select
multiplexed address and data operation or separate address and
data. When mux is a high, multiplexed address and data is used.
MUX/
TIMPRM
43
K2
I
TIMPRM: In hardware mode, this pin selects the internal transmit
termination impedance and receive impedance match for E1 mode
and T1/J1 mode.
0 → 75W for E1 mode or 100W for T1 mode
1 → 120W for E1 mode or 110W for J1 mode
Note: If the part number ends with 120, the default is 120W when
low and 75W when high for El mode only.
Motorola Intel Select/Code
MOTEL/
CODE
88
H12
I
MOTEL: When in parallel host mode, this pin selects Motorola
mode when low and Intel mode when high.
CODE: In hardware mode, AMI encoding/decoding is selected
when the pin is high for all the LIUs. When the pin is low, B8ZS is
selected for T1 mode and HDB3 for E1 mode for all the LIUs.
14 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
NAME
PIN
eLQFP
PBGA
TYPE
FUNCTION
Chip Select Bar/Jitter Attenuator Select
CSB: This signal must be low during all accesses to the registers.
CSB/
JAS
87
J11
I
(In HW
mode,
pulled
to
VDD/2)
JAS: In hardware mode, this pin is used as a jitter attenuator
select.
Low → Jitter attenuator is in the transmit path.
VDDIO/2 → Jitter attenuator is not used.
High → Jitter attenuator is in the receive path.
Note: When left unconnected and in hardware mode, do not route
signals with fast transitions near JAS. This practice minimizes
capacitive coupling.
Shift Clock/Address Latch Enable/Address Strobe
Bar/Template Selection 2
SCLK: In the serial host mode, this pin is the serial clock. Data on
SDI is clocked on the rising edge of SCLK. The data is clocked on
SDO on the rising edge of SCLK if CLKE is high. If CLKE is low
the data on SDO is clocked on the falling edge of SCLK.
SCLK/ALE/
ASB/TS2
86
J12
I
ALE: In parallel Intel multiplexed mode, the address lines are
latched on the falling edge of ALE. Tie ALE pin high if using
nonmultiplexed mode.
ASB: In parallel Motorola multiplexed mode, the address is
sampled on the falling edge of ASB. Tie ASB pin high if using
nonmultiplexed mode.
TS2: In hardware mode, this pin signal is the most significant bit
position in Table 5-11.
Read Bar/Read Write Bar/Template Selection 1
RDB: In Intel host mode, this pin must be low for read operation.
RDB/RWB/TS1
85
J13
I
RWB: In Motorola mode, this pin is low for write operation and
high for read operation.
TS1: In hardware mode, this pin signal is the second significant bit
position in Table 5-11.
Serial Data Input/Write Bar/Data Strobe Bar/Template
Selection 0
SDI: In the serial host mode, this pin is the serial input SDI. It is
sampled on the rising edge of SCLK.
WRB: In Intel host mode, this pin is active low during write
operation. The data or address (multiplexed mode) is sampled on
the rising edge of WRB.
SDI/WRB/DSB/TS0
84
J14
I
DSB: In the parallel Motorola mode, this pin is active low. During a
write operation the data or address is sampled on the rising edge
of DSB. During a read operation the data (D[7:0] or AD[7:0]) is
driven on the rising edge of DSB. In the nonmultiplexed Motorola
mode, the address bus (A [5:0]) is latched on the falling edge of
DSB.
TS0: In hardware mode, this pin signal is the least significant bit
position in Table 5-11.
15 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
NAME
PIN
eLQFP
PBGA
TYPE
FUNCTION
Serial Data Out/Ready Output/Acknowledge Bar/Receive
Impedance Off
SDO: In serial host mode, the SDO data is output on this pin. If a
serial write is in progress this pin is in high impedance. During a
read SDO is high impedance when the SDI is in command/
address mode. If CLKE is low, SDO is output on the rising edge of
SCLK, if CLKE is high on the falling edge.
SDO/RDY/ACKB/
RIMPOFF
83
K14
I/O
RDY: A low on this pin reports to the host that the cycle is not
complete and wait states must be inserted. A high means the
cycle is complete.
ACKB: In Motorola parallel mode, a low on this pin indicates that
the read data is available for the host or that the written data cycle
is complete.
RIMPOFF: In hardware mode when this pin is high, all the RTIP
and RING pins have internal impedance switched off.
O,
open
drain
Active-Low Interrupt Bar. This interrupt signal is driven low when
an event is detected on any of the enabled interrupt sources in any
of the register banks. When there are no active and enabled
interrupt sources, the pin can be programmed to either drive high
or not drive high. The reset default is to not drive high when there
are no active enabled interrupt sources. All interrupt sources are
disabled after a software reset and they must be programmed to
be enabled.
INTB
82
K13
D7/AD7/BSWP/LP8
28
K1
Data Bus 7–0/Address/Data Bus 7–0/Bit Swap/
Loopback Select 7–0
D6/AD6/LP7
27
J1
D[7:0]: In nonmultiplexed host mode, these pins are the
bidirectional data bus.
D5/AD5/LP6
26
J2
D4/AD4/LP5
25
J3
D3/AD3/LP4
24
J4
D2/AD2/LP3
23
H2
D1/AD1/LP2
22
H3
D0/AD0/LP1
21
G2
I/O (In
HW
mode,
pulled
to
VDD / 2)
AD[7:0]: In multiplexed host mode, these pins are the bidirectional
address/data bus. Note that AD7 and AD6 do not carry address
information, and in serial host mode AD6–AD0 should be
grounded.
BSWP: In serial host mode, this pin defines the serial data position
to be LSB first when low and MSB first when high.
LP[8:1] In hardware mode, these pins set the loopback modes for
the corresponding LIU as follows:
Low → Remote Loopback
VDDIO / 2 → No Loopback
High → Analog Loopback
Note: When left unconnected and in hardware mode, do not route
signals with fast transitions near LP1–LP8. This practice minimizes
capacitive coupling.
16 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
NAME
A4/RIMPMSB
A3/GMC3
PIN
12
F4
Address Bus 4–0/G.772 Monitoring Control/Rx Impedance
Mode Select
F3
A[4:0]: These five pins are address pins in parallel host mode. In
serial host mode and multiplexed host mode, these pins should be
grounded.
13
14
F2
A1/GMC1
15
F1
A0/GMC0
16
G3
CLKE
FUNCTION
PBGA
A2/GMC2
OE
TYPE
eLQFP
114
115
E14
E13
RIMPMSB: In hardware mode when this pin is low, the internal
impedance mode is selected, so RTIP and RING require no
external resistance component. When high, external impedance
mode is selected so RTIP and RING require external resistance.
I
GMC[3:0]: In hardware mode, these signal pins are used to select
transmitter or receiver for nonintrusive monitoring. Receiver 1 is
used to monitor channels 2 to 8 of one receiver from RTIP2–
RTIP8/RRING2–RRING8 or one transmitter from TTIP2–
TTIP8/TRING2–TRING8. These signal pins correspond to the bits
in Table 5-9.
I
Output Enable. If this pin is pulled low, all the transmitter outputs
(TTIP and TRING) are high impedance. Additionally, the user may
use this same pin to turn off all the impedance matching for the
receivers at the same time if register bit GMR.RHPMC is set.
I
Clock Edge. When CLKE is high, SDO is valid on the falling edge
of SCLK. When CLKE is low SDO is valid on the rising edge of
SCLK. When CLKE is high, the RCLK for all the channels is
inverted. This aligns RPOS/RNEG on the falling edge of RCLK
and overrides the settings in register RCLKI. When low,
RPOS/RNEG is aligned on the settings in register RCLKI.
JTAG
JTRSTB
95
G12
I, pullup
JTMS
96
F11
I, pullup
JTCLK
97
F14
I
JTDO
98
F13
O,
high-Z
JTDI
99
F12
I, pullup
JTAG Test Port Reset. This pin if low resets the JTAG port. If not
used it can be left floating.
JTAG Test Mode Select. This pin is clocked on the rising edge of
JTCLK and is used to control the JTAG selection between scan
and test machine control.
JTAG Test Clock. The data JTDI and JTMS are clocked on rising
edge of JTCLK and JTDO is clocked out on the falling edge of
JTCLK.
JTAG Test Data Out. This is the serial output of the JTAG port.
The data is clocked out on the falling edge of JTCLK.
Test Data Input. This pin input is the serial data of the JTAG test.
The data on JTDI is clocked on the rising edge of JTCLK. This pin
can be left unconnected.
POWER SUPPLIES
DVDD
19
H1
—
3.3V Digital Power Supply
DVSS
20
H4
—
Digital Ground
VDDIO
17, 92
—
3.3V I/O Power Supply
VSSIO
18, 91
—
I/O Ground
G1,
G14
G4,
G11
17 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
NAME
PIN
eLQFP
PBGA
TVDD1
44
N4, P4
TVDD2
53
L4, M4
TVDD3
56
TVDD4
65
L11,
M11
N11,
P11
A11,
B11
C11,
D11
C4,
D4
TYPE
FUNCTION
—
3.3V Power Supply for the Transmitter. All TVDD pins must be
connected to TVDD, which must be 3.3V.
—
Analog Ground for Transmitters
TVDD5
116
TVDD6
125
TVDD7
128
TVDD8
137
A4, B4
TVSS1
47
N6, P6
TVSS2
50
L6, M6
TVSS3
59
L9, M9
TVSS4
62
N9, P9
TVSS5
119
A9, B9
TVSS6
122
TVSS7
131
TVSS8
134
A6, B6
AVDD
90
H14
—
3.3V Analog Core Power Supply
AVSS
89
H11
—
Analog Core Ground
C9,
D9
C6,
D6
18 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 4-1. 160-Pin PBGA Pin Assignment
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
RCLK5
RPOS5/ RNEG5/
TVDD5 TRING5 TVSS5 RTIP5
RDATA5 CV5
B
TCLK5
TPOS5/
TPOS8/
TNEG5 TVDD5 TTIP5 TVSS5 RRING5 RRING8 TVSS8 TTIP8 TVDD8 TNEG8
TCLK8
TDATA5
TDATA8
C
RCLK6
RPOS6/ RNEG6/
TVDD6 TRING6 TVSS6 RTIP6
RDATA6 CV6
D
TCLK6
TPOS6/
TPOS7/
TNEG6 TVDD6 TTIP6 TVSS6 RRING6 RRING7 TVSS7 TTIP7 TVDD7 TNEG7
TCLK7
TDATA6
TDATA7
E
OE
CLKE
RTIP8 TVSS8 TRING8 TVDD8
RTIP7 TVSS7 TRING7 TVDD7
RLOS6/ RLOS5/
scan_di scan_do
RNEG8/ RPOS8/
RCLK8
CV8 RDATA8
RNEG7/ RPOS7/
RCLK7
CV7 RDATA7
RLOS8/ RLOS7/
MODESEL MCLK
scan_en scan_clk
F
JTCLK JTDO
G
VDDIO CLKA JTRSTB GNDIO1
H
AVDD
J
TS0
TS1
K
SDO
INTB RXPROBE RXPROBE
L
TCLK3
TPOS3/
TPOS2/
TNEG3 TVDD3 TTIP3 TVSS3 RRING3 RRING2 TVSS2 TTIP2 TVDD2 TNEG2
TCLK2
TDATA3
TDATA2
M
RCLK3
RPOS3/ RNEG3/
TVDD3 TRING3 TVSS3 RTIP3
RDATA3 CV3
N
TCLK4
TPOS4/
TPOS1/
TNEG4 TVDD4 TTIP4 TVSS4 RRING4 RRING1 TVSS1 TTIP1 TVDD1 TNEG1
TCLK1
TDATA4
TDATA1
P
RCLK4
RPOS4/ RNEG4/
TVDD4 TRING4 TVSS4 RTIP4
RDATA4 CV4
JTDI
JTMS
scan_ MOTEL/
AVSS
mode CODE
TS2
A4
DS26303
HARDWARE MODE
(BOTTOM VIEW)
CSB/
JAS
RLOS3/ RLOS4/
B1
GMC3 GMC2 GMC1
GNDIO0 GMC0
LP1
VDDIO0
DVSS
LP2
LP3
DVDD
LP4
LP5
LP6
LP7
RLOS2/
RLOS1/
MUX/
RXPROBE
TECLK
TIMPRM
A1
C1
19 of 97
RTIP2 TVSS2 TRING2 TVDD2
RTIP1 TVSS1 TRING1 TVDD1
LP8
RNEG2/ RPOS2/
RCLK2
CV2 RDATA2
RNEG1/ RPOS1/
RCLK1
CV1 RDATA1
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 4-2. 144-Pin eLQFP Pin Assignment
NAME
PIN
NAME
PIN
NAME
PIN
NAME
PIN
TPOS8/TDATA8
TCLK8
RLOS7
RNEG7/CV7
RPOS7/RDATA7
RCLK7
TNEG7
TPOS7/TDATA7
TCLK7
MCLK
1
2
3
4
5
6
7
8
9
10
TPOS1/TDATA1
TNEG1
RCLK1
RPOS1/RDATA1
RNEG1/CV1
RLOS1/TECLK
MUX/TIMPRM
TVDD1
TTIP1
TRING1
37
38
39
40
41
42
43
44
45
46
73
74
75
76
77
78
79
80
81
82
TNEG5
RCLK5
RPOS5/RDATA5
RNEG5/CV5
RLOS5
OE
CLKE
TVDD5
TTIP5
TRING5
109
110
111
112
113
114
115
116
117
118
MODESEL
11
TVSS1
47
83
TVSS5
119
A4/RIMPMSB
A3/GMC3
A2/GMC2
A1/GMC1
A0/GMC0
VDDIO
VSSIO
DVDD
DVSS
D0/AD0/LP1
D1/AD1/LP2
D2/AD2/LP3
D3/AD3/LP4
D4/AD4/LP5
D5/AD5/LP6
D6/AD6/LP7
D7/AD7/BSWP/LP8
TCLK2
TPOS2/TDATA2
TNEG2
RCLK2
RPOS2/RDATA2
RNEG2/CV2
RLOS2/RXPROBEA1
TCLK1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
RTIP1
RRING1
TVSS2
TRING2
TTIP2
TVDD2
RRING2
RTIP2
TVDD3
TTIP3
TRING3
TVSS3
RTIP3
RRING3
TVSS4
TRING4
TTIP4
TVDD4
RRING4
RTIP4
RLOS4/RXPROBEC1
RNEG4/CV4
RPOS4/RDATA4
RCLK4
TNEG4
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TPOS4/TDATA4
TCLK4
RLOS3/RXPROBEB1
RNEG3/CV3
RPOS3/RDATA3
RCLK3
TNEG3
TPOS3/TDATA3
TCLK3
INTB
SD0/RDY/ACKB/
RIMOFF
SDI/WRB/DSB/TS0
RDB/RWB/TS1
SCLK/ALE/ASB/TS2
CSB/JAS
MOTEL/CODE
AVSS
AVDD
VSSIO
VDDIO
CLKA
scan_mode
JTRSTB
JTMS
JTCLK
JTDO
JTDI
TCLK6
TPOS6/TDATA6
TNEG6
RCLK6
RPOS6/RDATA6
RNEG6/CV6
RLOS6
TCLK5
TPOS5/TDATA5
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
RTIP5
RRING5
TVSS6
TRING6
TTIP6
TVDD6
RRING6
RTIP6
TVDD7
TTIP7
TRING7
TVSS7
RTIP7
RRING7
TVSS8
TRING8
TTIP8
TVDD8
RRING8
RTIP8
RLOS8
RNEG8/CV8
RPOS8/RDATA8
RCLK8
TNEG8
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
20 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
4.1
Hardware and Host Port Operation
4.1.1
Hardware Mode
The DS26303 supports a hardware configuration mode that allows the user to configure the device through setting
levels on the device’s pins. This mode allows the configuration of the DS26303 without the use of a
microprocessor. Not all of the device features are supported in the hardware mode. To see all available options for
this hardware mode, see the pin descriptions in Table 4-1.
The following table provides two basic examples of configurations available in hardware mode by setting pins.
Table 4-2. Hardware Mode Configuration Examples
PIN NAME,
HARDWARE
MODE
TTIP[8:1]
TRING[8:1]
RTIP[8:1]
RRING[8:1]
TPOS[8:1]
TNEG[8:1]
TCLK[8:1]
RPOS[8:1]
RNEG[8:1]
RCLK[8:1]
MCLK
RLOS[8:1]
MODESEL
T1
Output
Output
Input
Input
Input
Input
Input: 1.544MHz
Output
Output
Output: 1.544MHz
Input: 1.544MHz
Output
0
TIMPRM
0
CODE
JAS
TS[2:0]
1
N.C.: Pulled to VDDIO/2
111
E1
Output
Output
Input
Input
Input
Input
Input: 2.048MHz
Output
Output
Output: 2.048MHz
Input: 2.048MHz
Output
0
0
(Part number ends in –75)
1
N.C.: Pulled to VDDIO/2
000
RIMPOFF
0
0
INTB
LP[8:1]
RIMPMS
GMC[3:0]
OE
N.C.
N.C.: Pulled to VDDIO/2
0
0000
1
N.C.
N.C.: Pulled to VDDIO/2
0
0000
1
CLKE
0
0
JTRSTB
JTMS
JTCLK
JTDO
JTDI
RSTB
CLKA
Input, Pulled Up
Input
Input
Output, High-Z
Input, Pulled Up
Input, Pullup
N.C.
Input, Pulled Up
Input
Input
Output, High-Z
Input, Pulled Up
Input, Pullup
N.C.
scan_mode
0
0
STANDARD MODE CONFIGURATION
21 of 97
NOTES
—
—
—
—
—
—
—
—
—
—
Used as recovery clock.
Meets T1.231 and ITU G.775.
Low for hardware mode.
100W for T1 mode/75W E1 mode.
AMI endocoding/decoding.
Jitter attenuator is not used.
Set template T1 (655ft)-100W/E1-75W.
Receive impedance should default to
on.
Not used in hardware mode.
Internally pulled to VDDIO/2.
Internal impedance mode selected.
No monitoring enabled.
TTIP and TRING are outputs.
RPOSn/RNEGn are clocked on rising
edge.
JTAG.
Reset.
Not available in hardware node.
Pull low or ground. Used only in factory
test.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
4.1.2
Serial Port Operation
Setting MODESEL = VDDIO/2 enables the serial bus interface on the DS26303. Port read/write timing is unrelated
to the system transmit and receive timing, allowing asynchronous reads or writes by the host. See Section 10.3 for
the AC timing of the serial port. All serial port accesses are LSB first when BSWP pin is low and MSB first when
BSWP is high. Figure 4-3 to Figure 4-5 show operation with LSB first.
This port is compatible with the SPI interface defined for Motorola processors. An example of this is Motorola’s
MMC2107.
Reading or writing to the internal registers requires writing one address/command byte prior to transferring register
data. The first bit written (LSB) of the address/command byte specifies whether the access is a read (1) or a write
(0). The next 5 bits identify the register address (A1 to A5; A6 and A7 are ignored).
All data transfers are initiated by driving the CSB input low. When CLKE is low, SDO data is output on the rising
edge of SCLK and when CLKE is high, data is output on the falling edge of SCLK. Data is held until the next falling
or rising edge. All data transfers are terminated if CSB input transitions high. Port control logic is disabled and SDO
is tri-stated when CSB is high. SDI is always sampled on the rising edge of SCLK.
Figure 4-3. Serial Port Operation for Write Access
SCLK 1
2
3
4
5
6
7
A1
A2
A3
A4
A5
A6
8
9
10
11
12
13
14
15
D4
D5
D6
16
CSB
SDI
0
(lsb)
X
DO
(msb)
(lsb)
D1
D2
D3
D7
(msb)
WRITE ACCESS ENABLED
SDO
Figure 4-4. Serial Port Operation for Read Access with CLKE = 0
1
SCLK
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CSB
SDI
A1
0
(lsb)
A2
A3
A4
A5
A6
X
(msb)
SDO
D0
Read
Access
Enabled
(lsb)
22 of 97
D1
D2
D3
D4
D5
D6
D7
(msb)
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 4-5. Serial Port Operation for Read Access with CLKE = 1
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CSB
SDI
0
SDO
A1
A2
A3
A4
A5
A6
X
(msb)
(lsb)
D0
D1
D2
(lsb)
4.1.3
D3
D4
D5
D6
D7
(msb)
Parallel Port Operation
When using the parallel interface on the DS26303 the user has the option for either multiplexed bus operation or
nonmultiplexed bus operation. The ALE pin is pulled high in nonmultiplexed bus operation. The DS26303 can
operate with either Intel or Motorola bus-timing configurations selected by MOTEL pin. This pin being high selects
the Intel mode. The parallel port is only operational if MODESEL pin is pulled high. The following table lists all the
pins and their functions in the parallel port mode. See the timing diagrams in Section 10 for more details.
Table 4-3. Parallel Port Mode Selection and Pin Functions
MODESEL, MOTEL,
MUX
100
110
101
111
4.1.4
PARALLEL HOST
INTERFACE
Nonmultiplexed Motorola
Nonmultiplexed Intel
Multiplexed Motorola
Multiplexed Intel
ADDRESS, DATA, AND CONTROL
CSB, ACKB, DSB, RWB, ASB, A [4:0], D [7:0], INTB
CSB, RDY, WRB, RDB, ALE, A [4:0], D [7:0], INTB
CSB, ACKB, DSB, RWB, ASB, AD [7:0], INTB
CSB, RDY, WRB, RDB, ALE, AD [7:0], INTB
Interrupt Handling
There are four sets of events that can potentially trigger an interrupt. The interrupt functions as follows:
·
·
·
When status changes on an interruptible event, the INTB pin will go low if the event is enabled through the
corresponding interrupt-enable register. INTB must be pulled high externally with a 10kW resistor for wired-OR
operation. If a wired-OR operation is not required, the INTB pin can be configured to be high when not active
by setting register GISC.INTM.
When an interrupt occurs, the host processor must read the interrupt status register to determine the source of
the interrupt. The read also clears the Interrupt Status register and clears the output INTB pin. The interrupt
status register can also be configured as clear-on-write as per register GISC.CWE. This clears INTB when a
clear-on-write is performed.
Subsequently, the host processor can read the corresponding status register to check the real-time status of
the event.
23 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 4-6. Interrupt Handling Flow Diagram
Interrupt Allowed
No
Interrupt Conditon
Exist?
Yes
Read Interrupt Status
Register
Read Corresponding Status
Register (Optional)
Service the Interrupt
24 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
5 REGISTERS
Five address bits are used to control the settings of the registers. In the parallel nonmultiplexed mode, AD[4:0] is
used. In multiplexed mode, AD[4:0] is used and AD[5:1] is used in serial mode.The register space contains control
for channels 1 to 8 from address 00 hex to 1F hex. The ADDP (1F) register is used as a pointer to access the
different banks of registers. This register must be set to AA hex for access of the secondary bank of registers, 01
hex for access to the individual LIU bank of registers, and 02 hex for access of the BERT bank of registers. The
primary bank of registers is accessed upon reset of this register to 00 hex.
Table 5-1. Primary Register Set
NAME
Identification
Analog Loopback Configuration
Remote Loopback Configuration
Transmit All-Ones Enable
LOS Status
Driver Fault Monitor Status
LOS Interrupt Enable
Driver Fault Monitor Interrupt Enable
LOS Interrupt Status
Driver Fault Monitor Interrupt Status
Software Reset
G.772 Monitor Configuration
Digital Loopback Configuration
LOS/AIS Criteria Selection
Automatic Transmit All-Ones Select
Global Configuration
Template Select Transceiver Register
Template Select
Output-Enable Bar
Alarm Indication Signal
AIS Interrupt Enable
AIS Interrupt Status
Reserved
Address Pointer for Secondary Register
Set
SYMBOL
HEX
ID
ALBC
RLBC
TAOE
LOSS
DFMS
LOSIE
DFMIE
LOSIS
DFMIS
SWR
GMC
DLBC
LASCS
ATAOS
GC
TST
TS
OEB
AIS
AISIE
AISIS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
—
16–1E
ADDP
1F
25 of 97
ADDRESS
PARALLEL
SERIAL
INTERFACE
INTERFACE
A7–A0 (HEX)
A7–A1 (HEX)
xxx00000
xx00000
xxx00001
xx00001
xxx00010
xx00010
xxx00011
xx00011
xxx00100
xx00100
xxx00101
xx00101
xxx00110
xx00110
xxx00111
xx00111
xxx01000
xx01000
xxx01001
xx01001
xxx01010
xx01010
xxx01011
xx01011
xxx01100
xx01100
xxx01101
xx01101
xxx01110
xx01110
xxx01111
xx01111
xxx10000
xx10000
xxx10001
xx10001
xxx10010
xx10010
xxx10011
xx10011
xxx10100
xx10100
xxx10101
xx10101
xxx10110–
xx10110–
xxx11110
xx11110
xxx11111
xx11111
RW
R
RW
RW
RW
R
R
RW
RW
R
R
W
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
R
—
RW
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 5-2. Secondary Register Set
NAME
Single Rail-Mode Select
Line Code Selection
Not Used
Receive Power-Down Enable
Transmit Power-Down Enable
Excessive Zero Detect Enable
Code Violation Detect Enable Bar
Not Used
Address Pointer for Secondary Register Set
SYMBOL
HEX
SRMS
LCS
—
RPDE
TPDE
EZDE
CVDEB
00
01
02
03
04
05
06
—
07–1E
ADDP
1F
ADDRESS
PARALLEL
SERIAL
INTERFACE
INTERFACE
A7–A0 (HEX)
A7–A1 (HEX)
xxx00000
xx00000
xxx00001
xx00001
xxx00010
xx00010
xxx00011
xx00011
xxx00100
xx00100
xxx00101
xx00101
xxx00110
xx00110
xxx00111–
xx00111–
xxx11110
xx11110
xxx11111
xx11111
RW
RW
RW
—
RW
RW
RW
RW
—
RW
Table 5-3. Individual LIU Register Set
NAME
Individual JA Enable
Individual JA Position Select
Individual JA FIFO Depth Select
Individual JA FIFO Limit Trip
Individual Short Circuit Protection Disable
Individual AIS Select
Master Clock Select
Global Management Register
SYMBOL
HEX
IJAE
IJAPS
IJAFDS
IJAFLT
ISCPD
IAISEL
MC
GMR
00
01
02
03
04
05
06
07
Reserved
Reserved
08–0B
Reserved
Reserved
0C–0F
BTCR
LVDS
RCLKI
TCLKI
CCR
RDULR
GISC
ADDP
10
12
13
14
15
16
1E
1F
Bit Error Rate Tester Control Register
Line Violation Detect Status
Receive Clock Invert
Transmit Clock Invert
Clock Control Register
RCLK Disable Upon LOS Register
Global Interrupt Status Control
Address Pointer for Secondary Register Set
26 of 97
ADDRESS
PARALLEL
SERIAL
INTERFACE
INTERFACE
A7–A0 (HEX)
A7–A1 (HEX)
xxx00000
xx00000
xxx00001
xx00001
xxx00010
xx00010
xxx00011
xx00011
xxx00100
xx00100
xxx00101
xx00101
xxx00110
xx00110
xxx00111
xx00111
xxx01000–
xx01000–
xxx01011
xx01011
xxx01100–
xx01100–
xxx01111
xx01111
xxx10000
xx10000
xxx10010
xx10010
xxx10011
xx10011
xxx10100
xx10100
xxx10101
xx10101
xxx10110
xx10110
xxx11110
xx11110
xxx11111
xx11111
RW
RW
RW
RW
R
RW
RW
RW
RW
RW
R
RW
R
RW
RW
RW
RW
RW
RW
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 5-4. BERT Register Set
NAME
BERT Control Register
Reserved
BERT Pattern Configuration 1
BERT Pattern Configuration 2
BERT Seed/Pattern 1
BERT Seed/Pattern 2
BERT Seed/Pattern 3
BERT Seed/Pattern 4
Transmit Error Insertion Control
Reserved
BERT Status Register
Reserved
BERT Status Register Latched
BERT Status Register Interrupt Enable
Reserved
Receive Bit Error Count Register 1
Receive Bit Error Count Register 2
Receive Bit Error Count Register 3
Receive Bit Error Count Register 4
Receive Bit Count Register 1
Receive Bit Count Register 2
Receive Bit Count Register 3
Receive Bit Count Register 4
Reserved
Address Pointer for Secondary Register Set
SYMBOL
HEX
BCR
—
BPCR1
BPCR2
BSPR1
BSPR2
BSPR3
BSPR4
TEICR
00
01
02
03
04
05
06
07
08
—
09–0A
BSR
BSRL
BSRIE
0C
0D
0E
10
—
11–13
RBECR1
RBECR2
RBECR3
RBECR4
RBCR1
RBCR2
RBCR3
RBCR4
14
15
16
17
18
19
1A
1B
—
1C–1E
ADDP
1F
27 of 97
ADDRESS
PARALLEL
SERIAL
INTERFACE
INTERFACE
A7–A0 (HEX)
A7–A1 (HEX)
xxx00000
xx00000
xxx00001
xx00001
xxx00010
xx00010
xxx00011
xx00011
xxx00100
xx00100
xxx00101
xx00101
xxx00110
xx00110
xxx00111
xx00111
xxx01000
xx01000
xxx01001–
—
xx01010
xxx01100
xx01100
xxx01101
xx01101
xxx10011
xx10011
xxx10000
xx10000
xxx10001–
xx10001–
xxx10011
xx10011
xxx10100
xx10100
xxx10101
xx10101
xxx10110
xx10110
xxx10111
xx10111
xxx11000
xx11000
xxx11001
xx11001
xxx11010
xx11010
xxx11011
xx11011
xxx11100–
xx11100–
xxx11110
xx11110
xxx11111
xx11111
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
R
RW
RW
—
R
R
R
R
R
R
R
R
—
RW
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 5-5. Primary Register Set Bit Map
REGISTER
ID
ALBC
RLBC
TAOE
LOSS
DFMS
LOSIE
DFMIE
LOSIS
DFMIS
SWR
GMC
DLBC
LASCS
ATAOS
GC
TST
TS
OEB
AIS
AISIE
AISI
Not Used
ADDP
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16-1E
1F
TYPE
R
RW
RW
RW
RW
RW
RW
RW
R
R
W
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
R
—
RW
BIT 7
ID7
ALC8
RLBC8
TAOE8
LOSS8
DFMS8
LOSIE8
DFMIE8
LOSIS8
DFMIS8
SWR8
—
DLBC8
LASCS8
ATAOS8
RIMPMS
—
RIMPOFF
OEB8
AIS8
AISIE8
AISI8
—
ADDP7
BIT 6
ID6
ALBC7
RLBC7
TAOE7
LOSS7
DFMS7
LOSIE7
DFMIE7
LOSIS7
DFMIS7
SWR7
—
DLBC7
LASCS7
ATAOS7
AISEL
—
TIMPOFF
OEB7
AIS7
AISIE7
AISI7
—
ADDP6
BIT 5
ID5
ALBC6
RLBC6
TAOE6
LOSS6
DFMS6
LOSIE6
DFMIE6
LOSIS6
DFMIS6
SWR6
—
DLBC6
LASCS6
ATAOS6
SCPD
—
T1MODE
OEB6
AIS6
AISIE6
AISI6
—
ADDP5
BIT 4
ID4
ALBC5
RLBC5
TAOE5
LOSS5
DFMS5
LOSIE5
DFMIE5
LOSIS5
DFMIS5
SWR5
—
DLBC5
LASCS5
ATAOS5
CODE
—
TIMPRM1
OEB5
AIS5
AISIE5
AISI5
—
ADDP4
BIT 3
ID3
ALBC4
RLBC4
TAOE4
LOSS4
DFMS4
LOSIE4
DFMIE4
LOSIS4
DFMIS4
SWR4
GMC4
DLBC4
LASCS4
ATAOS4
JADS
—
TIMPRM
OEB4
AIS4
AISIE4
AISI4
—
ADDP3
BIT 2
ID2
ALBC3
RLBC3
TAOE3
LOSS3
DFMS3
LOSIE3
DFMIE3
LOSIS3
DFMIS3
SWR3
GMC3
DLBC3
LASCS3
ATAOS3
—
TST2
TS2
OEB3
AIS3
AISIE3
AISI3
—
ADDP2
BIT 1
ID1
ALBC2
RLBC2
TAOE2
LOSS2
DFMS2
LOSIE2
DFMIE2
LOSIS2
DFMIS2
SWR2
GMC2
DLBC2
LASCS2
ATAOS2
JAPS
TST1
TS1
OEB2
AIS2
AISIE2
AISI2
—
ADDP1
BIT 0
ID0
ALBC1
RLBC1
TAOE1
LOSS1
DFMS1
LOSIE1
DFMIE1
LOSIS1
DFMIS1
SWR1
GMC1
DLBC1
LASCS1
ATAOS1
JAE
TST0
TS0
OEB1
AIS1
AISIE1
AISI1
—
ADDP0
BIT 5
SRMS6
LCS6
—
RPDE6
TPDE6
EZDE6
CVDEB6
—
ADDP5
BIT 4
SRMS5
LCS5
—
RPDE5
TPDE5
EZDE5
CVDEB5
—
ADDP4
BIT 3
SRMS4
LSC4
—
RPDE4
TPDE4
EZDE4
CVDEB4
—
ADDP3
BIT 2
SRMS3
LCS3
—
RPDE3
TPDE3
EZDE3
CVDEB3
—
ADDP2
BIT 1
SRMS2
LSC2
—
RPDE2
TPDE2
EZDE2
CVDEB2
—
ADDP1
BIT 0
SRMS1
LSC1
—
RPDE1
TPDE1
EZDE1
CVDEB1
—
ADDP0
BIT 4
IJAE5
IJAPS5
IJAFDS5
IJAFLT5
ISCPD5
IAISEL5
CLKAE
—
—
—
—
—
—
—
—
—
—
BEIR5
LVDS5
RCLKI5
TCLKI5
TECLKS
RDULR5
—
ADDP4
BIT 3
IJAE4
IJAPS4
IJAFDS4
IJAFLT4
ISCPD4
IAISEL4
MPS1
—
—
—
—
—
—
—
—
—
—
BEIR4
LVDS4
RCLKI4
TCLKI4
CLKA3
RDULR4
—
ADDP3
BIT 2
IJAE3
IJAPS3
IJAFDS3
IJAFLT3
ISCPD3
IAISEL3
MPS0
—
—
—
—
—
—
—
—
—
—
BEIR3
LVDS3
RCLKI3
TCLKI3
CLKA2
RDULR3
—
ADDP2
Table 5-6. Secondary Register Set Bit Map
REGISTER
SRS
LCS
Not Used
RPDE
TPDE
EZDE
CVDEB
Not Used
ADDP
ADDRESS
00
01
02
03
04
05
06
07-1E
1F
TYPE
RW
RW
RW
RW
RW
RW
RW
—
RW
BIT 7
SRMS8
LCS8
—
RPDE8
TPDE8
EZDE8
CVDEB8
—
ADDP7
BIT 6
SRMS7
LCS7
—
RPDE7
TDPE7
EZDE7
CVDEB7
—
ADDP6
Table 5-7. Individual LIU Register Set Bit Map
REGISTER
IJAE
IJAPS
IJAFDS
IJAFLT
ISCPD
IAISEL
MC
GMR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
BTCR
BEIR
LVDS
RCLKI
TCLKI
CCR
RDULR
GISC
ADDP
ADDRESS
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
1E
1F
TYPE
RW
RW
RW
R
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
RW
RW
R
RW
RW
RW
RW
RW
RW
BIT 7
IJAE8
IJAPS8
IJAFDS8
IJAFLT8
ISCPD8
IAISEL8
—
—
—
—
—
—
—
—
—
—
BTS2
BEIR8
LVDS8
RCLKI8
TCLKI8
PCLKS2
RDULR8
—
ADDP7
BIT 6
IJAE7
IJAPS7
IJAFDS7
IJAFLT7
ISCPD7
IAISEL7
PCLKI
—
—
—
—
—
—
—
—
—
BTS1
BEIR7
LVDS7
RCLKI7
TCLKI7
PCLKS1
RDULR7
—
ADDP6
BIT 5
IJAE6
IJAPS6
IJAFDS6
IJAFLT6
ISCPD6
IAISEL6
TECLKE
—
—
—
—
—
—
—
—
—
BTS0
BEIR6
LVDS6
RCLKI6
TCLKI6
PCLKS0
RDULR6
—
ADDP5
28 of 97
BIT 1
IJAE2
IJAPS2
IJAFDS2
IJAFLT2
ISCPD2
IAISEL2
FREQS
—
—
—
—
—
—
—
—
—
—
BEIR2
LVDS2
RCLKI2
TCLKI2
CLKA1
RDULR2
INTM
ADDP1
BIT 0
IJAE1
IJAPS1
IJAFDS1
IJAFLT1
ISCPD1
IAISEL1
PLLE
RHPMC
—
—
—
—
—
—
—
—
BERTE
BEIR1
LVDS1
RCLKI1
TCLKI1
CLKA0
RDULR1
CWE
ADDP0
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 5-8. BERT Register Bit Map
REGISTER
ADDRESS
TYPE
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BCR
00
RW
PMUM
LPMU
RNPL
RPIC
MPR
APRD
TNPL
TPIC
Not Used
BPCR1
BPCR2
01
02
03
—
RW
—
—
—
—
—
QRSS
—
—
PTS
—
—
PLF4
PTF4
—
PLF3
PTF3
—
PLF2
PTF2
—
PLF1
PTF1
—
PLF0
PTF0
BSPR1
BSPR2
04
05
RW
—
BSP7
BSP15
BSP6
BSP14
BSP5
BSP13
BSP4
BSP12
BSP3
BSP11
BSP2
BSP10
BSP1
BSP9
BSP0
BSP8
BSPR3
BSPR4
TEICR
06
07
08
RW
—
RW
BSP23
BSP31
—
BSP22
BSP30
—
BSP21
BSP29
TEIR2
BSP20
BSP28
TEIR1
BSP19
BSP27
TEIR0
BSP18
BSP26
BEI
BSP17
BSP25
TSEI
BSP16
BSP24
MEIMS
Not Used
BSR
09–0B
0C
—
R/W
—
—
—
—
—
—
—
—
—
PMS
—
—
—
BEC
—
OOS
Not Used
BSRL
Not Used
0D
0E
0F
—
RL/W
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PMSL
—
—
BEL
—
—
BECL
—
—
OOSL
—
BSRIE
Not Used
RBECR1
10
11–13
14
RW
—
R
—
—
BEC7
—
—
BEC6
—
—
BEC5
—
—
BEC4
PMSIE
—
BEC3
BEIE
—
BEC2
BECIE
—
BEC1
OOSIE
—
BEC0
RBECR2
RBECR3
15
16
R
R
BEC15
BEC23
BEC14
BEC22
BEC13
BEC21
BEC12
BEC20
BEC11
BEC19
BEC10
BEC18
BEC9
BEC17
BEC8
BEC16
Not Used
RBCR1
RBCR2
17
18
19
—
R
R
—
BC7
BC15
—
BC6
BC14
—
BC5
BC13
—
BC4
BC12
—
BC3
BC11
—
BC2
BC10
—
BC1
BC9
—
BC0
BC8
RBCR3
RBCR4
1A
1B
R
R
BC23
BC31
BC22
BC30
BC21
BC29
BC20
BC28
BC19
BC27
BC18
BC26
BC17
BC25
BC16
BC24
Not Used
ADDP
1C–1E
1F
—
RW
—
ADDP7
—
ADDP6
—
ADDP5
—
ADDP4
—
ADDP3
—
ADDP2
—
ADDP1
—
ADDP0
Note: Underlined bits are read-only.
29 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
5.1
Register Description
This section details the register description of each bit. Whenever the variable ‘n’ in italics is used in any of the
register descriptions, it represents 1, 2, 3, 4, 5, 6, 7, and 8.
5.1.1
Primary Registers
ID
ID Register
00h
Register Name:
Register Description:
Register Address:
Bit #
Name
7
ID7
6
ID6
5
ID5
4
ID4
3
ID3
2
ID2
1
ID1
0
ID0
Bit 7: Device CODE ID Bit 7 (ID7). This bit is zero for the 75W impedance part number and one for the 120W
impedance part number.
Bits 6 to 3: Device CODE ID Bits 6 to 3 (ID6 to ID3). These bits tell the user the number of ports the device
contains.
Bits 2 to 0: Device CODE ID Bits 2 to 0 (ID2 to ID0). These bits tell the user the revision of the part. Contact the
factory for details.
ALBC
Analog Loopback Control
01h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ALBC8
0
6
ALBC7
0
5
ALBC6
0
4
ALBC5
0
3
ALBC4
0
2
ALBC3
0
1
ALBC2
0
0
ALBC1
0
Bits 7 to 0: Analog Loopback Control Bits Channel n (ALBCn). When this bit is set, LIUn is placed in analog
loopback. TTIP and TRING are looped back to RTIP and RRING. The data at RTIP and RRING is ignored. LOS
detector is still in operation. The jitter attenuator is in use if enabled for the transmitter or receiver.
RLBC
Remote Loopback Control
02h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RLBC8
0
6
RLBC7
0
5
RLBC6
0
4
RLBC5
0
3
RLBC4
0
2
RLBC3
0
1
RLBC2
0
0
RLBC1
0
Bits 7 to 0: Remote Loopback Control Bits Channel n (RLBCn). When this bit is set, remote loopback is
enabled on LIUn. The analog-received signal goes through the receive digital and is looped back to the
transmitter. The data at TPOS and TNEG is ignored. The jitter attenuator is in use if enabled.
30 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
TAOE
Transmit All-Ones Enable
03h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TAOE8
0
6
TAOE7
0
5
TAOE6
0
4
TAOE5
0
3
TAOE4
0
2
TAOE3
0
1
TAOE2
0
0
TAOE1
0
Bits 7 to 0: Transmit All-Ones Enable Channel n (TAOEn). When this bit is set, a continuous stream of all ones
on TTIP and TRING are sent on channel n. MCLK is used as a reference clock for the transmit all-ones signal. The
data arriving at TPOS and TNEG is ignored.
LOSS
Loss-of-Signal Status
04h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LOS8
0
6
LOS7
0
5
LOS6
0
4
LOS5
0
3
LOS4
0
2
LOS3
0
1
LOS2
0
0
LOS1
0
Bits 7 to 0: Loss-of-Signal Status Channel n (LOSn). When this bit is set, an LOS condition has been detected
on LIUn. The criteria and conditions of LOS are described in Section 6.4.3: Loss of Signal.
DFMS
Driver Fault Monitor Status
05h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
DFMS8
0
6
DFMS7
0
5
DFMS6
0
4
DFMS5
0
3
DFMS4
0
2
DFMS3
0
1
DFMS2
0
0
DFMS1
0
Bits 7 to 0: Driver Fault Monitor Status Channel n (DFMSn). When this bit is set, it indicates that there is a short
circuit at the transmit driver for LIUn.
LOSIE
Loss-of-Signal Interrupt Enable
06h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LOSIE8
0
6
LOSIE7
0
5
LOSIE6
0
4
LOSIE5
0
3
LOSIE4
0
2
LOSIE3
0
1
LOSIE2
0
0
LOSIE1
0
Bits 7 to 0: Loss-of-Signal Interrupt Enable Channel n (LOSIEn). When this bit is set, a change in the LOS
status for LIUn can generate an interrupt.
31 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
DFMIE
Driver Fault Monitor Interrupt Enable
07h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
DFMIE8
0
6
DFMIE7
0
5
DFMIE6
0
4
DFMIE5
0
3
DFMIE4
0
2
DFMIE3
0
1
DFMIE2
0
0
DFMIE1
0
Bits 7 to 0: Driver Fault Monitor Interrupt Enable Channel n (DFMIEn). When this bit is set, a change in DFM
status can generate an interrupt in monitor n.
LOSIS
Loss-of-Signal Interrupt Status
08h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LOSIS8
0
6
LOSIS7
0
5
LOSIS6
0
4
LOSIS5
0
3
LOSIS4
0
2
LOSIS3
0
1
LOSIS2
0
0
LOSIS1
0
Bits 7 to 0: Loss-of-Signal Interrupt Status Channel n (LOSISn). When this bit is set, it indicates an LOS status
has transitioned from a 0 to 1 or 1 to 0 and was detected for LIUn. The bit for LIUn is enabled by register
LOSIE(06h). This bit when latched is cleared on a read operation.
DFMIS
Driver Fault Monitor Interrupt Status
09h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
DFMIS8
0
6
DFMIS7
0
5
DFMIS6
0
4
DFMIS5
0
3
DFMIS4
0
2
DFMIS3
0
1
DFMIS2
0
0
DFMIS1
0
Bits 7 to 0: Driver Fault Status Register Channel n (DFMISn). When this bit is set, it indicates a DFM status has
transitioned from “0 to 1” or “1 to 0” and was detected for LIUn. The bit for LIUn is enabled by register DFMIE(07h).
This bit when latched is cleared on a read operation.
SWR
Software Reset
0Ah
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SWR8
0
6
SWR7
0
5
SWR6
0
4
SWR5
0
3
SWR4
0
2
SWR3
0
1
SWR2
0
0
SWR1
0
Bits 7 to 0: Software Reset (SWR). Whenever any write is performed to this register, at least a 1ms reset will be
generated that resets the DS26303. All the registers will be restored to their default values. A read operation will
always read back all zeros.
32 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
GMC
G.772 Monitoring Control
0Bh
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
GMC3
0
2
GMC2
0
1
GMC1
0
0
GMC0
0
Bits 3 to 0: G.772 Monitoring Control (GMC). These bits are used to select transmitter or receiver for
nonintrusive monitoring. Receiver 1 is used to monitor channels 2 to 8 of one receiver from RTIP2–
RTIP8/RRING2–RRING8 or of one transmitter from TTIP2–TTIP8/TRING2–TRING8. See Table 5-9.
Table 5-9. G.772 Monitoring Control
GMC3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
GMC2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
GMC1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
7
DLBC8
0
SELECTION
No Monitoring
Receiver 2
Receiver 3
Receiver 4
Receiver 5
Receiver 6
Receiver 7
Receiver 8
No Monitoring
Transmitter 2
Transmitter 3
Transmitter 4
Transmitter 5
Transmitter 6
Transmitter 7
Transmitter 8
DLBC
Digital Loopback Control
0Ch
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
GMC0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
6
DLBC7
0
5
DLBC6
0
4
DLBC5
0
3
DLBC4
0
2
DLBC3
0
1
DLBC2
0
0
DLBC1
0
Bits 7 to 0: Digital Loopback Control Channel n (DLBCn). When this bit is set, the LIUn is placed in digital
loopback. The data at TPOS/TNEG is encoded and looped back to the decoder and output on RPOS/RNEG. The
jitter attenuator can optionally be included in the transmit or receive paths.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LASCS8
0
LASCS
LOS/AIS Criteria Selection
0Dh
6
LASCS7
0
5
LASCS6
0
4
LASCS5
0
3
LASCS4
0
2
LASCS3
0
1
LASCS2
0
0
LASCS1
0
Bits 7 to 0: LOS/AIS Criteria Selection Channel n (LASCSn). This bit is used for LOS/AIS selection criteria for
LIUn. In E1 mode if set, these bits use ETSI (300233) mode selections. If reset, these bits use G.775 criteria. In
T1/J1 mode, T1.231 criteria is selected.
33 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
ATAOS
Automatic Transmit All-Ones Select
0Eh
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ATAOS8
0
6
ATAOS7
0
5
ATAOS6
0
4
ATAOS5
0
3
ATAOS4
0
2
ATAOS3
0
1
ATAOS2
0
0
ATAOS1
0
Bit 7 to 0: Automatic Transmit All-Ones Select Channel n (ATAOSn). When this bit is set an all-ones signal is
sent if a loss of signal is detected for LIUn. All-ones signal uses MCLK as the reference clock.
GC
Global Configuration
0Fh
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RIMPMS
0
6
AISEL
0
5
SCPD
0
4
CODE
0
3
JADS
0
2
—
0
1
JAPS
0
0
JAE
0
Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, the internal impedance mode is selected,
so RTIP and RING require no external resistance component. When this mode is selected, the die attach pad on
the bottom of the package should be connected to ground for thermal dissipation. When reset, external impedance
mode is selected so RTIP and RING require external resistance. Note that when in external impedance mode, the
resistance is still adjusted internally for the T1 (100W), J1 (110W), and E1(75W) modes of operation by the template
selected so that only one resistor value is required externally. In E1 (120W), external impedance mode has no need
for any internal adjustment.
Bit 6: AIS Enable During Loss (AISEL). When this bit is set, an AIS is sent to the system side upon detecting an
LOS for each channel. The individual LIU register IAISEL settings are ignored when this bit is set. When reset, the
IAISEL register has control.
Bit 5: Short-Circuit-Protection Disable (SCPD). If this bit is set, the short-circuit protection is disabled for all the
transmitters. The individual LIU register ISCPD settings are ignored when this bit is set. When reset, the ISCPD
register has control.
Bit 4: Code (CODE). If this bit is set, AMI encoder/decoder is selected. The LCS register settings are ignored when
this bit is set. If reset, the LCS register has control.
Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The
settings in the IJAFDS register are ignored if this register is set. If reset, the IJAFDS register has control.
Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the JA is in the receive path, and
when it is default or set low, it is in the transmit path. These settings can be changed for an individual LIU by
settings in register IJAPS. Note that when bit JAE is set, the settings in register IJAPS are ignored.
Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the JA is enabled. The settings in the IJAE register are
ignored if this register is set. If reset, the IJAE register has control.
34 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
TST
Template Select Transmitter Register
10h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
5
—
—
0
4
3
—
—
0
0
0
2
TST2
0
1
TST1
0
0
TST0
0
Bits 2 to 0: TST Template Select Transceiver [2:0] (TST [2:0]). TST[2:0] is used to select the transceiver that the
transmit template select register (hex 11) applies to. See Table 5-10.
Table 5-10. TST Template Select Transmitter Register
TST[2:0]
000
001
010
011
CHANNEL
1
2
3
4
CHANNEL
5
6
7
8
TS
Template Select Register
11h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
TST[2:0]
100
101
110
111
7
RIMPOFF
0
6
TIMPOFF
0
5
—
—
4
—
—
3
TIMPRM
0
2
TS2
0
1
TS1
0
0
TS0
0
Bit 7: Receive Impedance Match Off (RIMPOFF). If this bit is set, all the receive impedance match is turned off.
Bit 6: Transmit Impedance Termination Off (TIMPOFF). If this bit is set, all the internal transmit terminating
impedance is turned off.
Bits 5 and 4: Reserved
Bit 3: Transmit Impedance Receive Match (TIMPRM). This bit selects the internal transmit termination
impedance and receive impedance match for E1 mode and T1/J1 mode. Note: If the part number ends with –120,
then the default is 120W and 75W when set for El mode only.
DEVICE
DS26303L-120
DS26303L-120
DS26303L-75
DS26303L-75
BIT SETTING
0
1
0
1
E1 MODE (W)
120
75
75
120
T1 MODE (W)
100
110
100
110
Bits 2 to 0: Template Selection [2:0] (TS[2:0]). Bits TS[2:0] are used to select E1 or T1/J1 mode, the template,
and the settings for various cable lengths. The impedance termination for the transmitter and impedance match for
the receiver are specified by bit TIMPRM. See Table 5-11 for bit selection of TS[2:0].
35 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 5-11. Template Selection
TS[2:0]
011
100
101
110
111
000
001 and 010
1
CABLE LOSS
(dB)
0–133ft. ABAM
0.6
133–266ft. ABAM
1.2
266–399ft. ABAM
1.8
399–533ft. ABAM
2.4
533–655ft. ABAM
3.0
G.703 coaxial and twisted pair cable
Reserved
—
LINE LENGTH
IMPEDANCE (W)
1
100/110
100/110
100/110
100/110
100/110
75/120
—
OPERATION MODE
T1/J1
T1
T1
T1
T1
E1
—
See TIMPRM bit in SWM or TIMPRM pin in HWM for transmit impedance and receive match selection.
OEB
Output-Enable Bar
12h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
OEB8
0
6
OEB7
0
5
OEB6
0
4
OEB5
0
3
OEB4
0
2
OEB3
0
1
OEB2
0
0
OEB1
0
Bits 7 to 0: Output-Enable Bar Channel n (OEBn). When this bit is set the transmitter output for LIUn is placed in
high impedance. Note that the OE pin overrides this setting when low.
AIS
Alarm Indication Signal Status
13h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
AIS8
0
6
AIS7
0
5
AIS6
0
4
AIS5
0
3
AIS4
0
2
AIS3
0
1
AIS2
0
0
AIS1
0
Bits 7 to 0: Alarm Indication Signal Channel n (AISn). This bit is set when AIS is detected for LIUn. The criteria
for AIS selection is detailed in Section 6.4.4: AIS. The selection of the AIS criteria is done by settings in LASCS
(0D) register.
36 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
AISIE
AIS Interrupt Enable
14h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
AISIE8
0
6
AISIE7
0
5
AISIE6
0
4
AISIE5
0
3
AISIE4
0
2
AISIE3
0
1
AISIE2
0
0
AISIE1
0
Bits 7 to 0: AIS Interrupt Mask Channel n (AISIEn). When this bit is set, interrupts can be generated for LIUn if
AIS status transitions.
AISI
AIS Interrupt
15h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
AISI8
0
6
AISI7
0
5
AISI6
0
4
AISI5
0
3
AISI4
0
2
AISI3
0
1
AISI2
0
0
AISI1
0
Bits 7 to 0: AIS Interrupt Channel n (AISIn). This bit is set when AIS transitions from a 0 to 1 or 1 to 0 and
interrupts are enabled by the AISIE(14) register for LIUn. This bit if set is cleared on a read operation or when the
interrupt-enable register is disabled.
ADDP
Address Pointer
1Fh
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ADDP7
0
6
ADDP6
0
5
ADDP5
0
4
ADDP4
0
3
ADDP3
0
2
ADDP2
0
1
ADDP1
0
0
ADDP0
0
Bits 7 to 0: Address Pointer (ADDP). This pointer is used to switch between pointing to the primary registers, the
secondary registers, individual registers, BERT registers, and all the test registers. See Table 5-12 for bank
selection.
Table 5-12. Address Pointer Bank Selection
ADDP7 TO ADDP0
(HEX)
00
AA
01
02
03
04
05
06
07
08
09
0A
0B
BANK NAME
Primary Bank
Secondary Bank
Individual LIU Bank
BERT Bank
Global Test Bank
LIU1 Test Bank
LIU2 Test Bank
LIU3 Test Bank
LIU4 Test Bank
LIU5 Test Bank
LIU6 Test Bank
LIU7 Test Bank
LIU8 Test Bank
37 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
5.1.2
Secondary Registers
SRMS
Single-Rail Mode Select
00h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
SRMS8
0
6
SRMS7
0
5
SRMS6
0
4
SRMS5
0
3
SRMS4
0
2
SRMS3
0
1
SRMS2
0
0
SRMS1
0
Bits 7 to 0: Single-Rail Mode Select Channel n (SRMSn). When this bit is set, single-rail mode is selected for the
system transmit and receive n. If this bit is reset, dual-rail mode is selected.
LCS
Line Code Selection
01h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LCS8
0
6
LCS7
0
5
LCS6
0
4
LCS5
0
3
LCS4
0
2
LCS3
0
1
LCS2
0
0
LCS1
0
Bits 7 to 0: Line Code Select Channel n (LCSn). When this bit is set, AMI encoding/decoding is selected for
LIUn. If reset B8ZS or HDB3 encoding/decoding is selected for LIUn. Note that if the GC.CODE (0F) register is set
it will ignore this register.
RPDE
Receive Power-Down Enable
03h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RPDE8
0
6
RPDE7
0
5
RPDE6
0
4
RPDE5
0
3
RPDE4
0
2
RPDE3
0
1
RPDE2
0
0
RPDE1
0
Bits 7 to 0: Receive Power-Down Enable Channel n (RPDEn). When this bit is set, the receiver for LIUn is
powered down.
TPDE
Transmit Power-Down Enable
04h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TPDE7
0
6
TPDE6
0
5
TPDE5
0
4
TPDE4
0
3
TPDE3
0
2
TPDE2
0
1
TPDE1
0
0
TPDE0
0
Bits 7 to 0: Transmit Power-Down Enable Channel n(TPDEn). When this bit is set, the transmitter for LIUn is
powered down.
38 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
EZDE
Excessive Zero Detect Enable
05h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
EXZDE8
0
6
EXZDE7
0
5
EXZDE6
0
4
EXZDE5
0
3
EXZDE4
0
2
EXZDE3
0
1
EXZDE2
0
0
EXZDE1
0
Bits 7 to 0: Excessive Zero Detect Enable Channel n (EZDEn). When this bit is reset, excessive zero detection
is disabled for LIUn. When this bit is set, excessive zero detect enable is enabled. Excessive zero detection is only
relevant in single-rail mode with HDB3 or B8ZS encoding.
CVDEB
Code Violation Detect Enable Bar
06h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
CVDEB8
0
6
CVDEB7
0
5
CVDEB6
0
4
CVDEB5
0
3
CVDEB4
0
2
CVDEB3
0
1
CVDEB2
0
0
CVDEB1
0
Bits 7 to 0: Code Violation Detect Enable Bar Channel n (CVDEBn). If this bit is set, code violation detection is
disabled for the LIUn. If this bit is reset, code violation detection is enabled. Code violation detection is only
relevant in single-rail mode with HDB3 encoding. Note that if the GC.CODE register bit is set, it ignored the settings
of this register.
5.1.3
Individual LIU Registers
IJAE
Individual Jitter Attenuator Enable
00h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
IJAE8
0
6
IJAE7
0
5
IJAE6
0
4
IJAE5
0
3
IJAE4
0
2
IJAE3
0
1
IJAE2
0
0
IJAE1
0
Bits 7 to 0: Individual Jitter Attenuator Enable Channel n (IJAEn). When this bit is set, the LIU jitter attenuator
n is enabled. Note that if the GC.JAE register bit is set, this register is ignored.
IJAPS
Individual Jitter Attenuator Position Select
01h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
IJAPS8
0
6
IJAPS7
0
5
IJAPS6
0
4
IJAPS5
0
3
IJAPS4
0
2
IJAPS3
0
1
IJAPS2
0
0
IJAPS1
0
Bits 7 to 0: Individual Jitter Attenuator Position Select Channel n (IJAPSn). When this bit is set high, the jitter
attenuator is in the receive path n, and when this bit is default or set low the jitter attenuator is in the transmit path
n. Note that if the GC.JAE register bit is set, this register is ignored.
39 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
IJAFDS8
0
IJAFDS
Individual Jitter Attenuator FIFO Depth Select
02h
6
IJAFDS7
0
5
IJAFDS6
0
4
IJAFDS5
0
3
IJAFDS4
0
2
IJAFDS3
0
1
IJAFDS2
0
0
IJAFDS1
0
Bits 7 to 0: Individual Jitter Attenuator FIFO Depth Select n (IJAFDSn). When this bit is set for LIUn, the jitter
attenuator FIFO depth is 128 bits. When reset, the jitter attenuator FIFO depth is 32 bits. Note that if the
GC.IJAFDS register is set, this register is ignored.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
IJAFLT8
0
IJAFLT
Individual Jitter Attenuator FIFO Limit Trip
03h
6
IJAFLT7
0
5
IJAFLT6
0
4
IJAFLT5
0
3
IJAFLT4
0
2
IJAFLT3
0
1
IJAFLT2
0
0
IJAFLT1
0
Bits 7 to 0: Individual Jitter Attenuator FIFO Limit Trip n (IJAFLTn). Set when the jitter attenuator FIFO
reaches to within 4 bits of its useful limit for transmitter n. This bit is cleared when read.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
ISCPD8
0
ISCPD
Individual Short-Circuit Protection Disabled
04h
6
ISCPD7
0
5
ISCPD6
0
4
ISCPD5
0
3
ISCPD4
0
2
ISCPD3
0
1
ISCPD2
0
0
ISCPD1
0
Bits 7 to 0: Individual Short-Circuit Protection Disabled n (ISCPDn). When this bit is set, the short-circuit
protection is disabled for the individual transmitter n. Note that if the GC.SCPD register bit is set, the settings in this
register are ignored.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
IAISEL8
0
IAISEL
Individual AIS Select
05h
6
IAISEL7
0
5
IAISEL6
0
4
IAISEL5
0
3
IAISEL4
0
2
IAISEL3
0
1
IAISEL2
0
0
IAISEL1
0
Bits 7 to 0: Individual AIS Enable During Loss n (IAISELn). When this bit is set, individual-AIS-enable during
loss is enabled for the individual receiver n and AIS is sent to the system side upon detection of an LOS. Note that
if the GC.AISEL register bit is set, the settings in this register are ignored.
40 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
MC
Master Clock Select
06h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
PCLKI
0
5
TECLKE
0
4
CLKAE
0
3
MPS1
0
2
MPS0
0
1
FREQS
0
0
PLLE
0
Bit 6: PLL Clock Input (PCLKI). This bit selects the input into to the PLL.
0 = MCLK is used.
1 = RCLK1–RCLK8 is used based on the selection in register CCR.
Bit 5: T1/E1 Clock Enable (TECLKE). When this bit is set the TECLK output is enabled. If not set TECLK is
disabled and the TECLK output is an RLOS output. TECLK requires PLLE to be set for correct functionality.
Bit 4: Clock A Enable (CLKAE). When this bit is set the CLKA output is enabled. If not set CLKA is disabled to tristate. CLKA requires PLLE to be set for correct functionality.
Bits 3 to 2: Master Period Select [1:0] (MPS[1:0]). These bits MPS[1:0] selects the external MCLK frequency for
the DS26303. See Table 5-13 for details.
Bit 1: Frequency Select (FREQS). In conjunction with MPS[1:0], this bit selects the external MCLK frequency for
the DS26303. If this bit is set the external master clock can be 1.544MHz or a multiple thereof. If not set the
external master clock can be 2.048MHz or a multiple thereof. See Table 5-13 for details.
Bit 0: Phase Lock Loop Enable (PLLE). When this bit is set the phase lock loop is enabled. If not set MCLK is the
applied input clock.
Table 5-13. MCLK Selections
PLLE
MPS1, MPS0
0
0
1
1
1
1
1
1
1
1
xx
xx
00
01
10
11
00
01
10
11
7
—
0
FREQS
MODE
x
x
1
1
1
1
0
0
0
0
T1
E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
T1/J1 or E1
GMR
Global Management Register
07h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
MCLK
(MHz/±50ppm)
1.544
2.048
1.544
3.088
6.176
12.352
2.048
4.096
8.192
16.384
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
—
0
0
RHPMC
0
Bit 0: Receive Hitless-Protection Mode Control (RHPMC). This bit when set and, when the OE pin goes low, will
force all the receivers to turn off any internal impedance matching on RTIP and RRING. This is used for hitlessprotection switching when the user would like a system requiring no external relays in the system.
41 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
BTCR
Bit Error-Rate Tester Control Register
10h
Register Name:
Register Description:
Register Address:
Bit #
Name
7
BTS2
6
BTS1
5
BTS0
4
—
Default
0
0
0
0
3
—
0
2
—
0
1
—
0
0
BERTE
0
Bits 7 to 5: Bit Error-Rate Transceiver Select [2:0] (BTS[2:0]). These bits BTS[2:0] select the LIU that the BERT
applies to. This is only applicable if the BERTE bit is set.
Bit 0: Bit Error-Rate Tester Enable (BERTE). When this bit is set, the BERT is enabled. The BERT is only active
for one transceiver at a time selected by BTS[2:0].
BEIR
BPV Error Insertion Register
11h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BEIR8
0
6
BEIR7
0
5
BEIR6
0
4
BEIR5
0
3
BEIR4
0
2
BEIR3
0
1
BEIR2
0
0
BEIR1
0
Bits 7 to 0: BPV Error Insertion Register n (BEIRn). A 0-to-1 transition on this bit causes a single bipolar
violation (BPV) to be inserted into the transmit data stream channel n. This bit must be cleared and set again for a
subsequent error to be inserted.
LVDS
Line Violation Detect Status
12h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
LVDS8
0
6
LVDS7
0
5
LVDS6
0
4
LVDS5
0
3
LVDS4
0
2
LVDS3
0
1
LVDS2
0
0
LVDS1
0
Bits 7 to 0: Line Violation Detect Status n (LVDSn). A bipolar violation, code violation, or excessive zeros cause
the associated LVDSn bit to latch. This bit is cleared on a read operation. The LVDS register captures the first
violation within a three-clock-period window. If a second violation occurs after the first violation within the threeclock-period window, then the second violation will not be latched even if a read to the LVDS register was
performed. Excessive zeros need to be enabled by the EZDE register for detection by this register. Code violations
are only relative when in HDB3 mode and can be disabled for detection by this register by setting the CVDEB
register. In dual-rail mode only bipolar violations are relevant for this register.
42 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
RCLKI
Receive Clock Invert
13h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RCLKI8
0
6
RCLKI7
0
5
RCLKI6
0
4
RCLKI5
0
3
RCLKI4
0
2
RCLKI3
0
1
RCLKI2
0
0
RCLKI1
0
Bits 7 to 0: Receive Clock Invert n (RCLKIn). When this bit is set the RCLK for channel n is inverted. This aligns
RPOS/RNEG on the falling edge of RCLK. When reset or default, RPOS/RNEG is aligned on the rising edge of
RCLK. Note that if the CLKE pin is high, the RPOS/RNEG is set on the falling edge of RCLK regardless of the
settings in the register.
TCLKI
Transmit Clock Invert
14h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
TCLKI8
0
6
TCLKI7
0
5
TCLKI6
0
4
TCLKI5
0
3
TCLKI4
0
2
TCLKI3
0
1
TCLKI2
0
0
TCLKI1
0
Bits 7 to 0: Transmit Clock Invert n (TCLKIn). When this bit is set the expected TCLK for channel n is inverted.
TPOS/TNEG should be aligned on the rising edge of TCLK. When reset or default TPOS/TNEG should be aligned
on the falling edge of TCLK.
43 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
CCR
Clock Control Register
15h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
PCLKS2
0
6
PCLKS1
0
5
PCLKS0
0
4
TECLKS
0
3
CLKA3
0
2
CLKA2
0
1
CLKA1
0
0
CLKA0
0
Bits 7 to 5: PLL Clock Select (PCLKS[2:0]). These bits determine the RCLK that is to be used as the input to the
PLL. If an LOS is detected for the channel that RCLK is recovered from, the PLL switches to MCLK until the LOS is
cleared. When the LOS is cleared, RCLK is used again. See Table 5-14. for RCLK selection.
Table 5-14. PLL Clock Select
PCLKS2 TO
PCLKS0
000
001
010
011
100
101
110
111
PLL CLOCK
SELECTED
MC.PCLKI = 1
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
RCLK8
Bit 4: T1/E1 Clock Select (TECLKS). When this bit is set the T1/E1 clock output is 2.048MHz. When this bit is
reset the T1/E1 clock rate is 1.544MHz.
Bits 3 to 0: Clock A Select (CLKA[3:0]). These bits select the output frequency for CLKA pin. See Table 5-15. for
available frequencies.
Table 5-15. Clock A Select
CLKA3 TO CLKA0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MCLK (Hz)
2.048M
4.096M
8.192M
16.384M
1.544M
3.088M
6.176M
12.352M
1.536M
3.072M
6.144M
12.288M
32k
64k
128k
256k
44 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
RDULR
RCLK Disable Upon LOS Register
16h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
RDULR8
0
6
RDULR7
0
5
RDULR6
0
4
RDULR5
0
3
RDULR4
0
2
RDULR3
0
1
RDULR2
0
0
RDULR1
0
Bits 7 to 0: RCLK Disable Upon LOS Register n (RDULRn). When this bit is set the RCLK for channel n is
disabled upon a loss of signal and set as a low output. When reset or default, RCLK switches to MCLK upon a loss
of signal within 10ms.
GISC
Global Interrupt Status Control
1Eh
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
—
0
2
—
0
1
INTM
0
0
CWE
0
Bit 1: INT Pin Mode (INTM). This bit determines the inactive mode of the INT pin. The INT pin always drives low
when active.
0 = Pin is high impedance when not active.
1 = Pin drives high when not active.
Bit 0: Clear-On-Write Enable (CWE). When this bit is set, the clear-on-write is enabled for all the latched interrupt
status registers. The host processor must write a 1 to the latched interrupt status register bit position before the
particular bit is cleared. Default for all the latched interrupt status registers is to clear on a read.
45 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
5.1.4
BERT Registers
BCR
BERT Control Register
00h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
PMUM
0
6
LPMU
0
5
RNPL
0
4
RPIC
0
3
MPR
0
2
APRD
0
1
TNPL
0
0
TPIC
0
Bit 7: Performance-Monitoring Update Mode (PMUM). When 0, a performance-monitoring update is initiated by
the LPMU register bit. When 1, a performance-monitoring update is initiated by the receive performance-monitoring
update signal (RPMU). Note: If RPMU or LPMU is 1, changing the state of this bit may cause a performancemonitoring update to occur.
Bit 6: Local Performance-Monitoring Update (LPMU). This bit causes a performance-monitoring update to be
initiated if the local performance-monitoring update is enabled (PMUM = 0). A 0-to-1 transition causes the
performance-monitoring registers to be updated with the latest data, and the counters reset (0 or 1). For a second
performance-monitoring update to be initiated, this bit must be set to 0, and back to 1. If LPMU goes low before the
PMS bit goes high, an update might not be performed. This bit has no affect when PMUM = 1.
Bit 5: Receive New Pattern Load (RNPL). A 0-to-1 transition of this bit causes the programmed test pattern
(QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the receive pattern generator. This bit must be
changed to 0 and back to 1 for another pattern to be loaded. Loading a new pattern forces the receive pattern
generator out of the sync state, which causes a resynchronization to be initiated. Note: QRSS, PTS, PLF[4:0},
PTF[4:0], and BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four RXCK clock cycles
after this bit transitions from 0 to 1.
Bit 4: Receive Pattern Inversion Control (RPIC). When 0, the receive incoming data stream is not altered. When
1, the receive incoming data stream is inverted.
Bit 3: Manual Pattern Resynchronization (MPR). A 0-to-1 transition of this bit causes the receive pattern
generator to resynchronize to the incoming pattern. This bit must be changed to 0 and back to 1 for another
resynchronization to be initiated. Note: A manual resynchronization forces the receive pattern generator out of the
sync state.
Bit 2: Automatic Pattern Resynchronization Disable (APRD). When 0, the receive pattern generator
automatically resynchronizes to the incoming pattern if six or more times during the current 64-bit window the
incoming data stream bit and the receive pattern generator output bit did not match. When 1, the receive pattern
generator does not automatically resynchronize to the incoming pattern. Note: Automatic synchronization is
prevented by not allowing the receive pattern generator to automatically exit the sync state.
Bit 1: Transmit New Pattern Load (TNPL). A 0-to-1 transition of this bit causes the programmed test pattern
(QRSS, PTS, PLF[4:0], PTF[4:0], and BSP[31:0]) to be loaded in to the transmit pattern generator. This bit must be
changed to zero and back to one for another pattern to be loaded. Note: QRSS, PTS, PLF[4:0}, PTF[4:0], and
BSP[31:0] must not change from the time this bit transitions from 0 to 1 until four TXCK clock cycles after this bit
transitions from 0 to 1.
Bit 0: Transmit Pattern Inversion Control (TPIC). When 0, the transmit outgoing data stream is not altered.
When 1, the transmit outgoing data stream is inverted.
46 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
BPCR1
BERT Pattern Configuration Register 1
02h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
QRSS
0
5
PTS
0
4
PLF4
0
3
PLF3
0
2
PLF2
0
1
PLF1
0
0
PLF0
0
Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
20
17
generating polynomial of x + x + 1. The output of the pattern generator is forced to one if the next 14 output bits
are all 0.
Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). These bits control the “length” feedback of the pattern
generator. The length feedback is from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal, the
feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
BPCR 2
BERT Pattern Configuration Register 2
03h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
PTF4
0
3
PTF3
0
2
PTF2
0
1
PTF1
0
0
PTF0
0
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]). These bits control the PRBS “tap” feedback of the pattern
generator. The tap feedback is from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored when
programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
47 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
BSPR1
BERT Seed/Pattern Register #1
04h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BSP7
0
6
BSP6
0
7
BSP15
0
6
BSP14
0
7
BSP23
0
6
BSP22
0
7
BSP31
0
2
BSP2
0
1
BSP1
0
0
BSP0
0
5
BSP13
0
4
BSP12
0
3
BSP11
0
2
BSP10
0
1
BSP9
0
0
BSP8
0
5
BSP21
0
4
BSP20
0
3
BSP19
0
2
BSP18
0
1
BSP17
0
0
BSP16
0
2
BSP26
0
1
BSP25
0
0
BSP24
0
BSPR4
BERT Seed/Pattern Register #4
07h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
3
BSP3
0
BSPR3
BERT Seed/Pattern Register #3
06h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
4
BSP4
0
BSPR2
BERT Seed/Pattern Register #2
05h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
5
BSP5
0
6
BSP30
0
5
BSP29
0
4
BSP28
0
3
BSP27
0
Bits 31 to 0: BERT Seed/Pattern (BSP[31:0]). These 32 bits are the programmable seed for a transmit PRBS
pattern, or the programmable pattern for a transmit or receive repetitive pattern. BSP(31) is the first bit output on
the transmit side for a 32-bit repetitive pattern or 32-bit length PRBS. BSP(31) is the first bit input on the receive
side for a 32-bit repetitive pattern.
48 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
TEICR
Transmit Error-Insertion Control Register
08h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
—
0
5
TEIR2
0
4
TEIR1
0
3
TEIR0
0
2
BEI
0
1
TSEI
0
0
MEIMS
0
Bits 5 to 3: Transmit Error-Insertion Rate (TEIR[2:0]). These bits indicate the rate at which errors are inserted in
n
the output data stream. One out of every 10 bits is inverted. TEIR[2:0] is the value n. A TEIR[2:0] value of 0
disables error insertion at a specific rate. A TEIR[2:0] value of 1 result in every 10th bit being inverted. A TEIR[2:0]
value of 2 result in every 100th bit being inverted. Error insertion starts when this register is written to with a
TEIR[2:0] value that is non-zero. If this register is written to during the middle of an error insertion process, the new
error rate will be started after the next error is inserted.
Bit 2: Bit-Error-Insertion Enable (BEI). When 0, single bit-error insertion is disabled. When 1, single bit-error
insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI). This bit causes a bit error to be inserted in the transmit data stream if
manual error insertion is disabled (MEIMS = 0) and single bit-error insertion is enabled. A 0-to-1 transition causes a
single bit error to be inserted. For a second bit error to be inserted, this bit must be set to 0, and back to 1. Note: If
MEIMS is low, and this bit transitions more than once between error insertion opportunities, only one error is
inserted.
Bit 0: Manual-Error Insert-Mode Select (MEIMS). When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual-error-insertion signal (TMEI). Note: If TMEI or TSEI is 1,
changing the state of this bit may cause a bit error to be inserted.
BSR
BERT Status Register
0Ch
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
PMS
0
2
—
0
1
BEC
0
0
OOS
0
Bit 3: Performance-Monitoring Update Status (PMS). This bit indicates the status of the receive performancemonitoring register (counters) update. This bit transitions from low to high when the update is completed. PMS is
asynchronously forced low when the LPMU bit (PMUM = 0) or RPMU signal (PMUM = 1) goes low.
Bit 1: Bit Error Count (BEC). When 0, the bit error count is 0. When 1, the bit error count is 1 or more.
Bit 0: Out of Synchronization (OOS). When 0, the receive pattern generator is synchronized to the incoming
pattern. When 1, the receive pattern generator is not synchronized to the incoming pattern.
49 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
BSRL
BERT Status Register Latched
0Eh
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
PMSL
0
2
BEL
0
1
BECL
0
0
OOSL
0
Bit 3: Performance-Monitoring Update Status Latched (PMSL). This bit is set when the PMS bit transitions from
0 to 1. A read operation clears this bit.
Bit 2: Bit Error Latched (BEL). This bit is set when a bit error is detected. A read operation clears this bit.
Bit 1: Bit-Error Count Latched (BECL). This bit is set when the BEC bit transitions from 0 to 1. A read operation
clears this bit.
Bit 0: Out-of-Synchronization Latched (OOSL). This bit is set when the OOS bit changes state. A read operation
clears this bit.
BSRIE
BERT Status Register Interrupt Enable
10h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
—
0
6
—
0
5
—
0
4
—
0
3
PMSIE
0
2
BEIE
0
1
BECIE
0
0
OOSIE
0
Bit 3: Performance-Monitoring Update Status-Interrupt Enable (PMSIE). This bit enables an interrupt if the
PMSL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Bit-Error-Interrupt Enable (BEIE). This bit enables an interrupt if the BEL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Bit-Error-Count Interrupt Enable (BECIE). This bit enables an interrupt if the BECL bit is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 0: Out-of-Synchronization Interrupt Enable (OOSIE). This bit enables an interrupt if the OOSL bit is set.
0 = interrupt disabled
1 = interrupt enabled
50 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
RBECR1
Receive Bit-Error-Count Register #1
14h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BEC7
0
6
BEC6
0
7
BEC15
0
6
BEC14
0
7
BEC23
0
3
BEC3
0
2
BEC2
0
1
BEC1
0
0
BEC0
0
5
BEC13
0
4
BEC12
0
3
BEC11
0
2
BEC10
0
1
BEC9
0
0
BEC8
0
2
BEC18
0
1
BEC17
0
0
BEC16
0
RBECR3
Receive Bit-Error-Count Register #2
16h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
4
BEC4
0
RBECR2
Receive Bit-Error-Count Register #1
15h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
5
BEC5
0
6
BEC22
0
5
BEC21
0
4
BEC20
0
3
BEC19
0
Bits 23 to 1: Bit Error Count (BEC[23:0]). These 24 bits indicate the number of bit errors detected in the incoming
data stream. This count stops incrementing when it reaches a count of FF FFFFh. The associated bit-error counter
is not incremented when an OOS condition exists.
51 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
RBCR1
Receive Bit Count Register #1
18h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
7
BC7
0
6
BC6
0
15
BC15
0
14
BC14
0
7
BC23
0
6
BC22
0
15
BC31
0
2
BC2
0
1
BC1
0
0
BC0
0
13
BC13
0
12
BC12
0
11
BC11
0
10
BC10
0
9
BC9
0
8
BC8
0
5
BC21
0
4
BC20
0
3
BC19
0
2
BC18
0
1
BC17
0
0
BC16
0
11
BC27
0
10
BC26
0
9
BC25
0
8
BC24
0
RBCR4
Receive Bit Count Register #4
1Bh
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
3
BC3
0
RBCR3
Receive Bit Count Register #3
1Ah
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
4
BC4
0
RBCR2
Receive Bit Count Register #2
19h
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
5
BC5
0
14
BC30
0
13
BC29
0
12
BC28
0
Bits 31 to 0: Bit Count (BC[31:0]). These 32 bits indicate the number of bits in the incoming data stream. This
count stops incrementing when it reaches a count of FFFF FFFFh. The associated bit counter is not incremented
when an OOS condition exists.
52 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6 FUNCTIONAL DESCRIPTION
6.1
Power-Up and Reset
Internal Power_On_Reset circuitry generates a reset during power-up. All registers are reset to the default values.
Writing to the software-reset register generates at least 1ms reset cycle, which has the same effect as the power-up
reset. A reset can also be performed in software by writing to SWR register.
6.2
Master Clock
The DS26303 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or multiple thereof. The receiver uses the MCLK
as a reference for clock recovery, jitter attenuation, and generating RCLK during LOS. The AIS transmission uses
MCLK for transmit all-ones condition. See register MC to set desired incoming frequency. If the PLLE bit is not set,
MCLK is whatever the incoming frequency is.
MCLK or RCLK can also be used to output CLKA. Register CCR is used to select the clock generated for CLKA
and the TECLK. Any RCLK can also be selected as an input to the clock generator using this same register. For a
detailed description of selections available, see Figure 6-1.
Figure 6-1. Pre-Scaler PLL and Clock Generator
PCLKS2..0
RLCK1..8
CLKA3..0
PLLE
RLOS16
PCLKI1..0
T1CLK
MPS1..0
MCLK
CLKAE
FREQS
CLK
GEN
Pre
Scaler
PLL
CLKA
CLKAI
E1CLK
TECLKI
TECLK
PLLE
TECLKS
TECLKE
RLOS1
53 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.3
Transmitter
NRZ data arrives on TPOS and TNEG on the transmit system side. The TPOS and TNEG data is sampled on the
falling edge of TCLK (Figure 10-12).
The data is encoded with HDB3 or B8ZS or NRZ encoding when single-rail mode is selected (only TPOS as the
data source). When in single-rail mode only, BPV errors can be inserted for test purposes by register BEIR.
Preencoded data is expected when dual-rail mode is selected. The encoded data passes through a jitter attenuator
if it is enabled for the transmit path. A digital sequencer and DAC generate transmit waveforms compliant with
T1.102 and G.703 pulse masks.
A line driver drives an internal matched-impedance circuit for provision of 100W, 110W, 120W, and 75W termination.
The DS26303 drivers have short-circuit driver-fail-monitor detection. There is an OE pin that can high-Z the
transmitter outputs for protection switching. The individual transmitters can be placed in high impedance by register
OEB. The DS26303 also has functionality for powering down the transmitters individually. The registers that control
the transmitter operation are shown in Table 6-3.
Table 6-1. Telecommunications Specification Compliance for DS26303 Transmitters
TRANSMITTER FUNCTION
AMI Coding, B8ZS Substitution, DS1 Electrical
Interface
T1 Telecom Pulse Mask Compliance
T1 Telecom Pulse Mask Compliance
Transmit Electrical Characteristics for E1
Transmission and Return Loss Compliance
TELECOMMUNICATIONS COMPLIANCE
ANSI T1.102
ANSI T1.403
ANSI T1.102
ITUT G.703
Table 6-2. Registers Related to Control of DS26303 Transmitters
REGISTER NAME
ACRONYM
Transmit All-Ones Enable
TAOE
Transmit All-Ones Enable.
Driver Fault Monitor Status
DFMS
Driver Fault Status.
Driver Fault Monitor Interrupt Enable
DFMIE
Driver Fault Status Interrupt Mask.
Driver Fault Monitor Interrupt Status
DFMIS
Global Configuration Register
GC
Driver Fault Status Interrupt Mask.
Selection of the jitter attenuator in the transmit receive or not
used and code for B8ZS or HDB3 substitution.
Template Select Transmitter
TST
Template Select
TS
Output Enable Configuration
Register
Master Clock Selection
OEB
MC
Single-Rail Mode Select Register
SRMS
Line Code Selection
LCS
Transmit Power-Down
Individual Short-Circuit-Protection
Disable
TPDE
BERT Control Register
ISCPD
BTCR
FUNCTION
The transmitter that the template select applies to.
The TS2 to TS0 bits for selection of the templates for
transmitter and match impedance for the receiver.
This bits can be used to place the transmitter outputs in highimpedance mode.
Selects the MCLK frequency used for transmit and receive.
This register can be used to select between single-rail and
dual-rail mode.
The individual LIU line codes can be selected to overwrite
the global setting.
Individual transmitters can be powered down.
This register allows the individual transmitters short-circuit
protection disable.
This register is used for sending different BERT patterns for
the individual transmitters.
54 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.3.1
Transmit Line Templates
The DS26303 the transmitters can be selected individually to meet the pulse masks for E1 and T1/J1 mode. The
T1/J1 pulse mask is shown in the transmit pulse template and can be configured on an individual LIU basis. The
TIMPRM pin/bit is used to select the internal transmit terminating impedance of 100W/110W for T1/J1 mode or
75W/120W for E1 mode. The T1 pulse mask is shown in Figure 6-2 and the E1 pulse template is shown in
Figure 6-3.
Table 6-3. DS26303 Template Selections
TS2, TS1, TS0
000
001
010
011
100
101
110
111
APPLICATION
E1
Reserved
DSX-1 (0-133 ft)
DSX-1 (133-266 ft)
DSX-1 (266-399 ft)
DSX-1 (399-533 ft)
DSX-1 (533-655 ft)
Figure 6-2. T1 Transmit Pulse Templates
1 .2
1 .1
1 .0
0 .9
0 .8
NORMALIZEDAMPLITUDE
0 .7
0 .6
0 .5
0 .4
0 .3
0 .2
0 .1
0
-0 .1
T 1 .1 0 2 / 8 7 , T 1 .4 0 3 ,
C B 1 1 9 (O c t. 7 9 ), &
I.4 3 1 T e m p la te
-0 .2
-0 .3
-0 .4
-0 .5
-5 0 0
-4 0 0
-3 0 0
-2 0 0
-1 0 0
0
100
200
T IM E (n s )
D S X -1 T e m p la te (p e r A N S I T 1 .1 0 2 -1 9 9 3 )
M A X IM U M C U R V E
UI
T im e
Am p.
- 0 .7 7
- 0 .3 9
- 0 .2 7
- 0 .2 7
- 0 .1 2
0 .0 0
0 .2 7
0 .3 5
0 .9 3
1 .1 6
-5 0 0
-2 5 5
-1 7 5
-1 7 5
-7 5
0
175
225
600
750
0 .0 5
0 .0 5
0 .8 0
1 .1 5
1 .1 5
1 .0 5
1 .0 5
- 0 .0 7
0 .0 5
0 .0 5
M IN IM U M C U R V E
UI
T im e
Am p.
- 0 .7 7
- 0 .2 3
- 0 .2 3
- 0 .1 5
0 .0 0
0 .1 5
0 .2 3
0 .2 3
0 .4 6
0 .6 6
0 .9 3
1 .1 6
-5 0 0
-1 5 0
-1 5 0
-1 0 0
0
100
150
150
300
430
600
750
- 0 .0 5
- 0 .0 5
0 .5 0
0 .9 5
0 .9 5
0 .9 0
0 .5 0
- 0 .4 5
- 0 .4 5
- 0 .2 0
- 0 .0 5
- 0 .0 5
300
400
500
600
D S 1 T e m p l a t e ( p e r A N S I T 1 .4 0 3 - 1 9 9 5 )
M A X IM U M C U R V E
UI
T im e
Am p.
- 0 .7 7
- 0 .3 9
- 0 .2 7
- 0 .2 7
- 0 .1 2
0 .0 0
0 .2 7
0 .3 4
0 .7 7
1 .1 6
55 of 97
-5 0 0
-2 5 5
-1 7 5
-1 7 5
-7 5
0
175
225
600
750
0 .0 5
0 .0 5
0 .8 0
1 .2 0
1 .2 0
1 .0 5
1 .0 5
- 0 .0 5
0 .0 5
0 .0 5
M IN IM U M C U R V E
UI
T im e
Am p.
- 0 .7 7
- 0 .2 3
- 0 .2 3
- 0 .1 5
0 .0 0
0 .1 5
0 .2 3
0 .2 3
0 .4 6
0 .6 1
0 .9 3
1 .1 6
-5 0 0
-1 5 0
-1 5 0
-1 0 0
0
100
150
150
300
430
600
750
- 0 .0 5
- 0 .0 5
0 .5 0
0 .9 5
0 .9 5
0 .9 0
0 .5 0
- 0 .4 5
- 0 .4 5
- 0 .2 6
- 0 .0 5
- 0 .0 5
700
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 6-3 E1 Transmit Pulse Templates
1.2
1.1
269ns
SCALED AMPLITUDE
(in 75 ohm systems, 1.0 on the scale = 2.37Vpeak
in 120 ohm systems, 1.0 on the scale = 3.00Vpeak)
1.0
0.9
0.8
0.7
G.703
Template
194ns
0.6
0.5
219ns
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-250
-200
-150
-100
-50
0
TIME (ns)
56 of 97
50
100
150
200
250
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.3.2
LIU Transmit Front End
It is recommended to configure the transmitter’s LIU as described in Figure 6-4 and in Table 6-4. No series
resistors are required. The transmitter has internal termination for E1, J1, and T1 modes.
Figure 6-4. LIU Front End
3.3V
TFt
1:2
Dt
TVDDn
C1
TTIP
Dt
C2
Tx Line
Ct
Dt
TVSSn
TRING
Dt
DS26303
(One Channel)
3.3V
AVDDn
C3
TFr
1:2
RTIP
Rt
C4
A75 A100 A110
AVSSn
30
C5
Rx Line
Rt
RRING
3.3V
TVS1
Table 6-4. LIU Front-End Values
MODE
COMPONENT
Tx Capacitance
Ct
Tx Protection
Dt
Rx Transformer 1:2
Tx Transformer 1:2
Tx Decoupling (ATVDD)
Tx Decoupling (ATVDD)
Rx Decoupling (AVDDn)
Rx Decoupling (AVDDn)
TFr
TFt
C1
C2
C3
C4
Rx Termination
C5
Rx Termination
Rt
Voltage Protection
TVS1
75W COAX
120W TWISTED
PAIR
100W/110W
TWISTED PAIR
560pF typical. Adjust for board parasitics for optimal return loss.
International Rectifier: 11DQ04 or 10BQ060
Motorola: MBR0540T1
Pulse: T1124 (0°C to +70°C)
Pulse: T1114 (-40°C to +85°C)
Common decoupling for all eight channels is 68mF.
Recommended decoupling per channel is 0.1mF.
Common decoupling for all eight channels is 68mF.
Common decoupling for all eight channels is 0.1mF.
When in external impedance mode, Rx capacitance for all eight
channels is 0.1mF. Do not populate if using internal impedance
mode.
When in external impedance mode, the two resistors for all modes
are 15.0W ±1%. Do not populate if using internal impedance mode.
SGS-Thomson: SMLVT 3V3 (3.3V transient suppressor)
57 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.3.3
Dual-Rail Mode
Dual-rail mode consists of TPOS, TNEG, and TCLK pins on the system side. NRZ data is sampled on the falling
edge of TCLK as shown in Figure 10-12. The zero substitution B8ZS or HDB3 is not allowed. The TPOS/TNEG
data is encoded in AMI format on the TTIP and TRING pins. The data that appears on the TPOS pin is output on
TTIP and data on the TRING is output on TRING after pulse shaping. The single-rail-select register (SRMS) is
used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS and TNEG can be overwritten
in the maintenance mode by setting the BERT Control Register (BTCR).
6.3.4
Single-Rail Mode
Single-rail mode consists of TPOS, TNEG, and TCLK pins on the system side. NRZ data is sampled on the falling
edge of TCLK as shown in Figure 10-12. The zero substitution B8ZS or HDB3 is allowed. The TPOS data is
encoded in AMI format on the TTIP and TRING pins after pulse shaping. The single-rail-mode select (SRMS) is
used for selection of dual-rail or single-rail mode. The data that arrives at the TPOS can be overwritten in the
maintenance mode by setting in BERT control register (BTCR).
6.3.5
Zero Suppression—B8ZS or HDB3
B8ZS coding is available when the device is in T1 mode selected by the TS2, TS1, and TS0 bits in the TS register.
Setting the LCS bit in the LCS register enables B8ZS. Note that if the individual LIU is configured in E1 mode, then
HDB3 code substitution can be selected. Bipolar violations can be inserted via the TNEG/BPVI pin or transmit
maintenance register settings only if B8ZS or HDB3 coding is turned off. B8ZS substitution is defined in ANSI
T1.102 and HDB3 in ITUT G.703 standards.
6.3.6
Transmit Power-Down
The transmitter is powered down if the relevant bits in the TPDE register are set.
6.3.7
Transmit All Ones
When transmit all ones is invoked, continuous 1s are transmitted using MCLK as the timing reference. Data input at
TPOS and TNEG is ignored. Transmit all ones can be sent by setting bits in the TAOE register. Transmit all ones
are enabled if bits in register ATAOS are set and the corresponding receiver goes into an LOS state in the status
register LOSS.
6.3.8
Drive Failure Monitor
The Driver Fail Monitor is connected to the TTIP and TRING pins. It will detect a Short Circuit on the Secondary
side of the Transmit Transformer. The drive current will be limited to 50 ma if a short circuit is detected. The DFMS
status registers and the corresponding Interrupt and Enable Registers can be used to monitor the driver failure.
6.4
Receiver
The DS26303’s eight receivers are all identical. A 2:1 transformer steps down the input from the line. The DS26303
is designed to be fully software-selectable for E1 and T1/J1 without the need to change any external resistors for
the receive side. The output of the internal termination circuitry is fed into a peak detector.
The peak detector and data slicer process the received signal. The output of the data slicer goes to clock and data
recovery. A 2.048/1.544 PLL is internally multiplied by 8 by another internal PLL and fed to the clock recovery
system derives E1 or T1 clock. The clock-recovery system uses the clock from the PLL circuit to form an 8-times
oversampler, which is used to recover the clock and data. This oversampling technique offers outstanding
performance to meet jitter tolerance specifications. Depending on selection options, B8ZS/HDB3/AMI decoding is
performed. These decoded data is provided to the system side in either single-rail or dual-rail mode. The selection
of single rail or dual rail is done by settings in the SRMS register.
6.4.1
Peak Detector and Slicer
The slicer determines the polarity and presence of the received data. The output of the slicer is sent to the clock
and data recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for determination
of the slicing threshold.
58 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.4.2
Clock and Data Recovery
The resultant E1 or T1 clock derived from the 2.048/1.544 PLL (JACLK in) is internally multiplied by 16 by another
internal PLL and fed to the clock recovery system. The clock recovery system uses the clock from the PLL circuit to
form a 16-times oversampler, which is used to recover the clock and data. This oversampling technique offers
outstanding performance to meet jitter tolerance specifications.
6.4.3
Loss of Signal
The DS26303 uses both the digital and analog loss-detection method in compliance with the latest T1.231 for
T1/J1 and ITU G.775 or ETSI 300 233 for E1 mode of operation.
LOS is detected if the receiver level falls bellow a threshold analog voltage for a certain duration. Alternatively, this
can be termed as having received zeros for a certain duration. The signal level and timing duration are defined in
accordance with the T1.231 or G.775 or ETSI 300 233 specifications.
The loss-detection thresholds are based on cable loss of 15dB for both T1 and E1 mode. RCLK is replaced by
MCLK when the receiver detects a loss of signal if the AISEL bit is set in the GC register, or if the IAISEL.ILAISE bit
is set. The RPOS/RNEG data is replaced by an all-ones signal upon receiving an LOS to indicate AIS to the
downstream device. The loss state is exited when the receiver detects a certain number of ones density at a higher
signal level than the loss-detection level. The loss-detection-signal level and loss-reset-signal level are defined with
a hysteresis to prevent the receiver from bouncing between LOS and no-LOS states.
The following table outlines the specifications governing the loss function.
Table 6-5. Loss Criteria T1.231, G.775, and ETSI 300 233 Specifications
CRITERIA
T1.231
Loss
Detection
No pulses are detected for 175
±75 bits.
Loss Reset
Loss is terminated if a duration of
12.5% ones are detected over
duration of 175 ±75 bits. Loss is
not terminated if eight consecutive
0s are found if B8ZS encoding is
used. If B8ZS is not used, loss is
not terminated if 100 consecutive
pulses are 0.
6.4.3.1
STANDARD
ITU G.775
No pulses are detected for
duration of 10 to 255 bit
periods.
The incoming signal has
transitions for duration of 10
to 255 bit periods.
ETSI 300 233
No pulses are detected for a
duration of 2048 bit periods or
1ms,
Loss reset criteria is not
defined.
ANSI T1.231 for T1 and J1 Modes
Loss is detected if the received signal level is less than 200mV for duration of 192 bit periods. LOS is reset if the all
of the following criteria are met:
·
·
·
6.4.3.2
24 or more 1s are detected in a 192-bit period with a detection threshold of 300mV measured
at RTIP and RRING.
During the 192 bits less than 100 consecutive zeros are detected.
Eight consecutive 0s are not detected if B8ZS is set.
ITU G.775 for E1 Modes
LOS is detected if the received signal level is less than 200mV for a continuous duration of 192 bit periods. LOS is
reset if the receive signal level is greater than 300mV for a duration of 192 bit periods.
6.4.3.3
ETSI 300 233 for E1 Modes
LOS is detected if the received signal level is less than 200mV for a continuous duration of 2048 (1ms) bit periods.
LOS is reset if the receive signal level is greater than 300mV for a duration of 192 bit periods.
59 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.4.4
AIS
Table 6-6 outlines the DS26303 AIS-related specifications. Table 6-7 states the AIS functionality in the DS26303.
The registers related to the AIS detection are shown in Table 6-8.
Table 6-6. AIS Criteria T1.231, G.775, and ETSI 300 233 Specifications
CRITERIA
STANDARD
ETSI 300233 FOR E1
ITU G.775 FOR E1
AIS
Detection
Two or fewer 0s in each of two
consecutive 512-bit streams
received.
Fewer than three 0s detected
in 512-bit period.
AIS
Clearance
Three or more 0s in each of two
consecutive 512-bit streams
received.
Three or more 0s in a 512-bit
period received.
ANSI T1.231 FOR T1
Fewer than nine 0s detected
in a 8192-bit period (a ones
density of 99.9% over a period
of 5.3ms) are received.
Nine or more 0s detected in a
8192-bit period are received.
Table 6-7. AIS Detection and Reset Criteria
CRITERIA
STANDARD
ETSI 300233 FOR E1
ITU G.775 FOR E1
ANSI T1.231 FOR T1
AIS
Detection
Two or fewer 0 in each of two
consecutive 512-bit streams
received.
Fewer than three 0s detected
in 512-bit period.
Fewer than nine 0s contained
in 8192 bits.
AIS
Clearance
Three or more 0s in each of two
consecutive 512-bit streams
received.
Three or more 0s in a 512-bit
period received.
Nine or more bits received in a
8192-bit stream.
Table 6-8. Registers Related to AIS Detection
REGISTER
ACRONYM POINTER
LOS/AIS Criteria
LASCS
AIS Register
AIS
AIS Enable Register
AISIE
AIS Interrupt
AISI
FUNCTIONALITY
Section criteria for AIS. T1.231,
G.775, ETSI 300233 for E1.
Set when AIS is detected.
If reset interrupt due to AIS is not
generated.
Latched if there is a change in AIS
and the Interrupt is enabled.
60 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.4.5
Bipolar Violation and Excessive Zero Detector
The DS26303 detects code violations, BPV, and excessive zero errors. The reporting of the errors is done through
the pin RNEGn/CVn.
Excessive zeros are detected if eight consecutive 0s are detected with B8ZS enabled and four consecutive 0s are
detected with HDB3 enabled. Excessive zero detection is selectable when single-rail mode and HDB3/B8ZS
encoding/decoding is selected.
The bits in EZDE and CVDEB registers determine the combinations that are reported. Table 6-9 outlines the
functionality:
Table 6-9. BPV, Code Violation, and Excessive Zero Error Reporting
CONDITIONS
EZDE is reset, CVDEB is reset
EZDE is set, CVDEB is reset
EZDE is reset, CVDEB is set
EZDE is set, CVDEB is set
6.4.6
CVn PIN REPORTS
BPV + code violation
BPV + code violation + excessive zero
BPV
BPV + excessive zero
LIU Receiver Front End
It is recommended that the receiver be configured as per Table 6-4 and Figure 6-4. Internal or external mode for
the receiver front end can be selected by register GC.RIMPMS. When this bit is set to external mode the user is
required to supply two 15W resistors as shown in Figure 6-4. The internal adjust resistors A75, A100, and A110 will
still be set in external mode if 75W, 100W, or 110W impedance is selected during template selection. However, the
internal 30W resistor will be disconnected. If the user would like all the adjust resistors to be disconnected or any
internal impedance matching, then the user should set the TS.RIMPOFF bit for each LIU or the RIMPOFF pin when
in hardware mode.
6.5
Hitless-Protection Switching (HPS)
Many current redundancy protection implementations use mechanical relays to switch between primary and
backup boards. The switching time in relays is typically in the milliseconds, making T1/E1 HPS impossible. The
switching event likely causes frame-synchronization loss in any equipment downstream, affecting the quality of
service. The same is also true for tri-stating mechanisms that use software or inactive clocks for the triggering of
HPS.
The DS26303 LIU includes fast tri-statable outputs for TTIP and TRING and fast turn-off impedance matching for
the RTIP and RRING within less than one bit cycle. The control logic is shown in Figure 6-5. In software mode, the
user can set the RHPMC bit, which allows the OE pin to control both the transmitter outputs and the receive
impedance matching. This is a very useful function in that control can be done through a hardware pin, allowing a
quick switch to the backup system for both the receiver and the transmitter. Figure 6-6 shows a typical HPS
application in software mode where the OE is used for control. In hardware mode, the receiver can have
impedance matching turned off quickly by using the RIMPOFF pin, and the transmitter output can be turned off
quickly by using the OE pin.
61 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 6-5. HPS Logic
D
SET
CLR
OEB
Q
int_oe_off
Q
OE
D
SET
Q
Rint_imp_off
RHPMC
CLR
D
SET
CLR
Q
Q
RIMPOFF
Q
hw/sw
mode
RIMPOFF
Figure 6-6. HPS Block Diagram
RTIP
RRING
Primary
Board
OE
TTIP
TRING
RX
Line Interface
Card
Switching
Control
TX
OE
RTIP
RRING
Backup
Board
TTIP
TRING
62 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.6
Jitter Attenuator
The DS26303 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits by the JADS
bit in register GC. It can also be controlled on an individual LIU basis by settings in the IJAFDS register. The 128bit mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in delaysensitive applications. The characteristics of the attenuation are shown in Figure 6-7. The jitter attenuator can be
placed in either the receive path or the transmit path or none by appropriately setting the JAPS and the JAE bits in
register GC. These selections can be changed on an individual LIU basis by settings in the IJAPS and IJAE.
For the jitter attenuator to properly operate, a 2.048MHz or multiple thereof, or 1.544MHz clock or multiple thereof
must be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1
applications. TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. On-board circuitry adjusts
either the recovered clock from the clock/data recovery block or the clock applied at the TCLK pin to create a
smooth jitter-free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming jitter
exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), then the DS26303 divides the
internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17 instead of the normal 16 to keep the
buffer from overflowing. When the device divides by either 15 or 17, it also sets the jitter attenuator limit trip (JFLT)
bits in the IJAFLT register described.
Figure 6-7. Jitter Attenuation
ITU G.7XX
Prohibited Area
TBR12
Prohibited
Area
-20dB
C
ve
ur
A
E1
T1
-40dB
TR 62411 (Dec. 90)
Prohibited Area
B
rve
Cu
JITTER ATTENUATION (dB)
0dB
-60dB
1
10
100
1K
FREQUENCY (Hz)
63 of 97
10K
100K
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.7
G.772 Monitor
In this application, only seven LIUs are functional and one LIU is used for nonintrusive monitoring of input and
output of the other seven channels. Channel 1 is used for monitoring channels 2 to 8. G.772 monitoring is
configured by the GMC register (see Table 5-9). While monitoring with channel 1, the device can be configured in
remote loopback and the monitored signal can be output on TTIP1 and TRING1.
6.8
Loopbacks
The DS26303 provides four loopbacks for diagnostic purposes: analog loopback, digital loopback, remote
loopback, and dual loopback.
6.8.1
Analog Loopback
The analog output of the transmitter TTIP and TRING is looped back to RTIP and RRING of the receiver. Data at
RTIP and RRING is ignored in analog loopback. See Figure 6-8.
Figure 6-8. Analog Loopback
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
6.8.2
H D B 3 /
B 8 Z S
E n c o d e r
H D B 3 /
B 8 Z S
D e c o d e r
O p tio n a l
J itt e r
A tte n u a to r
O p t io n a l
J it te r
A tte n u a to r
T r a n s m it
D ig it a l
R e c e iv e
D ig i ta l
T ra n s m it
A n a lo g
R e c e iv e
A n a lo g
Line
Driver
Rtip
Rring
Digital Loopback
The transmit system data TPOS, TNEG, and TCLK are looped back to output on RCLK, RPOS, and RNEG. The
data input at TPOS and TNEG is encoded and output on TTIP and TRING. Signals at RTIP and RRING are
ignored. This loopback is conceptually shown in Figure 6-9.
64 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 6-9. Digital Loopback
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
6.8.3
H D B 3 /
B 8 Z S
E n c o d e r
H D B 3 /
B 8 Z S
D e c o d e r
TPOS
O p tio n a l
J itt e r
A tte n u a to r
O p t io n a l
J it te r
A tte n u a to r
T r a n s m it
D ig it a l
R e c e iv e
D ig i ta l
T ra n s m it
A n a lo g
Line
Driver
TNEG
RTIP
R e c e iv e
A n a lo g
RRING
Remote Loopback
The inputs at RTIP and RRING are looped back to TTIP and TRING. The inputs at TCLK, TPOS, and TNEG are
ignored during a remote loopback. This loopback is conceptually shown in Figure 6-10.
Figure 6-10. Remote Loopback
TCLK
TPOS
TNEG
RCLK
RPOS
RNEG
H D B 3 /
B 8 Z S
E n c o d e r
H D B 3 /
B 8 Z S
D e c o d e r
TPOS
O p tio n a l
J itt e r
A tte n u a to r
O p t io n a l
J it te r
A tte n u a to r
T r a n s m it
D ig it a l
R e c e iv e
D ig i ta l
65 of 97
T ra n s m it
A n a lo g
Line
Driver
TNEG
RTIP
R e c e iv e
A n a lo g
RRING
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.9
BERT
The BERT is a software-programmable test-pattern generator and monitor capable of meeting most errorperformance requirements for digital transmission equipment. It generates and synchronizes to pseudorandom
n
y
patterns with a generation polynomial of the form x + x + 1, where n and y can take on values from 1 to 32 and to
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern. The features include:
n
·
y
Programmable PRBS pattern. The pseudorandom bit sequence (PRBS) polynomial (x + x + 1) and seed
n
are programmable (length n = 1 to 32, tap y = 1 to n – 1, and seed = 0 to 2 – 1).
Programmable repetitive pattern. The repetitive pattern length and pattern are programmable (the length n =
n
1 to 32 and pattern = 0 to 2 – 1).
24-bit error count and 32-bit bit count registers
Programmable bit-error insertion. Errors can be inserted individually, on a pin transition, or at a specific rate.
n
The rate 1/10 is programmable (n = 1 to 7).
-3
Pattern synchronization at a 10 BER. Pattern synchronization is achieved even in the presence of a
-3
random bit-error rate (BER) of 10 .
·
·
·
·
6.9.1
Configuration and Monitoring
Set PORT.CR1.BENA = 1 to enable the BERT. The following tables show how to configure the on-board BERT to
send and receive common patterns.
Table 6-10. Pseudorandom Pattern Generation
PATTERN TYPE
9
2 -1 O.153 (511 type)
11
2 -1 O.152 and O.153
(2047 type)
15
2 -1 O.151
PTF[4:0]
(hex)
04
BPCR REGISTER
PLF[4:0]
PTS
(hex)
08
0
QRSS
BERT.
PCR
BERT.
SPR2
BERT.
SPR1
0
0x0408
0xFFFF
0xFFFF
BERT.CR
TPIC,
RPIC
0
08
0A
0
0
0x080A
0xFFFF
0xFFFF
0
0D
0E
0
0
0x0D0E
0xFFFF
0xFFFF
1
20
10
13
0
0
0x1013
0xFFFF
0xFFFF
0
20
02
13
0
1
0x0253
0xFFFF
0xFFFF
0
23
11
16
0
0
0x1116
0xFFFF
0xFFFF
1
2 -1 O.153
2 -1 O.151 QRSS
2 -1 O.151
Table 6-11. Repetitive Pattern Generation
PATTERN TYPE
All 1s
BPCR REGISTER
PTF[4:0] PLF[4:0]
PTS
(hex)
(hex)
NA
00
1
QRSS
BERT.
PCR
BERT.
SPR2
BERT.
SPR1
0
0x0020
0xFFFF
0xFFFF
All 0s
NA
00
1
0
0x0020
0xFFFF
0xFFFE
Alternating 1s and 0s
NA
01
1
0
0x0021
0xFFFF
0xFFFE
Double alternating and 0s
NA
03
1
0
0x0023
0xFFFF
0xFFFC
3 in 24
NA
17
1
0
0x0037
0xFF20
0x0022
1 in 16
NA
0F
1
0
0x002F
0xFFFF
0x0001
1 in 8
NA
07
1
0
0x0027
0xFFFF
0xFF01
1 in 4
NA
03
1
0
0x0023
0xFFFF
0xFFF1
66 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
After configuring these bits, the pattern must be loaded into the BERT. This is accomplished through a 0-to-1
transition on BCR.TNPL and BCR.RNPL
Monitoring the BERT requires reading the BSR register that contains the BEC bit and the OOS bit. The BEC bit is 1
when the bit-error counter is 1 or more. The OOS is 1 when the receive pattern generator is not synchronized to
the incoming pattern, which will occur when it receives a minimum 6 bit errors within a 64-bit window. The receive
BERT bit-count register (RBCR) and the receive BERT bit-error count register (RBECR) are updated upon the
reception of a performance-monitor update signal (e.g., BCR.LPMU). This signal updates the registers with the
values of the counters since the last update and resets the counters.
6.9.2
Receive Pattern Detection
The receive BERT receives only the payload data and synchronizes the receive pattern generator to the incoming
pattern. The receive pattern generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or
bit 1 to the most significant bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating
n
y
polynomial x + x + 1), the feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is
bit n. The values for n and y are individually programmable (1 to 32). The output of the receive pattern generator is
the feedback. If QRSS is enabled, the feedback is an XOR of bits 17 and 20, and the output is forced to 1 if the
next 14 bits are all 0s. QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback is forced to
1 if bits 1 through 31 are all 0s. Depending on the type of pattern programmed, pattern detection performs either
PRBS synchronization or repetitive pattern synchronization.
6.9.2.1
Receive PRBS Synchronization
PRBS synchronization synchronizes the receive pattern generator to the incoming PRBS or QRSS pattern. The
receive pattern generator is synchronized by loading 32 data stream bits into the receive pattern generator, and
then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match the incoming pattern. If
at least six incoming bits in the current 64-bit window do not match the receive pattern generator, automatic pattern
re-synchronization is initiated. Automatic pattern resynchronization can be disabled.
Refer to Figure 6-11 for the PRBS synchronization diagram.
Figure 6-11. PRBS Synchronization State Diagram
Sync
f6
err
ors
6o
32
ors
err
bi t
sw
ith
h
wit
its
out
4b
1 bit error
Verify
Load
32 bits loaded
67 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
6.9.2.2
Receive Repetitive Pattern Synchronization
Repetitive pattern synchronization synchronizes the receive pattern generator to the incoming repetitive pattern.
The receive pattern generator is synchronized by searching each incoming data stream bit position for the
repetitive pattern, and then checking the next 32 data stream bits. Synchronization is achieved if all 32 bits match
the incoming pattern. If at least six incoming bits in the current 64-bit window do not match the receive PRBS
pattern generator, automatic pattern resynchronization is initiated. Automatic pattern resynchronization can be
disabled.
See Figure 6-12 for the repetitive pattern synchronization state diagram.
Figure 6-12. Repetitive Pattern Synchronization State Diagram
Sync
f6
err
ors
6o
32
ors
err
bi t
sw
ith
h
wit
its
out
4b
1 bit error
Verify
Match
Pattern Matches
6.9.2.3
Receive Pattern Monitoring
Receive pattern monitoring monitors the incoming data stream for both an OOS condition and bit errors and counts
the incoming bits. An out-of-synchronization (OOS) condition is declared when the synchronization state machine
is not in the sync state. An OOS condition is terminated when the synchronization state machine is in the sync
state.
Bit errors are determined by comparing the incoming data stream bit to the receive pattern generator output. If they
do not match, a bit error is declared, and the bit error and bit counts are incremented. If they match, only the bit
count is incremented. The bit count and bit-error count are not incremented when an OOS condition exists.
6.9.3
Transmit Pattern Generation
Pattern generation generates the outgoing test pattern and passes it onto error insertion. The transmit pattern
generator is a 32-bit shift register that shifts data from the least significant bit (LSB) or bit 1 to the most significant
n
y
bit (MSB) or bit 32. The input to bit 1 is the feedback. For a PRBS pattern (generating polynomial x + x + 1), the
feedback is an XOR of bit n and bit y. For a repetitive pattern (length n), the feedback is bit n. The values for n and
y are individually programmable (1 to 32). The output of the receive pattern generator is the feedback. If QRSS is
enabled, the feedback is an XOR of bits 17 and 20, and the output will be forced to one if the next 14 bits are all 0s.
QRSS is programmable (on or off). For PRBS and QRSS patterns, the feedback will be forced to 1 if bits 1 to 31
68 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
are all 0s. When a new pattern is loaded, the pattern generator is loaded with a seed/pattern value before pattern
n
generation starts. The seed/pattern value is programmable (0 – 2 – 1).
6.9.3.1
Transmit Error Insertion
Error insertion inserts errors into the outgoing pattern data stream. Errors are inserted one at a time or at a rate of
n
one out of every 10 bits. The value of n is programmable (1 to 7 or off). Single bit-error insertion can be initiated
from the microprocessor interface, or by the manual error-insertion input (TMEI). The method of single error
insertion is programmable (register or input). If pattern inversion is enabled, the data stream is inverted before the
overhead/stuff bits are inserted. Pattern inversion is programmable (on or off).
6.10 Special Test Functions
This section is used for designer notes. Any special features or test functions that are for internal use or possible
future features that may be needed should be documented here.
6.10.1 Metal Options
The DS26303 has a metal option to allow for pins D0 to D7 to be metal revised. The metal revision adds VDDIO/2
pullup and pulldown to pins D0 to D7. This has been added in case compatibility in hardware mode needs to match
the LXT384 part.
69 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
7 JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS26303 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26303 contains the
following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture:
·
·
·
·
·
·
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990, IEEE
1149.1a-1993, and IEEE 1149.1b-1994. The Test Access Port has the necessary interface pins: JTRSTB, TCLK,
JTMS, JTDI, and JTDO. See the pin descriptions for details. For the latest BSDL file go to
www.maxim-ic.com/tools/bsdl/ and search for DS26303.
Figure 7-1. JTAG Functional Block Diagram
BOUNDARY SCAN
REGISTER
IDENTIFICATION
REGISTER
BYPASS REGISTER
MUX
INSTRUCTION
REGISTER
SELECT
TEST ACCESS PORT
CONTROLLER
+V
+V
10kW
+V
10kW
JTD1
OUTPUT ENABLE
10kW
JTMS
TCLK
70 of 97
JTRSTB
JTDO
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
7.1
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of TCLK.
The state diagram is shown in Figure 7-2.
Test-Logic-Reset
Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will contain the
IDCODE instruction. All system logic of the device will operate normally. This state is automatically entered during
power up. This state is entered from any state if the JTMS is held high for at least 5 clocks.
Run-Test-Idle
The run-test-idle is used between scan operations or during specific tests. The instruction register and test
registers will remain idle. The controller remains in this state when JTMS is held low. When the JTMS is high and
rising edge of TCLK is applied the controller moves to the Select-DR-Scan State.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of TCLK moves the controller into the
capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge on TCLK moves the controller
to the select-IR-scan state.
Capture-DR
Data can be parallel-loaded into the test-data registers if the current instruction is EXTEST or SAMPLE/PRELOAD.
If the instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register will remain at its current value. On the rising edge of TCLK, the controller will go to the shift-DR state if
JTMS is LOW or it will go to the exit1-DR state if JTMS is HIGH.
Shift-DR
The test-data register selected by the current instruction will be connected between JTDI and JTDO and will shift
data one stage towards its serial output on each rising edge of TCLK. If a test register selected by the current
instruction is not placed in the serial path, it will maintain its previous state. When the TAP Controller is in this state
and a rising edge of TCLK is applied, the controller enters the EXIT1-DR state if JTMS is high or remains in SHIFTDR state if JTMS is low.
Exit1-DR
While in this state, a rising edge on TCLK will put the controller in the Update-DR state, which terminates the
scanning process, if JTMS is HIGH. A rising edge on TCLK with JTMS LOW will put the controller in the Pause-DR
state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current instruction will
retain their previous state. The controller will remain in this state while JTMS is LOW. A rising edge on TCLK with
JTMS HIGH will put the controller in the exit2-DR state.
Exit2-DR
A rising edge on TCLK with JTMS HIGH while in this state will put the controller in the update-DR state and
terminate the scanning process. A rising edge on TCLK with JTMS LOW will enter the shift-DR state.
71 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Update-DR
A falling edge on TCLK while in the update-DR state will latch the data from the shift register path of the test
registers into the data output latches. This prevents changes at the parallel output due to changes in the shift
register.
Select-IR-Scan
All test registers retain their previous state. The instruction register will remain unchanged during this state. With
JTMS LOW, a rising edge on TCLK moves the controller into the capture-IR state and will initiate a scan sequence
for the instruction register. JTMS HIGH during a rising edge on TCLK puts the controller back into the Test-logicreset state.
Capture-IR
The capture-IR state is used to load the shift register in the instruction register with a fixed value. This value is
loaded on the rising edge of TCLK. If JTMS is HIGH on the rising edge of TCLK, the controller will enter the exit1IR state. If JTMS is LOW on the rising edge of TCLK, the controller will enter the shift-IR state.
Shift-IR
In this state, the shift register in the instruction register is connected between JTDI and JTDO and shifts data one
stage for every rising edge of TCLK towards the serial output. The parallel registers as well as all test registers
remain at their previous states. A rising edge on TCLK with JTMS HIGH will move the controller to the exit1-IR
state. A rising edge on TCLK with JTMS LOW will keep the controller in the shift-IR state while moving data one
stage thorough the instruction shift register.
Exit1-IR
A rising edge on TCLK with JTMS LOW will put the controller in the pause-IR state. If JTMS is HIGH on the rising
edge of TCLK, the controller will enter the update-IR state and terminate the scanning process.
Pause-IR
Shifting of the instruction shift register is halted temporarily. With JTMS HIGH, a rising edge on TCLK will put the
controller in the Exit2-IR state. The controller will remain in the Pause-IR state if JTMS is LOW during a rising edge
on TCLK.
Exit2-IR
A rising edge on TCLK with JTMS High will put the controller in the Update-IR state. The controller will loop back to
shift-IR if JTMS is LOW during a rising edge of TCLK in this state.
Update-IR
The instruction code shifted into the instruction shift register is latched into the parallel output on the falling edge of
TCLK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising
edge on TCLK with JTMS LOW will put the controller in the run-test-idle state. With JTMS HIGH, the controller will
enter the select-DR-scan state.
72 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 7-2. TAP Controller State Diagram
1
Test Logic
Reset
0
0
Run Test/
Idle
1
Select
DR-Scan
1
Select
IR-Scan
0
1
0
1
Capture DR
Capture IR
0
Shift DR
0
Shift IR
0
1
Exit DR
Exit IR
Exit2 DR
Pause IR
0
1
0
Exit2 IR
1
Update DR
1
0
73 of 97
1
0
1
0
0
1
1
0
Pause DR
1
1
Update IR
1
0
0
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
7.2
Instruction Register
The instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. When the
TAP controller enters the shift-IR state, the instruction shift register will be connected between JTDI and JTDO.
While in the shift-IR state, a rising edge on TCLK with JTMS LOW will shift the data one stage towards the serial
output at JTDO. A rising edge on TCLK in the exit1-IR state or the exit2-IR state with JTMS HIGH will move the
controller to the update-IR state. The falling edge of that same TCLK will latch the data in the instruction shift
register to the instruction parallel output. Instructions supported by the DS26303 and its respective operational
binary codes are shown in Table 7-1.
Table 7-1. Instruction Codes for IEEE 1149.1 Architecture
INSTRUCTION
SELECTED REGISTER
INSTRUCTION CODES
EXTEST
HIGHZ
CLAMP
SAMPLE/PRELOAD
IDCODE
BYPASS
Boundary Scan
Bypass
Bypass
Boundary Scan
Device Identification
Bypass
000
010
011
100
110
111
EXTEST
This allows testing of all interconnections to the device. When the EXTEST instruction is latched in the instruction
register, the following actions occur. Once enabled via the Update-IR state, the parallel outputs of all digital output
pins will be driven. The boundary scan register will be connected between JTDI and JTDO. The Capture-DR will
sample all digital inputs into the boundary scan register.
HIGHZ
All digital outputs of the device will be placed in a HIGHZ state. The BYPASS register will be connected between
JTDI and JTDO.
CLAMP
All digital outputs of the device will output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs will not change during the CLAMP instruction.
SAMPLE/PRELOAD
This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the
device can be sampled at the boundary scan register without interfering with the normal operation of the device by
using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the boundary scan
register via JTDI using the Shift-DR state.
IDCODE
When the IDCODE instruction is latched into the parallel instruction register, the identification test register is
selected. The device identification code will be loaded into the identification register on the rising edge of TCLK
following entry into the capture-DR state. Shift-DR can be used to shift the identification code out serially via JTDO.
During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel output. The ID code
will always have a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number
of continuation bytes followed by 16 bits for the device and 4 bits for the version Table 7-2. Table 7-3 lists the
device ID code for the DS26303.
BYPASS
When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO through the
one-bit bypass test register. This allows data to pass from JTDI to JTDO not affecting the device’s normal
operation.
74 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 7-2. ID Code Structure
MSB
Version
Contact Factory
4 bits
Device ID
JEDEC
LSB
1
16 bits
00010100001
1
Table 7-3 Device ID Codes
PART
DS26303-075
DS26303-125
7.3
DIE REV
A1
A1
JTAG REV
0h
0h
JTAG ID
0080h
0081h
Test Registers
IEEE 1149.1 requires a minimum of two test registers: the bypass register and the boundary scan register. An
optional test register has been included with the DS26303 design. This test register is the identification register and
is used with the IDCODE instruction and the Test-Logic-Reset state of the TAP controller.
7.3.1
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells
and is n bits in length.
7.3.2
Bypass Register
This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions that provide a short
path between JTDI and JTDO.
7.3.3
Identification Register
The identification register contains a 32-bit shift register and a 32-bit latched parallel output. This register is
selected during the IDCODE instruction and when the TAP controller is in the test-logic-reset state. See Table 7-2
and Table 7-3 for more information about bit usage.
75 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
8 OPERATING PARAMETERS
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Lead with Respect to VSS (except VDD)…………………………………………….-0.3V to +5.5V
Supply Voltage (VDD) Range with Respect to VSS………..…………………………………………………-0.3V to +3.63V
Operating Temperature Range for DS26303G/DS26303L…...……………………………………………...0°C to +70°C
Operating Temperature Range for DS26303GN/DS26303LN.……………………………………………-40°C to +85°C
Storage Temperature…………………………………………………………………………………………-55°C to +125°C
Soldering Temperature………………………………………………………….See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
Table 8-1. Recommended DC Operating Conditions
(TA = -40°C to +85°C for DS26303GN and DS26303LN.)
PARAMETER
SYMBOL
Logic 1
VIH
Logic 0
VIL
Midrange Level
Supply Voltage
Note 1:
CONDITIONS
MIN
TYP
MAX
2
2/3VDD +
0.2
(Note 1)
(Note 1)
5.5
1/3VDD +
0.2
3.135
VDD
V
3.3
0.8
1/3VDD 0.2
2/3VDD 0.2
3.465
V
TYP
MAX
UNITS
-0.3
(Note 1)
UNITS
1/2 x VDD
V
V
Applies to pins LP1–LP8, JAS, and MODESEL.
Table 8-2. Capacitance
(TA = +25°C)
PARAMETER
Input Capacitance
Output Capacitance
SYMBOL
CONDITIONS
MIN
CIN
COUT
7
7
pF
pF
Table 8-3. DC Characteristics
(VDD = 3.135V to 3.465V, TA = -40°C to +85°C.)
PARAMETER
Supply Current
Input Leakage
Tri-State Output Leakage
Output Voltage (Io = –4.0mA)
Output Voltage (Io = +4.0mA)
Note 1:
Note 2:
SYMBOL
IDD
CONDITIONS
MIN
3.465V
(Notes 1, 2)
3.3V
IIL
IOL
VOH
VOL
TYP
MAX
478
mA
250
–10.0
–10.0
2.4
+10.0
+10.0
0.4
RCLK1-n = TCLK1-n = 1.544MHz.
Power dissipation with all ports active, TTIP and TRING driving a 25W load, for an all-ones data density.
76 of 97
UNITS
µA
µA
V
V
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
9 THERMAL CHARACTERISTICS
Table 9-1. Thermal Characteristics
PARAMETER
TYP
MAX
UNITS
Power Dissipation with RIMPMS = 0 (Notes 1, 2)
0.7
1.40
W
Power Dissipation with RIMPMS = 1(Notes 1, 2)
0.9
1.65
W
+85
°C
+125
°C
Ambient Temperature (Note 3)
MIN
-40
Junction Temperature
+21.3
(Note 4)
29.0
(Note 5)
Theta-JA (qJA) in Still Air for 144-Pin eLQFP
°C/W
Note 1:
RCLK1-n = TCLK1-n = 1.544MHz.
Note 2:
Power dissipation with all ports active, TTIP and TRIN driving a 25W load, for an all-ones data density.
Note 3:
The package is mounted on a four-layer JEDEC standard test board.
Note 4:
Theta-JA (qJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test
board and the die attach pad is soldered to the test board.
Note 5:
Theta-JA (qJA) is the junction-to-ambient thermal resistance, when the package is mounted on a four-layer JEDEC standard test
board and the die attach pad is not soldered to the test board.
77 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
10 AC CHARACTERISTICS
10.1 Line Interface Characteristics
Table 10-1. Transmitter Characteristics
PARAMETER
SYMBOL
Output Mark Amplitude
V
Output Zero Amplitude (Note 1)
CONDITIONS
MIN
TYP
MAX
E1 75W
2.14
2.37
2.6
E1 120W
2.7
3.0
3.3
T1 100W
2.4
3.0
3.6
T1 110W
2.4
3.0
3.6
Vs
Transmit Amplitude Variation with
Supply
Transmit Path Delay
UNITS
V
-0.3
+0.3
V
-1
+1
%
Single rail
8
Dual rail
3
UI
Table 10-2. Receiver Characteristics
PARAMETER
SYMBOL
Cable Attenuation
Analog Loss-of-Signal Threshold
Hysteresis Short-Haul Mode
CONDITIONS
MIN
Attn
(Note 1)
200
100
MAX
UNITS
12
dB
mV
192
192
2048
24
192
192
Allowable Zeros Before Loss
(Note 2)
Allowable Ones Before Loss (Note 3)
Receive Path Delay
TYP
Dual rail
3
Single rail
8
UI
Note 1:
Measured at the RRING and RTIP pins.
Note 2:
192 zeros for T1 and T1.231 specification compliance. 192 zeros for E1 and G.775 specification compliance. 2048 Zeros for ETSI
300 233 compliance.
Note 3:
24 ones in 192-bit period for T1.231. 192 ones for G.775, 192 ones for ETSI 300 233.
78 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
10.2 Parallel Host Interface Timing Characteristics
Table 10-3. Intel Read Mode Characteristics
(VDD = 3.3V ±5%, Tj = -40°C to +125°C.) (Figure 10-1 and Figure 10-2)
SIGNAL
NAME(S)
RDB
CSB
CSB
AD[7:0]
A[5:0]
D[7:0], AD[7:0]
D[7:0], AD[7:0]
RDYB
RDYB
A[5:0]
ALE
A[5:0]
RDB
RDYB
RDYB
ALE
Note 1:
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
DESCRIPTION (NOTE 1)
Pulse Width
Setup Time to RDB
Hold Time from RDB
Setup Time to ALE
Hold Time from RDB
Delay Time RDB, CSB Active
Deassert Delay from RDB, CSB Inactive
Enable Delay Time from CSB Active
Disable Delay Time from the CSB Inactive
Setup Time to RDB Active
Pulse Width
Hold Time from ALE
Output Delay Time of AD[7:0], D[7:0]
Delay Time from RDB Inactive
Active Output Delay Time from RDB
Inactive Time to RDB Active
The input/output timing reference level for all signals is VDD/2.
79 of 97
MIN
60
0
0
10
0
6
3
0
6
10
5
10
0
40
2
TYP
MAX
48
35
12
12
50
12
52
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 10-1. Intel Nonmuxed Read Cycle
t3
t2
CSB
t1
t13
RDB
ALE=(1)
t5
t10
A[5:0]
ADDRESS
t7
t6
D[7:0]
DATA OUT
t8
t14
RDY
t15
80 of 97
t9
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 10-2. Intel Mux Read Cycle
t3
t2
CSB
t1
RDB
t11
t16
t13
ALE
t12
t4
AD[7:0]
t7
t6
DATA OUT
ADDRESS
t8
t14
RDY
t15
81 of 97
t9
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 10-4. Intel Write Cycle Characteristics
(VDD = 3.3V ±5%, Tj = -40°C to +125°C.) (Figure 10-3 and Figure 10-4)
SIGNAL
NAME(S)
WRB
CSB
CSB
AD[7:0]
A[5:0]
D[7:0], AD[7:0]
D[7:0], AD[7:0]
RDYB
RDYB
RDYB
RDYB
ALE
ALE
A[5:0]
A[5:0]
Note 1:
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
DESCRIPTION (NOTE 1)
Pulse Width
Setup Time to WRB
Hold Time to WRB
Setup Time to ALE
Hold Time from WRB Inactive
Input Setup time to WRB Inactive
Input Hold Time to WRB Inactive
Enable Delay from CSB Active
Delay Time from WRB Active
Delay Time from WRB Inactive
Disable Delay Time from CSB Inactive
Pulse Width
Inactive Time to WRB Active
Hold Time from ALE Inactive
Setup Time to WRB Inactive
The input/output timing reference level for all signals is VDD/2.
82 of 97
MIN
60
0
0
10
2
40
30
0
40
0
10
10
10
17
TYP
MAX
UNITS
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
12
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 10-3. Intel Nonmux Write Cycle
t3
t2
CSB
t1
WRB
ALE=(1)
t5
t15
A[5:0]
ADDRESS
t7
t6
D[7:0]
WRITE DATA
t10
t8
RDY
t9
83 of 97
t11
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 10-4. Intel Mux Write Cycle
t3
t2
CSB
t1
WRB
t12
t13
ALE
t14
t4
AD[7:0]
t6
t7
WRITE DATA
ADDRESS
t8
t10
RDY
t9
84 of 97
t11
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 10-5. Motorola Read Cycle Characteristics
(VDD = 3.3V ±5%, Tj = -40°C to +125°C.) (Figure 10-5 and Figure 10-6)
SIGNAL
NAME(S)
DS
CSB
CSB
RWB
RWB
AD[7:0]
AD[7:0]
AD[7:0], D[7:0]
AD[7:0], D[7:0]
AD[7:0], D[7:0]
ACKB
ACKB
ASB
SYMBOL
DESCRIPTION
MIN
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
Pulse Width (Note 1)
Setup Time to DSB Active (Note 1)
Hold Time from DSB Inactive (Note 1)
Setup Time to DSB Active (Note 1)
Hold Time from DSB Inactive (Note 1)
Setup Time to ASB/DSB Active (Notes 1, 2)
Hold Time from ASB/DSB Active (Notes 1, 2)
Output Valid Delay Time from DSB Active (Note 1)
Invalid Output Delay Time from DSB Active (Note 1)
Output Valid Delay Time from DSB Inactive (Note 1)
Asserted Delay from DSB Active (Note 1)
Output Delay Time from DSB Inactive (Note 1)
Active Delay Time to DSB Active (Note 1)
60
0
0
10
0
10
5
3
2
3
10
TYP
MAX
30
30
40
12
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
The input/output timing reference level for all signals is VDD/2.
Note 2:
In a nonmux cycle, the timing reference refers only to the DSB signal. While in a mux cycle, the timing reference refers only to the
ASB signal.
85 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 10-5. Motorola Nonmux Read Cycle
t3
t2
CSB
t4
t5
RWB
t1
DSB
ASB=(1)
A[5:0]
t6
t7
ADDRESS
t8
D[7:0]
t10
DATA OUT
t9
t12
ACKB
t11
86 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 10-6. Motorola Mux Read Cycle
t3
t2
CSB
t4
t5
RWB
t1
DSB
t13
ASB
t9
t6
AD[7:0]
t8
t10
t7
ADDRESS
DATA OUT
t12
ACKB
t11
87 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 10-6. Motorola Write Cycle Characteristics
(VDD = 3.3V ±5%, Tj = -40°C to +125°C.) (Figure 10-7 and Figure 10-8)
SIGNAL
NAME(S)
DSB
CSB
CSB
RWB
RWB
AD[7:0]
AD[7:0]
AD[7:0], D[7:0]
AD[7:0], D[7:0]
A[5:0]
ACKB
ASB
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
DESCRIPTION
Pulse Width (Note 1)
Setup Time to DSB Active (Note 1)
Hold Time from DSB Inactive (Note 1)
Setup Time to DSB Active (Note 1)
Hold Time to DSB Inactive (Note 1)
Setup Time to ASB/DSB Active (Notes 1, 2)
Hold Time from ASB/DSB Active (Notes 1, 2)
Setup Time to DSB Inactive (Note 1)
Hold Time from DSB Inactive (Note 1)
Assert Time from DSB Active (Note 1)
Output Delay from DSB Inactive (Note 1)
Active Time to DSB Active (Note 1)
MIN
TYP
MAX
60
0
0
10
0
10
5
40
30
0
10
40
12
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
The input/output timing reference level for all signals is VDD/2.
Note 2:
In a nonmux cycle, the timing reference refers only to the DSB signal. While in a mux cycle, the timing reference refers only to the
ASB signal.
88 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 10-7. Motorola Nonmux Write Cycle
t3
t2
CSB
t4
t5
RWB
t1
DSB
ASB=(1)
A[5:0]
t6
t7
ADDRESS
t8
D[7:0]
t9
WRITE DATA
t11
ACKB
t10
89 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Figure 10-8. Motorola Mux Write Cycle
t3
t2
CSB
t4
t5
RWB
t1
DSB
t13
t12
ASB
t6
AD[7:0]
t7
t9
t8
WRITE DATA
ADDRESS
t10
ACKB
90 of 97
t11
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
10.3 Serial Port
Table 10-7. Serial Port Timing Characteristics
(Figure 10-9, Figure 10-10, and Figure 10-11)
PARAMETER
SYMBOL
SCLK High Time
SCLK Low Time
Active CSB to SCLK Setup Time
Last SCLK to CSB Inactive Time
CSB Idle Time
SDI to SCLK Setup Time
SCLK to SDI Hold Time
t1
t2
t3
t4
t5
t6
t7
SCLK Falling Edge to SDO High
Impedance (CLKE = 0);
CSB Rising to SDO High
Impedance (CLKE = 1)
t8
CONDITIONS
MIN
TYP
25
25
50
50
50
5
5
100
ns
t5
CSB
t3
t4
SCLK
t2
t6
SDI
t7
LSB
MSB
Figure 10-10. Serial Bus Timing Read Operation with CLKE = 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCLK
CSB
16
t4
SDO
t8
Figure 10-11. Serial Bus Timing Read Operation with CLKE = 1
1
2
3
4
5
6
7
8
SCLK
CSB
9
10
11
12
13
14
15
t4
SDO
t8
91 of 97
UNITS
ns
ns
ns
ns
ns
ns
ns
Figure 10-9. Serial Bus Timing Write Operation
t1
MAX
16
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
10.4 System Timing
Table 10-8. Transmitter System Timing
(Figure 10-12)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
TPOS, TNEG Setup Time with Respect to
TCLK Falling Edge
t1
40
ns
TPOS, TNEG Hold Time with Respect to
TCLK Falling Edge
t2
40
ns
TCLK Pulse-Width High
TCLK Pulse-Width Low
t3
t4
75
75
ns
ns
TCLK Period
t5
TCLK Rise Time
TCLK Fall Time
t6
t7
488
648
ns
25
25
Figure 10-12. Transmitter Systems Timing
t5
t7
t3
t6
TCLK
t1
TPO S , TN EG
t2
92 of 97
UNITS
t4
ns
ns
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
Table 10-9. Receiver System Timing
(Figure 10-13)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Delay RCLK to RPOS, RNEG Valid
Delay RCLK to RNEG Valid in SinglePolarity Mode
t1
50
ns
t2
50
ns
RCLK Pulse-Width High
t3
75
ns
RCLK Pulse-Width Low
t4
75
ns
RCLK Period
t5
488
648
Figure 10-13. Receiver Systems Timing
RCLK1
t4
t3
RCLK2
t5
t1
RPOS, RNEG
t1
RPOS, RNEG
t2
RNEG
BPV/
EXZ/
CV
BPV/
EXZ/
CV
t2
RNEG
BPV/
EXZ/
CV
BPV/
EXZ/
CV
93 of 97
ns
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
10.5 JTAG Timing
Table 10-10. JTAG Timing Characteristics
(Figure 10-14)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
JTCLK Period
t1
100
ns
JTMS and JTDI Setup to JTCLK
t2
25
ns
JTMS and JTDI Hold to JTCLK
t3
25
ns
JTCLK to JTDO Hold
t4
50
Figure 10-14. JTAG Timing
t1
TC K
t2
TM S
TD I
t3
t4
TD O
94 of 97
ns
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
11 PACKAGE INFORMATION
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to
www.maxim-ic.com/DallasPackInfo.)
11.1 eLQFP Package Outline (1 of 2)
95 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
11.2 eLQFP Package Outline (2 of 2)
96 of 97
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
12 DOCUMENT REVISION HISTORY
REVISION
072205
DESCRIPTION
New product release.
97 of 97
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products · Printed USA
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.