HMU16, HMU17 TM Data Sheet itle MU , U1 bt x -Bit OS ralltiers) utho ) eyrds terrpoion, inctor, ral- November 1999 2803.4 16 x 16-Bit CMOS Parallel Multipliers Features The HMU16 and HMU17 are high speed, low power CMOS 16-bit x 16-bit multipliers ideal for fast, real time digital signal processing applications. • 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product The X and Y operands along with their mode controls (TCX and TCY) have 17-bit input registers. The mode controls independently specify the operands as either two’s complement or unsigned magnitude format, thereby allowing mixed mode multiplication operations. Two 16-bit output registers are provided to hold the most and least significant halves of the result (MSP and LSP). For asynchronous output, these registers may be made transparent through the use of the Feedthrough Control (FT). Additional inputs are provided for format adjustment and rounding. The Format Adjust control (FA) allows the user to select either a left shifted 31-bit product or a full 32-bit product, whereas the round control (RND) provides the capability of rounding the most significant portion of the result. The HMU16 has independent clocks (CLKX, CLKY, CLKL, CLKM) associated with each of these registers to maximize throughput and simplify bus interfacing. The HMU17 has only a single clock input (CLK), but makes use of three register enables (ENX, ENY and ENP). The ENX and ENY inputs control the X and Y Input Registers, while ENP controls both the MSP and LSP Output Registers. This configuration facilitates the use of the HMU17 for microprogrammed systems. • High-Speed (35ns) Clocked Multiply Time • Low Power Operation - ICCSB = 500µA Maximum - ICCOP = 7.0mA Maximum at 1MHz • Supports Two’s Complement, Unsigned Magnitude and Mixed Mode Multiplication • HMU16 is Compatible with the AM29516, LMU16, IDT7216 and the CY7C516 • HMU17 is Compatible with the AM29517, LMU17, IDT7217 and the CY7C517 • TTL Compatible Inputs/Outputs • Three-State Outputs Applications • Fast Fourier Transform Analysis • Digital Filtering • Graphic Display Systems • Image Processing • Radar and Sonar • Speech Synthesis and Recognition Ordering Information PART NUMBER ltier, C, gi, P, el ncn, send, File Number The two halves of the product may be routed to a single 16-bit three-state output port via a multiplexer, and in addition, the LSP is connected to the Y-input port through a separate three-state buffer. 1 TEMP. RANGE ( oC) PACKAGE PKG. NO. HMU16JC-35 0 to 70 68 Ld PLCC N68.95 HMU16JC-45 0 to 70 68 Ld PLCC N68.95 HMU16GC-35 0 to 70 68 Ld CPGA G68.B HMU16GC-45 0 to 70 68 Ld CPGA G68.B HMU17JC-35 0 to 70 68 Ld PLCC N68.95 HMU17JC-45 0 to 70 68 Ld PLCC N68.95 HMU17GC-35 0 to 70 68 Ld CPGA G68.B HMU17GC-45 0 to 70 68 Ld CPGA G68.B CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2001, All Rights Reserved HMU16, HMU17 Pinouts NC CLKM (ENP) OEP FA FT MSPSEL GND GND VCC VCC TCY TCX RND CLKX (ENX) X15 X14 X13 68 LEAD PLCC TOP VIEW 9 8 7 6 5 4 3 2 1 6867666564636261 P15, P31 P14, P30 P13, P29 P12, P28 P11, P27 P10, P26 P9, P25 P8, P24 P7, P23 P6, P22 P5, P21 P4, P20 P3, P19 P2, P18 P1, P17 P0, P16 NC NC X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 OEL CLKL (CLK) CLKY (ENY) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Y15, P15 Y14, P14 Y13, P13 Y12, P12 Y11, P11 Y10, P10 Y9, P9 Y8, P8 Y7, P7 Y6, P6 Y5, P5 Y4, P4 Y3, P3 Y2, P2 Y1, P1 Y0, P0 NC 27282930313233 34 35 36 37 38 39 40 41 42 43 68 LEAD CPGA TOP VIEW 11 N/C X13 X15 RND TCY VCC GND FT OEP X14 CLKX (ENX) TCX VCC GND MSP SEL FA CLKM (ENP) N/C 10 X11 X12 9 X9 X10 P30/ P14 P31/ P15 8 X7 X8 P28/ P12 P29/ P13 7 X5 X6 P26/ P10 P27/ P11 6 X3 X4 P24/ P8 P25/ P9 5 X1 X2 P22/ P6 P23/ P7 4 OEL X0 P20/ P4 P21/ P5 3 CLKY (ENY) CLKL (CLK) P18/ P2 P19/ P3 2 N/C Y0/P0 Y2/P2 Y4/P4 Y6/P6 Y8/P8 Y10/ P10 Y12/ P12 Y14/ P14 P16/ P0 P17/ P1 Y1/P1 Y3/P3 Y5/P5 Y7/P7 Y9/P9 Y11/ P11 Y13/ P13 Y15/ P15 N/C G H J K 1 A 2 B C D E F L HMU16, HMU17 Functional Block Diagrams HMU16 X0 - 15 TCX REGISTER RND TCY REGISTER Y0 - 15/PO - 15 REGISTER OEL CLKX CLKY MULTIPLIER ARRAY FORMAT ADJUST FA MSP RESISTER FT LSP RESISTER CLKM CLKL MULTIPLEXER MSPSEL OEP P16 - 31/PO - 15 HMU17 X0 - 15 TCX TCX REGISTER RND TCY REGISTER Y0 - 15/PO - 15 REGISTER OEL CLK ENX ENY MULTIPLIER ARRAY FA FT FORMAT ADJUST MSP RESISTER LSP RESISTER ENP MSPSEL MULTIPLEXER OEP P16 - 31/PO - 15 3 HMU16, HMU17 Pin Description SYMBOL PLCC PIN NUMBER VCC 1, 68 VCC. The +5V power supply pins. A 0.1µF capacitor between the VCC and GND pins is recommended. GND 2, 3 GND. The device ground. X0-X15 47-59, 61-63 I X-Input Data. These 16 data inputs provide the multiplicand which may be in two's complement or unsigned magnitude format. Y0-Y15/ P0-P15 27-42 I/O Y-Input/LSP Output Data. This 16-bit port is used to provide the multiplier which may be in two's complement or unsigned magnitude format. It may also be used for output of the Least Significant Product (LSP). P16-P31/ P0-P15 10-25 O Output Data. This 16-bit port may provide either the MSP (P16-31) or the LSP (P0-15). TCY, TCX 66, 67 I Two's Complement Control. Input data is interpreted as two's complement when this control is HIGH. A LOW indicates the data is to be interpreted as unsigned magnitude format. FT 5 I Feed through Control. When this control is HIGH, both the MSP and LSP Registers are transparent. When LOW, the registers are latched by their associated clock signals. FA 6 I Format Adjust Control. A full 32-bit product is selected when this control line is HIGH. A LOW on this control line selects a left shifted 31-bit product with the sign bit replicated in the LSP. This control is normally HIGH, except for certain two's complement integer and fractional applications. RND 65 I Round Control. When this control is HIGH, a one is added to the Most Significant Bit (MSB) of the LSP. This position is dependent on the FA control; FA = HIGH indicates RND adds to the 2-15 bit (P15), and FA = LOW indicates RND adds to the 2-16 bit (P14). MSPSEL 4 I Output Multiplexer Control. When this control is LOW, the MSP is available for output at the dedicated output port, and the LSP is available at the Y-input/LSP output port. When MSPSEL is HIGH, the LSP is available at both ports and the MSP is not available for output. OEL 46 I Y-In/P0-15 Output Port Three-State Control. When OEL is HIGH, the output drivers are in the high impedance state. This state is required for Ydata input. When OEL is LOW, the port is enabled for LSP output. OEP 7 I P16-31/P0-15 Output Port Three-State Control. A LOW on this control line enables the output port. When OEP is HIGH, the output drivers are in the high impedance state. TYPE DESCRIPTION THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU16 ONLY CLKX 64 I X-Register Clock. The rising edge of this clock loads the X-data Input Register along with the TCX and RND Registers. CLKY 44 I Y-Register Clock. The rising edge of this clock loads the Y-data Input Register along with the TCY and RND Registers. CLKM 8 I MSP Register Clock. The rising edge of CLKM loads the Most Significant Product (MSP) Register. CLKL 45 I LSP Register Clock. The rising edge of CLKL loads the Least Significant Product (LSP) Register. THE FOLLOWING PIN DESCRIPTIONS APPLY TO THE HMU17 ONLY CLK 45 I Clock. The rising edge of this clock will load all enabled registers. ENX 64 I X-Register Enable. When ENX is LOW, the X-register is enabled; X-input data and TCX will be latched at the rising edge of CLK. When ENX is high, the X-register is in a hold mode. ENY 44 I Y-Register Enable. ENY enables the Y-register. (See ENX). ENP 8 I Product Register Enable. ENP enables the Product Register. Both the MSP and LSP Sections are enabled by ENP. (See ENX). 4 HMU16, HMU17 Functional Description The HMU16/HMU17 are high speed 16 x 16-bit multipliers designed to perform very fast multiplication of two 16-bit binary numbers. The two 16-bit operands (X and Y) may be independently specified as either two's complement or unsigned magnitude format by the two's complement controls (TCX and TCY). When either of these control lines is LOW, the respective operand is treated as an unsigned 16-bit value; and when it is HIGH, the operand is treated as a signed value represented in two's complement format. The operands along with their respective controls are latched at the rising edge of the associated clock signal. The HMU16 accomplishes this through the use of independent clock inputs for each of the Input Registers (CLKX and CLKY), while the HMU17 utilizes a single clock signal (CLK) along with the X and Y register enable inputs (ENX and ENY). Input controls are also provided for rounding and format adjustment of the 32-bit product. The Round input (RND) is provided to accommodate rounding of the most significant portion of the product by adding one to the Most Significant Bit (MSB) of the LSP Register. The position of the MSB is dependent on the state of the Format Adjust Control (see Pin Descriptions and Multiplier Input/Output Format Tables). The Round input is latched into the RND Register whenever either of the input registers is clocked. The Format Adjust control (FA) allows the product output to be formatted. When the FA control is HIGH, a full 32-bit product is output; and when FA is LOW, a left-shifted 31-bit product is output with the sign bit replicated in bit position 15 of the LSP. The FA control must be HIGH for unsigned magnitude, and mixed mode multiplication operations. It may be LOW for certain two's complement integer and fractional operations only (see Multiplier Input/ Output Formats Table). 5 The HMU16/HMU17 multipliers are equipped with two 16-bit Output Registers (MSP and LSP) which are provided to hold the most and least significant portions of the resultant product respectively. The HMU16 uses independent clocks (CLKM and CLKL) for latching the two output registers, while the HMU17 uses a single clock input (CLK) along with the Product Latch Enable (ENP). The MSP and LSP Registers may also be made transparent for asynchronous output through the use of the Feed through Control (FT). There are two output configurations which may be selected when using the HMU16/HMU17 multipliers. The first configuration allows the simultaneous access of the most and least significant halves of the product. When the MSPSEL input is LOW, the Most Significant Product will be available at the dedicated output port (P16-31/P0-15). The Least Significant Product is simultaneously available at the bidirectional port shared with the Y-inputs (Y0-15/P0-15) through the use of the LSP output enable (OEL). The other output configuration involves multiplexing the MSP and LSP Registers onto the dedicated output port through the use of the MSPSEL control. When the MSPSEL control is LOW, the Most Significant Product will be available at the dedicated output port; and when MSPSEL is HIGH, the Least Significant Product will be available at this port. This configuration allows access of the entire 32-bit product by a 16-bit wide system bus. 6 2-3 2-6 2-7 2-8 Y7 2-8 X5 X4 X3 X2 X1 X0 Y5 Y4 Y3 Y2 Y1 Y0 2-9 2-10 2-11 2-12 2 -13 2-14 2-15 Y6 2-9 2-10 2-11 2-12 2 -13 2-14 2-15 X6 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL 2-1 2-2 2-3 2-4 2-5 2-6 2-7 -21 20 2-1 2-2 2-3 2-4 2-5 2-6 P8 P7 P6 P5 P4 P3 P2 P1 P8 P7 P6 LSP P5 P4 P3 P2 P1 P0 LSP 2-7 2-8 2 -9 2-10 2-11 2 -12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2 -20 2 -21 2-22 2-23 2-24 2-25 2-26 2-27 2 -28 2-29 2-30 MSP P0 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL 2-9 2-10 2-11 2-12 2 -13 2-14 2-15 -20 2-16 2-17 2-18 2-19 2-20 2 -21 2-22 2-23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 MSP 2-8 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 -20 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 2-2 2-5 Y8 -2 -0 2-1 2-4 Y15 Y14 Y13 Y12 Y11 Y10 Y9 2-3 X7 FA = 1 FA = 0 = X 2-3 2-5 2-6 2-7 2-8 X6 X5 X4 X3 X2 X1 X0 Y6 Y5 Y4 Y3 Y2 Y1 Y0 2-9 2-10 2-11 2 -12 2-13 2 -14 2-15 2-16 Y7 2-9 2-10 2-11 2 -12 2-13 2 -14 2-15 2-16 X7 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL 2-1 2-2 2-3 2-4 2-5 2-6 2-7 P8 P7 P6 P5 P4 P3 P2 P1 P0 FIGURE 2. FRACTIONAL UNSIGNED MAGNITUDE NOTATION LSP 2-9 2-10 2-11 2-12 2-13 2 -14 2-15 2-16 2 -17 2-18 2-19 2-20 2-21 2 -22 2 -23 2-24 2-25 2-26 2-27 2-28 2-29 2-30 2-31 2-32 MSP 2-8 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 2-2 2-4 Y8 2-1 2-3 Y15 Y14 Y13 Y12 Y11 Y10 Y9 2-2 2-8 X8 2-6 2-7 2-1 2-4 2-5 X15 X14 X13 X12 X11 X10 X9 BINARY POINT DIGIT VALUE SIGNAL MANDATORY FA = 1 FIGURE 1. FRACTIONAL TWO’S COMPLEMENT NOTATION NOTE: In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000 . . . 0 yielding an erroneous product of -1 in the fraction case and -230 in the integer case. = *= X 2-2 2-7 2-1 2-5 X8 2-6 -20 2-4 X15 X14 X13 X12 X11 X10 X9 BINARY POINT Multiplier Input/Output Formats HMU16, HMU17 7 2-3 2-4 2-5 2-6 2-7 2-2 2-3 2-4 2 -5 2-6 2-7 X6 X5 X4 X3 X2 X1 X0 2-8 Y8 Y6 Y5 Y4 Y3 Y2 Y1 Y0 DIGIT VALUE = 2-8 P6 P5 P4 P3 P2 P1 P0 X X8 28 Y8 X15 X14 X13 X12 X11 X10 X9 29 -2 15 214 213 212 211 2 10 Y15 Y14 Y13 Y12 Y11 Y10 Y9 FIGURE 3. FRACTIONAL MIXED MODE NOTATION LSP 27 P7 LSP 28 -2 31 2 30 229 228 2 27 226 225 224 223 222 2 21 2 20 219 2 18 2 17 216 215 214 2 13 2 12 211 210 MSP P8 29 27 P7 LSP P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 MSP 29 27 Y7 27 X7 26 P6 26 P6 26 Y6 26 X6 25 P5 25 P5 25 Y5 25 X5 24 P4 24 P4 2-4 Y4 24 X4 23 P3 23 P3 23 Y3 23 X3 22 P2 22 P2 22 Y2 22 X2 DIGIT VALUE SIGNAL 21 P1 21 P1 21 Y1 21 X1 20 P0 20 P0 20 Y0 20 X0 FA = 1 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL DIGIT VALUE FA = 1 FA = 0 MANDATORY SIGNAL BINARY POINT 2-9 2-10 2-11 2-12 2 -13 2-14 2-15 2 -16 2-17 2 -18 2-19 2-20 2-21 2 -22 2-23 2-24 2-25 2 -26 2-27 2-28 2 -29 2-30 2-31 28 MSP 2-7 P8 2-6 -2 30 2 29 228 227 2 26 225 224 223 222 221 2 20 2 19 218 2 17 2 16 215 -230 214 213 2 12 211 210 2-5 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 2-4 28 2-3 P7 -2 15 214 213 212 211 2 10 29 -20 2 -1 2-2 P8 SIGNAL (UNSIGNED MAGNITUDE) DIGIT VALUE SIGNAL (TWO’S COMPLEMENT) 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 Y7 2-8 2-9 2 -10 2-11 2-12 2 -13 2-14 2-15 X7 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 2-1 Y15 Y14 Y13 Y12 Y11 Y10 Y9 2-2 X8 (Continued) FIGURE 4. INTEGER TWO’S COMPLEMENT NOTATION NOTE: In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000 . . . 0 yielding an erroneous product of -1 in the fraction case and -230 in the integer case. = X -20 2-1 X15 X14 X13 X12 X11 X10 X9 BINARY POINT Multiplier Input/Output Formats HMU16, HMU17 8 = 29 -231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 2 11 210 27 P7 27 Y7 27 X7 FIGURE 6. INTEGER MIXED MODE NOTATION LSP P8 P9 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 28 28 X Y8 28 29 -215 214 213 212 211 210 29 X8 X15 X14 X13 X12 X11 X10 X9 26 P6 26 Y6 26 X6 FIGURE 5. INTEGER UNSIGNED MAGNITUDE NOTATION 2 15 214 213 212 211 210 MSP 27 P7 27 Y7 27 X7 LSP 28 MSP P8 231 230 229 228 2 27 2 26 225 224 223 222 2 21 29 P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 216 215 214 213 2 12 211 2 10 28 29 215 214 213 212 2 11 2 10 220 2 19 218 217 Y8 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y15 Y14 Y13 Y12 Y11 Y10 Y9 = 28 29 215 214 213 212 2 11 2 10 X X8 (Continued) X15 X14 X13 X12 X11 X10 X9 Multiplier Input/Output Formats 25 P5 25 Y5 25 X5 26 P6 26 Y6 26 X6 24 P4 24 Y4 24 X4 25 P5 25 Y5 25 X5 23 P3 23 Y3 23 X3 24 P4 24 Y4 24 X4 22 P2 22 Y2 22 X2 23 P3 23 Y3 23 X3 21 P1 21 Y1 21 X1 20 P0 20 Y0 20 X0 21 P1 21 Y1 21 X1 20 P0 20 Y0 20 X0 DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL DIGIT VALUE SIGNAL MANDATORY FA = 1 DIGIT VALUE SIGNAL DIGIT VALUE MANDATORY FA = 1 SIGNAL (UNSIGNED MAGNITUDE) DIGIT VALUE SIGNAL (TWO’S COMPLEMENT) BINARY POINT 22 P2 22 Y2 22 X2 BINARY POINT HMU16, HMU17 HMU16, HMU17 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input, Output or I/O Voltage Applied . . . . . GND 0.5V to VCC +0.5V Storage Temperature Range . . . . . . . . . . . . . . . . . . . 65oC to 150oC Thermal Resistance (Typical, Note 1) θJA(oC/W) θJC (oC/W) PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . 43.2 15.1 CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . 42.69 10.0 Maximum Package Power Dissipation at 70oC PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.7W CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.46 Maximum Junction Temperature PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC CPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Lead Temperature (Soldering, 10s). . . . . . . . . . . . . 300oC Operating Conditions Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4500 Gates CAUTION: Stresses above those listed in the ``Absolute Maximum Ratings'' may cause permanent damage to the device. This is a stress only rating, and operation at these or any other conditions above those indicated in the operations sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. DC Electrical Specifications PARAMETER VCC = 5.0V ±5%, TA = 0oC to 70oC SYMBOL TEST CONDITIONS MIN MAX UNITS Logical One Input Voltage VIH VCC = 5.25V 2.0 - V Logical Zero Input Voltage VIL VCC = 4.75V - 0.8 V Output High Voltage VOH IOH = 400mA, VCC = 4.75V 2.6 - V Output Low Voltage VOL IOL = +4.0mA, VCC = 4.75V - 0.4 V Input Leakage Current II VI = VCC or GND, V CC = 5.25V 10 10 µA Output or I/O Leakage Current IO VO = VCC or GND, V CC = 5.25V 10 10 µA Standby Power Supply Current ICCSB VI = VCC or GND, V CC = 5.25V Outputs Open - 500 µA Operating Power Supply Current ICCOP VI = VCC or GND, V CC = 5.25V f = 1MHz (Note 2) - 7.0 mA NOTE: 2. Operating Supply Current is proportional to frequency, Typical rating is 5mA/MHz. Capacitance TA = 25oC, Note 3 PARAMETER SYMBOL Input Capacitance CIN Output Capacitance COUT I/O Capacitance TEST CONDITIONS Frequency = 1MHz. All measurements referenced to device ground. CI/O NOTE: 3. Not tested, but characterized at initial design and at major process/design changes. 9 TYPICAL UNITS 15 pF 10 pF 10 pF HMU16, HMU17 AC Electrical Specifications VCC = 5.0V ±5%, TA = 0oC to 70oC, Note 6 PARAMETER TEST CONDITIONS HMU16/HMU17-35 HMU16/HMU17-45 MIN MAX MIN MAX UNITS tMUC - 55 - 70 ns Clocked Multiply Time tMC - 35 - 45 ns X, Y, RND Setup Time tS 15 - 18 - ns X, Y, RND Hold Time tH 2 - 2 - ns Clock Pulse Width High tPWH 10 - 15 - ns Clock Pulse Width Low tPWL 10 - 15 - ns MSPSEL to Product Out tPDSEL - 22 - 25 ns Output Clock to P tPDP - 22 - 25 ns Output Clock to Y tPDY - 22 - 25 ns Three-State Enable Time tENA - 22 - 25 ns Three-State Disable Time tDIS - 22 - 25 ns Clock Enable Setup Time (HMU17 Only) tSE 15 - 15 - ns Clock Enable Hold Time (HMU17 Only) tHE 2 - 2 - ns Clock Low Hold Time CLKXY Relative to CLKML (HMU16 Only) tHCL Note 5 0 - 0 - ns SYMBOL Unclocked Multiply Time Note 4 Output Rise Time tr From 0.8V to 2.0V - 8 - 8 ns Output Fall Time tf From 2.0V to 0.8V - 8 - 8 ns NOTES: 4. Transition is measured at ±200mV from steady state voltage with loading specified in AC Test Circuit, V1 = 1.5V, R1 = 500Ω and C1 = 40pF. 5. To ensure the correct product is entered in the output registers, new data may not be entered into the input registers before the output registers have been clocked. 6. Refer to AC Test Circuit, with V1 = 2.4V, R1 = 500Ω and C1 = 40pF. AC Test Circuit AC Testing Input, Output Waveforms V1 R1 0.3V DUT 0V 1.5V 1.5V VOH VOL C1 (SEE NOTE) NOTE: Includes Stray and Jig Capacitance. 10 NOTE: AC Testing: All parameters tested as per test circuit. Input rise and fall times are driven at 1ns/V. HMU16, HMU17 Timing Diagrams DATA INPUT 3.0V 1.5V 0V tH tS 3.0V 1.5V 0V CLOCK INPUT THREE STATE CONTROL OUTPUT THREE STATE FIGURE 7. SETUP AND HOLD TIME tPWH CLKM CLKL tENA HIGH IMPEDANCE 1.7V 1.3V FIGURE 8. THREE-STATE CONTROL tPWH tHCL CLK CLKX CLKY INPUT XI YI RND 1.5V tDIS tS tH tPWL ENX ENY INPUT XI YI RND tMC tSE tS tPWL tHE tH tSE tPDY tHE ENP OUTPUT Y tPDY tMC tPDSEL OUTPUT Y tPDSEL MSPSEL tPDP MSPSEL tPDP OUTPUT P tMUC OUTPUT P tMUC FIGURE 9. HMU16 TIMING DIAGRAM 11 FIGURE 10. HMU17 TIMING DIAGRAM HMU16, HMU17 Ceramic Pin Grid Array Packages (CPGA) S1 G68.B MIL-STD-1835 CMGA3-P68D (P-AC) 68 LEAD CERAMIC PIN GRID ARRAY PACKAGE –A– D INCHES D1 –B– S E1 E MIN MAX MIN MAX A 0.215 0.345 5.46 8.76 - 0.070 0.145 1.78 3.68 3 b 0.016 0.0215 0.41 0.55 8 b1 0.016 0.020 0.41 0.51 - b2 0.042 0.058 1.07 1.47 4 C - 0.080 - 2.03 - D 1.140 1.180 E INDEX CORNER SEE NOTE 9 1.140 28.96 - 29.97 - 25.4 BSC - e 0.100 BSC 2.54 BSC 6 k 0.008 REF 0.20 REF - L 0.120 0.140 3.05 3.56 - Q1 0.025 0.060 0.64 1.52 5 S b1 S1 N SECTION B-B 1.180 29.97 25.4 BSC 1.000 BSC 0.000 BSC 0.003 M A 28.96 1.000 BSC E1 S SEE NOTE 7 NOTES A1 D1 C MILLIMETERS SYMBOL 0.00 BSC - 0.08 121 - 11 - 10 - - 121 2 11 1 Rev. 0 6/20/95 b 0.008 C NOTES: SEATING PLANE AT STANDOFF –C– B k B A1 L b2 e 1. “M” represents the maximum pin matrix size. 2. “N” represents the maximum allowable number of pins. Number of pins and location of pins within the matrix is shown on the pinout listing in this data sheet. 3. Dimension “A1” includes the package body and Lid for both cavity-up and cavity-down configurations. This package is cavity down. Dimension “A1” does not include heatsinks or other attached features. 4. Standoffs are required and shall be located on the pin matrix diagonals. The seating plane is defined by the standoffs at dimension “Q1”. 5. Dimension “Q1” applies to cavity-down configurations only. Q SECTION A-A 7. Datum C is the plane of pin to package interface for both cavity up and down configurations. Ø0.030 M C A M B M 8. Pin diameter includes solder dip or custom finishes. Pin tips shall have a radius or chamfer. Ø0.010 M C b A A 6. All pins shall be on the 0.100 inch grid. 9. Corner shape (chamfer, notch, radius, etc.) may vary from that shown on the drawing. The index corner shall be clearly unique. 10. Dimension “S” is measured with respect to datums A and B. L 11. Dimensioning and tolerancing per ANSI Y14.5M-1982. A1 12. Controlling dimension: INCH. Q 12 HMU16, HMU17 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” 0.020 (0.51) MIN A1 A D1 D N68.95 (JEDEC MS-018AE ISSUE A) 68 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.985 0.995 25.02 25.27 - D1 0.950 0.958 24.13 24.33 3 D2 0.441 0.469 11.21 11.91 4, 5 E 0.985 0.995 25.02 25.27 - E1 0.950 0.958 24.13 24.33 3 E2 0.441 0.469 11.21 11.91 4, 5 N 68 68 6 Rev. 2 11/97 SEATING -C- PLANE 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN 0.045 (1.14) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at website www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site www.intersil.com 13