Intersil HI5804KCB 12-bit, 5 msps a/d converter Datasheet

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IGN
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HI5804
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Semiconductor
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EN
I580
OMM See H
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12-Bit, 5 MSPS A/D Converter
October 1998
Features
Description
• Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . 5 MSPS
The HI5804 is a monolithic, 12-bit, Analog-to-Digital
Converter fabricated in Harris’ HBC10 BiCMOS process. It is
designed for high speed, high resolution applications where
wide bandwidth and low power consumption are essential.
• Low Power
• Internal Sample and Hold
The HI5804 is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold (S/H). The HI5804 has excellent dynamic
performance while consuming 300mW power at 5 MSPS.
• Fully Differential Architecture
• Full Power Input Bandwidth . . . . . . . . . . . . . . . 100MHz
[ /Title (HI5804)
• Low Distortion
/Subject (12-Bit, 5 MSPS A/D Converter)
The 100MHz full power input bandwidth is ideal for
•/Author
Internal()Reference
communication
systems
and
document
scanner
•/Keywords
TTL/CMOS(Harris
Compatible
Digital I/O
Semiconductor,
A/D, Analog to Digapplications. Data output latches are provided which present
Converter,
Highvalid data to the output bus with a latency of 3 clock cycles.
•ital
Digital
OutputsNarrow
. . . . . . . .Band,
. . . . . .Communications,
. . . . . . . . . . . . 3V to 5V
The digital outputs have a separate supply pin which can be
Speed Converters, High Resolution Converters, Basestapowered from a 3.0V to 5.0V supply.
Applications
tion, Cellular)
/Creator
() Data Acquisition Systems
Ordering Information
• High Speed
/DOCINFO
pdfmark
• Digital IF Communication Systems
PART
NUMBER
SAMPLE
RATE
TEMP.
RANGE (oC)
[ /PageMode /UseOutlines
•/DOCVIEW
Medical Imaging
pdfmark
HI5804KCB
5 MSPS
0 to 70
• Radar Signal Analysis
HI5804EVAL
• Document and Film Scanners
25
PACKAGE
28 Ld SOIC
PKG.
NO.
M28.3
Evaluation Board
• Vibration/Waveform Spectrum Analysis
• Digital Servo Loop Control
• Reference Literature
- AN9214 Using Harris High Speed Converters
- AN9647 Using the HI5804 Evaluation Board
Pinout
HI5804
(SOIC)
TOP VIEW
CLK 1
28 D0
DVCC1 2
27 D1
DGND1 3
26 D2
DVCC1 4
25 D3
DGND1 5
24 D4
6
23 D5
AVCC
22
AGND 7
DVCC2
21 DGND2
VIN+ 8
VIN- 9
20 D6
VDC 10
19 D7
VROUT 11
18 D8
VRIN 12
17 D9
AGND 13
16 D10
14
15 D11
AVCC
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number
4026.5
HI5804
Functional Block Diagram
VDC
VINVIN+
BIAS
CLOCK
CLK
VROUT
VRIN
REF
S/H
STAGE 1
DVCC2
4-BIT
DAC
4-BIT
FLASH
+
∑
-
D11 (MSB)
D10
X8
DIGITAL DELAY
AND
DIGITAL ERROR CORRECTION
STAGE 3
4-BIT
FLASH
4-BIT
DAC
+
∑
D9
D8
D7
D6
D5
D4
D3
D2
D1
X8
D0 (LSB)
STAGE 4
4-BIT
FLASH
AVCC
AGND
DGND2
DVCC1
DGND1
Typical Application Schematic
(LSB) (28) D0
(27) D1
(26) D2
VROUT (11)
(25) D3
VRIN (12)
(24) D4
AGND (7)
(23) D5
AGND (13)
(20) D6
DGND1 (3)
(19) D7
DGND1 (5)
(18) D8
DGND2 (21)
(17) D9
(16) D10
(MSB) (15) D11
VIN+
VIN-
VIN+ (8)
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
DGND
AGND
D11
(4) DVCC1
VDC (10)
(2) DVCC1
VIN- (9)
(22) DVCC2
+
0.1µF
CLOCK
CLK (1)
10µF
(6) AVCC
(14) AVCC
HI5804
2
+
0.1µF
10µF
BNC
HI5804
Absolute Maximum Ratings
Thermal Information
Supply Voltage, AVCC or DVCC to AGND or DGND . . . . . . . . . . . +6.0V
DGND to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3V
Digital I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DGND to DVCC
Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AGND to AVCC
Thermal Resistance (Typical, Note 1)
θJA(oC/W)
HI5804KCB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
70
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range, HI5804KCB . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
AVCC = DVCC1 = DVCC2 = +5.0V, fS = 5 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF,
TA = 25oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ACCURACY
Resolution
12
-
-
Bits
Integral Linearity Error, INL
fIN = DC
-
±2
-
LSB
Differential Linearity Error, DNL
(Guaranteed No Missing Codes)
fIN = DC
-
±0.5
±1
LSB
Offset Error, VOS
fIN = DC
-
12
-
LSB
Full Scale Error, FSE
fIN = DC
-
24
-
LSB
Minimum Conversion Rate
No Missing Codes
-
0.5
-
MSPS
Maximum Conversion Rate
No Missing Codes
-
5
-
MSPS
Effective Number of Bits, ENOB
fIN = 1MHz
-
10.3
-
Bits
Signal to Noise and Distortion Ratio, SINAD
fIN = 1MHz
-
64
-
dB
fIN = 1MHz
-
65
-
dB
Total Harmonic Distortion, THD
fIN = 1MHz
-
-70
-
dBc
2nd Harmonic Distortion
fIN = 1MHz
-
-73
3rd Harmonic Distortion
fIN = 1MHz
-
-73
-
dBc
Spurious Free Dynamic Range, SFDR
fIN = 1MHz
-
73
-
dBc
Intermodulation Distortion, IMD
f1 = 1MHz, f2 = 1.02MHz
-
-66
-
dBc
-
1
-
Cycle
-
2
-
Cycle
Maximum Peak-to-Peak Differential Analog Input Range
(VIN+ - VIN-)
-
±2.0
-
V
Maximum Peak-to-Peak Single-Ended Analog Input Range
-
4.0
-
V
1
-
-
MΩ
-
10
-
pF
-10
-
+10
µA
Differential Analog Input Bias Current IB DIFF = (IB+ - IB-)
-
±0.5
-
µA
Full Power Input Bandwidth, FPBW
-
100
-
MHz
1
2.3
4
V
DYNAMIC CHARACTERISTICS
RMS Signal
= -------------------------------------------------------------RMS Noise + Distortion
Signal to Noise Ratio, SNR
RMS Signal
= ------------------------------RMS Noise
Transient Response
Over-Voltage Recovery
0.2V Overdrive
dBc
ANALOG INPUT
Analog Input Resistance, RIN
(Notes 2, 3)
Analog Input Capacitance, CIN
Analog Input Bias Current, IB+ or IB-
Analog Input Common Mode Voltage (VIN+ + VIN-)/2
Differential Mode (Note 2)
3
HI5804
Electrical Specifications
AVCC = DVCC1 = DVCC2 = +5.0V, fS = 5 MSPS at 50% Duty Cycle, VRIN = 3.5V, CL = 10pF,
TA = 25oC, Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Reference Output Voltage, VROUT
-
3.5
-
V
Reference Output Current
-
-
1
mA
INTERNAL VOLTAGE REFERENCE
REFERENCE INPUT
Total Reference Resistance, RL
-
7.8
-
kΩ
Reference Current
-
450
-
µA
DC Bias Voltage Output, VDC
-
2.3
-
V
Max Output Current (Not to Exceed)
-
-
1
mA
2.0
-
-
V
-
-
0.8
V
-
-
10.0
µA
DC BIAS VOLTAGE
DIGITAL INPUT, CLK
Input Logic High Voltage, VIH
Input Logic Low Voltage, VIL
Input Logic High Current, IIH
VCLK = 5V
Input Logic Low Current, IIL
VCLK = 0V
-
-
10.0
µA
-
7
-
pF
1.6
-
-
mA
-
1.6
-
mA
-0.2
-
-
mA
-
-0.2
-
mA
-
5
-
pF
Aperture Delay, tAP
-
5
-
ns
Aperture Jitter, tAJ
-
5
-
psRMS
Data Output Delay, tOD
-
8
-
ns
-
8
-
ns
-
-
3
Cycle
Input Capacitance, CIN
DIGITAL OUTPUTS, D0-D11
Output Logic Sink Current, IOL
VO = 0.4V (Note 2)
DVCC2 = 3.0V, VO = 0.4V
Output Logic Source Current, IOH
VO = 2.4V (Note 2)
DVCC2 = 3.0V, VO = 2.4V
Output Capacitance, COUT
TIMING CHARACTERISTICS
Data Output Hold, t H
Data Latency, tLAT
For a Valid Sample (Note 2)
Clock Pulse Width (Low)
5MHz Clock
90
100
110
ns
Clock Pulse width (High)
5MHz Clock
90
100
110
ns
Analog Supply Voltage, AVCC
4.75
5.0
5.25
V
Digital Supply Voltage, DVCC1
4.75
5.0
5.25
V
Digital Output Supply Voltage, DVCC2
2.85
-
5.25
V
POWER SUPPLY CHARACTERISTICS
Total Supply Current, ICC
VIN+ - VIN- = 2V
-
60
-
mA
Analog Supply Current, AICC
VIN+ - VIN- = 2V
-
46
-
mA
Digital Supply Current, DICC1
VIN+ - VIN- = 2V
-
13
-
mA
Digital Output Supply Current, DICC2
VIN+ - VIN- = 2V
-
1
-
mA
Power Dissipation
VIN+ - VIN- = 2V
-
300
-
mW
Offset Error Sensitivity, ∆VOS
AVCC or DVCC = 5V ±5%
-
± 16
-
LSB
Gain Error Sensitivity, ∆FSE
AVCC or DVCC = 5V ±5%
-
± 16
-
LSB
NOTES:
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock off (clock low, hold mode).
4
HI5804
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT
SN - 1
HN - 1
SN
HN
SN + 1
HN + 1
SN + 2
HN + 2
SN + 3
HN + 3
SN + 4
HN + 4
SN+5
HN + 5
SN + 6
HN + 6
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N - 1
B2, N - 2
3RD
STAGE
4TH
STAGE
B1, N
B2, N - 1
B3, N - 2
B4, N - 3
DATA
OUTPUT
B1, N + 1
B2, N
B3, N - 1
B4, N - 2
DN - 3
B1, N + 2
B2, N + 1
B3, N
B2, N + 2
B3, N + 1
B4, N - 1
DN - 2
B1, N + 3
B4, N
DN - 1
B2, N + 3
B3, N + 2
B4, N + 1
DN
DN + 1
tLAT
4. SN : N-th sampling period.
5. HN : N-th holding period.
6. BM , N : M-th stage digital output corresponding to N-th sampled input.DN :
Final data output corresponding to N-th sampled input.
FIGURE 1. HI5804 INTERNAL CIRCUIT TIMING
ANALOG
INPUT
t AP
t AJ
1.5V
1.5V
tOD
tH
2.0V
DATA
OUTPUT
DATA N-1
DATA N
0.8V
FIGURE 2. INPUT-TO-OUTPUT TIMING
5
B1, N + 5
B2, N + 4
B3, N + 3
B4, N + 2
NOTES:
CLOCK
INPUT
B1, N + 4
B3, N + 4
B4, N + 3
DN + 2
DN + 3
HI5804
Typical Performance Curves
67
fS = 5 MSPS
fS = 5 MSPS
10.8
66
25oC
70oC
SINAD (dB)
EFFECTIVE NUMBER OF BITS (ENOB)
11.0
10.6
10.4
10.2
25oC
70oC
65
64
63
10.0
62
1
2
3
4
INPUT FREQUENCY (MHz)
5
1
FIGURE 3. TYPICAL ENOB vs INPUT FREQUENCY
2
3
4
INPUT FREQUENCY (MHz)
5
FIGURE 4. TYPICAL SINAD vs INPUT FREQUENCY
68
78
fS = 5 MSPS
fS = 5 MSPS
67
77
66
76
25oC
70oC
-THD (dBc)
SNR (dB)
25oC
65
70oC
75
64
74
63
73
62
72
1
2
3
4
INPUT FREQUENCY (MHz)
5
1
FIGURE 5. TYPICAL SNR vs INPUT FREQUENCY
3
4
INPUT FREQUENCY (MHz)
5
FIGURE 6. TYPICAL -THD vs INPUT FREQUENCY
340
80
fS = 5 MSPS
VIN+ = VIN- = VDC
POWER DISSIPATION (mW)
fS = 5 MSPS
25oC
70oC
78
SFDR (dBc)
2
76
70oC
74
25oC
2
3
4
INPUT FREQUENCY (MHz)
300
280
260
240
15
72
1
320
5
25
35
45
55
65
75
TEMPERATURE (oC)
FIGURE 7. TYPICAL SFDR vs INPUT FREQUENCY
FIGURE 8. TYPICAL POWER DISSIPATION vs TEMPERATURE
6
HI5804
clock which is a non-overlapping two phase signal, φ1 and φ2 ,
derived from the master clock. During the sampling phase,
φ1 , the input signal is applied to the sampling capacitors, CS .
At the same time the holding capacitors, CH , are discharged
to analog ground. At the falling edge of φ1 the input signal is
sampled on the bottom plates of the sampling capacitors. In
the next clock phase, φ2 , the two bottom plates of the sampling capacitors are connected together and the holding
capacitors are switched to the op-amp output nodes. The
charge then redistributes between CS and CH completing one
sample-and-hold cycle. The output is a fully-differential, sampled-data representation of the analog input. The circuit not
only performs the sample-and-hold function but will also convert a single-ended input to a fully-differential output for the
converter core. During the sampling phase, the VIN pins see
only the on-resistance of a switch and CS . The relatively
small values of these components result in a typical full
power input bandwidth of 100MHz for the converter.
Pin Descriptions
PIN #
NAME
DESCRIPTION
1
CLK
2
DVCC1
Digital Supply (+5.0V).
3
DGND1
Digital Ground.
4
DVCC1
Digital Supply (+5.0V).
5
DGND1
Digital Ground.
6
AVCC
Analog Supply (+5.0V).
7
AGND
Analog Ground.
8
VIN+
Positive Analog Input.
9
VIN-
Negative Analog Input.
10
VDC
DC Bias Voltage Output.
11
VROUT
12
VRIN
13
AGND
Sample Clock Input.
φ1
Reference Voltage Output.
VIN +
Reference Voltage Input.
VIN -
AVCC
Analog Supply (+5.0V).
15
D11
Data Bit 11 Output (MSB).
16
D10
Data Bit 10 Output.
17
D9
Data Bit 9 Output.
18
D8
Data Bit 8 Output.
19
D7
Data Bit 7 Output.
20
D6
Data Bit 6 Output.
21
DGND2
Digital Output Ground.
22
DVCC2
Digital Output Supply (+3.0V to +5.0V).
23
D5
Data Bit 5 Output.
24
D4
Data Bit 4 Output.
25
D3
Data Bit 3 Output.
26
D2
Data Bit 2 Output.
27
D1
Data Bit 1 Output.
28
D0
Data Bit 0 Output (LSB).
φ1
φ1
CS
VOUT +
-+
-
φ2
Analog Ground.
14
φ1
CH
+
VOUT -
CS
φ1
CH
φ1
FIGURE 9. ANALOG INPUT SAMPLE-AND-HOLD
As illustrated in the functional block diagram and the timing
diagram in Figure 1, three identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fourth stage being
only a four bit flash converter. Each converter stage in the
pipeline will be sampling in one phase and amplifying in the
other clock phase. Each individual sub-converter clock signal is offset by 180 degrees from the previous stage clock
signal with the result that alternate stages in the pipeline will
perform the same operation.
The 4-bit digital output of each stage is fed to a digital delay
line controlled by the internal clock. The purpose of the delay
line is to align the digital output data to the corresponding
sampled analog input signal. This delayed data is fed to the
digital error correction circuit which corrects the error in the
output data with the information contained in the redundant
bits to form the final twelve bit output for the converter.
Because of the pipeline nature of this converter, the data on
the bus is output at the 3rd cycle of the clock after the analog
sample is taken. This delay is specified as the data latency.
After the data latency time, the data representing each succeeding sample is output at the following clock pulse. The
output data is synchronized to the external clock by a latch.
The digital outputs are in offset binary format (See Table 1).
Detailed Description
Theory of Operation
The HI5804 is a 12-bit, fully-differential, sampling pipeline
A/D converter with digital error correction. Figure 9 depicts
the circuit for the front end differential-in-differential-out sample-and-hold (S/H). The switches are controlled by an internal
7
HI5804
Internal Reference Generator, VROUT and VRIN
The HI5804 has an internal reference voltage generator,
therefore no external reference voltage is required. VROUT
must be connected to VRIN when using the internal reference voltage.
VIN+
VIN
VDC
The HI5804 can be used with an external reference voltage.
The converter requires only one external reference voltage
connected to the VRIN pin with VROUT left open.
VIN-
The HI5804 is tested with VRIN equal to 3.5V. Internal to the
converter two reference voltages of 1.3V and 3.3V are generated for a fully differential input signal range of ±2V.
FIGURE 11. AC COUPLED SINGLE ENDED INPUT
Again, the difference between the two internal voltage
references is 2V. If VIN is a 4VP-P sinewave, then VIN+ is a
4VP-P sinewave riding on a positive voltage equal to VDC. The
converter will be at positive full scale when VIN+ is at VDC + 2V
(VIN+ - VIN- = 2V) and will be at negative full scale when VIN+ is
equal to VDC - 2V (VIN+ - VIN- = -2V). In this case, VDC could
range between 2V and 3V without a significant change in ADC
performance. The simplest way to produce VDC is to use the
VDC bias voltage output of the HI5804.
In order to minimize overall converter noise it is recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, VRIN .
Analog Input, Differential Connection
The analog input to the HI5804 can be configured in various
ways depending on the signal source and the required level
of performance. A fully differential connection (Figure 10) will
give the best performance for the converter.
VIN
A single ended source will give better overall system
performance if it is first converted to differential before
driving the analog input of the HI5804.
VIN+
Digital I/O and Clock Requirements
HI5804
The HI5804 provides a standard high-speed interface to
external TTL/CMOS logic families. The digital CMOS clock
input has TTL level thresholds. The low input bias current
allows the HI5804 to be driven by CMOS logic.
VDC
-VIN
HI5804
VIN-
The digital CMOS outputs have a separate digital supply.
This allows the digital outputs to operate from a 3.0V to 5.0V
supply. When driving CMOS logic, the digital outputs will
swing to the rails. When driving standard TTL loads, the digital outputs will meet standard TTL level requirements even
with a 3.0V supply.
FIGURE 10. AC COUPLED DIFFERENTIAL INPUT
Since the HI5804 is powered off a single +5V supply, the
analog input must be biased so it lies within the analog input
common mode voltage range of 1.0V to 4.0V. The performance of the ADC does not change significantly with the
value of the common mode voltage.
In order to ensure rated performance of the HI5804, the duty
cycle of the clock should be held at 50% ±5%. It must also
have low jitter and operate at standard TTL levels.
A 2.3V DC bias voltage source, VDC , half way between the
top and bottom internal reference voltages, is made available to the user to help simplify circuit design when using a
differential input. This low output impedance voltage source
is not designed to be a reference but makes an excellent
bias source and stays within the analog input common mode
voltage range over temperature.
Performance of the HI5804 will only be guaranteed at conversion rates above 0.5 MSPS. This ensures proper performance of the internal dynamic circuits.
Supply and Ground Considerations
The HI5804 has separate analog and digital supply and
ground pins to keep digital noise out of the analog signal
path. The part should be mounted on a board that provides
separate low impedance connections for the analog and digital supplies and grounds. For best performance, the supplies to the HI5804 should be driven by clean, linear
regulated supplies. The board should also have good high
frequency decoupling capacitors mounted as close as possible to the converter. If the part is powered off a single supply
then the analog supply and ground pins should be isolated
by ferrite beads from the digital supply and ground pins.
The difference between the converter’s two internal voltage
references is 2V. For the AC coupled differential input,
(Figure 10), if VIN is a 2VP-P sinewave with -VIN being 180
degrees out of phase with VIN, the converter will be at positive
full scale when the VIN+ input is at VDC + 1V and the VINinput is at VDC - 1V (VIN+ - VIN- = 2V). Conversely, the ADC
will be at negative full scale when the VIN+ input is equal to
VDC - 1V and VIN- is at VDC + 1V (VIN+ - VIN- = -2V).
Analog Input, Single-Ended Connection
The configuration shown in Figure 11 may be used with a
single ended AC coupled input. Sufficient headroom must be
provided such that the input voltage never goes above +5V
or below AGND.
Refer to Application Note AN9214, “Using Harris High Speed
A/D Converters” for additional considerations when using
high speed converters.
8
HI5804
TABLE 1. A/D CODE TABLE
OFFSET BINARY OUTPUT CODE
DIFFERENTIAL
INPUT VOLTAGE†
(USING INTERNAL
REFERENCE)
MSB
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
+Full Scale
(+FS) - 1/4 LSB
+1.99976V
1
1
1
1
1
1
1
1
1
1
1
1
+FS - 11/4 LSB
1.99878V
1
1
1
1
1
1
1
1
1
1
1
0
+ 3/4 LSB
732.4µV
1
0
0
0
0
0
0
0
0
0
0
0
- 1/4 LSB
-244.1µV
0
1
1
1
1
1
1
1
1
1
1
1
-FS + 13/4 LSB
-1.99829V
0
0
0
0
0
0
0
0
0
0
0
1
-Full Scale (-FS)
+ 3/4 LSB
-1.99927V
0
0
0
0
0
0
0
0
0
0
0
0
CODE CENTER
DESCRIPTION
LSB
† The voltages listed above represent the ideal center of each offset binary output code.
Static Performance Definitions
Offset Error (VOS)
Signal-to-Noise Ratio (SNR)
The midscale code transition should occur at a level 1/4 LSB
above half-scale. Offset is defined as the deviation of the
actual code transition from this point.
SNR is the measured RMS signal to RMS noise at a
specified input and sampling frequency. The noise is the
RMS sum of all of the spectral components except the
fundamental and the first five harmonics.
Full-Scale Error (FSE)
Signal-to-Noise + Distortion Ratio (SINAD)
The last code transition should occur for an analog input that
is 3/4 LSB below positive full-scale with the offset error
removed. Full-scale error is defined as the deviation of the
actual code transition from this point.
SINAD is the measured RMS signal to RMS sum of all other
spectral components below the Nyquist frequency, excluding DC.
Effective Number Of Bits (ENOB)
Differential Linearity Error (DNL)
The effective number of bits (ENOB) is calculated from the
SINAD data by:
DNL is the worst case deviation of a code width from the
ideal value of 1 LSB.
ENOB = (SINAD + V CORR – 1.76 )/6.02
Integral Linearity Error (INL)
where:
INL is the worst case deviation of a code center from a best
fit straight line calculated from the measured data.
VCORR = 0.5dB
VCORR adjusts the ENOB for the amount the input is below
fullscale.
Power Supply Sensitivity
Total Harmonic Distortion (THD)
Each of the power supplies are moved plus and minus 5%
and the shift in the offset and gain error (in LSBs) is noted.
THD is the ratio of the RMS sum of the first 5 harmonic
components to the RMS value of the fundamental input
signal.
Dynamic Performance Definitions
2nd and 3rd Harmonic Distortion
Fast Fourier Transform (FFT) techniques are used to
evaluate the dynamic performance of the HI5804. A low
distortion sine wave is applied to the input, it is coherently
sampled, and the output is stored in RAM. The data is then
transformed into the frequency domain with an FFT and analyzed to evaluate the dynamic performance of the A/D. The
sine wave input to the part is -0.5dB down from full scale for
all these tests. SNR and SINAD are quoted in dB. The
distortion numbers are quoted in dBc (decibels with respect
to carrier) and DO NOT include any correction factors for
normalizing to full scale.
This is the ratio of the RMS value of the applicable harmonic
component to the RMS value of the fundamental input signal.
Intermodulation Distortion (IMD)
Nonlinearities in the signal path will tend to generate intermodulation products when two tones, f1 and f2 , are present on the
inputs. The ratio of the measured distortion terms to the signal
is calculated. The terms included in the calculation are (f1 + f2),
(f1 - f2), (2f1), (2f2), (2f1 + f2), (2f1 - f2), (f1 + 2f2), (f1 - 2f2). The
ADC is tested with each tone 6dB below full scale.
9
HI5804
Spurious Free Dynamic Range (SFDR)
Timing Definitions
SFDR is the ratio of the fundamental RMS amplitude to the
RMS amplitude of the next largest spur or spectral
component in the spectrum below fS/2.
Refer to Figure 1 and Figure 2 for these definitions.
Transient Response
Aperture delay is the time delay between the external sample command (the falling edge of the clock) and the time at
which the signal is actually sampled. This delay is due to
internal clock path propagation delays.
Aperture Delay (tAP)
Transient response is measured by providing a full scale
transition to the analog input of the ADC and measuring the
number of cycles it takes for the output code to settle within
12-bit accuracy.
Aperture Jitter (tAJ)
Aperture Jitter is the RMS variation in the aperture delay due
to variation of internal clock path delays.
Overvoltage Recovery
Overvoltage Recovery is measured by providing a full scale
transition to the analog input of the ADC which overdrives
the input by 200mV, and measuring the number of cycles it
takes for the output code to settle within 12-bit accuracy.
Data Hold Time (tH)
Data hold time is the time to where the previous data (N - 1)
is no longer valid.
Full Power Input Bandwidth (FPBW)
Data Output Delay Time (tOD)
Full power input bandwidth is the frequency at which the
amplitude of the digitally reconstructed output has
decreased 3dB below the amplitude of the input sine wave.
The input sine wave has a peak-to-peak amplitude equal to
the difference between the two internal voltage references.
The bandwidth given is measured at the specified sampling
frequency.
Data output delay time is the time to where the new data (N)
is valid.
Data Latency (tLAT)
After the analog sample is taken, the digital data is output on
the bus after the third cycle of the clock. This is due to the
pipeline nature of the converter where the data has to ripple
through the stages. This delay is specified as the data latency.
After the data latency time, the data representing each
succeeding sample is output at the following clock pulse. The
digital data lags the analog input sample by 3 clock cycles.
10
HI5804
Small Outline Plastic Packages (SOIC)
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.6969
0.7125
17.70
18.10
3
E
0.2914
0.2992
7.40
7.60
4
0.05 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.01
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
MAX
A1
e
α
MIN
28
0o
28
7
8o
Rev. 0 12/93
11
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